diff options
Diffstat (limited to 'gas/config')
34 files changed, 67 insertions, 67 deletions
diff --git a/gas/config/obj-ecoff.c b/gas/config/obj-ecoff.c index b994986..e337ff1 100644 --- a/gas/config/obj-ecoff.c +++ b/gas/config/obj-ecoff.c @@ -53,7 +53,7 @@ ecoff_frob_file_before_fix (void) This output ordering of sections is magic, on the Alpha, at least. The .lita section must come before .lit8 and .lit4, otherwise the OSF/1 linker may silently trash the .lit{4,8} - section contents. Also, .text must preceed .rdata. These differ + section contents. Also, .text must precede .rdata. These differ from the order described in some parts of the DEC OSF/1 Assembly Language Programmer's Guide, but that order doesn't seem to work with their linker. diff --git a/gas/config/obj-macho.c b/gas/config/obj-macho.c index 13d0043..9d64ac6 100644 --- a/gas/config/obj-macho.c +++ b/gas/config/obj-macho.c @@ -29,7 +29,7 @@ which subsections are generated like __text, __const etc. The well-known as short-hand section switch directives like .text, .data - etc. are mapped onto predefined segment/section pairs using facilites + etc. are mapped onto predefined segment/section pairs using facilities supplied by the mach-o port of bfd. A number of additional mach-o short-hand section switch directives are diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 7c518c7..c71b32b 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -647,7 +647,7 @@ first_error (const char *error) set_syntax_error (error); } -/* Similiar to first_error, but this function accepts formatted error +/* Similar to first_error, but this function accepts formatted error message. */ static void first_error_fmt (const char *format, ...) diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c index 376ac43..4eb6d6d 100644 --- a/gas/config/tc-arc.c +++ b/gas/config/tc-arc.c @@ -2659,7 +2659,7 @@ md_pcrel_from_section (fixS *fixP, /* The hardware calculates relative to the start of the insn, but this relocation is relative to location of the LIMM, compensate. The base always needs to be - substracted by 4 as we do not support this type of PCrel + subtracted by 4 as we do not support this type of PCrel relocation for short instructions. */ base -= 4; /* Fall through. */ diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index e37d354..4adcfda 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -3045,7 +3045,7 @@ s_ccs_ref (int unused ATTRIBUTE_UNUSED) } /* If name is not NULL, then it is used for marking the beginning of a - function, wherease if it is NULL then it means the function end. */ + function, whereas if it is NULL then it means the function end. */ static void asmfunc_debug (const char * name) { @@ -7306,7 +7306,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) The only binary encoding difference is the Coprocessor number. Coprocessor 9 is used for half-precision calculations or conversions. The format of the - instruction is the same as the equivalent Coprocessor 10 instuction that + instruction is the same as the equivalent Coprocessor 10 instruction that exists for Single-Precision operation. */ static void @@ -13083,7 +13083,7 @@ do_t_swi (void) if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m)) { if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os) - /* This only applies to the v6m howver, not later architectures. */ + /* This only applies to the v6m however, not later architectures. */ && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)) as_bad (_("SVC is not permitted on this architecture")); ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os); @@ -17950,7 +17950,7 @@ now_it_add_mask (int cond) for covering other cases. Calling handle_it_state () may not transition the IT block state to - OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be + OUTSIDE_IT_BLOCK immediately, since the (current) state could be still queried. Instead, if the FSM determines that the state should be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed after the tencode () function: that's what it_fsm_post_encode () does. @@ -18041,7 +18041,7 @@ handle_it_state (void) switch (inst.it_insn_type) { case OUTSIDE_IT_INSN: - /* The closure of the block shall happen immediatelly, + /* The closure of the block shall happen immediately, so any in_it_block () call reports the block as closed. */ force_automatic_it_block_close (); break; diff --git a/gas/config/tc-avr.c b/gas/config/tc-avr.c index ee3140d..568316a 100644 --- a/gas/config/tc-avr.c +++ b/gas/config/tc-avr.c @@ -398,7 +398,7 @@ static struct exp_mod_s exp_mod[] = {"hhi8", BFD_RELOC_AVR_MS8_LDI, BFD_RELOC_AVR_MS8_LDI_NEG, 0}, }; -/* A union used to store indicies into the exp_mod[] array +/* A union used to store indices into the exp_mod[] array in a hash table which expects void * data types. */ typedef union { diff --git a/gas/config/tc-cr16.c b/gas/config/tc-cr16.c index 186cfb9..7a3e9d8 100644 --- a/gas/config/tc-cr16.c +++ b/gas/config/tc-cr16.c @@ -1471,7 +1471,7 @@ gettrap (char *s) if (strcasecmp (trap->name, s) == 0) return trap->entry; - /* To make compatable with CR16 4.1 tools, the below 3-lines of + /* To make compatible with CR16 4.1 tools, the below 3-lines of * code added. Refer: Development Tracker item #123 */ for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++) if (trap->entry == (unsigned int) atoi (s)) @@ -2385,7 +2385,7 @@ next_insn: for (i = 0; i < insn->nargs; i++) { - /* For BAL (ra),disp17 instuction only. And also set the + /* For BAL (ra),disp17 instruction only. And also set the DISP24a relocation type. */ if (IS_INSN_MNEMONIC ("bal") && (instruction->size == 2) && i == 0) { diff --git a/gas/config/tc-epiphany.c b/gas/config/tc-epiphany.c index d14c3a0..d1c531c 100644 --- a/gas/config/tc-epiphany.c +++ b/gas/config/tc-epiphany.c @@ -288,7 +288,7 @@ epiphany_apply_fix (fixS *fixP, valueT *valP, segT seg) case BFD_RELOC_EPIPHANY_HIGH: value >>= 16; - /* fall thru */ + /* fallthru */ case BFD_RELOC_EPIPHANY_LOW: value = (((value & 0xff) << 5) | insn[0]) | (insn[1] << 8) @@ -340,7 +340,7 @@ epiphany_handle_align (fragS *fragp) } /* Read a comma separated incrementing list of register names - and form a bit mask of upto 15 registers 0..14. */ + and form a bit mask of up to 15 registers 0..14. */ static const char * parse_reglist (const char * s, int * mask) @@ -502,7 +502,7 @@ epiphany_assemble (const char *str) return; } } - /* fall-thru. */ + /* fallthru */ case OP4_LDSTRX: { @@ -994,7 +994,7 @@ md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED, return BFD_RELOC_EPIPHANY_LOW; else as_bad ("unknown imm16 operand"); - /* fall-thru */ + /* fallthru */ default: break; diff --git a/gas/config/tc-frv.c b/gas/config/tc-frv.c index f49096d..375f638 100644 --- a/gas/config/tc-frv.c +++ b/gas/config/tc-frv.c @@ -727,7 +727,7 @@ frv_tomcat_shuffle (enum vliw_nop_type this_nop_type, buffer[0] |= 0x80; } /* The branch is in the middle. Split this vliw insn into first - and second parts. Insert the NOP inbetween. */ + and second parts. Insert the NOP between. */ second_part->insn_list = insert_before_insn; second_part->insn_list->type = VLIW_BRANCH_HAS_NOPS; @@ -767,7 +767,7 @@ frv_tomcat_shuffle (enum vliw_nop_type this_nop_type, } /* The branch is in the middle. Split this vliw insn into first - and second parts. Insert the NOP inbetween. */ + and second parts. Insert the NOP in between. */ second_part->insn_list = insert_before_insn; second_part->insn_list->type = VLIW_BRANCH_HAS_NOPS; second_part->next = vliw_to_split->next; diff --git a/gas/config/tc-hppa.c b/gas/config/tc-hppa.c index 2ed06a2..16ca402 100644 --- a/gas/config/tc-hppa.c +++ b/gas/config/tc-hppa.c @@ -1440,7 +1440,7 @@ tc_gen_reloc (asection *section, fixS *fixp) /* Facilitate hand-crafted unwind info. */ if (strcmp (section->name, UNWIND_SECTION_NAME) == 0) code = R_PARISC_SEGREL32; - /* Fall thru */ + /* Fallthru */ default: reloc->addend = fixp->fx_offset; diff --git a/gas/config/tc-hppa.h b/gas/config/tc-hppa.h index 4f3a7cd..aaeff64 100644 --- a/gas/config/tc-hppa.h +++ b/gas/config/tc-hppa.h @@ -166,7 +166,7 @@ int hppa_fix_adjustable (struct fix *); limitations as those for the 32-bit SOM target. */ #define DIFF_EXPR_OK 1 -/* Handle .type psuedo. Given a type string of `millicode', set the +/* Handle .type pseudo. Given a type string of `millicode', set the internal elf symbol type to STT_PARISC_MILLI, and return BSF_FUNCTION for the BFD symbol type. */ #define md_elf_symbol_type(name, sym, elf) \ diff --git a/gas/config/tc-i370.c b/gas/config/tc-i370.c index 6299cc7..6290f24 100644 --- a/gas/config/tc-i370.c +++ b/gas/config/tc-i370.c @@ -1376,7 +1376,7 @@ symbol_locate (symbolS *symbolP, } /* i370_addr_offset() will convert operand expressions - that appear to be absolute into thier base-register + that appear to be absolute into their base-register relative form. These expressions come in two types: (1) of the form "* + const" * where "*" means @@ -1482,7 +1482,7 @@ i370_addr_cons (expressionS *exp) expression (exp); /* We use a simple string name to collapse together - multiple refrences to the same address literal. */ + multiple references to the same address literal. */ name_len = strcspn (sym_name, ", "); delim = *(sym_name + name_len); *(sym_name + name_len) = 0x0; diff --git a/gas/config/tc-m68hc11.c b/gas/config/tc-m68hc11.c index 1fc52b1..8f1bbf0 100644 --- a/gas/config/tc-m68hc11.c +++ b/gas/config/tc-m68hc11.c @@ -555,7 +555,7 @@ md_parse_option (int c, const char *arg) current_architecture = cpu6812 | cpu6812s | cpu9s12x; else if ((strcasecmp (arg, "m9s12xg") == 0) || (strcasecmp (arg, "xgate") == 0)) - /* xgate for backwards compatability */ + /* xgate for backwards compatibility */ current_architecture = cpuxgate; else as_bad (_("Option `%s' is not recognized."), arg); diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c index 4f64f5c..56e5599 100644 --- a/gas/config/tc-m68k.c +++ b/gas/config/tc-m68k.c @@ -513,7 +513,7 @@ struct m68k_cpu unsigned long arch; /* Architecture features. */ const enum m68k_register *control_regs; /* Control regs on chip */ const char *name; /* Name */ - int alias; /* Alias for a cannonical name. If 1, then + int alias; /* Alias for a canonical name. If 1, then succeeds canonical name, if -1 then succeeds canonical name, if <-1 ||>1 this is a deprecated name, and the next/previous name @@ -1469,7 +1469,7 @@ m68k_ip (char *instring) char *old = input_line_pointer; *old = '\n'; input_line_pointer = p; - /* Ahh - it's a motorola style psuedo op. */ + /* Ahh - it's a motorola style pseudo op. */ mote_pseudo_table[opcode->m_opnum].poc_handler (mote_pseudo_table[opcode->m_opnum].poc_val); input_line_pointer = old; @@ -4597,7 +4597,7 @@ md_begin (void) m68k_rel32 = 0; } - /* First sort the opcode table into alphabetical order to seperate + /* First sort the opcode table into alphabetical order to separate the order that the assembler wants to see the opcodes from the order that the disassembler wants to see them. */ m68k_sorted_opcodes = XNEWVEC (const struct m68k_opcode *, m68k_numopcodes); diff --git a/gas/config/tc-mcore.c b/gas/config/tc-mcore.c index ec03a29..0eea818 100644 --- a/gas/config/tc-mcore.c +++ b/gas/config/tc-mcore.c @@ -1766,7 +1766,7 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, case C (COND_JUMP, DISP32): case C (COND_JUMP, UNDEF_WORD_DISP): { - /* A conditional branch wont fit into 12 bits so: + /* A conditional branch won't fit into 12 bits so: b!cond 1f jmpi 0f .align 2 diff --git a/gas/config/tc-mep.c b/gas/config/tc-mep.c index dac10c9..bec757f 100644 --- a/gas/config/tc-mep.c +++ b/gas/config/tc-mep.c @@ -1146,7 +1146,7 @@ mep_check_ivc2_scheduling (void) /* The scheduling functions are just filters for invalid combinations. If there is a violation, they terminate assembly. Otherise they - just fall through. Succesful combinations cause no side effects + just fall through. Successful combinations cause no side effects other than valid nop insertion. */ static void @@ -1219,7 +1219,7 @@ md_assemble (char * str) + copro insn We want to handle the general case where more than - one instruction can be preceeded by a +. This will + one instruction can be preceded by a +. This will happen later if we add support for internally parallel coprocessors. We'll make the parsing nice and general so that it can handle an arbitrary number of insns @@ -1299,7 +1299,7 @@ md_assemble (char * str) /* Check for a + with a core insn and abort if found. */ if (!thisInsnIsCopro) { - as_fatal("A core insn cannot be preceeded by a +.\n"); + as_fatal("A core insn cannot be preceded by a +.\n"); return; } @@ -2185,7 +2185,7 @@ mep_cleanup (void) { /* Take care of any insns left to be parallelized when the file ends. This is mainly here to handle the case where the file ends with an - insn preceeded by a + or the file ends unexpectedly. */ + insn preceded by a + or the file ends unexpectedly. */ if (mode == VLIW) mep_process_saved_insns (); } diff --git a/gas/config/tc-metag.c b/gas/config/tc-metag.c index b56f9d2..3e81629 100644 --- a/gas/config/tc-metag.c +++ b/gas/config/tc-metag.c @@ -4717,7 +4717,7 @@ parse_dtemplate (const char *line, metag_insn *insn, return l; } -/* Parse a DSP Template definiton memory reference, e.g +/* Parse a DSP Template definition memory reference, e.g [A0.7+A0.5++]. DSPRAM is set to true by this function if this template definition is a DSP RAM template definition. */ static const char * @@ -4739,7 +4739,7 @@ template_mem_ref(const char *line, metag_addr *addr, return l; } -/* Sets LOAD to TRUE if this is a Template load definiton (otherwise +/* Sets LOAD to TRUE if this is a Template load definition (otherwise it's a store). Fills out ADDR, TEMPLATE_REG and ADDR_UNIT. */ static const char * parse_template_regs (const char *line, bfd_boolean *load, @@ -5626,7 +5626,7 @@ parse_dalu (const char *line, metag_insn *insn, if ((template->meta_opcode >> 26) & 0x1) ls_shift = INVALID_SHIFT; - /* The Condition Is Always (CA) bit must be set if we're targetting a + /* The Condition Is Always (CA) bit must be set if we're targeting a Ux.r register as the destination. This means that we can't have any other condition bits set. */ if (!is_same_data_unit (regs[1]->unit, regs[0]->unit)) diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 283ed80..a9d6f6b 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -4711,7 +4711,7 @@ struct mips_arg_info unsigned int last_op_int; /* If true, match routines should assume that no later instruction - alternative matches and should therefore be as accomodating as + alternative matches and should therefore be as accommodating as possible. Match routines should not report errors if something is only invalid for !LAX_MATCH. */ bfd_boolean lax_match; @@ -9785,7 +9785,7 @@ small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) * optimizing code generation. * One interesting optimization is when several store macros appear * consecutively that would load AT with the upper half of the same address. - * The ensuing load upper instructions are ommited. This implies some kind + * The ensuing load upper instructions are omitted. This implies some kind * of global optimization. We currently only optimize within a single macro. * For many of the load and store macros if the address is specified as a * constant expression in the first 64k of memory (ie ld $2,0x4000c) we @@ -11809,7 +11809,7 @@ macro (struct mips_cl_insn *ip, char *str) else if (offbits != 16) { /* The offset field is too narrow to be used for a low-part - relocation, so load the whole address into the auxillary + relocation, so load the whole address into the auxiliary register. */ load_address (tempreg, &offset_expr, &used_at); if (breg != 0) diff --git a/gas/config/tc-mn10200.c b/gas/config/tc-mn10200.c index 8275c1a..2db07ef 100644 --- a/gas/config/tc-mn10200.c +++ b/gas/config/tc-mn10200.c @@ -1161,7 +1161,7 @@ keep_going: as the size of a pointer, so we need a union to convert the opindex field of the fr_cgen structure into a char * so that it can be stored in the frag. We do not have - to worry about loosing accuracy as we are not going to + to worry about losing accuracy as we are not going to be even close to the 32bit limit of the int. */ union { diff --git a/gas/config/tc-mn10300.c b/gas/config/tc-mn10300.c index 4ce2ee4..6f9c3cc 100644 --- a/gas/config/tc-mn10300.c +++ b/gas/config/tc-mn10300.c @@ -1865,7 +1865,7 @@ keep_going: as the size of a pointer, so we need a union to convert the opindex field of the fr_cgen structure into a char * so that it can be stored in the frag. We do not have - to worry about loosing accuracy as we are not going to + to worry about losing accuracy as we are not going to be even close to the 32bit limit of the int. */ union { @@ -2618,7 +2618,7 @@ mn10300_handle_align (fragS *frag) relocs will prevent the contents from being merged. */ && (bfd_get_section_flags (now_seg->owner, now_seg) & SEC_MERGE) == 0) /* Create a new fixup to record the alignment request. The symbol is - irrelevent but must be present so we use the absolute section symbol. + irrelevant but must be present so we use the absolute section symbol. The offset from the symbol is used to record the power-of-two alignment value. The size is set to 0 because the frag may already be aligned, thus causing cvt_frag_to_fill to reduce the size of the frag to zero. */ diff --git a/gas/config/tc-nds32.c b/gas/config/tc-nds32.c index de59f46..8696724 100644 --- a/gas/config/tc-nds32.c +++ b/gas/config/tc-nds32.c @@ -91,7 +91,7 @@ static int enable_relax_relocs = 1; static int enable_relax_ex9 = 0; /* The value will be used in RELAX_ENTRY. */ static int enable_relax_ifc = 0; -/* Save option -O for perfomance. */ +/* Save option -O for performance. */ static int optimize = 0; /* Save option -Os for code size. */ static int optimize_for_space = 0; @@ -5233,7 +5233,7 @@ md_assemble (char *str) if (!nds32_check_insn_available (insn, str)) return; - /* Make sure the begining of text being 2-byte align. */ + /* Make sure the beginning of text being 2-byte align. */ nds32_adjust_label (1); fld = insn.field; /* Try to allocate the max size to guarantee relaxable same branch @@ -6440,7 +6440,7 @@ elf_nds32_final_processing (void) elf_elfheader (stdoutput)->e_flags |= nds32_elf_flags; } -/* Implement md_apply_fix. Apply the fix-up or tranform the fix-up for +/* Implement md_apply_fix. Apply the fix-up or transform the fix-up for later relocation generation. */ void @@ -6463,7 +6463,7 @@ nds32_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) fixP->fx_addnumber = value; fixP->tc_fix_data = NULL; - /* Tranform specific relocations here for later relocation generation. + /* Transform specific relocations here for later relocation generation. Tag data here for ex9 relaxtion and tag tls data for linker. */ switch (fixP->fx_r_type) { diff --git a/gas/config/tc-nios2.c b/gas/config/tc-nios2.c index 0a1286a..3e12eee 100644 --- a/gas/config/tc-nios2.c +++ b/gas/config/tc-nios2.c @@ -206,7 +206,7 @@ static segT nios2_current_align_seg; static int nios2_auto_align_on = 1; /* The last seen label in the current section. This is used to auto-align - labels preceeding instructions. */ + labels preceding instructions. */ static symbolS *nios2_last_label; /* If we saw a 16-bit CDX instruction, we can align on 2-byte boundaries diff --git a/gas/config/tc-ns32k.c b/gas/config/tc-ns32k.c index 570916d..31b23ba 100644 --- a/gas/config/tc-ns32k.c +++ b/gas/config/tc-ns32k.c @@ -333,7 +333,7 @@ const pseudo_typeS md_pseudo_table[] = displacement base-adjust as there are other routines that must consider this. Also, as we have two various offset-adjusts in the ns32k (acb versus br/brs/jsr/bcond), two set of limits would have - had to be used. Now we dont have to think about that. */ + had to be used. Now we don't have to think about that. */ const relax_typeS md_relax_table[] = { @@ -985,10 +985,10 @@ encode_operand (int argc, argv[i] = freeptr; pcrel -= 1; /* Make pcrel 0 in spite of what case 'p': wants. */ - /* fall thru */ + /* fallthru */ case 'p': /* Displacement - pc relative addressing. */ pcrel += 1; - /* fall thru */ + /* fallthru */ case 'd': /* Displacement. */ iif.instr_size += suffixP[i] ? suffixP[i] : 4; IIF (12, 2, suffixP[i], (unsigned long) argv[i], 0, @@ -1818,7 +1818,7 @@ convert_iif (void) { /* Frag it. */ if (exprP.X_op_symbol) - /* We cant relax this case. */ + /* We can't relax this case. */ as_fatal (_("Can't relax difference")); else { diff --git a/gas/config/tc-pdp11.c b/gas/config/tc-pdp11.c index f6cf025..d343194 100644 --- a/gas/config/tc-pdp11.c +++ b/gas/config/tc-pdp11.c @@ -1286,7 +1286,7 @@ md_show_usage (FILE *stream) { fprintf (stream, "\ \n\ -PDP-11 instruction set extentions:\n\ +PDP-11 instruction set extensions:\n\ \n\ -m(no-)cis allow (disallow) commersial instruction set\n\ -m(no-)csm allow (disallow) CSM instruction\n\ diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index 84d4ebc..c546859 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -2952,7 +2952,7 @@ md_assemble (char *str) } break; } - /* Fall thru */ + /* Fallthru */ case BFD_RELOC_PPC64_ADDR16_HIGH: ex.X_add_number = PPC_HI (ex.X_add_number); @@ -2974,7 +2974,7 @@ md_assemble (char *str) } break; } - /* Fall thru */ + /* Fallthru */ case BFD_RELOC_PPC64_ADDR16_HIGHA: ex.X_add_number = PPC_HA (ex.X_add_number); @@ -6579,7 +6579,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg) } break; } - /* Fall thru */ + /* Fallthru */ case BFD_RELOC_PPC_VLE_HI16A: case BFD_RELOC_PPC_VLE_HI16D: @@ -6602,7 +6602,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg) } break; } - /* Fall thru */ + /* Fallthru */ case BFD_RELOC_PPC_VLE_HA16A: case BFD_RELOC_PPC_VLE_HA16D: @@ -6744,7 +6744,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg) case BFD_RELOC_PPC_VLE_SDAREL_HA16A: case BFD_RELOC_PPC_VLE_SDAREL_HA16D: gas_assert (fixP->fx_addsy != NULL); - /* Fall thru */ + /* Fallthru */ case BFD_RELOC_PPC_TLS: case BFD_RELOC_PPC_TLSGD: @@ -6868,7 +6868,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg) && !S_IS_DEFINED (fixP->fx_addsy) && !S_IS_WEAK (fixP->fx_addsy)) S_SET_WEAK (fixP->fx_addsy); - /* Fall thru */ + /* Fallthru */ case BFD_RELOC_VTABLE_ENTRY: fixP->fx_done = 0; diff --git a/gas/config/tc-rx.c b/gas/config/tc-rx.c index 07dccc6..575ed4b 100644 --- a/gas/config/tc-rx.c +++ b/gas/config/tc-rx.c @@ -1077,7 +1077,7 @@ scan_for_infix_rx_pseudo_ops (char * str) if (dot == NULL || dot == str) return FALSE; - /* A real pseudo-op must be preceeded by whitespace. */ + /* A real pseudo-op must be preceded by whitespace. */ if (dot[-1] != ' ' && dot[-1] != '\t') return FALSE; @@ -2671,7 +2671,7 @@ rx_elf_final_processing (void) elf_elfheader (stdoutput)->e_flags |= elf_flags; } -/* Scan the current input line for occurances of Renesas +/* Scan the current input line for occurrences of Renesas local labels and replace them with the GAS version. */ void diff --git a/gas/config/tc-score.c b/gas/config/tc-score.c index f68cc6f..2b0c0a8 100644 --- a/gas/config/tc-score.c +++ b/gas/config/tc-score.c @@ -7250,7 +7250,7 @@ s3_apply_fix (fixS *fixP, valueT *valP, segT seg) } else { - /* In differnt section. */ + /* In different section. */ if ((S_GET_SEGMENT (fixP->fx_addsy) != seg) || (fixP->fx_addsy != NULL && S_IS_EXTERNAL (fixP->fx_addsy))) value = fixP->fx_offset; diff --git a/gas/config/tc-score7.c b/gas/config/tc-score7.c index d7dd108..ee96348 100644 --- a/gas/config/tc-score7.c +++ b/gas/config/tc-score7.c @@ -6787,7 +6787,7 @@ s7_apply_fix (fixS *fixP, valueT *valP, segT seg) } else { - /* In differnt section. */ + /* In different section. */ if ((S_GET_SEGMENT (fixP->fx_addsy) != seg) || (fixP->fx_addsy != NULL && S_IS_EXTERNAL (fixP->fx_addsy))) value = fixP->fx_offset; diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c index 52c1b24..9509b37 100644 --- a/gas/config/tc-sparc.c +++ b/gas/config/tc-sparc.c @@ -1263,7 +1263,7 @@ BSR (bfd_vma val, int amount) static char *expr_end; /* Values for `special_case'. - Instructions that require wierd handling because they're longer than + Instructions that require weird handling because they're longer than 4 bytes. */ #define SPECIAL_CASE_NONE 0 #define SPECIAL_CASE_SET 1 diff --git a/gas/config/tc-tic54x.c b/gas/config/tc-tic54x.c index 409e4a0..09fd12a 100644 --- a/gas/config/tc-tic54x.c +++ b/gas/config/tc-tic54x.c @@ -1670,7 +1670,7 @@ tic54x_align_words (int arg) s_align_bytes (count << 1); } -/* Initialize multiple-bit fields withing a single word of memory. */ +/* Initialize multiple-bit fields within a single word of memory. */ static void tic54x_field (int ignore ATTRIBUTE_UNUSED) diff --git a/gas/config/tc-vax.c b/gas/config/tc-vax.c index e358c84..7e0aa04 100644 --- a/gas/config/tc-vax.c +++ b/gas/config/tc-vax.c @@ -188,7 +188,7 @@ int flag_want_pic; /* -k */ #define BB (1+-128) #define WF (2+ 32767) #define WB (2+-32768) -/* Dont need LF, LB because they always reach. [They are coded as 0.] */ +/* Don't need LF, LB because they always reach. [They are coded as 0.] */ #define C(a,b) ENCODE_RELAX(a,b) /* This macro has no side-effects. */ diff --git a/gas/config/tc-xgate.h b/gas/config/tc-xgate.h index cce73ae..ad6ccf4 100644 --- a/gas/config/tc-xgate.h +++ b/gas/config/tc-xgate.h @@ -75,7 +75,7 @@ extern struct relax_type md_relax_table[]; /* GAS only handles relaxations for pc-relative data targeting addresses in the same segment, we have to encode all other cases */ -/* FIXME: impliment this. */ +/* FIXME: implement this. */ /* #define md_relax_frag(SEG, FRAGP, STRETCH) \ ((FRAGP)->fr_symbol != NULL \ && S_GET_SEGMENT ((FRAGP)->fr_symbol) == (SEG) \ diff --git a/gas/config/tc-xtensa.c b/gas/config/tc-xtensa.c index ca261ae..b4a3222 100644 --- a/gas/config/tc-xtensa.c +++ b/gas/config/tc-xtensa.c @@ -5507,7 +5507,7 @@ md_assemble (char *str) orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); orig_insn.opcode = xtensa_opcode_lookup (isa, opname); - /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its + /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its extra argument and set the opcode to "CALLXn". */ if (orig_insn.opcode == XTENSA_UNDEFINED && strncasecmp (opname, "callx", 5) == 0) @@ -5556,7 +5556,7 @@ md_assemble (char *str) } } - /* Special case: Check for "j.l" psuedo op. */ + /* Special case: Check for "j.l" pseudo op. */ if (orig_insn.opcode == XTENSA_UNDEFINED && strncasecmp (opname, "j.l", 3) == 0) { diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c index b7e075a..0953541 100644 --- a/gas/config/tc-z80.c +++ b/gas/config/tc-z80.c @@ -540,7 +540,7 @@ contains_register(symbolS *sym) return 0; } -/* Parse general expression, not loooking for indexed adressing. */ +/* Parse general expression, not loooking for indexed addressing. */ static const char * parse_exp_not_indexed (const char *s, expressionS *op) { |