diff options
Diffstat (limited to 'gas/config/tc-mips.c')
| -rw-r--r-- | gas/config/tc-mips.c | 41 |
1 files changed, 2 insertions, 39 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 53e10ea..9e2183c 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -505,11 +505,6 @@ static int mips_32bitmode = 0; /* True if CPU has seq/sne and seqi/snei instructions. */ #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) -/* True if CPU does not implement the all the coprocessor insns. For these - CPUs only those COP insns are accepted that are explicitly marked to be - available on the CPU. ISA membership for COP insns is ignored. */ -#define NO_ISA_COP(CPU) (CPU_IS_OCTEON (CPU)) - /* True if mflo and mfhi can be immediately followed by instructions which write to the HI and LO registers. @@ -580,15 +575,6 @@ static int mips_32bitmode = 0; #define MF_HILO_INSN(PINFO) \ ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) -/* Returns true for a (non floating-point) coprocessor instruction. Reading - or writing the condition code is only possible on the coprocessors and - these insns are not marked with INSN_COP. Thus for these insns use the - condition-code flags. */ -#define COP_INSN(PINFO) \ - (PINFO != INSN_MACRO \ - && ((PINFO) & (FP_S | FP_D)) == 0 \ - && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) - /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) has been selected. This implies, in particular, that addresses of text labels have their LSB set. */ @@ -2221,13 +2207,7 @@ is_opcode_valid (const struct mips_opcode *mo) if (mips_opts.ase_mcu) isa |= INSN_MCU; - /* Don't accept instructions based on the ISA if the CPU does not implement - all the coprocessor insns. */ - if (NO_ISA_COP (mips_opts.arch) - && COP_INSN (mo->pinfo)) - isa = 0; - - if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) + if (!opcode_is_member (mo, isa, mips_opts.arch)) return FALSE; /* Check whether the instruction or macro requires single-precision or @@ -2259,7 +2239,7 @@ is_opcode_valid (const struct mips_opcode *mo) static bfd_boolean is_opcode_valid_16 (const struct mips_opcode *mo) { - return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; + return opcode_is_member (mo, mips_opts.isa, mips_opts.arch); } /* Return TRUE if the size of the microMIPS opcode MO matches one @@ -8265,15 +8245,6 @@ macro (struct mips_cl_insn *ip) tempreg = AT; used_at = 1; ld_noat: - if (coproc - && NO_ISA_COP (mips_opts.arch) - && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) - { - as_bad (_("Opcode not supported on this processor: %s"), - mips_cpu_info_from_arch (mips_opts.arch)->name); - break; - } - if (offset_expr.X_op != O_constant && offset_expr.X_op != O_symbol) { @@ -9199,14 +9170,6 @@ macro (struct mips_cl_insn *ip) s = "c3"; copz: gas_assert (!mips_opts.micromips); - if (NO_ISA_COP (mips_opts.arch) - && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) - { - as_bad (_("Opcode not supported on this processor: %s"), - mips_cpu_info_from_arch (mips_opts.arch)->name); - break; - } - /* For now we just do C (same as Cz). The parameter will be stored in insn_opcode by mips_ip. */ macro_build (NULL, s, "C", ip->insn_opcode); |