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Diffstat (limited to 'gas/config/tc-m32r.c')
-rw-r--r--gas/config/tc-m32r.c323
1 files changed, 133 insertions, 190 deletions
diff --git a/gas/config/tc-m32r.c b/gas/config/tc-m32r.c
index ed72922..ab574fe 100644
--- a/gas/config/tc-m32r.c
+++ b/gas/config/tc-m32r.c
@@ -166,7 +166,8 @@ struct m32r_hi_fixup
static struct m32r_hi_fixup *m32r_hi_fixup_list;
-struct {
+struct
+{
enum bfd_architecture bfd_mach;
int mach_flags;
} mach_table[] =
@@ -176,8 +177,6 @@ struct {
{ bfd_mach_m32r2, (1<<MACH_M32R2) }
};
-static void allow_m32rx (int);
-
static void
allow_m32rx (int on)
{
@@ -194,25 +193,29 @@ allow_m32rx (int on)
const char *md_shortopts = M32R_SHORTOPTS;
+enum md_option_enums
+{
+ OPTION_M32R = OPTION_MD_BASE,
+ OPTION_M32RX,
+ OPTION_M32R2,
+ OPTION_BIG,
+ OPTION_LITTLE,
+ OPTION_PARALLEL,
+ OPTION_NO_PARALLEL,
+ OPTION_WARN_PARALLEL,
+ OPTION_NO_WARN_PARALLEL,
+ OPTION_IGNORE_PARALLEL,
+ OPTION_NO_IGNORE_PARALLEL,
+ OPTION_SPECIAL,
+ OPTION_SPECIAL_M32R,
+ OPTION_NO_SPECIAL_M32R,
+ OPTION_SPECIAL_FLOAT,
+ OPTION_WARN_UNMATCHED,
+ OPTION_NO_WARN_UNMATCHED
+};
+
struct option md_longopts[] =
{
-#define OPTION_M32R (OPTION_MD_BASE)
-#define OPTION_M32RX (OPTION_M32R + 1)
-#define OPTION_M32R2 (OPTION_M32RX + 1)
-#define OPTION_BIG (OPTION_M32R2 + 1)
-#define OPTION_LITTLE (OPTION_BIG + 1)
-#define OPTION_PARALLEL (OPTION_LITTLE + 1)
-#define OPTION_NO_PARALLEL (OPTION_PARALLEL + 1)
-#define OPTION_WARN_PARALLEL (OPTION_NO_PARALLEL + 1)
-#define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1)
-#define OPTION_IGNORE_PARALLEL (OPTION_NO_WARN_PARALLEL + 1)
-#define OPTION_NO_IGNORE_PARALLEL (OPTION_IGNORE_PARALLEL + 1)
-#define OPTION_SPECIAL (OPTION_NO_IGNORE_PARALLEL + 1)
-#define OPTION_SPECIAL_M32R (OPTION_SPECIAL + 1)
-#define OPTION_NO_SPECIAL_M32R (OPTION_SPECIAL_M32R + 1)
-#define OPTION_SPECIAL_FLOAT (OPTION_NO_SPECIAL_M32R + 1)
-#define OPTION_WARN_UNMATCHED (OPTION_SPECIAL_FLOAT + 1)
-#define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1)
{"m32r", no_argument, NULL, OPTION_M32R},
{"m32rx", no_argument, NULL, OPTION_M32RX},
{"m32r2", no_argument, NULL, OPTION_M32R2},
@@ -244,9 +247,6 @@ struct option md_longopts[] =
size_t md_longopts_size = sizeof (md_longopts);
-static void little (int);
-static int parallel (void);
-
static void
little (int on)
{
@@ -268,9 +268,7 @@ parallel (void)
}
int
-md_parse_option (c, arg)
- int c;
- char *arg ATTRIBUTE_UNUSED;
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
{
switch (c)
{
@@ -371,8 +369,7 @@ md_parse_option (c, arg)
}
void
-md_show_usage (stream)
- FILE *stream;
+md_show_usage (FILE *stream)
{
fprintf (stream, _(" M32R specific command line options:\n"));
@@ -433,30 +430,10 @@ md_show_usage (stream)
-KPIC generate PIC\n"));
}
-static void fill_insn PARAMS ((int));
-static void m32r_scomm PARAMS ((int));
-static void debug_sym PARAMS ((int));
-static void expand_debug_syms PARAMS ((sym_linkS *, int));
-
/* Set by md_assemble for use by m32r_fill_insn. */
static subsegT prev_subseg;
static segT prev_seg;
-/* The target specific pseudo-ops which we support. */
-const pseudo_typeS md_pseudo_table[] =
-{
- { "word", cons, 4 },
- { "fillinsn", fill_insn, 0 },
- { "scomm", m32r_scomm, 0 },
- { "debugsym", debug_sym, 0 },
- { "m32r", allow_m32rx, 0 },
- { "m32rx", allow_m32rx, 1 },
- { "m32r2", allow_m32rx, 2 },
- { "little", little, 1 },
- { "big", little, 0 },
- { NULL, NULL, 0 }
-};
-
#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
symbolS * GOT_symbol;
@@ -528,8 +505,7 @@ m32r_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p)
of an rs_align_code fragment. */
void
-m32r_handle_align (fragp)
- fragS *fragp;
+m32r_handle_align (fragS *fragp)
{
static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
@@ -575,8 +551,7 @@ m32r_handle_align (fragp)
seen after an insn that is relaxable. */
static void
-fill_insn (ignore)
- int ignore ATTRIBUTE_UNUSED;
+fill_insn (int ignore ATTRIBUTE_UNUSED)
{
frag_align_code (2, 0);
prev_insn.insn = NULL;
@@ -590,14 +565,13 @@ fill_insn (ignore)
16 bit instruction. */
static void
-debug_sym (ignore)
- int ignore ATTRIBUTE_UNUSED;
+debug_sym (int ignore ATTRIBUTE_UNUSED)
{
- register char *name;
- register char delim;
- register char *end_name;
- register symbolS *symbolP;
- register sym_linkS *link;
+ char *name;
+ char delim;
+ char *end_name;
+ symbolS *symbolP;
+ sym_linkS *link;
name = input_line_pointer;
delim = get_symbol_end ();
@@ -605,9 +579,7 @@ debug_sym (ignore)
if ((symbolP = symbol_find (name)) == NULL
&& (symbolP = md_undefined_symbol (name)) == NULL)
- {
- symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
- }
+ symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
symbol_table_insert (symbolP);
if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section
@@ -633,9 +605,7 @@ debug_sym (ignore)
list of symbols and reassign the address. */
static void
-expand_debug_syms (syms, align)
- sym_linkS *syms;
- int align;
+expand_debug_syms (sym_linkS *syms, int align)
{
char *save_input_line = input_line_pointer;
sym_linkS *next_syms;
@@ -657,7 +627,7 @@ expand_debug_syms (syms, align)
}
void
-m32r_flush_pending_output()
+m32r_flush_pending_output (void)
{
if (debug_sym_link)
{
@@ -671,8 +641,7 @@ m32r_flush_pending_output()
current line is a label. */
int
-m32r_fill_insn (done)
- int done;
+m32r_fill_insn (int done)
{
if (prev_seg != NULL)
{
@@ -698,7 +667,7 @@ m32r_fill_insn (done)
/* The default target format to use. */
const char *
-m32r_target_format ()
+m32r_target_format (void)
{
#ifdef TE_LINUX
if (target_big_endian)
@@ -714,7 +683,7 @@ m32r_target_format ()
}
void
-md_begin ()
+md_begin (void)
{
flagword applicable;
segT seg;
@@ -756,12 +725,12 @@ md_begin ()
but with the name .scommon. */
scom_section = bfd_com_section;
scom_section.name = ".scommon";
- scom_section.output_section = &scom_section;
- scom_section.symbol = &scom_symbol;
- scom_section.symbol_ptr_ptr = &scom_section.symbol;
- scom_symbol = *bfd_com_section.symbol;
+ scom_section.output_section = & scom_section;
+ scom_section.symbol = & scom_symbol;
+ scom_section.symbol_ptr_ptr = & scom_section.symbol;
+ scom_symbol = * bfd_com_section.symbol;
scom_symbol.name = ".scommon";
- scom_symbol.section = &scom_section;
+ scom_symbol.section = & scom_section;
allow_m32rx (enable_m32rx);
@@ -778,14 +747,10 @@ md_begin ()
of instruction 'b'. If 'check_outputs' is true then b's outputs are
checked, otherwise its inputs are examined. */
-static int first_writes_to_seconds_operands
- PARAMS ((m32r_insn *, m32r_insn *, const int));
-
static int
-first_writes_to_seconds_operands (a, b, check_outputs)
- m32r_insn *a;
- m32r_insn *b;
- const int check_outputs;
+first_writes_to_seconds_operands (m32r_insn *a,
+ m32r_insn *b,
+ const int check_outputs)
{
const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn);
const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn);
@@ -858,11 +823,8 @@ first_writes_to_seconds_operands (a, b, check_outputs)
/* Returns true if the insn can (potentially) alter the program counter. */
-static int writes_to_pc PARAMS ((m32r_insn *));
-
static int
-writes_to_pc (a)
- m32r_insn *a;
+writes_to_pc (m32r_insn *a)
{
if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI)
|| CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI))
@@ -873,12 +835,8 @@ writes_to_pc (a)
/* Return NULL if the two 16 bit insns can be executed in parallel.
Otherwise return a pointer to an error message explaining why not. */
-static const char *can_make_parallel PARAMS ((m32r_insn *, m32r_insn *));
-
static const char *
-can_make_parallel (a, b)
- m32r_insn *a;
- m32r_insn *b;
+can_make_parallel (m32r_insn *a, m32r_insn *b)
{
PIPE_ATTR a_pipe;
PIPE_ATTR b_pipe;
@@ -912,11 +870,8 @@ can_make_parallel (a, b)
/* Force the top bit of the second 16-bit insn to be set. */
-static void make_parallel PARAMS ((CGEN_INSN_BYTES_PTR));
-
static void
-make_parallel (buffer)
- CGEN_INSN_BYTES_PTR buffer;
+make_parallel (CGEN_INSN_BYTES_PTR buffer)
{
#if CGEN_INT_INSN_P
*buffer |= 0x8000;
@@ -928,11 +883,8 @@ make_parallel (buffer)
/* Same as make_parallel except buffer contains the bytes in target order. */
-static void target_make_parallel PARAMS ((char *));
-
static void
-target_make_parallel (buffer)
- char *buffer;
+target_make_parallel (char *buffer)
{
buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
|= 0x80;
@@ -941,13 +893,8 @@ target_make_parallel (buffer)
/* Assemble two instructions with an explicit parallel operation (||) or
sequential operation (->). */
-static void assemble_two_insns PARAMS ((char *, char *, int));
-
static void
-assemble_two_insns (str, str2, parallel_p)
- char *str;
- char *str2;
- int parallel_p;
+assemble_two_insns (char *str1, char *str2, int parallel_p)
{
char *str3;
m32r_insn first;
@@ -971,7 +918,7 @@ assemble_two_insns (str, str2, parallel_p)
/* Parse the first instruction. */
if (! (first.insn = m32r_cgen_assemble_insn
- (gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg)))
+ (gas_cgen_cpu_desc, str1, & first.fields, first.buffer, & errmsg)))
{
as_bad (errmsg);
return;
@@ -981,7 +928,7 @@ assemble_two_insns (str, str2, parallel_p)
if (CGEN_FIELDS_BITSIZE (&first.fields) != 16)
{
/* xgettext:c-format */
- as_bad (_("not a 16 bit instruction '%s'"), str);
+ as_bad (_("not a 16 bit instruction '%s'"), str1);
return;
}
#ifdef E_M32R2_ARCH
@@ -993,7 +940,7 @@ assemble_two_insns (str, str2, parallel_p)
& (1 << MACH_M32RX)))))
{
/* xgettext:c-format */
- as_bad (_("instruction '%s' is for the M32R2 only"), str);
+ as_bad (_("instruction '%s' is for the M32R2 only"), str1);
return;
}
else if ((! enable_special
@@ -1006,7 +953,7 @@ assemble_two_insns (str, str2, parallel_p)
#endif
{
/* xgettext:c-format */
- as_bad (_("unknown instruction '%s'"), str);
+ as_bad (_("unknown instruction '%s'"), str1);
return;
}
else if (! enable_m32rx
@@ -1015,7 +962,7 @@ assemble_two_insns (str, str2, parallel_p)
== (1 << MACH_M32RX)))
{
/* xgettext:c-format */
- as_bad (_("instruction '%s' is for the M32RX only"), str);
+ as_bad (_("instruction '%s' is for the M32RX only"), str1);
return;
}
@@ -1024,7 +971,7 @@ assemble_two_insns (str, str2, parallel_p)
&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
{
/* xgettext:c-format */
- as_bad (_("instruction '%s' cannot be executed in parallel."), str);
+ as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
return;
}
@@ -1032,10 +979,10 @@ assemble_two_insns (str, str2, parallel_p)
*str2 = save_str2;
/* Save the original string pointer. */
- str3 = str;
+ str3 = str1;
/* Advanced past the parsed string. */
- str = str2 + 2;
+ str1 = str2 + 2;
/* Remember the entire string in case it is needed for error
messages. */
@@ -1043,7 +990,7 @@ assemble_two_insns (str, str2, parallel_p)
/* Convert the opcode to lower case. */
{
- char *s2 = str;
+ char *s2 = str1;
while (ISSPACE (*s2++))
continue;
@@ -1085,7 +1032,7 @@ assemble_two_insns (str, str2, parallel_p)
/* Parse the second instruction. */
if (! (second.insn = m32r_cgen_assemble_insn
- (gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg)))
+ (gas_cgen_cpu_desc, str1, & second.fields, second.buffer, & errmsg)))
{
as_bad (errmsg);
return;
@@ -1095,7 +1042,7 @@ assemble_two_insns (str, str2, parallel_p)
if (CGEN_FIELDS_BITSIZE (&second.fields) != 16)
{
/* xgettext:c-format */
- as_bad (_("not a 16 bit instruction '%s'"), str);
+ as_bad (_("not a 16 bit instruction '%s'"), str1);
return;
}
#ifdef E_M32R2_ARCH
@@ -1107,7 +1054,7 @@ assemble_two_insns (str, str2, parallel_p)
& (1 << MACH_M32RX)))))
{
/* xgettext:c-format */
- as_bad (_("instruction '%s' is for the M32R2 only"), str);
+ as_bad (_("instruction '%s' is for the M32R2 only"), str1);
return;
}
else if ((! enable_special
@@ -1120,14 +1067,14 @@ assemble_two_insns (str, str2, parallel_p)
#endif
{
/* xgettext:c-format */
- as_bad (_("unknown instruction '%s'"), str);
+ as_bad (_("unknown instruction '%s'"), str1);
return;
}
else if (! enable_m32rx
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
{
/* xgettext:c-format */
- as_bad (_("instruction '%s' is for the M32RX only"), str);
+ as_bad (_("instruction '%s' is for the M32RX only"), str1);
return;
}
@@ -1136,7 +1083,7 @@ assemble_two_insns (str, str2, parallel_p)
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
{
/* xgettext:c-format */
- as_bad (_("instruction '%s' cannot be executed in parallel."), str);
+ as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
return;
}
@@ -1246,8 +1193,7 @@ assemble_two_insns (str, str2, parallel_p)
}
void
-md_assemble (str)
- char *str;
+md_assemble (char *str)
{
m32r_insn insn;
char *errmsg;
@@ -1494,8 +1440,7 @@ md_assemble (str)
We just ignore it. */
void
-md_operand (expressionP)
- expressionS *expressionP;
+md_operand (expressionS *expressionP)
{
if (*input_line_pointer == '#')
{
@@ -1505,17 +1450,15 @@ md_operand (expressionP)
}
valueT
-md_section_align (segment, size)
- segT segment;
- valueT size;
+md_section_align (segT segment, valueT size)
{
int align = bfd_get_section_alignment (stdoutput, segment);
+
return ((size + (1 << align) - 1) & (-1 << align));
}
symbolS *
-md_undefined_symbol (name)
- char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
{
return 0;
}
@@ -1528,14 +1471,13 @@ md_undefined_symbol (name)
correctly link the object file. */
static void
-m32r_scomm (ignore)
- int ignore ATTRIBUTE_UNUSED;
+m32r_scomm (int ignore ATTRIBUTE_UNUSED)
{
- register char *name;
- register char c;
- register char *p;
+ char *name;
+ char c;
+ char *p;
offsetT size;
- register symbolS *symbolP;
+ symbolS *symbolP;
offsetT align;
int align2;
@@ -1652,6 +1594,21 @@ m32r_scomm (ignore)
demand_empty_rest_of_line ();
}
+
+/* The target specific pseudo-ops which we support. */
+const pseudo_typeS md_pseudo_table[] =
+{
+ { "word", cons, 4 },
+ { "fillinsn", fill_insn, 0 },
+ { "scomm", m32r_scomm, 0 },
+ { "debugsym", debug_sym, 0 },
+ { "m32r", allow_m32rx, 0 },
+ { "m32rx", allow_m32rx, 1 },
+ { "m32r2", allow_m32rx, 2 },
+ { "little", little, 1 },
+ { "big", little, 0 },
+ { NULL, NULL, 0 }
+};
/* Interface to relax_segment. */
@@ -1684,10 +1641,7 @@ const relax_typeS md_relax_table[] =
};
long
-m32r_relax_frag (segment, fragP, stretch)
- segT segment;
- fragS *fragP;
- long stretch;
+m32r_relax_frag (segT segment, fragS *fragP, long stretch)
{
/* Address of branch insn. */
long address = fragP->fr_address + fragP->fr_fix - 2;
@@ -1737,16 +1691,13 @@ m32r_relax_frag (segment, fragP, stretch)
with a 0 value. */
int
-md_estimate_size_before_relax (fragP, segment)
- fragS *fragP;
- segT segment;
+md_estimate_size_before_relax (fragS *fragP, segT segment)
{
/* The only thing we have to handle here are symbols outside of the
current segment. They may be undefined or in a different segment in
which case linker scripts may place them anywhere.
However, we can't finish the fragment here and emit the reloc as insn
alignment requirements may move the insn about. */
-
if (S_GET_SEGMENT (fragP->fr_symbol) != segment
|| S_IS_EXTERNAL (fragP->fr_symbol)
|| S_IS_WEAK (fragP->fr_symbol))
@@ -1791,10 +1742,9 @@ md_estimate_size_before_relax (fragP, segment)
fragP->fr_subtype is the subtype of what the address relaxed to. */
void
-md_convert_frag (abfd, sec, fragP)
- bfd *abfd ATTRIBUTE_UNUSED;
- segT sec;
- fragS *fragP;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+ segT sec,
+ fragS *fragP)
{
char *opcode;
char *displacement;
@@ -1890,9 +1840,7 @@ md_convert_frag (abfd, sec, fragP)
given a PC relative reloc. */
long
-md_pcrel_from_section (fixP, sec)
- fixS *fixP;
- segT sec;
+md_pcrel_from_section (fixS *fixP, segT sec)
{
if (fixP->fx_addsy != (symbolS *) NULL
&& (! S_IS_DEFINED (fixP->fx_addsy)
@@ -1919,10 +1867,9 @@ md_pcrel_from_section (fixP, sec)
*FIXP may be modified if desired. */
bfd_reloc_code_real_type
-md_cgen_lookup_reloc (insn, operand, fixP)
- const CGEN_INSN *insn ATTRIBUTE_UNUSED;
- const CGEN_OPERAND *operand;
- fixS *fixP;
+md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
+ const CGEN_OPERAND *operand,
+ fixS *fixP)
{
switch (operand->type)
{
@@ -1946,21 +1893,17 @@ md_cgen_lookup_reloc (insn, operand, fixP)
/* Record a HI16 reloc for later matching with its LO16 cousin. */
-static void m32r_record_hi16 PARAMS ((int, fixS *, segT));
-
static void
-m32r_record_hi16 (reloc_type, fixP, seg)
- int reloc_type;
- fixS *fixP;
- segT seg ATTRIBUTE_UNUSED;
+m32r_record_hi16 (int reloc_type,
+ fixS *fixP,
+ segT seg ATTRIBUTE_UNUSED)
{
struct m32r_hi_fixup *hi_fixup;
assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
|| reloc_type == BFD_RELOC_M32R_HI16_ULO);
- hi_fixup = ((struct m32r_hi_fixup *)
- xmalloc (sizeof (struct m32r_hi_fixup)));
+ hi_fixup = xmalloc (sizeof (* hi_fixup));
hi_fixup->fixp = fixP;
hi_fixup->seg = now_seg;
hi_fixup->next = m32r_hi_fixup_list;
@@ -1972,14 +1915,13 @@ m32r_record_hi16 (reloc_type, fixP, seg)
We need to check for HI16 relocs and queue them up for later sorting. */
fixS *
-m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
- fragS *frag;
- int where;
- const CGEN_INSN *insn;
- int length;
- const CGEN_OPERAND *operand;
- int opinfo;
- expressionS *exp;
+m32r_cgen_record_fixup_exp (fragS *frag,
+ int where,
+ const CGEN_INSN *insn,
+ int length,
+ const CGEN_OPERAND *operand,
+ int opinfo,
+ expressionS *exp)
{
fixS *fixP;
bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
@@ -2018,6 +1960,7 @@ m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
r_type = BFD_RELOC_M32R_GOTPC_LO;
break;
+
case BFD_RELOC_M32R_GOT24:
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
r_type = BFD_RELOC_M32R_GOT16_HI_SLO;
@@ -2026,6 +1969,7 @@ m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
r_type = BFD_RELOC_M32R_GOT16_LO;
break;
+
case BFD_RELOC_M32R_GOTOFF:
if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
r_type = BFD_RELOC_M32R_GOTOFF_HI_SLO;
@@ -2034,6 +1978,7 @@ m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
r_type = BFD_RELOC_M32R_GOTOFF_LO;
break;
+
case BFD_RELOC_M32R_26_PLTREL:
as_bad (_("Invalid PIC expression."));
break;
@@ -2054,7 +1999,7 @@ m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
tc_gen_reloc. */
void
-m32r_frob_file ()
+m32r_frob_file (void)
{
struct m32r_hi_fixup *l;
@@ -2136,8 +2081,7 @@ m32r_frob_file ()
relaxing. */
int
-m32r_force_relocation (fix)
- fixS *fix;
+m32r_force_relocation (fixS *fix)
{
if (generic_force_reloc (fix))
return 1;
@@ -2151,10 +2095,7 @@ m32r_force_relocation (fix)
/* Write a value out to the object file, using the appropriate endianness. */
void
-md_number_to_chars (buf, val, n)
- char *buf;
- valueT val;
- int n;
+md_number_to_chars (char *buf, valueT val, int n)
{
if (target_big_endian)
number_to_chars_bigendian (buf, val, n);
@@ -2171,10 +2112,7 @@ md_number_to_chars (buf, val, n)
#define MAX_LITTLENUMS 6
char *
-md_atof (type, litP, sizeP)
- char type;
- char *litP;
- int *sizeP;
+md_atof (int type, char *litP, int *sizeP)
{
int i;
int prec;
@@ -2233,7 +2171,7 @@ md_atof (type, litP, sizeP)
}
void
-m32r_elf_section_change_hook ()
+m32r_elf_section_change_hook (void)
{
/* If we have reached the end of a section and we have just emitted a
16 bit insn, then emit a nop to make sure that the section ends on
@@ -2247,8 +2185,7 @@ m32r_elf_section_change_hook ()
(such as .data) instead of relative to some symbol. */
bfd_boolean
-m32r_fix_adjustable (fixP)
- fixS *fixP;
+m32r_fix_adjustable (fixS *fixP)
{
bfd_reloc_code_real_type reloc_type;
@@ -2258,6 +2195,7 @@ m32r_fix_adjustable (fixP)
int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
const CGEN_OPERAND *operand =
cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
+
reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
}
else
@@ -2310,16 +2248,14 @@ m32r_elf_final_processing (void)
format. */
arelent *
-tc_gen_reloc (section, fixP)
- asection * section;
- fixS * fixP;
+tc_gen_reloc (asection * section, fixS * fixP)
{
arelent * reloc;
bfd_reloc_code_real_type code;
- reloc = (arelent *) xmalloc (sizeof (arelent));
+ reloc = xmalloc (sizeof (* reloc));
- reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+ reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
@@ -2334,6 +2270,7 @@ printf("%s",bfd_get_reloc_code_name(code));
case BFD_RELOC_M32R_26_PCREL:
code = BFD_RELOC_M32R_26_PLTREL;
break;
+
case BFD_RELOC_M32R_24:
if (fixP->fx_addsy != NULL
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
@@ -2341,6 +2278,7 @@ printf("%s",bfd_get_reloc_code_name(code));
else
code = BFD_RELOC_M32R_GOT24;
break;
+
case BFD_RELOC_M32R_HI16_ULO:
if (fixP->fx_addsy != NULL
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
@@ -2348,6 +2286,7 @@ printf("%s",bfd_get_reloc_code_name(code));
else
code = BFD_RELOC_M32R_GOT16_HI_ULO;
break;
+
case BFD_RELOC_M32R_HI16_SLO:
if (fixP->fx_addsy != NULL
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
@@ -2355,6 +2294,7 @@ printf("%s",bfd_get_reloc_code_name(code));
else
code = BFD_RELOC_M32R_GOT16_HI_SLO;
break;
+
case BFD_RELOC_M32R_LO16:
if (fixP->fx_addsy != NULL
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
@@ -2362,6 +2302,7 @@ printf("%s",bfd_get_reloc_code_name(code));
else
code = BFD_RELOC_M32R_GOT16_LO;
break;
+
default:
break;
}
@@ -2371,10 +2312,12 @@ printf(" => %s",bfd_get_reloc_code_name(code));
}
reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
+
#ifdef DEBUG_PIC
printf(" => %s\n",reloc->howto->name);
#endif
- if (reloc->howto == (reloc_howto_type *) NULL)
+
+ if (reloc->howto == (reloc_howto_type *) NULL)
{
as_bad_where (fixP->fx_file, fixP->fx_line,
_("internal error: can't export reloc type %d (`%s')"),
generated by cgit v1.1 at 2024-12-23 09:56:26 +0000