diff options
Diffstat (limited to 'gas/config/tc-i386.c')
| -rw-r--r-- | gas/config/tc-i386.c | 30 |
1 files changed, 27 insertions, 3 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 3a98b21..2bc7616 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -556,6 +556,11 @@ static int omit_lock_prefix = 0; "lock addl $0, (%{re}sp)". */ static int avoid_fence = 0; +/* 1 if the assembler should generate relax relocations. */ + +static int generate_relax_relocations + = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; + static enum check_kind { check_none = 0, @@ -7267,9 +7272,14 @@ output_disp (fragS *insn_start_frag, offsetT insn_start_off) /* Check for "call/jmp *mem", "mov mem, %reg", "test %reg, mem" and "binop mem, %reg" where binop is one of adc, add, and, cmp, or, sbb, sub, xor - instructions. */ - if ((i.rm.mode == 2 - || (i.rm.mode == 0 && i.rm.regmem == 5)) + instructions. Always generate R_386_GOT32X for + "sym*GOT" operand in 32-bit mode. */ + if ((generate_relax_relocations + || (!object_64bit + && i.rm.mode == 0 + && i.rm.regmem == 5)) + && (i.rm.mode == 2 + || (i.rm.mode == 0 && i.rm.regmem == 5)) && ((i.operands == 1 && i.tm.base_opcode == 0xff && (i.rm.reg == 2 || i.rm.reg == 4)) @@ -9643,6 +9653,7 @@ const char *md_shortopts = "qn"; #define OPTION_MAMD64 (OPTION_MD_BASE + 22) #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) +#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25) struct option md_longopts[] = { @@ -9675,6 +9686,7 @@ struct option md_longopts[] = #endif {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, + {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, {"mamd64", no_argument, NULL, OPTION_MAMD64}, {"mintel64", no_argument, NULL, OPTION_MINTEL64}, @@ -10003,6 +10015,15 @@ md_parse_option (int c, char *arg) as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); break; + case OPTION_MRELAX_RELOCATIONS: + if (strcasecmp (arg, "yes") == 0) + generate_relax_relocations = 1; + else if (strcasecmp (arg, "no") == 0) + generate_relax_relocations = 0; + else + as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); + break; + case OPTION_MAMD64: cpu_arch_flags.bitfield.cpuamd64 = 1; cpu_arch_flags.bitfield.cpuintel64 = 0; @@ -10187,6 +10208,9 @@ md_show_usage (FILE *stream) encode lfence, mfence and sfence as\n\ lock addl $0x0, (%%{re}sp)\n")); fprintf (stream, _("\ + -mrelax-relocations=[no|yes]\n\ + generate relax relocations\n")); + fprintf (stream, _("\ -mamd64 accept only AMD64 ISA\n")); fprintf (stream, _("\ -mintel64 accept only Intel64 ISA\n")); |