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-rw-r--r--binutils/ChangeLog4
-rw-r--r--binutils/doc/binutils.texi8
2 files changed, 12 insertions, 0 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 163211f..1ecb042 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,7 @@
+2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
+
+ * doc/binutils.texi: Document new cpu=... disassembler options for ARC.
+
2017-05-30 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/21519
diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi
index 23d8685..a2a670a 100644
--- a/binutils/doc/binutils.texi
+++ b/binutils/doc/binutils.texi
@@ -2314,6 +2314,14 @@ of double precision assist instructions, @option{fpus} selects the
printing of FPU single precision FP instructions, while @option{fpud}
selects the printing of FPU souble precision FP instructions.
+@option{cpu=...} allows to enforce a particular ISA when disassembling
+instructions, overriding the @option{-m} value or whatever is in the ELF file.
+This might be useful to select ARC EM or HS ISA, because architecture is same
+for those and disassembler relies on private ELF header data to decide if code
+is for EM or HS. This option might be specified multiple times - only the
+latest value will be used. Valid values are same as for the assembler
+@option{-mcpu=...} option.
+
If the target is an ARM architecture then this switch can be used to
select which register name set is used during disassembler. Specifying
@option{-M reg-names-std} (the default) will select the register names as