5 files changed, 74 insertions, 0 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 5c9c18b..1b6a2f9 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,15 @@
+2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
+
+	* testsuite/binutils-all/arm/vdup-cond.d: New test for testing that
+	conditional VDUP instructions are disassembled correctly.
+	* testsuite/binutils-all/arm/vdup-cond.s: New file used by
+	vdup-cond.d.
+	* testsuite/binutils-all/arm/vdup-thumb.d: New test for testing
+	that VDUP instructions (which are conditional in A32) can be
+	disassembled in thumb mode.
+	* testsuite/binutils-all/arm/vdup-cond.s: New file used by
+	vdup-thumb.d.
+
 2020-04-17  Alan Modra  <amodra@gmail.com>
 
 	PR 25840
diff --git a/binutils/testsuite/binutils-all/arm/vdup-cond.d b/binutils/testsuite/binutils-all/arm/vdup-cond.d
new file mode 100644
index 0000000..f75931b
--- /dev/null
+++ b/binutils/testsuite/binutils-all/arm/vdup-cond.d
@@ -0,0 +1,27 @@
+#PROG: objcopy
+#source vdup-cond.s
+#as: -mfpu=neon
+#objdump: -d
+#skip: *-*-pe *-wince-* *-*-coff
+#name: Check if disassembler can handle conditional neon (vdup) instructions
+
+.*: +file format .*arm.*
+
+Disassembly of section \.vdups:
+
+.+ <\.vdups>:
+[^:]+:	0e800b10 	vdupeq.32	d0, r0
+[^:]+:	1e800b10 	vdupne.32	d0, r0
+[^:]+:	2e800b10 	vdupcs.32	d0, r0
+[^:]+:	3e800b10 	vdupcc.32	d0, r0
+[^:]+:	4e800b10 	vdupmi.32	d0, r0
+[^:]+:	5e800b10 	vduppl.32	d0, r0
+[^:]+:	6e800b10 	vdupvs.32	d0, r0
+[^:]+:	7e800b10 	vdupvc.32	d0, r0
+[^:]+:	8e800b10 	vduphi.32	d0, r0
+[^:]+:	9e800b10 	vdupls.32	d0, r0
+[^:]+:	ae800b10 	vdupge.32	d0, r0
+[^:]+:	be800b10 	vduplt.32	d0, r0
+[^:]+:	ce800b10 	vdupgt.32	d0, r0
+[^:]+:	de800b10 	vduple.32	d0, r0
+[^:]+:	ee800b10 	vdup.32	d0, r0
diff --git a/binutils/testsuite/binutils-all/arm/vdup-cond.s b/binutils/testsuite/binutils-all/arm/vdup-cond.s
new file mode 100644
index 0000000..cc544ef
--- /dev/null
+++ b/binutils/testsuite/binutils-all/arm/vdup-cond.s
@@ -0,0 +1,18 @@
+.text
+.arm
+.section .vdups, "ax"
+vdupeq.32  d0, r0
+vdupne.32  d0, r0
+vdupcs.32  d0, r0
+vdupcc.32  d0, r0
+vdupmi.32  d0, r0
+vduppl.32  d0, r0
+vdupvs.32  d0, r0
+vdupvc.32  d0, r0
+vduphi.32  d0, r0
+vdupls.32  d0, r0
+vdupge.32  d0, r0
+vduplt.32  d0, r0
+vdupgt.32  d0, r0
+vduple.32  d0, r0
+vdup.32    d0, r0
diff --git a/binutils/testsuite/binutils-all/arm/vdup-thumb.d b/binutils/testsuite/binutils-all/arm/vdup-thumb.d
new file mode 100644
index 0000000..30e8034
--- /dev/null
+++ b/binutils/testsuite/binutils-all/arm/vdup-thumb.d
@@ -0,0 +1,13 @@
+#PROG: objcopy
+#source vdup-cond.s
+#as: -mfpu=neon
+#objdump: -d
+#skip: *-*-pe *-wince-* *-*-coff
+#name: Check if disassembler can handle vdup instructions in thumb
+
+.*: +file format .*arm.*
+
+Disassembly of section \.vdups:
+
+.+ <\.vdups>:
+[^:]+:	ee80 0b10 	vdup.32	d0, r0
diff --git a/binutils/testsuite/binutils-all/arm/vdup-thumb.s b/binutils/testsuite/binutils-all/arm/vdup-thumb.s
new file mode 100644
index 0000000..d98b6a4
--- /dev/null
+++ b/binutils/testsuite/binutils-all/arm/vdup-thumb.s
@@ -0,0 +1,4 @@
+.text
+.thumb
+.section .vdups, "ax"
+vdup.32    d0, r0