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Diffstat (limited to 'binutils/doc/binutils.texi')
| -rw-r--r-- | binutils/doc/binutils.texi | 34 |
1 files changed, 28 insertions, 6 deletions
diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi index ffa7dfd..da4ed52 100644 --- a/binutils/doc/binutils.texi +++ b/binutils/doc/binutils.texi @@ -2369,12 +2369,34 @@ When in AT&T mode, instructs the disassembler to print a mnemonic suffix even when the suffix could be inferred by the operands. @end table -For PowerPC, @option{booke} controls the disassembly of BookE -instructions. @option{32} and @option{64} select PowerPC and -PowerPC64 disassembly, respectively. @option{e300} selects -disassembly for the e300 family. @option{440} selects disassembly for -the PowerPC 440. @option{ppcps} selects disassembly for the paired -single instructions of the PPC750CL. +For PowerPC, the @option{-M} argument @option{raw} selects +disasssembly of hardware insns rather than aliases. For example, you +will see @code{rlwinm} rather than @code{clrlwi}, and @code{addi} +rather than @code{li}. All of the @option{-m} arguments for +@command{gas} that select a CPU are supported. These are: +@option{403}, @option{405}, @option{440}, @option{464}, @option{476}, +@option{601}, @option{603}, @option{604}, @option{620}, @option{7400}, +@option{7410}, @option{7450}, @option{7455}, @option{750cl}, +@option{821}, @option{850}, @option{860}, @option{a2}, @option{booke}, +@option{booke32}, @option{cell}, @option{com}, @option{e200z4}, +@option{e300}, @option{e500}, @option{e500mc}, @option{e500mc64}, +@option{e500x2}, @option{e5500}, @option{e6500}, @option{efs}, +@option{power4}, @option{power5}, @option{power6}, @option{power7}, +@option{power8}, @option{power9}, @option{ppc}, @option{ppc32}, +@option{ppc64}, @option{ppc64bridge}, @option{ppcps}, @option{pwr}, +@option{pwr2}, @option{pwr4}, @option{pwr5}, @option{pwr5x}, +@option{pwr6}, @option{pwr7}, @option{pwr8}, @option{pwr9}, +@option{pwrx}, @option{titan}, and @option{vle}. +@option{32} and @option{64} modify the default or a prior CPU +selection, disabling and enabling 64-bit insns respectively. In +addition, @option{altivec}, @option{any}, @option{htm}, @option{vsx}, +and @option{spe} add capabilities to a previous @emph{or later} CPU +selection. @option{any} will disassemble any opcode known to +binutils, but in cases where an opcode has two different meanings or +different arguments, you may not see the disassembly you expect. +If you disassemble without giving a CPU selection, a default will be +chosen from information gleaned by BFD from the object files headers, +but the result again may not be as you expect. For MIPS, this option controls the printing of instruction mnemonic names and register names in disassembled instructions. Multiple |