diff options
Diffstat (limited to 'bfd')
| -rw-r--r-- | bfd/ChangeLog | 79 | ||||
| -rw-r--r-- | bfd/acinclude.m4 | 10 | ||||
| -rw-r--r-- | bfd/bfd-in2.h | 4 | ||||
| -rw-r--r-- | bfd/coff-h8300.c | 125 | ||||
| -rw-r--r-- | bfd/elf32-arm.h | 11 | ||||
| -rw-r--r-- | bfd/elf32-frv.c | 2 | ||||
| -rw-r--r-- | bfd/elf32-h8300.c | 95 | ||||
| -rw-r--r-- | bfd/elf64-mips.c | 8 | ||||
| -rw-r--r-- | bfd/elf64-ppc.c | 18 | ||||
| -rw-r--r-- | bfd/elfxx-ia64.c | 96 | ||||
| -rw-r--r-- | bfd/libbfd.h | 1 | ||||
| -rw-r--r-- | bfd/opncls.c | 22 | ||||
| -rw-r--r-- | bfd/peXXigen.c | 18 | ||||
| -rw-r--r-- | bfd/reloc.c | 7 | ||||
| -rw-r--r-- | bfd/version.h | 2 |
15 files changed, 397 insertions, 101 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 811fb8f..72a2e2f 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,11 +1,84 @@ +2004-01-30 H.J. Lu <hongjiu.lu@intel.com> + + * elfxx-ia64.c (elfNN_ia64_relax_brl): New function. + (elfNN_ia64_relax_section): Optimize brl to br during the relax + finalize pass. + +2004-01-30 Alexandre Oliva <aoliva@redhat.com> + + * elf32-frv.c (elf32_frv_always_size_sections): Initialize pointer + to bfd_link_hash_entry passed by reference to + _bfd_generic_link_add_one_symbol. + +2004-01-25 H.J. Lu <hongjiu.lu@intel.com> + + * elfxx-ia64.c (elfNN_ia64_relocate_section): Disallow imm + relocations against dynamic symbols. + +2004-01-23 Daniel Jacobowitz <drow@mvista.com> + + * elf32-arm.h (elf32_arm_check_relocs): Revert part of 2004-01-13 + change. + +2004-01-21 Tom Rix <tcrix@worldnet.att.net> + + * reloc.c: New 5 bit reloc, BFD_RELOC_M68HC12_5B, for m68hc12 movb/movw. + * bfd-in2.h, libbfd.h: Rebuilt. + +2004-01-20 Danny Smith <dannysmith@users.sourceforge.net> + + * peXXigen.c (_bfd_XXi_swap_scnhdr_out): Don't remove + IMAGE_SCN_MEM_WRITE flag from .text section if WP_TEXT + flag has been cleared. + +2004-01-19 Kazu Hirata <kazu@cs.umass.edu> + + * coff-h8300.c: Add and adjust comments about relaxation. + * elf32-h8300.c: Likewise. + +2004-01-16 Kazu Hirata <kazu@cs.umass.edu> + + * coff-h8300.c: Fix comment typos. + * elf32-h8300.c: Likewise. + +2004-01-16 Kazu Hirata <kazu@cs.umass.edu> + + * coff-h8300.c: Add comments about relaxation. + * elf32-h8300.c: Likewise. + +2004-01-14 Maciej W. Rozycki <macro@ds2.pg.gda.pl> + + * acinclude.m4: Quote names of macros to be defined by AC_DEFUN + throughout. + * aclocal.m4: Regenerate. + * configure: Regenerate. + +2004-01-13 Ian Lance Taylor <ian@wasabisystems.com> + + * elf64-mips.c (mips_elf64_slurp_one_reloc_table): Call + mips_elf64_rtype_to_howto instead of using howto_table. + +2004-01-13 Daniel Jacobowitz <drow@mvista.com> + + * elf32-arm.h (elf32_arm_final_link_relocate): Check that we created + the .plt section. + (elf32_arm_check_relocs): Don't increment the PLT refcount for + relocs which would not use the PLT. + +2004-01-13 Alan Modra <amodra@bigpond.net.au> + + * elf64-ppc.c (ppc64_elf_check_relocs): Ignore !SEC_ALLOC relocs. + (ppc64_elf_gc_sweep_hook): Likewise. + (ppc64_elf_size_dynamic_sections): Test for .plt directly. + 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> Adds linker relaxation support for bit manipulation insns like - band, bclr, biand, bild, bior, bist, bixor, bld, bnot, bor, bset, + band, bclr, biand, bild, bior, bist, bixor, bld, bnot, bor, bset, bst, btst, bxor. - * elf32-h8300.c : Opcode for bit manipulation insn is checked in + * elf32-h8300.c: Opcode for bit manipulation insn is checked in elf32_h8_relax_section function while relxation for aa:16 and aa:32. - * coff-h8300.c : Opcode for bit manipulation insn is checked in + * coff-h8300.c: Opcode for bit manipulation insn is checked in h8300_reloc16_extra_cases function while relxation for aa:16 and aa:32. 2004-01-12 Alan Modra <amodra@bigpond.net.au> diff --git a/bfd/acinclude.m4 b/bfd/acinclude.m4 index b1bd1be..63b4bf9 100644 --- a/bfd/acinclude.m4 +++ b/bfd/acinclude.m4 @@ -1,7 +1,7 @@ sinclude(../config/accross.m4) dnl See whether we need to use fopen-bin.h rather than fopen-same.h. -AC_DEFUN(BFD_BINARY_FOPEN, +AC_DEFUN([BFD_BINARY_FOPEN], [AC_REQUIRE([AC_CANONICAL_SYSTEM]) case "${host}" in changequote(,)dnl @@ -11,7 +11,7 @@ changequote([,])dnl esac])dnl dnl Get a default for CC_FOR_BUILD to put into Makefile. -AC_DEFUN(BFD_CC_FOR_BUILD, +AC_DEFUN([BFD_CC_FOR_BUILD], [# Put a plausible default for CC_FOR_BUILD in Makefile. if test -z "$CC_FOR_BUILD"; then if test "x$cross_compiling" = "xno"; then @@ -44,7 +44,7 @@ fi AC_SUBST(EXEEXT_FOR_BUILD)])dnl dnl See whether we need a declaration for a function. -AC_DEFUN(BFD_NEED_DECLARATION, +AC_DEFUN([BFD_NEED_DECLARATION], [AC_MSG_CHECKING([whether $1 must be declared]) AC_CACHE_VAL(bfd_cv_decl_needed_$1, [AC_TRY_COMPILE([ @@ -73,7 +73,7 @@ fi dnl Check for existence of a type $1 in sys/procfs.h -AC_DEFUN(BFD_HAVE_SYS_PROCFS_TYPE, +AC_DEFUN([BFD_HAVE_SYS_PROCFS_TYPE], [AC_MSG_CHECKING([for $1 in sys/procfs.h]) AC_CACHE_VAL(bfd_cv_have_sys_procfs_type_$1, [AC_TRY_COMPILE([ @@ -93,7 +93,7 @@ AC_DEFUN(BFD_HAVE_SYS_PROCFS_TYPE, dnl Check for existence of member $2 in type $1 in sys/procfs.h -AC_DEFUN(BFD_HAVE_SYS_PROCFS_TYPE_MEMBER, +AC_DEFUN([BFD_HAVE_SYS_PROCFS_TYPE_MEMBER], [AC_MSG_CHECKING([for $1.$2 in sys/procfs.h]) AC_CACHE_VAL(bfd_cv_have_sys_procfs_type_member_$1_$2, [AC_TRY_COMPILE([ diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 4cc59e0..f66c29c 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -3377,6 +3377,10 @@ value and a 8-bit page number. The symbol address is transformed to follow the 16K memory bank of 68HC12 (seen as mapped in the window). */ BFD_RELOC_M68HC11_24, +/* Motorola 68HC12 reloc. +This is the 5 bits of a value. */ + BFD_RELOC_M68HC12_5B, + /* These relocs are only used within the CRIS assembler. They are not (at present) written to any object files. */ BFD_RELOC_CRIS_BDISP8, diff --git a/bfd/coff-h8300.c b/bfd/coff-h8300.c index dc35ea9..bd798a6 100644 --- a/bfd/coff-h8300.c +++ b/bfd/coff-h8300.c @@ -265,8 +265,8 @@ static reloc_howto_type howto_table[] = { the function vector's entry in the jsr instruction. */ HOWTO (R_MEM_INDIRECT, 0, 0, 8, FALSE, 0, complain_overflow_bitfield, special, "8/indirect", FALSE, 0x000000ff, 0x000000ff, FALSE), - /* Internal reloc for relaxing. This is created when a 16bit pc-relative - branch is turned into an 8bit pc-relative branch. */ + /* Internal reloc for relaxing. This is created when a 16-bit pc-relative + branch is turned into an 8-bit pc-relative branch. */ HOWTO (R_PCRWORD_B, 0, 0, 8, TRUE, 0, complain_overflow_bitfield, special, "relaxed bCC:16", FALSE, 0x000000ff, 0x000000ff, FALSE), HOWTO (R_MOVL1, 0, 2, 32, FALSE, 0, complain_overflow_bitfield,special, "32/24 relaxable move", FALSE, 0xffffffff, 0xffffffff, FALSE), @@ -458,8 +458,8 @@ h8300_reloc16_estimate (bfd *abfd, asection *input_section, arelent *reloc, /* Only examine the relocs which might be relaxable. */ switch (reloc->howto->type) { - /* This is the 16/24 bit absolute branch which could become an 8 bit - pc-relative branch. */ + /* This is the 16-/24-bit absolute branch which could become an + 8-bit pc-relative branch. */ case R_JMP1: case R_JMPL1: /* Get the address of the target of this branch. */ @@ -547,7 +547,7 @@ h8300_reloc16_estimate (bfd *abfd, asection *input_section, arelent *reloc, } break; - /* This is the 16 bit pc-relative branch which could become an 8 bit + /* This is the 16-bit pc-relative branch which could become an 8-bit pc-relative branch. */ case R_PCRWORD: /* Get the address of the target of this branch, add one to the value @@ -575,8 +575,8 @@ h8300_reloc16_estimate (bfd *abfd, asection *input_section, arelent *reloc, } break; - /* This is a 16 bit absolute address in a mov.b insn, which can - become an 8 bit absolute address if it's in the right range. */ + /* This is a 16-bit absolute address in a mov.b insn, which can + become an 8-bit absolute address if it's in the right range. */ case R_MOV16B1: /* Get the address of the data referenced by this mov.b insn. */ value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); @@ -595,9 +595,9 @@ h8300_reloc16_estimate (bfd *abfd, asection *input_section, arelent *reloc, } break; - /* Similarly for a 24 bit absolute address in a mov.b. Note that - if we can't relax this into an 8 bit absolute, we'll fall through - and try to relax it into a 16bit absolute. */ + /* Similarly for a 24-bit absolute address in a mov.b. Note that + if we can't relax this into an 8-bit absolute, we'll fall through + and try to relax it into a 16-bit absolute. */ case R_MOV24B1: /* Get the address of the data referenced by this mov.b insn. */ value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); @@ -616,11 +616,11 @@ h8300_reloc16_estimate (bfd *abfd, asection *input_section, arelent *reloc, break; } - /* FALLTHROUGH and try to turn the 32/24 bit reloc into a 16 bit + /* FALLTHROUGH and try to turn the 24-/32-bit reloc into a 16-bit reloc. */ - /* This is a 24/32 bit absolute address in a mov insn, which can - become an 16 bit absolute address if it's in the right range. */ + /* This is a 24-/32-bit absolute address in a mov insn, which can + become an 16-bit absolute address if it's in the right range. */ case R_MOVL1: /* Get the address of the data referenced by this mov insn. */ value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); @@ -670,7 +670,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, switch (reloc->howto->type) { - /* Generic 8bit pc-relative relocation. */ + /* Generic 8-bit pc-relative relocation. */ case R_PCRBYTE: /* Get the address of the target of this branch. */ value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); @@ -700,7 +700,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, /* All done. */ break; - /* Generic 16bit pc-relative relocation. */ + /* Generic 16-bit pc-relative relocation. */ case R_PCRWORD: /* Get the address of the target of this branch. */ value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); @@ -731,7 +731,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, /* All done. */ break; - /* Generic 8bit absolute relocation. */ + /* Generic 8-bit absolute relocation. */ case R_RELBYTE: /* Get the address of the object referenced by this insn. */ value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); @@ -743,7 +743,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, /* All done. */ break; - /* Various simple 16bit absolute relocations. */ + /* Various simple 16-bit absolute relocations. */ case R_MOV16B1: case R_JMP1: case R_RELWORD: @@ -753,7 +753,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, src_address += 2; break; - /* Various simple 24/32bit absolute relocations. */ + /* Various simple 24-/32-bit absolute relocations. */ case R_MOV24B1: case R_MOVL1: case R_RELLONG: @@ -764,7 +764,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, src_address += 4; break; - /* Another 24/32bit absolute relocation. */ + /* Another 24-/32-bit absolute relocation. */ case R_JMPL1: /* Get the address of the target of this branch. */ value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); @@ -776,8 +776,15 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, src_address += 4; break; - /* A 16bit absolute relocation that was formerly a 24/32bit - absolute relocation. */ + /* This is a 24-/32-bit absolute address in one of the following + instructions: + + "band", "bclr", "biand", "bild", "bior", "bist", "bixor", + "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and + "mov.[bwl]" + + We may relax this into an 16-bit absolute address if it's in + the right range. */ case R_MOVL2: value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); value = bfd_h8300_pad_address (abfd, value); @@ -785,11 +792,12 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, /* Sanity check. */ if (value <= 0x7fff || value >= 0xffff8000u) { - /* Insert the 16bit value into the proper location. */ + /* Insert the 16-bit value into the proper location. */ bfd_put_16 (abfd, value, data + dst_address); - /* Fix the opcode. For all the move insns, we simply - need to turn off bit 0x20 in the previous byte. */ + /* Fix the opcode. For all the instructions that belong to + this relaxation, we simply need to turn off bit 0x20 in + the previous byte. */ data[dst_address - 1] &= ~0x20; dst_address += 2; src_address += 4; @@ -804,7 +812,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, } break; - /* A 16bit absolute branch that is now an 8-bit pc-relative branch. */ + /* A 16-bit absolute branch that is now an 8-bit pc-relative branch. */ case R_JMP2: /* Get the address of the target of this branch. */ value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); @@ -834,7 +842,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, bfd_put_8 (abfd, 0x55, data + dst_address - 1); break; case 0x5a: - /* jmp ->bra */ + /* jmp -> bra */ bfd_put_8 (abfd, 0x40, data + dst_address - 1); break; @@ -842,7 +850,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, abort (); } - /* Write out the 8bit value. */ + /* Write out the 8-bit value. */ bfd_put_8 (abfd, gap, data + dst_address); dst_address += 1; @@ -850,7 +858,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, break; - /* A 16bit pc-relative branch that is now an 8-bit pc-relative branch. */ + /* A 16-bit pc-relative branch that is now an 8-bit pc-relative branch. */ case R_PCRWORD_B: /* Get the address of the target of this branch. */ value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); @@ -877,12 +885,15 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, { case 0x58: /* bCC:16 -> bCC:8 */ - /* Get the condition code from the original insn. */ + /* Get the second byte of the original insn, which contains + the condition code. */ tmp = data[dst_address - 1]; + + /* Compute the fisrt byte of the relaxed instruction. The + original sequence 0x58 0xX0 is relaxed to 0x4X, where X + represents the condition code. */ tmp &= 0xf0; tmp >>= 4; - - /* Now or in the high nibble of the opcode. */ tmp |= 0x40; /* Write it. */ @@ -901,13 +912,13 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, /* Output the target. */ bfd_put_8 (abfd, gap, data + dst_address - 1); - /* We don't advance dst_address -- the 8bit reloc is applied at + /* We don't advance dst_address -- the 8-bit reloc is applied at dst_address - 1, so the next insn should begin at dst_address. */ src_address += 2; break; - /* Similarly for a 24bit absolute that is now 8 bits. */ + /* Similarly for a 24-bit absolute that is now 8 bits. */ case R_JMPL2: /* Get the address of the target of this branch. */ value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); @@ -940,15 +951,26 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, break; - /* A 16bit absolute mov.b that is now an 8bit absolute mov.b. */ + /* This is a 16-bit absolute address in one of the following + instructions: + + "band", "bclr", "biand", "bild", "bior", "bist", "bixor", + "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and + "mov.b" + + We may relax this into an 8-bit absolute address if it's in + the right range. */ case R_MOV16B2: value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); - /* Sanity check. */ + /* All instructions with R_H8_DIR16B2 start with 0x6a. */ if (data[dst_address - 2] != 0x6a) abort (); temp_code = data[src_address - 1]; + + /* If this is a mov.b instruction, clear the lower nibble, which + contains the source/destination register number. */ if ((temp_code & 0x10) != 0x10) temp_code &= 0xf0; @@ -956,15 +978,23 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, switch (temp_code) { case 0x00: + /* This is mov.b @aa:16,Rd. */ data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x20; break; case 0x80: + /* This is mov.b Rs,@aa:16. */ data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x30; break; case 0x18: + /* This is a bit-maniputation instruction that stores one + bit into memory, one of "bclr", "bist", "bnot", "bset", + and "bst". */ data[dst_address - 2] = 0x7f; break; case 0x10: + /* This is a bit-maniputation instruction that loads one bit + from memory, one of "band", "biand", "bild", "bior", + "bixor", "bld", "bor", "btst", and "bxor". */ data[dst_address - 2] = 0x7e; break; default: @@ -975,15 +1005,26 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, src_address += 2; break; - /* Similarly for a 24bit mov.b */ + /* This is a 24-bit absolute address in one of the following + instructions: + + "band", "bclr", "biand", "bild", "bior", "bist", "bixor", + "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and + "mov.b" + + We may relax this into an 8-bit absolute address if it's in + the right range. */ case R_MOV24B2: value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); - /* Sanity check. */ + /* All instructions with R_MOV24B2 start with 0x6a. */ if (data[dst_address - 2] != 0x6a) abort (); temp_code = data[src_address - 1]; + + /* If this is a mov.b instruction, clear the lower nibble, which + contains the source/destination register number. */ if ((temp_code & 0x30) != 0x30) temp_code &= 0xf0; @@ -991,15 +1032,23 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, switch (temp_code) { case 0x20: + /* This is mov.b @aa:24/32,Rd. */ data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x20; break; case 0xa0: + /* This is mov.b Rs,@aa:24/32. */ data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x30; break; case 0x38: + /* This is a bit-maniputation instruction that stores one + bit into memory, one of "bclr", "bist", "bnot", "bset", + and "bst". */ data[dst_address - 2] = 0x7f; break; case 0x30: + /* This is a bit-maniputation instruction that loads one bit + from memory, one of "band", "biand", "bild", "bior", + "bixor", "bld", "bor", "btst", and "bxor". */ data[dst_address - 2] = 0x7e; break; default: @@ -1046,7 +1095,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, src_address += 4; break; - /* An 8bit memory indirect instruction (jmp/jsr). + /* An 8-bit memory indirect instruction (jmp/jsr). There's several things that need to be done to handle this relocation. diff --git a/bfd/elf32-arm.h b/bfd/elf32-arm.h index a684546..7c284c1 100644 --- a/bfd/elf32-arm.h +++ b/bfd/elf32-arm.h @@ -1317,9 +1317,12 @@ elf32_arm_final_link_relocate (howto, input_bfd, output_bfd, branches in this object should go to it. */ if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32) && h != NULL + && splt != NULL && h->plt.offset != (bfd_vma) -1) { - BFD_ASSERT (splt != NULL); + /* If we've created a .plt section, and assigned a PLT entry to + this function, it should not be known to bind locally. If + it were, we would have cleared the PLT entry. */ BFD_ASSERT (!SYMBOL_CALLS_LOCAL (info, h)); value = (splt->output_section->vma @@ -2937,11 +2940,15 @@ elf32_arm_check_relocs (abfd, info, sec, relocs) h->elf_link_hash_flags |= ELF_LINK_NON_GOT_REF; /* We may need a .plt entry if the function this reloc - refers to is in a different object. */ + refers to is in a different object. We can't tell for + sure yet, because something later might force the + symbol local. */ if (ELF32_R_TYPE (rel->r_info) == R_ARM_PC24 || ELF32_R_TYPE (rel->r_info) == R_ARM_PLT32) h->elf_link_hash_flags |= ELF_LINK_HASH_NEEDS_PLT; + /* If we create a PLT entry, this relocation will reference + it, even if it's an ABS32 relocation. */ h->plt.refcount += 1; } diff --git a/bfd/elf32-frv.c b/bfd/elf32-frv.c index 016f233..488438e 100644 --- a/bfd/elf32-frv.c +++ b/bfd/elf32-frv.c @@ -3454,7 +3454,7 @@ elf32_frv_always_size_sections (bfd *output_bfd, || h->type != STT_OBJECT || !(h->elf_link_hash_flags & ELF_LINK_HASH_DEF_REGULAR)) { - struct bfd_link_hash_entry *bh; + struct bfd_link_hash_entry *bh = NULL; if (!(_bfd_generic_link_add_one_symbol (info, output_bfd, "__stacksize", diff --git a/bfd/elf32-h8300.c b/bfd/elf32-h8300.c index c803af1..1a17621 100644 --- a/bfd/elf32-h8300.c +++ b/bfd/elf32-h8300.c @@ -348,7 +348,7 @@ elf32_h8_final_link_relocate (unsigned long r_type, bfd *input_bfd, value += addend; /* HIT_DATA is the address for the first byte for the relocated - value. Subtract 1 so that we can manipulate the data in 32bit + value. Subtract 1 so that we can manipulate the data in 32-bit hunks. */ hit_data--; @@ -358,7 +358,7 @@ elf32_h8_final_link_relocate (unsigned long r_type, bfd *input_bfd, /* Retrieve the type byte for value from the section contents. */ value |= (bfd_get_32 (input_bfd, hit_data) & 0xff000000); - /* Now scribble it out in one 32bit hunk. */ + /* Now scribble it out in one 32-bit hunk. */ bfd_put_32 (input_bfd, value, hit_data); return bfd_reloc_ok; @@ -659,9 +659,16 @@ elf32_h8_merge_private_bfd_data (bfd *ibfd, bfd *obfd) bCC:16 -> bCC:8 2 bytes bsr:16 -> bsr:8 2 bytes + bset:16 -> bset:8 2 bytes + bset:24/32 -> bset:8 4 bytes + (also applicable to other bit manipulation instructions) + mov.b:16 -> mov.b:8 2 bytes mov.b:24/32 -> mov.b:8 4 bytes + bset:24/32 -> bset:16 2 bytes + (also applicable to other bit manipulation instructions) + mov.[bwl]:24/32 -> mov.[bwl]:16 2 bytes */ static bfd_boolean @@ -804,7 +811,7 @@ elf32_h8_relax_section (bfd *abfd, asection *sec, the linker is run. */ switch (ELF32_R_TYPE (irel->r_info)) { - /* Try to turn a 24 bit absolute branch/call into an 8 bit + /* Try to turn a 24-bit absolute branch/call into an 8-bit pc-relative branch/call. */ case R_H8_DIR24R8: { @@ -915,8 +922,10 @@ elf32_h8_relax_section (bfd *abfd, asection *sec, } if (code == 0x5e) + /* This is jsr. */ bfd_put_8 (abfd, 0x55, contents + irel->r_offset - 1); else if (code == 0x5a) + /* This is jmp. */ bfd_put_8 (abfd, 0x40, contents + irel->r_offset - 1); else abort (); @@ -937,7 +946,7 @@ elf32_h8_relax_section (bfd *abfd, asection *sec, break; } - /* Try to turn a 16bit pc-relative branch into a 8bit pc-relative + /* Try to turn a 16-bit pc-relative branch into a 8-bit pc-relative branch. */ case R_H8_PCREL16: { @@ -971,14 +980,21 @@ elf32_h8_relax_section (bfd *abfd, asection *sec, if (code == 0x58) { /* bCC:16 -> bCC:8 */ - /* Get the condition code from the original insn. */ + /* Get the second byte of the original insn, which + contains the condition code. */ code = bfd_get_8 (abfd, contents + irel->r_offset - 1); + + /* Compute the fisrt byte of the relaxed + instruction. The original sequence 0x58 0xX0 + is relaxed to 0x4X, where X represents the + condition code. */ code &= 0xf0; code >>= 4; code |= 0x40; bfd_put_8 (abfd, code, contents + irel->r_offset - 2); } else if (code == 0x5c) + /* This is bsr. */ bfd_put_8 (abfd, 0x55, contents + irel->r_offset - 2); else abort (); @@ -1000,8 +1016,15 @@ elf32_h8_relax_section (bfd *abfd, asection *sec, break; } - /* This is a 16 bit absolute address in a "mov.b" insn, which may - become an 8 bit absolute address if its in the right range. */ + /* This is a 16-bit absolute address in one of the following + instructions: + + "band", "bclr", "biand", "bild", "bior", "bist", "bixor", + "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and + "mov.b" + + We may relax this into an 8-bit absolute address if it's in + the right range. */ case R_H8_DIR16A8: { bfd_vma value; @@ -1021,28 +1044,41 @@ elf32_h8_relax_section (bfd *abfd, asection *sec, /* Get the opcode. */ code = bfd_get_8 (abfd, contents + irel->r_offset - 2); - /* Sanity check. */ + /* All instructions with R_H8_DIR16A8 start with + 0x6a. */ if (code != 0x6a) abort (); temp_code = code = bfd_get_8 (abfd, contents + irel->r_offset - 1); + /* If this is a mov.b instruction, clear the lower + nibble, which contains the source/destination + register number. */ if ((temp_code & 0x10) != 0x10) temp_code &= 0xf0; switch (temp_code) { case 0x00: + /* This is mov.b @aa:16,Rd. */ bfd_put_8 (abfd, (code & 0xf) | 0x20, contents + irel->r_offset - 2); break; case 0x80: + /* This is mov.b Rs,@aa:16. */ bfd_put_8 (abfd, (code & 0xf) | 0x30, contents + irel->r_offset - 2); break; case 0x18: + /* This is a bit-maniputation instruction that + stores one bit into memory, one of "bclr", + "bist", "bnot", "bset", and "bst". */ bfd_put_8 (abfd, 0x7f, contents + irel->r_offset - 2); break; case 0x10: + /* This is a bit-maniputation instruction that + loads one bit from memory, one of "band", + "biand", "bild", "bior", "bixor", "bld", "bor", + "btst", and "bxor". */ bfd_put_8 (abfd, 0x7e, contents + irel->r_offset - 2); break; default: @@ -1068,8 +1104,15 @@ elf32_h8_relax_section (bfd *abfd, asection *sec, break; } - /* This is a 24 bit absolute address in a "mov.b" insn, which may - become an 8 bit absolute address if its in the right range. */ + /* This is a 24-bit absolute address in one of the following + instructions: + + "band", "bclr", "biand", "bild", "bior", "bist", "bixor", + "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and + "mov.b" + + We may relax this into an 8-bit absolute address if it's in + the right range. */ case R_H8_DIR24A8: { bfd_vma value; @@ -1089,29 +1132,42 @@ elf32_h8_relax_section (bfd *abfd, asection *sec, /* Get the opcode. */ code = bfd_get_8 (abfd, contents + irel->r_offset - 2); - /* Sanity check. */ + /* All instructions with R_H8_DIR24A8 start with + 0x6a. */ if (code != 0x6a) abort (); temp_code = code = bfd_get_8 (abfd, contents + irel->r_offset - 1); + /* If this is a mov.b instruction, clear the lower + nibble, which contains the source/destination + register number. */ if ((temp_code & 0x30) != 0x30) temp_code &= 0xf0; switch (temp_code) { case 0x20: + /* This is mov.b @aa:24/32,Rd. */ bfd_put_8 (abfd, (code & 0xf) | 0x20, contents + irel->r_offset - 2); break; case 0xa0: + /* This is mov.b Rs,@aa:24/32. */ bfd_put_8 (abfd, (code & 0xf) | 0x30, contents + irel->r_offset - 2); break; case 0x38: + /* This is a bit-maniputation instruction that + stores one bit into memory, one of "bclr", + "bist", "bnot", "bset", and "bst". */ bfd_put_8 (abfd, 0x7f, contents + irel->r_offset - 2); break; case 0x30: + /* This is a bit-maniputation instruction that + loads one bit from memory, one of "band", + "biand", "bild", "bior", "bixor", "bld", "bor", + "btst", and "bxor". */ bfd_put_8 (abfd, 0x7e, contents + irel->r_offset - 2); break; default: @@ -1135,10 +1191,17 @@ elf32_h8_relax_section (bfd *abfd, asection *sec, } } - /* Fall through. */ + /* Fall through. */ + + /* This is a 24-/32-bit absolute address in one of the + following instructions: + + "band", "bclr", "biand", "bild", "bior", "bist", + "bixor", "bld", "bnot", "bor", "bset", "bst", "btst", + "bxor", and "mov.[bwl]" - /* This is a 24/32bit absolute address in a "mov" insn, which may - become a 16-bit absolute address if it is in the right range. */ + We may relax this into an 16-bit absolute address if it's + in the right range. */ case R_H8_DIR32A16: { bfd_vma value; @@ -1157,7 +1220,9 @@ elf32_h8_relax_section (bfd *abfd, asection *sec, /* Get the opcode. */ code = bfd_get_8 (abfd, contents + irel->r_offset - 1); - /* We just need to turn off bit 0x20. */ + /* Fix the opcode. For all the instructions that + belong to this relaxation, we simply need to turn + off bit 0x20 in the previous byte. */ code &= ~0x20; bfd_put_8 (abfd, code, contents + irel->r_offset - 1); diff --git a/bfd/elf64-mips.c b/bfd/elf64-mips.c index 71c3425..fa3b494 100644 --- a/bfd/elf64-mips.c +++ b/bfd/elf64-mips.c @@ -2015,7 +2015,7 @@ mips_elf64_slurp_one_reloc_table (bfd *abfd, asection *asect, arelent *relent; bfd_vma i; int entsize; - reloc_howto_type *howto_table; + bfd_boolean rela_p; allocated = bfd_malloc (rel_hdr->sh_size); if (allocated == NULL) @@ -2033,9 +2033,9 @@ mips_elf64_slurp_one_reloc_table (bfd *abfd, asection *asect, || entsize == sizeof (Elf64_Mips_External_Rela)); if (entsize == sizeof (Elf64_Mips_External_Rel)) - howto_table = mips_elf64_howto_table_rel; + rela_p = FALSE; else - howto_table = mips_elf64_howto_table_rela; + rela_p = TRUE; for (i = 0, relent = relents; i < reloc_count; @@ -2148,7 +2148,7 @@ mips_elf64_slurp_one_reloc_table (bfd *abfd, asection *asect, relent->addend = rela.r_addend; - relent->howto = &howto_table[(int) type]; + relent->howto = mips_elf64_rtype_to_howto (type, rela_p); ++relent; } diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c index 3ed9042..304a635 100644 --- a/bfd/elf64-ppc.c +++ b/bfd/elf64-ppc.c @@ -3590,6 +3590,15 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, if (info->relocatable) return TRUE; + /* Don't do anything special with non-loaded, non-alloced sections. + In particular, any relocs in such sections should not affect GOT + and PLT reference counting (ie. we don't allow them to create GOT + or PLT entries), there's no possibility or desire to optimize TLS + relocs, and there's not much point in propagating relocs to shared + libs that the dynamic linker won't relocate. */ + if ((sec->flags & SEC_ALLOC) == 0) + return TRUE; + htab = ppc_hash_table (info); symtab_hdr = &elf_tdata (abfd)->symtab_hdr; @@ -3947,10 +3956,6 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, if (NO_OPD_RELOCS && opd_sym_map != NULL) break; - /* Don't propagate relocs that the dynamic linker won't relocate. */ - if ((sec->flags & SEC_ALLOC) == 0) - break; - /* If we are creating a shared library, and this is a reloc against a global symbol, or a non PC relative reloc against a local symbol, then we need to copy the reloc @@ -4166,6 +4171,9 @@ ppc64_elf_gc_sweep_hook (bfd *abfd, struct bfd_link_info *info, struct got_entry **local_got_ents; const Elf_Internal_Rela *rel, *relend; + if ((sec->flags & SEC_ALLOC) == 0) + return TRUE; + elf_section_data (sec)->local_dynrel = NULL; htab = ppc_hash_table (info); @@ -6001,7 +6009,7 @@ ppc64_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, } /* .plt is in the bss section. We don't initialise it. */ - if ((s->flags & SEC_LOAD) == 0) + if (s == htab->plt) continue; /* Allocate memory for the section contents. We use bfd_zalloc diff --git a/bfd/elfxx-ia64.c b/bfd/elfxx-ia64.c index c699922..e223a10 100644 --- a/bfd/elfxx-ia64.c +++ b/bfd/elfxx-ia64.c @@ -672,6 +672,36 @@ bfd_elfNN_ia64_after_parse (int itanium) oor_branch_size = itanium ? sizeof (oor_ip) : sizeof (oor_brl); } +static void +elfNN_ia64_relax_brl (bfd *abfd, bfd_byte *contents, bfd_vma off) +{ + int template; + bfd_byte *hit_addr; + bfd_vma t0, t1, i0, i1, i2; + + hit_addr = (bfd_byte *) (contents + off); + hit_addr -= (long) hit_addr & 0x3; + t0 = bfd_get_64 (abfd, hit_addr); + t1 = bfd_get_64 (abfd, hit_addr + 8); + + /* Keep the instruction in slot 0. */ + i0 = (t0 >> 5) & 0x1ffffffffffLL; + /* Use nop.b for slot 1. */ + i1 = 0x4000000000LL; + /* For slot 2, turn brl into br by masking out bit 40. */ + i2 = (t1 >> 23) & 0x0ffffffffffLL; + + /* Turn a MLX bundle into a MBB bundle with the same stop-bit + variety. */ + template = 0x12; + if ((t0 & 0x1fLL) == 5) + template += 1; + t0 = (i1 << 46) | (i0 << 5) | template; + t1 = (i2 << 23) | (i1 >> 18); + + bfd_put_64 (abfd, t0, hit_addr); + bfd_put_64 (abfd, t1, hit_addr + 8); +} /* These functions do relaxation for IA-64 ELF. */ @@ -765,13 +795,30 @@ elfNN_ia64_relax_section (abfd, sec, link_info, again) case R_IA64_PCREL21BI: case R_IA64_PCREL21M: case R_IA64_PCREL21F: + /* In the finalize pass, all br relaxations are done. We can + skip it. */ if (!link_info->need_relax_finalize) continue; is_branch = TRUE; break; + case R_IA64_PCREL60B: + /* We can't optimize brl to br before the finalize pass since + br relaxations will increase the code size. Defer it to + the finalize pass. */ + if (link_info->need_relax_finalize) + { + sec->need_finalize_relax = 1; + continue; + } + is_branch = TRUE; + break; + case R_IA64_LTOFF22X: case R_IA64_LDXMOV: + /* We can't relax ldx/mov before the finalize pass since + br relaxations will increase the code size. Defer it to + the finalize pass. */ if (link_info->need_relax_finalize) { sec->need_finalize_relax = 1; @@ -885,6 +932,25 @@ elfNN_ia64_relax_section (abfd, sec, link_info, again) /* If the branch is in range, no need to do anything. */ if ((bfd_signed_vma) (symaddr - reladdr) >= -0x1000000 && (bfd_signed_vma) (symaddr - reladdr) <= 0x0FFFFF0) + { + /* If the 60-bit branch is in 21-bit range, optimize it. */ + if (r_type == R_IA64_PCREL60B) + { + elfNN_ia64_relax_brl (abfd, contents, roff); + + irel->r_info + = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), + R_IA64_PCREL21B); + + /* If the original relocation offset points to slot + 1, change it to slot 2. */ + if ((irel->r_offset & 3) == 1) + irel->r_offset += 1; + } + + continue; + } + else if (r_type == R_IA64_PCREL60B) continue; /* If the branch and target are in the same section, you've @@ -3951,6 +4017,24 @@ elfNN_ia64_relocate_section (output_bfd, info, input_bfd, input_section, BFD_ASSERT (srel != NULL); + switch (r_type) + { + case R_IA64_IMM14: + case R_IA64_IMM22: + case R_IA64_IMM64: + /* ??? People shouldn't be doing non-pic code in + shared libraries nor dynamic executables. */ + (*_bfd_error_handler) + (_("%s: non-pic code with imm relocation against dynamic symbol `%s'"), + bfd_archive_filename (input_bfd), + h->root.root.string); + ret_val = FALSE; + continue; + + default: + break; + } + /* If we don't need dynamic symbol lookup, find a matching RELATIVE relocation. */ dyn_r_type = r_type; @@ -3978,17 +4062,7 @@ elfNN_ia64_relocate_section (output_bfd, info, input_bfd, input_section, break; default: - /* We can't represent this without a dynamic symbol. - Adjust the relocation to be against an output - section symbol, which are always present in the - dynamic symbol table. */ - /* ??? People shouldn't be doing non-pic code in - shared libraries. Hork. */ - (*_bfd_error_handler) - (_("%s: linking non-pic code in a shared library"), - bfd_archive_filename (input_bfd)); - ret_val = FALSE; - continue; + break; } dynindx = 0; addend = value; diff --git a/bfd/libbfd.h b/bfd/libbfd.h index d6ee8f3..40e1b78 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -1430,6 +1430,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_M68HC11_LO16", "BFD_RELOC_M68HC11_PAGE", "BFD_RELOC_M68HC11_24", + "BFD_RELOC_M68HC12_5B", "BFD_RELOC_CRIS_BDISP8", "BFD_RELOC_CRIS_UNSIGNED_5", "BFD_RELOC_CRIS_SIGNED_6", diff --git a/bfd/opncls.c b/bfd/opncls.c index 96f1e14..6abd405 100644 --- a/bfd/opncls.c +++ b/bfd/opncls.c @@ -70,8 +70,7 @@ _bfd_new_bfd (void) nbfd->direction = no_direction; nbfd->iostream = NULL; nbfd->where = 0; - if (!bfd_hash_table_init_n (&nbfd->section_htab, - bfd_section_hash_newfunc, + if (!bfd_hash_table_init_n (& nbfd->section_htab, bfd_section_hash_newfunc, 251)) { free (nbfd); @@ -923,7 +922,7 @@ find_separate_debug_file (bfd *abfd, const char *debug_file_directory) for (i = strlen (dir) - 1; i >= 0; i--) if (IS_DIR_SEPARATOR (dir[i])) break; - + dir[i + 1] = '\0'; BFD_ASSERT (dir[i] == '/' || dir[0] == '\0') @@ -996,23 +995,26 @@ SYNOPSIS DESCRIPTION Takes a BFD and searches it for a .gnu_debuglink section. If this - section is found, examines the section for the name and checksum of - a '.debug' file containing auxiliary debugging - information. Searches filesystem for .debug file in some standard + section is found, it examines the section for the name and checksum + of a '.debug' file containing auxiliary debugging information. It + then searches the filesystem for this .debug file in some standard locations, including the directory tree rooted at @var{dir}, and if - found returns the full filename. If @var{dir} is NULL, will search - default path configured into libbfd at build time. + found returns the full filename. + + If @var{dir} is NULL, it will search a default path configured into + libbfd at build time. [XXX this feature is not currently + implemented]. RETURNS <<NULL>> on any errors or failure to locate the .debug file, otherwise a pointer to a heap-allocated string containing the - filename. The caller is responsible for freeing this string. + filename. The caller is responsible for freeing this string. */ char * bfd_follow_gnu_debuglink (bfd *abfd, const char *dir) { -#if 0 /* Disabled until DEBUGDIR can be defined by configure.in */ +#if 0 /* Disabled until DEBUGDIR can be defined by configure.in. */ if (dir == NULL) dir = DEBUGDIR; #endif diff --git a/bfd/peXXigen.c b/bfd/peXXigen.c index 2fe294f..559f2a2 100644 --- a/bfd/peXXigen.c +++ b/bfd/peXXigen.c @@ -1,5 +1,5 @@ /* Support for the generic parts of PE/PEI; the common executable parts. - Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 + Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Written by Cygnus Solutions. @@ -985,13 +985,21 @@ _bfd_XXi_swap_scnhdr_out (abfd, in, out) pe_required_section_flags * p; int flags = scnhdr_int->s_flags; + /* We have defaulted to adding the IMAGE_SCN_MEM_WRITE flag, but now + we know exactly what this specific section wants so we remove it + and then allow the must_have field to add it back in if necessary. + However, we don't remove IMAGE_SCN_MEM_WRITE flag from .text if the + default WP_TEXT file flag has been cleared. WP_TEXT may be cleared + by ld --enable-auto-import (if auto-import is actually needed), + by ld --omagic, or by obcopy --writable-text. */ + + if (strcmp (scnhdr_int->s_name, ".text") + || (bfd_get_file_flags (abfd) & WP_TEXT)) + flags &= ~IMAGE_SCN_MEM_WRITE; + for (p = known_sections; p->section_name; p++) if (strcmp (scnhdr_int->s_name, p->section_name) == 0) { - /* We have defaulted to adding the IMAGE_SCN_MEM_WRITE flag, but now - we know exactly what this specific section wants so we remove it - and then allow the must_have field to add it back in if necessary. */ - flags &= ~IMAGE_SCN_MEM_WRITE; flags |= p->must_have; break; } diff --git a/bfd/reloc.c b/bfd/reloc.c index d3a6534..9bffaa3 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -1,6 +1,6 @@ /* BFD support for handling relocation entries. Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003 + 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Written by Cygnus Support. @@ -3764,6 +3764,11 @@ ENUMDOC This is a 24-bit reloc that represents the address with a 16-bit value and a 8-bit page number. The symbol address is transformed to follow the 16K memory bank of 68HC12 (seen as mapped in the window). +ENUM + BFD_RELOC_M68HC12_5B +ENUMDOC + Motorola 68HC12 reloc. + This is the 5 bits of a value. ENUM BFD_RELOC_CRIS_BDISP8 diff --git a/bfd/version.h b/bfd/version.h index 0e98715..970afc6 100644 --- a/bfd/version.h +++ b/bfd/version.h @@ -1,3 +1,3 @@ -#define BFD_VERSION_DATE 20040113 +#define BFD_VERSION_DATE 20040208 #define BFD_VERSION @bfd_version@ #define BFD_VERSION_STRING @bfd_version_string@ |