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-rw-r--r--bfd/ChangeLog13
-rw-r--r--bfd/archures.c1
-rw-r--r--bfd/bfd-in2.h1
-rw-r--r--bfd/cpu-arm.c1
-rw-r--r--bfd/elf32-arm.c49
-rw-r--r--binutils/ChangeLog4
-rw-r--r--binutils/readelf.c2
-rw-r--r--gas/ChangeLog8
-rw-r--r--gas/config/tc-arm.c92
-rw-r--r--gas/testsuite/gas/arm/attr-march-armv8_1-m.main.d13
-rw-r--r--include/ChangeLog9
-rw-r--r--include/elf/arm.h3
-rw-r--r--include/opcode/arm.h6
-rw-r--r--ld/ChangeLog6
-rw-r--r--ld/testsuite/ld-arm/attr-merge-13.attr6
-rw-r--r--ld/testsuite/ld-arm/attr-merge-13a.s5
-rw-r--r--ld/testsuite/ld-arm/attr-merge-13b.s5
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/arm-dis.c1
19 files changed, 176 insertions, 53 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 506d54f..d9d1e9b 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,16 @@
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * archures.c (bfd_mach_arm_8_1M_MAIN): Define.
+ * bfd-in2.h: Regenerate.
+ * cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline.
+ * elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline
+ and update assert.
+ (using_thumb2): Likewise.
+ (using_thumb2_bl): Update assert.
+ (arch_has_arm_nop): Likewise.
+ (bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline.
+ (tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging.
+
2019-04-11 H.J. Lu <hongjiu.lu@intel.com>
* elf-linker-x86.h (elf_x86_cet_report): New.
diff --git a/bfd/archures.c b/bfd/archures.c
index 647cf0d..aaf2e11 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -341,6 +341,7 @@ DESCRIPTION
.#define bfd_mach_arm_8R 24
.#define bfd_mach_arm_8M_BASE 25
.#define bfd_mach_arm_8M_MAIN 26
+.#define bfd_mach_arm_8_1M_MAIN 27
. bfd_arch_nds32, {* Andes NDS32. *}
.#define bfd_mach_n1 1
.#define bfd_mach_n1h 2
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 33a2940..4f63fe5 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -2274,6 +2274,7 @@ enum bfd_architecture
#define bfd_mach_arm_8R 24
#define bfd_mach_arm_8M_BASE 25
#define bfd_mach_arm_8M_MAIN 26
+#define bfd_mach_arm_8_1M_MAIN 27
bfd_arch_nds32, /* Andes NDS32. */
#define bfd_mach_n1 1
#define bfd_mach_n1h 2
diff --git a/bfd/cpu-arm.c b/bfd/cpu-arm.c
index 568fdbf..5a5da93 100644
--- a/bfd/cpu-arm.c
+++ b/bfd/cpu-arm.c
@@ -248,6 +248,7 @@ static const bfd_arch_info_type arch_info_struct[] =
N (bfd_mach_arm_8R, "armv8-r", FALSE, & arch_info_struct[24]),
N (bfd_mach_arm_8M_BASE, "armv8-m.base", FALSE, & arch_info_struct[25]),
N (bfd_mach_arm_8M_MAIN, "armv8-m.main", FALSE, & arch_info_struct[26]),
+ N (bfd_mach_arm_8_1M_MAIN, "armv8.1-m.main", FALSE, & arch_info_struct[27]),
N (bfd_mach_arm_unknown, "arm_any", FALSE, NULL)
};
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 03f3a59..23bfbcb 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -3835,13 +3835,14 @@ using_thumb_only (struct elf32_arm_link_hash_table *globals)
arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
- BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
+ BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
if (arch == TAG_CPU_ARCH_V6_M
|| arch == TAG_CPU_ARCH_V6S_M
|| arch == TAG_CPU_ARCH_V7E_M
|| arch == TAG_CPU_ARCH_V8M_BASE
- || arch == TAG_CPU_ARCH_V8M_MAIN)
+ || arch == TAG_CPU_ARCH_V8M_MAIN
+ || arch == TAG_CPU_ARCH_V8_1M_MAIN)
return TRUE;
return FALSE;
@@ -3862,14 +3863,15 @@ using_thumb2 (struct elf32_arm_link_hash_table *globals)
arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
- BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
+ BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
return (arch == TAG_CPU_ARCH_V6T2
|| arch == TAG_CPU_ARCH_V7
|| arch == TAG_CPU_ARCH_V7E_M
|| arch == TAG_CPU_ARCH_V8
|| arch == TAG_CPU_ARCH_V8R
- || arch == TAG_CPU_ARCH_V8M_MAIN);
+ || arch == TAG_CPU_ARCH_V8M_MAIN
+ || arch == TAG_CPU_ARCH_V8_1M_MAIN);
}
/* Determine whether Thumb-2 BL instruction is available. */
@@ -3881,7 +3883,7 @@ using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
- BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
+ BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
/* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
return (arch == TAG_CPU_ARCH_V6T2
@@ -4101,7 +4103,7 @@ arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
- BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
+ BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
return (arch == TAG_CPU_ARCH_V6T2
|| arch == TAG_CPU_ARCH_V6K
@@ -13719,6 +13721,8 @@ bfd_arm_get_mach_from_attributes (bfd * abfd)
return bfd_mach_arm_8M_BASE;
case TAG_CPU_ARCH_V8M_MAIN:
return bfd_mach_arm_8M_MAIN;
+ case TAG_CPU_ARCH_V8_1M_MAIN:
+ return bfd_mach_arm_8_1M_MAIN;
default:
/* Force entry to be added for any new known Tag_CPU_arch value. */
@@ -14131,6 +14135,31 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
T(V8M_MAIN), /* V8-M BASELINE. */
T(V8M_MAIN) /* V8-M MAINLINE. */
};
+ const int v8_1m_mainline[] =
+ {
+ -1, /* PRE_V4. */
+ -1, /* V4. */
+ -1, /* V4T. */
+ -1, /* V5T. */
+ -1, /* V5TE. */
+ -1, /* V5TEJ. */
+ -1, /* V6. */
+ -1, /* V6KZ. */
+ -1, /* V6T2. */
+ -1, /* V6K. */
+ T(V8_1M_MAIN), /* V7. */
+ T(V8_1M_MAIN), /* V6_M. */
+ T(V8_1M_MAIN), /* V6S_M. */
+ T(V8_1M_MAIN), /* V7E_M. */
+ -1, /* V8. */
+ -1, /* V8R. */
+ T(V8_1M_MAIN), /* V8-M BASELINE. */
+ T(V8_1M_MAIN), /* V8-M MAINLINE. */
+ -1, /* Unused (18). */
+ -1, /* Unused (19). */
+ -1, /* Unused (20). */
+ T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
+ };
const int v4t_plus_v6_m[] =
{
-1, /* PRE_V4. */
@@ -14151,6 +14180,10 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
-1, /* V8R. */
T(V8M_BASE), /* V8-M BASELINE. */
T(V8M_MAIN), /* V8-M MAINLINE. */
+ -1, /* Unused (18). */
+ -1, /* Unused (19). */
+ -1, /* Unused (20). */
+ T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
};
const int *comb[] =
@@ -14165,6 +14198,10 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
v8r,
v8m_baseline,
v8m_mainline,
+ NULL,
+ NULL,
+ NULL,
+ v8_1m_mainline,
/* Pseudo-architecture. */
v4t_plus_v6_m
};
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 4b887a1..ac54754 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,7 @@
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline.
+
2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
* readelf.c (decode_x86_isa): Handle
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 701ab05..1ea4cef 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -14370,7 +14370,7 @@ typedef struct
static const char * arm_attr_tag_CPU_arch[] =
{"Pre-v4", "v4", "v4T", "v5T", "v5TE", "v5TEJ", "v6", "v6KZ", "v6T2",
"v6K", "v7", "v6-M", "v6S-M", "v7E-M", "v8", "v8-R", "v8-M.baseline",
- "v8-M.mainline"};
+ "v8-M.mainline", "", "", "", "v8.1-M.mainline"};
static const char * arm_attr_tag_ARM_ISA_use[] = {"No", "Yes"};
static const char * arm_attr_tag_THUMB_ISA_use[] =
{"No", "Thumb-1", "Thumb-2", "Yes"};
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 82fa9b2..bb30f84 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
+ Tag_CPU_arch build attribute value. Reindent.
+ (get_aeabi_cpu_arch_from_fset): Update assert.
+ (aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.
+ * testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.
+
2019-04-09 Matthew Fortune <matthew.fortune@mips.com>
* config/tc-mips.c (mips_cpu_info_table): Add i6500. Update
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 4218d05..4f96066 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -26570,6 +26570,7 @@ static const struct arm_arch_option_table arm_archs[] =
ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP,
armv8m_main),
+ ARM_ARCH_OPT ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP),
ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a),
ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a),
ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a),
@@ -27284,30 +27285,30 @@ typedef struct
stable when new architectures are added. */
static const cpu_arch_ver_table cpu_arch_ver[] =
{
- {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
- {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
- {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
- {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
- {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
- {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
- {TAG_CPU_ARCH_V4, ARM_ARCH_V4},
- {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
- {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
- {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
- {TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
- {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
- {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
- {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
- {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
- {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
- {TAG_CPU_ARCH_V6, ARM_ARCH_V6},
- {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
- {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
- {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
- {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
- {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
- {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
- {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
+ {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
+ {TAG_CPU_ARCH_V4, ARM_ARCH_V4},
+ {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
+ {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
+ {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
+ {TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
+ {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
+ {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
+ {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
+ {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
+ {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
+ {TAG_CPU_ARCH_V6, ARM_ARCH_V6},
+ {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
+ {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
+ {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
+ {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
+ {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
+ {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
+ {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
/* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
always selected build attributes to match those of ARMv6-M
@@ -27316,25 +27317,26 @@ static const cpu_arch_ver_table cpu_arch_ver[] =
would be selected when fully respecting chronology of architectures.
It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
move them before ARMv7 architectures. */
- {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
- {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
-
- {TAG_CPU_ARCH_V7, ARM_ARCH_V7},
- {TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
- {TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
- {TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
- {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
- {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
- {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
- {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
- {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
- {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
- {-1, ARM_ARCH_NONE}
+ {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
+ {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
+
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7},
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
+ {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
+ {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
+ {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
+ {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
+ {TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN},
+ {-1, ARM_ARCH_NONE}
};
/* Set an attribute if it has not already been set by the user. */
@@ -27417,7 +27419,7 @@ get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
{
/* Force revisiting of decision for each new architecture. */
- gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8M_MAIN);
+ gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8_1M_MAIN);
*profile = 'A';
return TAG_CPU_ARCH_V8;
}
@@ -27688,7 +27690,7 @@ aeabi_set_public_attributes (void)
by the base architecture.
For new architectures we will have to check these tests. */
- gas_assert (arch <= TAG_CPU_ARCH_V8M_MAIN);
+ gas_assert (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
|| ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
aeabi_set_attribute_int (Tag_DIV_use, 0);
diff --git a/gas/testsuite/gas/arm/attr-march-armv8_1-m.main.d b/gas/testsuite/gas/arm/attr-march-armv8_1-m.main.d
new file mode 100644
index 0000000..acae2e3
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-march-armv8_1-m.main.d
@@ -0,0 +1,13 @@
+# name: attributes for -march=armv8.1-m.main
+# source: blank.s
+# as: -march=armv8.1-m.main
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "8.1-M.MAIN"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
diff --git a/include/ChangeLog b/include/ChangeLog
index b0c92cf..d33d0b0 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,12 @@
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
+ (MAX_TAG_CPU_ARCH): Set value to above macro.
+ * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
+ (ARM_AEXT_V8_1M_MAIN): Likewise.
+ (ARM_AEXT2_V8_1M_MAIN): Likewise.
+ (ARM_ARCH_V8_1M_MAIN): Likewise.
+
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
diff --git a/include/elf/arm.h b/include/elf/arm.h
index 13f2000..daf1d94 100644
--- a/include/elf/arm.h
+++ b/include/elf/arm.h
@@ -111,7 +111,8 @@
#define TAG_CPU_ARCH_V8R 15
#define TAG_CPU_ARCH_V8M_BASE 16
#define TAG_CPU_ARCH_V8M_MAIN 17
-#define MAX_TAG_CPU_ARCH TAG_CPU_ARCH_V8M_MAIN
+#define TAG_CPU_ARCH_V8_1M_MAIN 21
+#define MAX_TAG_CPU_ARCH TAG_CPU_ARCH_V8_1M_MAIN
/* Pseudo-architecture to allow objects to be compatible with the subset of
armv4t and armv6-m. This value should never be stored in object files. */
#define TAG_CPU_ARCH_V4T_PLUS_V6_M (MAX_TAG_CPU_ARCH + 1)
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 4f5c89f..73fb2e3 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -72,6 +72,7 @@
#define ARM_EXT2_V8_5A 0x00001000 /* ARM V8.5A. */
#define ARM_EXT2_SB 0x00002000 /* Speculation Barrier instruction. */
#define ARM_EXT2_PREDRES 0x00004000 /* Prediction Restriction insns. */
+#define ARM_EXT2_V8_1M_MAIN 0x00008000 /* ARMv8.1-M Mainline. */
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
@@ -175,6 +176,9 @@
#define ARM_AEXT2_V8M_MAIN_DSP ARM_AEXT2_V8M_MAIN
#define ARM_AEXT_V8R ARM_AEXT_V8A
#define ARM_AEXT2_V8R ARM_AEXT2_V8AR
+#define ARM_AEXT_V8_1M_MAIN ARM_AEXT_V8M_MAIN
+#define ARM_AEXT2_V8_1M_MAIN (ARM_AEXT2_V8M_MAIN | ARM_EXT2_V8_1M_MAIN \
+ | ARM_EXT2_FP16_INST)
/* Processors with specific extensions in the co-processor space. */
#define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
@@ -353,6 +357,8 @@
#define ARM_ARCH_V8M_MAIN_DSP ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN_DSP, \
ARM_AEXT2_V8M_MAIN_DSP)
#define ARM_ARCH_V8R ARM_FEATURE_CORE (ARM_AEXT_V8R, ARM_AEXT2_V8R)
+#define ARM_ARCH_V8_1M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8_1M_MAIN, \
+ ARM_AEXT2_V8_1M_MAIN)
/* Some useful combinations: */
#define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0)
diff --git a/ld/ChangeLog b/ld/ChangeLog
index 94e6013..08733d0 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,9 @@
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * testsuite/ld-arm/attr-merge-13.attr: New test.
+ * testsuite/ld-arm/attr-merge-13a.s: New test.
+ * testsuite/ld-arm/attr-merge-13b.s: New test.
+
2019-04-13 Alan Modra <amodra@gmail.com>
* Makefile.am (GENSCRIPTS): Pass LIB_PATH as a parameter. Add
diff --git a/ld/testsuite/ld-arm/attr-merge-13.attr b/ld/testsuite/ld-arm/attr-merge-13.attr
new file mode 100644
index 0000000..9fabb5b
--- /dev/null
+++ b/ld/testsuite/ld-arm/attr-merge-13.attr
@@ -0,0 +1,6 @@
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "8.1-M.MAIN"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
diff --git a/ld/testsuite/ld-arm/attr-merge-13a.s b/ld/testsuite/ld-arm/attr-merge-13a.s
new file mode 100644
index 0000000..5349f7f
--- /dev/null
+++ b/ld/testsuite/ld-arm/attr-merge-13a.s
@@ -0,0 +1,5 @@
+ .arch armv8-m.main
+
+ @ Tag_CPU_arch & Tag_CPU_arch_profile = v8-M.mainline
+ .eabi_attribute Tag_CPU_arch, 17
+ .eabi_attribute Tag_CPU_arch_profile, 'M'
diff --git a/ld/testsuite/ld-arm/attr-merge-13b.s b/ld/testsuite/ld-arm/attr-merge-13b.s
new file mode 100644
index 0000000..20e0753
--- /dev/null
+++ b/ld/testsuite/ld-arm/attr-merge-13b.s
@@ -0,0 +1,5 @@
+ .arch armv8.1-m.main
+
+ @ Tag_CPU_arch & Tag_CPU_arch_profile = v8.1-M.mainline
+ .eabi_attribute Tag_CPU_arch, 18
+ .eabi_attribute Tag_CPU_arch_profile, 'M'
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 043e9fe..5027e9a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
+
2019-04-12 John Darrington <john@darrington.wattle.id.au>
s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 34acea2..e38296e 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -6525,6 +6525,7 @@ select_arm_features (unsigned long mach,
case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
+ case bfd_mach_arm_8_1M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); break;
/* If the machine type is unknown allow all architecture types and all
extensions. */
case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
generated by cgit v1.1 at 2024-11-22 09:33:04 +0000