diff options
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 20 |
2 files changed, 15 insertions, 10 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 34230ec..0a81ca4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2009-03-03 Peter Bergner <bergner@vnet.ibm.com> + + * ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that + instructions from newer processors are listed before older ones. + 2009-03-02 Qinwei <qinwei@sunnorth.com.cn> * score7-dis.c: New file. diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index c872db5..5e70395 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4560,8 +4560,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lhbrx", X(31,790), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, -{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}}, {"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRT, RA, RB}}, +{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}}, {"sraw", XRC(31,792,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, {"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, @@ -4638,8 +4638,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"sthbrx", X(31,918), X_MASK, COM, PPCNONE, {RS, RA0, RB}}, -{"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}}, {"stfdpx", X(31,919), X_MASK, POWER6, PPCNONE, {FRS, RA, RB}}, +{"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}}, {"sraq", XRC(31,920,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, {"sraq.", XRC(31,920,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, @@ -4801,12 +4801,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, +{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRT, D, RA0}}, + {"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}}, {"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, -{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRT, D, RA0}}, - {"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}}, {"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}}, {"lwa", DSO(58,2), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}}, @@ -4921,10 +4921,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, -{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, - -{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, - {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}}, {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}}, {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S, DMEX}}, @@ -5067,12 +5063,16 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, +{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, -{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, +{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, {"stfdp", OP(61), OP_MASK, POWER6, PPCNONE, {FRT, D, RA0}}, +{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, + +{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, + {"std", DSO(62,0), DS_MASK, PPC64, PPCNONE, {RS, DS, RA0}}, {"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}}, {"stq", DSO(62,2), DS_MASK, POWER4, PPCNONE, {RSQ, DS, RA0}}, |