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-rw-r--r--gas/ChangeLog19
-rw-r--r--gas/doc/c-riscv.texi14
-rw-r--r--gas/testsuite/gas/riscv/insn.d99
-rw-r--r--gas/testsuite/gas/riscv/insn.s19
-rw-r--r--opcodes/ChangeLog9
-rw-r--r--opcodes/riscv-opc.c30
6 files changed, 133 insertions, 57 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index c8eb546..9704865 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,22 @@
+2019-07-05 Kito Cheng <kito.cheng@sifive.com>
+
+ * doc/c-riscv.texi (Instruction Formats): Add r4 type.
+ * testsuite/gas/riscv/insn.d: Add testcase for r4 type.
+ * testsuite/gas/riscv/insn.s: Ditto.
+
+ * doc/c-riscv.texi (Instruction Formats): Add b and j type.
+ * testsuite/gas/riscv/insn.d: Add test case for b and j type.
+ * testsuite/gas/riscv/insn.s: Ditto.
+
+ * testsuite/gas/riscv/insn.s: Correct instruction type for load
+ and store.
+
+ * testsuite/gas/riscv/insn.d: Using regular expression to match
+ address.
+
+ * doc/c-riscv.texi (Instruction Formats): Fix encoding table for SB
+ type and fix typo.
+
2019-07-04 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_parse_option): Don't blindly accept all
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 42d1ce3..9bc8c82 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -286,7 +286,7 @@ Opcode space for msub instruction.
@item AMO
Opcode space for atomic memory operation instructions.
-@item MISC_IMM
+@item MISC_MEM
Opcode space for misc instructions.
@item SYSTEM
@@ -318,6 +318,7 @@ with the @samp{.insn} pseudo directive:
@end verbatim
@item R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3
+@itemx R4 type: .insn r4 opcode, func3, func2, rd, rs1, rs2, rs3
@verbatim
+-----+-------+-----+-----+-------+----+-------------+
| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode |
@@ -343,11 +344,13 @@ with the @samp{.insn} pseudo directive:
@item SB type: .insn sb opcode, func3, rd, rs1, symbol
@itemx SB type: .insn sb opcode, func3, rd, simm12(rs1)
+@itemx B type: .insn s opcode, func3, rd, rs1, symbol
+@itemx B type: .insn s opcode, func3, rd, simm12(rs1)
@verbatim
-+--------------+-----+-----+-------+-------------+-------------+
-| simm21[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode |
-+--------------+-----+-----+-------+-------------+-------------+
-31 25 20 15 12 7 0
++------------+--------------+-----+-----+-------+-------------+-------------+--------+
+| simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode |
++------------+--------------+-----+-----+-------+-------------+-------------+--------+
+31 30 25 20 15 12 7 0
@end verbatim
@item U type: .insn u opcode, rd, simm20
@@ -359,6 +362,7 @@ with the @samp{.insn} pseudo directive:
@end verbatim
@item UJ type: .insn uj opcode, rd, symbol
+@itemx J type: .insn j opcode, rd, symbol
@verbatim
+------------+--------------+------------+---------------+----+-------------+
| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode |
diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
index a1474c9..47b3a8e 100644
--- a/gas/testsuite/gas/riscv/insn.d
+++ b/gas/testsuite/gas/riscv/insn.d
@@ -7,46 +7,59 @@
Disassembly of section .text:
0+000 <target>:
-[ ]+0:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
-[ ]+4:[ ]+00d58513[ ]+addi[ ]+a0,a1,13
-[ ]+8:[ ]+00a58567[ ]+jalr[ ]+a0,10\(a1\)
-[ ]+c:[ ]+00458503[ ]+lb[ ]+a0,4\(a1\)
-[ ]+10:[ ]+feb508e3[ ]+beq[ ]+a0,a1,0 \<target\>
-[ ]+10: R_RISCV_BRANCH[ ]+target
-[ ]+14:[ ]+00a58223[ ]+sb[ ]+a0,4\(a1\)
-[ ]+18:[ ]+00fff537[ ]+lui[ ]+a0,0xfff
-[ ]+1c:[ ]+fe5ff56f[ ]+jal[ ]+a0,0 \<target\>
-[ ]+1c: R_RISCV_JAL[ ]+target
-[ ]+20:[ ]+0511[ ]+addi[ ]+a0,a0,4
-[ ]+22:[ ]+852e[ ]+mv[ ]+a0,a1
-[ ]+24:[ ]+002c[ ]+addi[ ]+a1,sp,8
-[ ]+26:[ ]+dde9[ ]+beqz[ ]+a1,0 \<target\>
-[ ]+26: R_RISCV_RVC_BRANCH[ ]+target
-[ ]+28:[ ]+bfe1[ ]+j[ ]+0 \<target\>
-[ ]+28: R_RISCV_RVC_JUMP[ ]+target
-[ ]+2a:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
-[ ]+2e:[ ]+00d58513[ ]+addi[ ]+a0,a1,13
-[ ]+32:[ ]+00a58567[ ]+jalr[ ]+a0,10\(a1\)
-[ ]+36:[ ]+00458503[ ]+lb[ ]+a0,4\(a1\)
-[ ]+3a:[ ]+fcb503e3[ ]+beq[ ]+a0,a1,0 \<target\>
-[ ]+3a: R_RISCV_BRANCH[ ]+target
-[ ]+3e:[ ]+00a58223[ ]+sb[ ]+a0,4\(a1\)
-[ ]+42:[ ]+00fff537[ ]+lui[ ]+a0,0xfff
-[ ]+46:[ ]+fbbff56f[ ]+jal[ ]+a0,0 \<target\>
-[ ]+46: R_RISCV_JAL[ ]+target
-[ ]+4a:[ ]+0511[ ]+addi[ ]+a0,a0,4
-[ ]+4c:[ ]+852e[ ]+mv[ ]+a0,a1
-[ ]+4e:[ ]+002c[ ]+addi[ ]+a1,sp,8
-[ ]+50:[ ]+8d6d[ ]+and[ ]+a0,a0,a1
-[ ]+52:[ ]+d5dd[ ]+beqz[ ]+a1,0 \<target\>
-[ ]+52: R_RISCV_RVC_BRANCH[ ]+target
-[ ]+54:[ ]+b775[ ]+j[ ]+0 \<target\>
-[ ]+54: R_RISCV_RVC_JUMP[ ]+target
-[ ]+56:[ ]+68c58543[ ]+fmadd.s[ ]+fa0,fa1,fa2,fa3,rne
-[ ]+5a:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
-[ ]+5e:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
-[ ]+62:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
-[ ]+66:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
-[ ]+6a:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
-[ ]+6e:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
-[ ]+72:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
+[^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
+[^:]+:[ ]+00d58513[ ]+addi[ ]+a0,a1,13
+[^:]+:[ ]+00a58567[ ]+jalr[ ]+a0,10\(a1\)
+[^:]+:[ ]+00458503[ ]+lb[ ]+a0,4\(a1\)
+[^:]+:[ ]+feb508e3[ ]+beq[ ]+a0,a1,0 \<target\>
+[^:]+: R_RISCV_BRANCH[ ]+target
+[^:]+:[ ]+feb506e3[ ]+beq[ ]+a0,a1,0 \<target\>
+[^:]+: R_RISCV_BRANCH[ ]+target
+[^:]+:[ ]+00a58223[ ]+sb[ ]+a0,4\(a1\)
+[^:]+:[ ]+00fff537[ ]+lui[ ]+a0,0xfff
+[^:]+:[ ]+fe1ff56f[ ]+jal[ ]+a0,0 \<target\>
+[^:]+: R_RISCV_JAL[ ]+target
+[^:]+:[ ]+fddff56f[ ]+jal[ ]+a0,0 \<target\>
+[^:]+: R_RISCV_JAL[ ]+target
+[^:]+:[ ]+0511[ ]+addi[ ]+a0,a0,4
+[^:]+:[ ]+852e[ ]+mv[ ]+a0,a1
+[^:]+:[ ]+002c[ ]+addi[ ]+a1,sp,8
+[^:]+:[ ]+d9e9[ ]+beqz[ ]+a1,0 \<target\>
+[^:]+: R_RISCV_RVC_BRANCH[ ]+target
+[^:]+:[ ]+bfc1[ ]+j[ ]+0 \<target\>
+[^:]+: R_RISCV_RVC_JUMP[ ]+target
+[^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
+[^:]+:[ ]+00d58513[ ]+addi[ ]+a0,a1,13
+[^:]+:[ ]+00a58567[ ]+jalr[ ]+a0,10\(a1\)
+[^:]+:[ ]+00458503[ ]+lb[ ]+a0,4\(a1\)
+[^:]+:[ ]+fab50fe3[ ]+beq[ ]+a0,a1,0 \<target\>
+[^:]+: R_RISCV_BRANCH[ ]+target
+[^:]+:[ ]+fab50de3[ ]+beq[ ]+a0,a1,0 \<target\>
+[^:]+: R_RISCV_BRANCH[ ]+target
+[^:]+:[ ]+00a58223[ ]+sb[ ]+a0,4\(a1\)
+[^:]+:[ ]+00fff537[ ]+lui[ ]+a0,0xfff
+[^:]+:[ ]+fafff56f[ ]+jal[ ]+a0,0 \<target\>
+[^:]+: R_RISCV_JAL[ ]+target
+[^:]+:[ ]+fabff56f[ ]+jal[ ]+a0,0 \<target\>
+[^:]+: R_RISCV_JAL[ ]+target
+[^:]+:[ ]+0511[ ]+addi[ ]+a0,a0,4
+[^:]+:[ ]+852e[ ]+mv[ ]+a0,a1
+[^:]+:[ ]+002c[ ]+addi[ ]+a1,sp,8
+[^:]+:[ ]+8d6d[ ]+and[ ]+a0,a0,a1
+[^:]+:[ ]+ddd9[ ]+beqz[ ]+a1,0 \<target\>
+[^:]+: R_RISCV_RVC_BRANCH[ ]+target
+[^:]+:[ ]+bf71[ ]+j[ ]+0 \<target\>
+[^:]+: R_RISCV_RVC_JUMP[ ]+target
+[^:]+:[ ]+68c58543[ ]+fmadd.s[ ]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ ]+68c58543[ ]+fmadd.s[ ]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ ]+68c58543[ ]+fmadd.s[ ]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ ]+68c58543[ ]+fmadd.s[ ]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ ]+68c58543[ ]+fmadd.s[ ]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ ]+68c58543[ ]+fmadd.s[ ]+fa0,fa1,fa2,fa3,rne
+[^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
+[^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
+[^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
+[^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
+[^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
+[^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
+[^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
index 13e5417..6c08f49 100644
--- a/gas/testsuite/gas/riscv/insn.s
+++ b/gas/testsuite/gas/riscv/insn.s
@@ -2,11 +2,13 @@ target:
.insn r 0x33, 0, 0, a0, a1, a2
.insn i 0x13, 0, a0, a1, 13
.insn i 0x67, 0, a0, 10(a1)
- .insn s 0x3, 0, a0, 4(a1)
+ .insn i 0x3, 0, a0, 4(a1)
.insn sb 0x63, 0, a0, a1, target
- .insn sb 0x23, 0, a0, 4(a1)
+ .insn b 0x63, 0, a0, a1, target
+ .insn s 0x23, 0, a0, 4(a1)
.insn u 0x37, a0, 0xfff
.insn uj 0x6f, a0, target
+ .insn j 0x6f, a0, target
.insn ci 0x1, 0x0, a0, 4
.insn cr 0x2, 0x8, a0, a1
@@ -17,11 +19,13 @@ target:
.insn r OP, 0, 0, a0, a1, a2
.insn i OP_IMM, 0, a0, a1, 13
.insn i JALR, 0, a0, 10(a1)
- .insn s LOAD, 0, a0, 4(a1)
+ .insn i LOAD, 0, a0, 4(a1)
.insn sb BRANCH, 0, a0, a1, target
- .insn sb STORE, 0, a0, 4(a1)
+ .insn b BRANCH, 0, a0, a1, target
+ .insn s STORE, 0, a0, 4(a1)
.insn u LUI, a0, 0xfff
.insn uj JAL, a0, target
+ .insn j JAL, a0, target
.insn ci C1, 0x0, a0, 4
.insn cr C2, 0x8, a0, a1
@@ -30,7 +34,12 @@ target:
.insn cb C1, 0x6, a1, target
.insn cj C1, 0x5, target
- .insn r MADD, 0, 0, a0, a1, a2, a3
+ .insn r MADD, 0, 0, a0, a1, a2, a3
+ .insn r4 MADD, 0, 0, a0, a1, a2, a3
+ .insn r4 MADD, 0, 0, fa0, a1, a2, a3
+ .insn r4 MADD, 0, 0, fa0, fa1, a2, a3
+ .insn r4 MADD, 0, 0, fa0, fa1, fa2, a3
+ .insn r4 MADD, 0, 0, fa0, fa1, fa2, fa3
.insn r 0x33, 0, 0, fa0, a1, a2
.insn r 0x33, 0, 0, a0, fa1, a2
.insn r 0x33, 0, 0, fa0, fa1, a2
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 882ab3f..85a2842 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+2019-07-05 Kito Cheng <kito.cheng@sifive.com>
+
+ * riscv-opc.c (riscv_insn_types): Add r4 type.
+
+ * riscv-opc.c (riscv_insn_types): Add b and j type.
+
+ * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
+ format for sb type and correct s type.
+
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
* aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index bd65259..113d1a5 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -812,6 +812,23 @@ const struct riscv_opcode riscv_insn_types[] =
{"r", 0, {"I", 0}, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, 0 },
{"r", 0, {"I", 0}, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,S,t,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,s,T,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,s,T,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,S,T,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,S,T,r", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,s,t,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,s,t,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,S,t,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,S,t,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,s,T,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,s,T,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,d,S,T,R", 0, 0, match_opcode, 0 },
+{"r4", 0, {"I", 0}, "O4,F3,F2,D,S,T,R", 0, 0, match_opcode, 0 },
+
{"i", 0, {"I", 0}, "O4,F3,d,s,j", 0, 0, match_opcode, 0 },
{"i", 0, {"I", 0}, "O4,F3,D,s,j", 0, 0, match_opcode, 0 },
{"i", 0, {"I", 0}, "O4,F3,d,S,j", 0, 0, match_opcode, 0 },
@@ -820,16 +837,18 @@ const struct riscv_opcode riscv_insn_types[] =
{"i", 0, {"I", 0}, "O4,F3,d,o(s)", 0, 0, match_opcode, 0 },
{"i", 0, {"I", 0}, "O4,F3,D,o(s)", 0, 0, match_opcode, 0 },
-{"s", 0, {"I", 0}, "O4,F3,d,o(s)", 0, 0, match_opcode, 0 },
-{"s", 0, {"I", 0}, "O4,F3,D,o(s)", 0, 0, match_opcode, 0 },
+{"s", 0, {"I", 0}, "O4,F3,t,q(s)", 0, 0, match_opcode, 0 },
+{"s", 0, {"I", 0}, "O4,F3,T,q(s)", 0, 0, match_opcode, 0 },
{"sb", 0, {"I", 0}, "O4,F3,s,t,p", 0, 0, match_opcode, 0 },
{"sb", 0, {"I", 0}, "O4,F3,S,t,p", 0, 0, match_opcode, 0 },
{"sb", 0, {"I", 0}, "O4,F3,s,T,p", 0, 0, match_opcode, 0 },
{"sb", 0, {"I", 0}, "O4,F3,S,T,p", 0, 0, match_opcode, 0 },
-{"sb", 0, {"I", 0}, "O4,F3,t,q(s)", 0, 0, match_opcode, 0 },
-{"sb", 0, {"I", 0}, "O4,F3,T,q(s)", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,s,t,p", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,S,t,p", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,s,T,p", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,S,T,p", 0, 0, match_opcode, 0 },
{"u", 0, {"I", 0}, "O4,d,u", 0, 0, match_opcode, 0 },
{"u", 0, {"I", 0}, "O4,D,u", 0, 0, match_opcode, 0 },
@@ -837,6 +856,9 @@ const struct riscv_opcode riscv_insn_types[] =
{"uj", 0, {"I", 0}, "O4,d,a", 0, 0, match_opcode, 0 },
{"uj", 0, {"I", 0}, "O4,D,a", 0, 0, match_opcode, 0 },
+{"j", 0, {"I", 0}, "O4,d,a", 0, 0, match_opcode, 0 },
+{"j", 0, {"I", 0}, "O4,D,a", 0, 0, match_opcode, 0 },
+
{"cr", 0, {"C", 0}, "O2,CF4,d,CV", 0, 0, match_opcode, 0 },
{"cr", 0, {"C", 0}, "O2,CF4,D,CV", 0, 0, match_opcode, 0 },
{"cr", 0, {"C", 0}, "O2,CF4,d,CT", 0, 0, match_opcode, 0 },
generated by cgit v1.1 at 2024-12-12 10:14:07 +0000