diff options
| -rw-r--r-- | gdb/doc/ChangeLog | 47 | ||||
| -rw-r--r-- | gdb/doc/gdb.texinfo | 4 | ||||
| -rw-r--r-- | gdb/doc/gdbint.texinfo | 903 |
3 files changed, 342 insertions, 612 deletions
diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog index 24cfe28..c98ed6b 100644 --- a/gdb/doc/ChangeLog +++ b/gdb/doc/ChangeLog @@ -1,3 +1,50 @@ +2007-07-03 Markus Deuling <deuling@de.ibm.com> + + * gdb.texinfo: Replace following macros by their appropriate gdbarch + routines: + (TARGET_CHAR_SIGNED, CALL_DUMMY_LOCATION, CANNOT_FETCH_REGISTER) + (CANNOT_STORE_REGISTER, GET_LONGJMP_TARGET, POINTER_TO_ADDRESS) + (ADDRESS_TO_POINTER, INNER_THAN, FRAME_NUM_ARGS) + (HAVE_NONSTEPPABLE_WATCHPOINT, TARGET_SHORT_BIT, TARGET_INT_BIT) + (TARGET_LONG_BIT, TARGET_LONG_LONG_BIT, TARGET_FLOAT_BIT) + (TARGET_DOUBLE_BIT, TARGET_LONG_DOUBLE_BIT, TARGET_PTR_BIT + (TARGET_ADDR_BIT, SP_REGNUM, PC_REGNUM, PS_REGNUM, FP0_REGNUM) + (STAB_REG_TO_REGNUM, ECOFF_REG_TO_REGNUM, DWARF_REG_TO_REGNUM) + (SDB_REG_TO_REGNUM, DWARF2_REG_TO_REGNUM, BELIEVE_PCC_PROMOTION) + (CONVERT_REGISTER_P, REGISTER_TO_VALUE, VALUE_TO_REGISTER) + (POINTER_TO_ADDRESS, ADDRESS_TO_POINTER, EXTRACT_RETURN_VALUE) + (STORE_RETURN_VALUE, SKIP_PROLOGUE, MEMORY_INSERT_BREAKPOINT) + (BREAKPOINT_FROM_PC, MEMORY_REMOVE_BREAKPOINT, DECR_PC_AFTER_BREAK) + (ADDR_BITS_REMOVE, TARGET_PRINT_INSN, SKIP_TRAMPOLINE_CODE) + (IN_SOLIB_RETURN_TRAMPOLINE, NAME_OF_MALLOC, ADDRESS_CLASS_TYPE_FLAGS) + (ADDRESS_CLASS_TYPE_FLAGS_TO_NAME, ADDRESS_CLASS_TYPE_FLAGS_P). + (ADDRESS_CLASS_NAME_to_TYPE_FLAGS, ADJUST_BREAKPOINT_ADDRESS) + (PRINT_FLOAT_INFO, PRINT_VECTOR_INFO, INTEGER_TO_ADDRESS) + (SKIP_PERMANENT_BREAKPOINT, TARGET_VIRTUAL_FRAME_POINTER) + (SOFTWARE_SINGLE_STEP_P) + + (push_dummy_call, stabs_argument_has_addr, unwind_sp, unwind_pc) + (print_registers_info, push_dummy_code, unwind_dummy_id): Rework + + (REGISTER_CONVERT_TO_TYPE, END_OF_TEXT_DEFAULT, GDB_MULTI_ARCH) + (GDB_TARGET_IS_HPPA, DEPRECATED_GET_SAVED_REGISTER) + (SYMBOLS_CAN_START_WITH_DOLLAR, DEPRECATED_INIT_EXTRA_FRAME_INFO) + (DEPRECATED_INIT_FRAME_PC, DEPRECATED_SIGTRAMP_START) + (IN_SOLIB_CALL_TRAMPOLINE, NO_HIF_SUPPORT, REGISTER_CONVERTIBLE) + (DEPRECATED_REGISTER_RAW_SIZE, PARM_BOUNDARY, DEPRECATED_STACK_ALIGN) + (PROLOGUE_FIRSTLINE_OVERLAP, DEPRECATED_POP_FRAME, STEP_SKIPS_DELAY) + (TARGET_COMPLEX_BIT, TARGET_DOUBLE_COMPLEX_BIT) + (OS9K_VARIABLES_INSIDE_BLOCK, KERNEL_U_ADDR, KERNEL_U_ADDR_HPUX) + (REGISTER_U_ADDR, U_REGS_OFFSET, DEBUG_PTRACE): Remove description. + + (Converting an existing Target Architecture to Multi-arch): Remove + section. + + (gdbarch_unwind_pc, gdbarch_unwind_sp): Renew code example. + (gdbarch_addr_bits_remove): Add code example. + + * gdb.texinfo: Replace REGISTER_NAME by gdbarch_register_name. + 2007-07-02 Daniel Jacobowitz <dan@codesourcery.com> * gdb.texinfo (Remote Configuration): Document library-info-packet. diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index ee592d9..b2f7f74 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -22789,8 +22789,8 @@ Reply: Each byte of register data is described by two hex digits. The bytes with the register are transmitted in target byte order. The size of each register and their position within the @samp{g} packet are -determined by the @value{GDBN} internal macros -@code{DEPRECATED_REGISTER_RAW_SIZE} and @code{REGISTER_NAME} macros. The +determined by the @value{GDBN} internal gdbarch functions +@code{DEPRECATED_REGISTER_RAW_SIZE} and @code{gdbarch_register_name}. The specification of several standard @samp{g} packets is specified below. @item E @var{NN} for an error. diff --git a/gdb/doc/gdbint.texinfo b/gdb/doc/gdbint.texinfo index e19a35b..0518f96 100644 --- a/gdb/doc/gdbint.texinfo +++ b/gdb/doc/gdbint.texinfo @@ -569,7 +569,7 @@ it could differ from @code{shadow_len}. For example, the remote target @samp{Z0} packet does not require shadowing memory, so @code{shadow_len} is left at zero. However, -the length reported by @code{BREAKPOINT_FROM_PC} is cached in +the length reported by @code{gdbarch_breakpoint_from_pc} is cached in @code{placed_size}, so that a matching @samp{z0} packet can be used to remove the breakpoint. @@ -604,9 +604,9 @@ stepping. This is done with a few specialized internal breakpoints, which are visible in the output of the @samp{maint info breakpoint} command. -@findex GET_LONGJMP_TARGET -To make this work, you need to define a macro called -@code{GET_LONGJMP_TARGET}, which will examine the @code{jmp_buf} +@findex gdbarch_get_longjmp_target +To make this work, you need to define a function called +@code{gdbarch_get_longjmp_target}, which will examine the @code{jmp_buf} structure and extract the longjmp target address. Since @code{jmp_buf} is target specific, you will need to define it in the appropriate @file{tm-@var{target}.h} file. Look in @file{tm-sun4os4.h} and @@ -732,9 +732,9 @@ primitives. If defined to a non-zero value, it is not necessary to disable a watchpoint to step over it. -@findex HAVE_NONSTEPPABLE_WATCHPOINT -@item HAVE_NONSTEPPABLE_WATCHPOINT -If defined to a non-zero value, @value{GDBN} should disable a +@findex gdbarch_have_nonsteppable_watchpoint +@item int gdbarch_have_nonsteppable_watchpoint (@var{gdbarch}) +If it returns a non-zero value, @value{GDBN} should disable a watchpoint to step the inferior over it. @findex HAVE_CONTINUABLE_WATCHPOINT @@ -1521,7 +1521,7 @@ Here's the new version: @{ if (nr_printable_breakpoints > 0) annotate_field (4); - if (TARGET_ADDR_BIT <= 32) + if (gdbarch_addr_bit (current_gdbarch) <= 32) ui_out_table_header (uiout, 10, ui_left, "addr", "Address");/* 5 */ else ui_out_table_header (uiout, 18, ui_left, "addr", "Address");/* 5 */ @@ -2794,7 +2794,7 @@ block of memory. Each register may have a different size. compiler's idea of which registers are which; however, it is critical that they do match up accurately. The only way to make this work is to get accurate information about the order that the compiler uses, -and to reflect that in the @code{REGISTER_NAME} and related macros. +and to reflect that in the @code{gdbarch_register_name} and related functions. @value{GDBN} can handle big-endian, little-endian, and bi-endian architectures. @@ -2908,27 +2908,27 @@ This function performs architecture-specific conversions as described above for @code{store_typed_address}. @end deftypefun -Here are some macros which architectures can define to indicate the +Here are two functions which architectures can define to indicate the relationship between pointers and addresses. These have default definitions, appropriate for architectures on which all pointers are simple unsigned byte addresses. -@deftypefn {Target Macro} CORE_ADDR POINTER_TO_ADDRESS (struct type *@var{type}, char *@var{buf}) +@deftypefun CORE_ADDR gdbarch_pointer_to_address (struct gdbarch *@var{current_gdbarch}, struct type *@var{type}, char *@var{buf}) Assume that @var{buf} holds a pointer of type @var{type}, in the appropriate format for the current architecture. Return the byte address the pointer refers to. This function may safely assume that @var{type} is either a pointer or a C@t{++} reference type. -@end deftypefn +@end deftypefun -@deftypefn {Target Macro} void ADDRESS_TO_POINTER (struct type *@var{type}, char *@var{buf}, CORE_ADDR @var{addr}) +@deftypefun void gdbarch_address_to_pointer (struct gdbarch *@var{current_gdbarch}, struct type *@var{type}, char *@var{buf}, CORE_ADDR @var{addr}) Store in @var{buf} a pointer of type @var{type} representing the address @var{addr}, in the appropriate format for the current architecture. This function may safely assume that @var{type} is either a pointer or a C@t{++} reference type. -@end deftypefn +@end deftypefun @node Address Classes @section Address Classes @@ -2946,32 +2946,32 @@ following macros should be defined in order to disambiguate these types within @value{GDBN} as well as provide the added information to a @value{GDBN} user when printing type expressions. -@deftypefn {Target Macro} int ADDRESS_CLASS_TYPE_FLAGS (int @var{byte_size}, int @var{dwarf2_addr_class}) +@deftypefun int gdbarch_address_class_type_flags (struct gdbarch *@var{current_gdbarch}, int @var{byte_size}, int @var{dwarf2_addr_class}) Returns the type flags needed to construct a pointer type whose size is @var{byte_size} and whose address class is @var{dwarf2_addr_class}. This function is normally called from within a symbol reader. See @file{dwarf2read.c}. -@end deftypefn +@end deftypefun -@deftypefn {Target Macro} char *ADDRESS_CLASS_TYPE_FLAGS_TO_NAME (int @var{type_flags}) +@deftypefun char *gdbarch_address_class_type_flags_to_name (struct gdbarch *@var{current_gdbarch}, int @var{type_flags}) Given the type flags representing an address class qualifier, return its name. -@end deftypefn -@deftypefn {Target Macro} int ADDRESS_CLASS_NAME_to_TYPE_FLAGS (int @var{name}, int *var{type_flags_ptr}) +@end deftypefun +@deftypefun int gdbarch_address_class_name_to_type_flags (struct gdbarch *@var{current_gdbarch}, int @var{name}, int *var{type_flags_ptr}) Given an address qualifier name, set the @code{int} referenced by @var{type_flags_ptr} to the type flags for that address class qualifier. -@end deftypefn +@end deftypefun Since the need for address classes is rather rare, none of -the address class macros defined by default. Predicate -macros are provided to detect when they are defined. +the address class functions are defined by default. Predicate +functions are provided to detect when they are defined. Consider a hypothetical architecture in which addresses are normally 32-bits wide, but 16-bit addresses are also supported. Furthermore, suppose that the @w{DWARF 2} information for this architecture simply uses a @code{DW_AT_byte_size} value of 2 to indicate the use of one of these "short" pointers. The following functions could be defined -to implement the address class macros: +to implement the address class functions: @smallexample somearch_address_class_type_flags (int byte_size, @@ -3169,37 +3169,37 @@ However, they do occasionally differ. Your architecture may define the following macros to request conversions between the register and memory representations of a data type: -@deftypefn {Target Macro} int CONVERT_REGISTER_P (int @var{reg}) +@deftypefun int gdbarch_convert_register_p (struct gdbarch *@var{gdbarch}, int @var{reg}) Return non-zero if the representation of a data value stored in this register may be different to the representation of that same data value when stored in memory. -When non-zero, the macros @code{REGISTER_TO_VALUE} and -@code{VALUE_TO_REGISTER} are used to perform any necessary conversion. -@end deftypefn +When non-zero, the macros @code{gdbarch_register_to_value} and +@code{value_to_register} are used to perform any necessary conversion. +@end deftypefun -@deftypefn {Target Macro} void REGISTER_TO_VALUE (int @var{reg}, struct type *@var{type}, char *@var{from}, char *@var{to}) +@deftypefun void gdbarch_register_to_value (struct gdbarch *@var{gdbarch}, int @var{reg}, struct type *@var{type}, char *@var{from}, char *@var{to}) Convert the value of register number @var{reg} to a data object of type @var{type}. The buffer at @var{from} holds the register's value in raw format; the converted value should be placed in the buffer at @var{to}. -Note that @code{REGISTER_TO_VALUE} and @code{VALUE_TO_REGISTER} take -their @var{reg} and @var{type} arguments in different orders. +Note that @code{gdbarch_register_to_value} and @code{gdbarch_value_to_register} +take their @var{reg} and @var{type} arguments in different orders. -You should only use @code{REGISTER_TO_VALUE} with registers for which -the @code{CONVERT_REGISTER_P} macro returns a non-zero value. -@end deftypefn +You should only use @code{gdbarch_register_to_value} with registers for which +the @code{gdbarch_convert_register_p} function returns a non-zero value. +@end deftypefun -@deftypefn {Target Macro} void VALUE_TO_REGISTER (struct type *@var{type}, int @var{reg}, char *@var{from}, char *@var{to}) +@deftypefun void gdbarch_value_to_register (struct gdbarch *@var{gdbarch}, struct type *@var{type}, int @var{reg}, char *@var{from}, char *@var{to}) Convert a data value of type @var{type} to register number @var{reg}' raw format. -Note that @code{REGISTER_TO_VALUE} and @code{VALUE_TO_REGISTER} take -their @var{reg} and @var{type} arguments in different orders. +Note that @code{gdbarch_register_to_value} and @code{gdbarch_value_to_register} +take their @var{reg} and @var{type} arguments in different orders. -You should only use @code{VALUE_TO_REGISTER} with registers for which -the @code{CONVERT_REGISTER_P} macro returns a non-zero value. -@end deftypefn +You should only use @code{gdbarch_value_to_register} with registers for which +the @code{gdbarch_convert_register_p} function returns a non-zero value. +@end deftypefun @deftypefn {Target Macro} void REGISTER_CONVERT_TO_TYPE (int @var{regnum}, struct type *@var{type}, char *@var{buf}) See @file{mips-tdep.c}. It does not do what you want. @@ -3217,27 +3217,33 @@ See @file{mips-tdep.c}. It does not do what you want. @node Target Conditionals @section Target Conditionals -This section describes the macros that you can use to define the target -machine. +This section describes the macros and functions that you can use to define the +target machine. @table @code -@item ADDR_BITS_REMOVE (addr) -@findex ADDR_BITS_REMOVE +@item CORE_ADDR gdbarch_addr_bits_remove (@var{gdbarch}, @var{addr}) +@findex gdbarch_addr_bits_remove If a raw machine instruction address includes any bits that are not -really part of the address, then define this macro to expand into an -expression that zeroes those bits in @var{addr}. This is only used for -addresses of instructions, and even then not in all contexts. +really part of the address, then this function is used to zero those bits in +@var{addr}. This is only used for addresses of instructions, and even then not +in all contexts. For example, the two low-order bits of the PC on the Hewlett-Packard PA 2.0 architecture contain the privilege level of the corresponding instruction. Since instructions must always be aligned on four-byte boundaries, the processor masks out these bits to generate the actual -address of the instruction. ADDR_BITS_REMOVE should filter out these -bits with an expression such as @code{((addr) & ~3)}. +address of the instruction. @code{gdbarch_addr_bits_remove} would then for +example look like that: +@smallexample +arch_addr_bits_remove (CORE_ADDR addr) +@{ + return (addr &= ~0x3); +@} +@end smallexample -@item ADDRESS_CLASS_NAME_TO_TYPE_FLAGS (@var{name}, @var{type_flags_ptr}) -@findex ADDRESS_CLASS_NAME_TO_TYPE_FLAGS +@item int address_class_name_to_type_flags (@var{gdbarch}, @var{name}, @var{type_flags_ptr}) +@findex address_class_name_to_type_flags If @var{name} is a valid address class qualifier name, set the @code{int} referenced by @var{type_flags_ptr} to the mask representing the qualifier and return 1. If @var{name} is not a valid address class qualifier name, @@ -3248,13 +3254,13 @@ The value for @var{type_flags_ptr} should be one of possibly some combination of these values or'd together. @xref{Target Architecture Definition, , Address Classes}. -@item ADDRESS_CLASS_NAME_TO_TYPE_FLAGS_P () -@findex ADDRESS_CLASS_NAME_TO_TYPE_FLAGS_P -Predicate which indicates whether @code{ADDRESS_CLASS_NAME_TO_TYPE_FLAGS} +@item int address_class_name_to_type_flags_p (@var{gdbarch}) +@findex address_class_name_to_type_flags_p +Predicate which indicates whether @code{address_class_name_to_type_flags} has been defined. -@item ADDRESS_CLASS_TYPE_FLAGS (@var{byte_size}, @var{dwarf2_addr_class}) -@findex ADDRESS_CLASS_TYPE_FLAGS (@var{byte_size}, @var{dwarf2_addr_class}) +@item int gdbarch_address_class_type_flags (@var{gdbarch}, @var{byte_size}, @var{dwarf2_addr_class}) +@findex gdbarch_address_class_type_flags Given a pointers byte size (as described by the debug information) and the possible @code{DW_AT_address_class} value, return the type flags used by @value{GDBN} to represent this address class. The value @@ -3263,33 +3269,32 @@ returned should be one of @code{TYPE_FLAG_ADDRESS_CLASS_1}, values or'd together. @xref{Target Architecture Definition, , Address Classes}. -@item ADDRESS_CLASS_TYPE_FLAGS_P () -@findex ADDRESS_CLASS_TYPE_FLAGS_P -Predicate which indicates whether @code{ADDRESS_CLASS_TYPE_FLAGS} has +@item int gdbarch_address_class_type_flags_p (@var{gdbarch}) +@findex gdbarch_address_class_type_flags_p +Predicate which indicates whether @code{gdbarch_address_class_type_flags_p} has been defined. -@item ADDRESS_CLASS_TYPE_FLAGS_TO_NAME (@var{type_flags}) -@findex ADDRESS_CLASS_TYPE_FLAGS_TO_NAME +@item const char *gdbarch_address_class_type_flags_to_name (@var{gdbarch}, @var{type_flags}) +@findex gdbarch_address_class_type_flags_to_name Return the name of the address class qualifier associated with the type flags given by @var{type_flags}. -@item ADDRESS_CLASS_TYPE_FLAGS_TO_NAME_P () -@findex ADDRESS_CLASS_TYPE_FLAGS_TO_NAME_P -Predicate which indicates whether @code{ADDRESS_CLASS_TYPE_FLAGS_TO_NAME} has -been defined. +@item int gdbarch_address_class_type_flags_to_name_p (@var{gdbarch}) +@findex gdbarch_address_class_type_flags_to_name_p +Predicate which indicates whether @code{gdbarch_address_class_type_flags_to_name} has been defined. @xref{Target Architecture Definition, , Address Classes}. -@item ADDRESS_TO_POINTER (@var{type}, @var{buf}, @var{addr}) -@findex ADDRESS_TO_POINTER +@item void gdbarch_address_to_pointer (@var{gdbarch}, @var{type}, @var{buf}, @var{addr}) +@findex gdbarch_address_to_pointer Store in @var{buf} a pointer of type @var{type} representing the address @var{addr}, in the appropriate format for the current architecture. -This macro may safely assume that @var{type} is either a pointer or a +This function may safely assume that @var{type} is either a pointer or a C@t{++} reference type. @xref{Target Architecture Definition, , Pointers Are Not Always Addresses}. -@item BELIEVE_PCC_PROMOTION -@findex BELIEVE_PCC_PROMOTION -Define if the compiler promotes a @code{short} or @code{char} +@item int gdbarch_believe_pcc_promotion (@var{gdbarch}) +@findex gdbarch_believe_pcc_promotion +Used to notify if the compiler promotes a @code{short} or @code{char} parameter to an @code{int}, but still reports the parameter as its original type, rather than the promoted type. @@ -3308,7 +3313,7 @@ pattern could be an invalid instruction. The breakpoint must be no longer than the shortest instruction of the architecture. @code{BREAKPOINT} has been deprecated in favor of -@code{BREAKPOINT_FROM_PC}. +@code{gdbarch_breakpoint_from_pc}. @item BIG_BREAKPOINT @itemx LITTLE_BREAKPOINT @@ -3317,11 +3322,11 @@ longer than the shortest instruction of the architecture. Similar to BREAKPOINT, but used for bi-endian targets. @code{BIG_BREAKPOINT} and @code{LITTLE_BREAKPOINT} have been deprecated in -favor of @code{BREAKPOINT_FROM_PC}. +favor of @code{gdbarch_breakpoint_from_pc}. -@item BREAKPOINT_FROM_PC (@var{pcptr}, @var{lenptr}) -@findex BREAKPOINT_FROM_PC -@anchor{BREAKPOINT_FROM_PC} Use the program counter to determine the +@item const gdb_byte *gdbarch_breakpoint_from_pc (@var{gdbarch}, @var{pcptr}, @var{lenptr}) +@findex gdbarch_breakpoint_from_pc +@anchor{gdbarch_breakpoint_from_pc} Use the program counter to determine the contents and size of a breakpoint instruction. It returns a pointer to a string of bytes that encode a breakpoint instruction, stores the length of the string to @code{*@var{lenptr}}, and adjusts the program @@ -3335,26 +3340,25 @@ instruction of the architecture. Replaces all the other @var{BREAKPOINT} macros. -@item MEMORY_INSERT_BREAKPOINT (@var{bp_tgt}) -@itemx MEMORY_REMOVE_BREAKPOINT (@var{bp_tgt}) -@findex MEMORY_REMOVE_BREAKPOINT -@findex MEMORY_INSERT_BREAKPOINT +@item int gdbarch_memory_insert_breakpoint (@var{gdbarch}, @var{bp_tgt}) +@itemx gdbarch_memory_remove_breakpoint (@var{gdbarch}, @var{bp_tgt}) +@findex gdbarch_memory_remove_breakpoint +@findex gdbarch_memory_insert_breakpoint Insert or remove memory based breakpoints. Reasonable defaults (@code{default_memory_insert_breakpoint} and @code{default_memory_remove_breakpoint} respectively) have been -provided so that it is not necessary to define these for most -architectures. Architectures which may want to define -@code{MEMORY_INSERT_BREAKPOINT} and @code{MEMORY_REMOVE_BREAKPOINT} will -likely have instructions that are oddly sized or are not stored in a +provided so that it is not necessary to set these for most +architectures. Architectures which may want to set +@code{gdbarch_memory_insert_breakpoint} and @code{gdbarch_memory_remove_breakpoint} will likely have instructions that are oddly sized or are not stored in a conventional manner. It may also be desirable (from an efficiency standpoint) to define custom breakpoint insertion and removal routines if -@code{BREAKPOINT_FROM_PC} needs to read the target's memory for some +@code{gdbarch_breakpoint_from_pc} needs to read the target's memory for some reason. -@item ADJUST_BREAKPOINT_ADDRESS (@var{address}) -@findex ADJUST_BREAKPOINT_ADDRESS +@item CORE_ADDR gdbarch_adjust_breakpoint_address (@var{gdbarch}, @var{bpaddr}) +@findex gdbarch_adjust_breakpoint_address @cindex breakpoint address adjusted Given an address at which a breakpoint is desired, return a breakpoint address adjusted to account for architectural constraints on @@ -3378,7 +3382,7 @@ instruction on any instruction other than the first one in the bundle. in parallel, so the @emph{first} instruction is the instruction at the lowest address and has nothing to do with execution order.) -The FR-V's @code{ADJUST_BREAKPOINT_ADDRESS} method will adjust a +The FR-V's @code{gdbarch_adjust_breakpoint_address} method will adjust a breakpoint's address by scanning backwards for the beginning of the bundle, returning the address of the bundle. @@ -3386,35 +3390,35 @@ Since the adjustment of a breakpoint may significantly alter a user's expectation, @value{GDBN} prints a warning when an adjusted breakpoint is initially set and each time that that breakpoint is hit. -@item CALL_DUMMY_LOCATION -@findex CALL_DUMMY_LOCATION +@item int gdbarch_call_dummy_location (@var{gdbarch}) +@findex gdbarch_call_dummy_location See the file @file{inferior.h}. -This method has been replaced by @code{push_dummy_code} -(@pxref{push_dummy_code}). +This method has been replaced by @code{gdbarch_push_dummy_code} +(@pxref{gdbarch_push_dummy_code}). -@item CANNOT_FETCH_REGISTER (@var{regno}) -@findex CANNOT_FETCH_REGISTER -A C expression that should be nonzero if @var{regno} cannot be fetched +@item int gdbarch_cannot_fetch_register (@var{gdbarch}, @var{regum}) +@findex gdbarch_cannot_fetch_register +This function should return nonzero if @var{regno} cannot be fetched from an inferior process. This is only relevant if @code{FETCH_INFERIOR_REGISTERS} is not defined. -@item CANNOT_STORE_REGISTER (@var{regno}) -@findex CANNOT_STORE_REGISTER -A C expression that should be nonzero if @var{regno} should not be +@item int gdbarch_cannot_store_register (@var{gdbarch}, @var{regnum}) +@findex gdbarch_cannot_store_register +This function should return nonzero if @var{regno} should not be written to the target. This is often the case for program counters, -status words, and other special registers. If this is not defined, -@value{GDBN} will assume that all registers may be written. +status words, and other special registers. This function returns 0 as +default so that @value{GDBN} will assume that all registers may be written. -@item int CONVERT_REGISTER_P(@var{regnum}) -@findex CONVERT_REGISTER_P +@item int gdbarch_convert_register_p (@var{gdbarch}, @var{regnum}, struct type *@var{type}) +@findex gdbarch_convert_register_p Return non-zero if register @var{regnum} can represent data values in a non-standard form. @xref{Target Architecture Definition, , Using Different Register and Memory Data Representations}. -@item DECR_PC_AFTER_BREAK -@findex DECR_PC_AFTER_BREAK -Define this to be the amount by which to decrement the PC after the +@item CORE_ADDR gdbarch_decr_pc_after_break (@var{gdbarch}) +@findex gdbarch_decr_pc_after_break +This function shall return the amount by which to decrement the PC after the program encounters a breakpoint. This is often the number of bytes in @code{BREAKPOINT}, though not always. For most targets this value will be 0. @@ -3423,13 +3427,13 @@ program encounters a breakpoint. This is often the number of bytes in If defined, this should evaluate to 1 if @var{addr} is in a shared library in which breakpoints cannot be set and so should be disabled. -@item PRINT_FLOAT_INFO() -@findex PRINT_FLOAT_INFO +@item void gdbarch_print_float_info (@var{gdbarch}, @var{file}, @var{frame},var{args}) +@findex gdbarch_print_float_info If defined, then the @samp{info float} command will print information about the processor's floating point unit. -@item print_registers_info (@var{gdbarch}, @var{frame}, @var{regnum}, @var{all}) -@findex print_registers_info +@item void gdbarch_print_registers_info (@var{gdbarch}, @var{frame}, @var{regnum}, @var{all}) +@findex gdbarch_print_registers_info If defined, pretty print the value of the register @var{regnum} for the specified @var{frame}. If the value of @var{regnum} is -1, pretty print either all registers (@var{all} is non zero) or a select subset of @@ -3438,36 +3442,31 @@ registers (@var{all} is zero). The default method prints one register per line, and if @var{all} is zero omits floating-point registers. -@item PRINT_VECTOR_INFO() -@findex PRINT_VECTOR_INFO +@item int gdbarch_print_vector_info (@var{gdbarch}, @var{file}, @var{frame}, @var{args}) +@findex gdbarch_print_vector_info If defined, then the @samp{info vector} command will call this function to print information about the processor's vector unit. By default, the @samp{info vector} command will print all vector registers (the register's type having the vector attribute). -@item DWARF_REG_TO_REGNUM -@findex DWARF_REG_TO_REGNUM -Convert DWARF register number into @value{GDBN} regnum. If not defined, -no conversion will be performed. - -@item DWARF2_REG_TO_REGNUM -@findex DWARF2_REG_TO_REGNUM -Convert DWARF2 register number into @value{GDBN} regnum. If not -defined, no conversion will be performed. +@item int gdbarch_dwarf_reg_to_regnum (@var{gdbarch}, @var{dwarf_regnr}) +@findex gdbarch_dwarf_reg_to_regnum +Convert DWARF register number @var{dwarf_regnr} into @value{GDBN} regnum. If +not defined, no conversion will be performed. -@item ECOFF_REG_TO_REGNUM -@findex ECOFF_REG_TO_REGNUM -Convert ECOFF register number into @value{GDBN} regnum. If not defined, -no conversion will be performed. +@item int gdbarch_dwarf2_reg_to_regnum (@var{gdbarch}, @var{dwarf2_regnr}) +@findex gdbarch_dwarf2_reg_to_regnum +Convert DWARF2 register number @var{dwarf2_regnr} into @value{GDBN} regnum. +If not defined, no conversion will be performed. -@item END_OF_TEXT_DEFAULT -@findex END_OF_TEXT_DEFAULT -This is an expression that should designate the end of the text section. -@c (? FIXME ?) +@item int gdbarch_ecoff_reg_to_regnum (@var{gdbarch}, @var{ecoff_regnr}) +@findex gdbarch_ecoff_reg_to_regnum +Convert ECOFF register number @var{ecoff_regnr} into @value{GDBN} regnum. If +not defined, no conversion will be performed. -@item EXTRACT_RETURN_VALUE(@var{type}, @var{regbuf}, @var{valbuf}) -@findex EXTRACT_RETURN_VALUE +@item void gdbarch_extract_return_value (@var{gdbarch}, @var{type}, @var{regbuf}, @var{valbuf}) +@findex gdbarch_extract_return_value Define this to extract a function's return value of type @var{type} from the raw register state @var{regbuf} and copy that, in virtual format, into @var{valbuf}. @@ -3502,7 +3501,7 @@ Define this to an expression that returns 1 if the function invocation represented by @var{fi} does not have a stack frame associated with it. Otherwise return 0. -@item frame_align (@var{address}) +@item CORE_ADDR frame_align (@var{gdbarch}, @var{address}) @anchor{frame_align} @findex frame_align Define this to adjust @var{address} so that it meets the alignment @@ -3519,15 +3518,15 @@ address in the direction of stack growth. By default, no frame based stack alignment is performed. -@item int frame_red_zone_size - +@item int gdbarch_frame_red_zone_size (@var{gdbarch}) +@findex gdbarch_frame_red_zone_size The number of bytes, beyond the innermost-stack-address, reserved by the @sc{abi}. A function is permitted to use this scratch area (instead of allocating extra stack space). When performing an inferior function call, to ensure that it does not modify this area, @value{GDBN} adjusts the innermost-stack-address by -@var{frame_red_zone_size} bytes before pushing parameters onto the +@var{gdbarch_frame_red_zone_size} bytes before pushing parameters onto the stack. By default, zero bytes are allocated. The value must be aligned @@ -3560,9 +3559,9 @@ current stack frame storing each in @code{frame->saved_regs}. Space for @code{FRAME_FIND_SAVED_REGS} is deprecated. -@item FRAME_NUM_ARGS (@var{fi}) -@findex FRAME_NUM_ARGS -For the frame described by @var{fi} return the number of arguments that +@item int gdbarch_frame_num_args (@var{gdbarch}, @var{frame}) +@findex gdbarch_frame_num_args +For the frame described by @var{frame} return the number of arguments that are being passed. If the number of arguments is not known, return @code{-1}. @@ -3571,29 +3570,29 @@ are being passed. If the number of arguments is not known, return @anchor{DEPRECATED_FRAME_SAVED_PC} Given @var{frame}, return the pc saved there. This is the return address. -This method is deprecated. @xref{unwind_pc}. +This method is deprecated. @xref{gdbarch_unwind_pc}. -@item CORE_ADDR unwind_pc (struct frame_info *@var{this_frame}) -@findex unwind_pc -@anchor{unwind_pc} Return the instruction address, in @var{this_frame}'s -caller, at which execution will resume after @var{this_frame} returns. -This is commonly referred to as the return address. +@item CORE_ADDR gdbarch_unwind_pc (@var{next_frame}) +@findex gdbarch_unwind_pc +@anchor{gdbarch_unwind_pc} Return the instruction address, in +@var{next_frame}'s caller, at which execution will resume after +@var{next_frame} returns. This is commonly referred to as the return address. The implementation, which must be frame agnostic (work with any frame), is typically no more than: @smallexample ULONGEST pc; -frame_unwind_unsigned_register (this_frame, D10V_PC_REGNUM, &pc); -return d10v_make_iaddr (pc); +pc = frame_unwind_unsigned_register (next_frame, S390_PC_REGNUM); +return gdbarch_addr_bits_remove (gdbarch, pc); @end smallexample @noindent @xref{DEPRECATED_FRAME_SAVED_PC}, which this method replaces. -@item CORE_ADDR unwind_sp (struct frame_info *@var{this_frame}) -@findex unwind_sp -@anchor{unwind_sp} Return the frame's inner most stack address. This is +@item CORE_ADDR gdbarch_unwind_sp (@var{gdbarch}, @var{next_frame}) +@findex gdbarch_unwind_sp +@anchor{gdbarch_unwind_sp} Return the frame's inner most stack address. This is commonly referred to as the frame's @dfn{stack pointer}. The implementation, which must be frame agnostic (work with any frame), @@ -3601,8 +3600,8 @@ is typically no more than: @smallexample ULONGEST sp; -frame_unwind_unsigned_register (this_frame, D10V_SP_REGNUM, &sp); -return d10v_make_daddr (sp); +sp = frame_unwind_unsigned_register (next_frame, S390_SP_REGNUM); +return gdbarch_addr_bits_remove (gdbarch, sp); @end smallexample @noindent @@ -3639,25 +3638,8 @@ look for to detect that GCC compiled the file. The default symbols are @code{gcc_compiled.} and @code{gcc2_compiled.}, respectively. (Currently only defined for the Delta 68.) -@item @value{GDBN}_MULTI_ARCH -@findex @value{GDBN}_MULTI_ARCH -If defined and non-zero, enables support for multiple architectures -within @value{GDBN}. - -This support can be enabled at two levels. At level one, only -definitions for previously undefined macros are provided; at level two, -a multi-arch definition of all architecture dependent macros will be -defined. - -@item @value{GDBN}_TARGET_IS_HPPA -@findex @value{GDBN}_TARGET_IS_HPPA -This determines whether horrible kludge code in @file{dbxread.c} and -@file{partial-stab.h} is used to mangle multiple-symbol-table files from -HPPA's. This should all be ripped out, and a scheme like @file{elfread.c} -used instead. - -@item GET_LONGJMP_TARGET -@findex GET_LONGJMP_TARGET +@item gdbarch_get_longjmp_target +@findex gdbarch_get_longjmp_target For most machines, this is a target-dependent parameter. On the DECstation and the Iris, this is a native-dependent parameter, since the header file @file{setjmp.h} is needed to define it. @@ -3667,11 +3649,6 @@ assuming that we have just stopped at a @code{longjmp} breakpoint. It takes a @code{CORE_ADDR *} as argument, and stores the target PC value through this pointer. It examines the current state of the machine as needed. -@item DEPRECATED_GET_SAVED_REGISTER -@findex DEPRECATED_GET_SAVED_REGISTER -Define this if you need to supply your own definition for the function -@code{DEPRECATED_GET_SAVED_REGISTER}. - @item DEPRECATED_IBM6000_TARGET @findex DEPRECATED_IBM6000_TARGET Shows that we are configured for an IBM RS/6000 system. This @@ -3683,63 +3660,28 @@ repenting at leisure. An x86-based target can define this to use the generic x86 watchpoint support; see @ref{Algorithms, I386_USE_GENERIC_WATCHPOINTS}. -@item SYMBOLS_CAN_START_WITH_DOLLAR -@findex SYMBOLS_CAN_START_WITH_DOLLAR -Some systems have routines whose names start with @samp{$}. Giving this -macro a non-zero value tells @value{GDBN}'s expression parser to check for such -routines when parsing tokens that begin with @samp{$}. - -On HP-UX, certain system routines (millicode) have names beginning with -@samp{$} or @samp{$$}. For example, @code{$$dyncall} is a millicode -routine that handles inter-space procedure calls on PA-RISC. - -@item DEPRECATED_INIT_EXTRA_FRAME_INFO (@var{fromleaf}, @var{frame}) -@findex DEPRECATED_INIT_EXTRA_FRAME_INFO -If additional information about the frame is required this should be -stored in @code{frame->extra_info}. Space for @code{frame->extra_info} -is allocated using @code{frame_extra_info_zalloc}. - -@item DEPRECATED_INIT_FRAME_PC (@var{fromleaf}, @var{prev}) -@findex DEPRECATED_INIT_FRAME_PC -This is a C statement that sets the pc of the frame pointed to by -@var{prev}. [By default...] - -@item INNER_THAN (@var{lhs}, @var{rhs}) -@findex INNER_THAN +@item int gdbarch_inner_than (@var{gdbarch}, @var{lhs}, @var{rhs}) +@findex gdbarch_inner_than Returns non-zero if stack address @var{lhs} is inner than (nearer to the -stack top) stack address @var{rhs}. Define this as @code{lhs < rhs} if -the target's stack grows downward in memory, or @code{lhs > rsh} if the -stack grows upward. +stack top) stack address @var{rhs}. Let the function return +@w{@code{lhs < rhs}} if the target's stack grows downward in memory, or +@w{@code{lhs > rsh}} if the stack grows upward. -@item gdbarch_in_function_epilogue_p (@var{gdbarch}, @var{pc}) +@item gdbarch_in_function_epilogue_p (@var{gdbarch}, @var{addr}) @findex gdbarch_in_function_epilogue_p -Returns non-zero if the given @var{pc} is in the epilogue of a function. +Returns non-zero if the given @var{addr} is in the epilogue of a function. The epilogue of a function is defined as the part of a function where the stack frame of the function already has been destroyed up to the final `return from function call' instruction. -@item DEPRECATED_SIGTRAMP_START (@var{pc}) -@findex DEPRECATED_SIGTRAMP_START -@itemx DEPRECATED_SIGTRAMP_END (@var{pc}) -@findex DEPRECATED_SIGTRAMP_END -Define these to be the start and end address of the @code{sigtramp} for the -given @var{pc}. On machines where the address is just a compile time -constant, the macro expansion will typically just ignore the supplied -@var{pc}. - -@item IN_SOLIB_CALL_TRAMPOLINE (@var{pc}, @var{name}) -@findex IN_SOLIB_CALL_TRAMPOLINE -Define this to evaluate to nonzero if the program is stopped in the -trampoline that connects to a shared library. - -@item IN_SOLIB_RETURN_TRAMPOLINE (@var{pc}, @var{name}) -@findex IN_SOLIB_RETURN_TRAMPOLINE -Define this to evaluate to nonzero if the program is stopped in the +@item int gdbarch_in_solib_return_trampoline (@var{gdbarch}, @var{pc}, @var{name}) +@findex gdbarch_in_solib_return_trampoline +Define this function to return nonzero if the program is stopped in the trampoline that returns from a shared library. @item IN_SOLIB_DYNSYM_RESOLVE_CODE (@var{pc}) @findex IN_SOLIB_DYNSYM_RESOLVE_CODE -Define this to evaluate to nonzero if the program is stopped in the +Define this to return nonzero if the program is stopped in the dynamic linker. @item SKIP_SOLIB_RESOLVER (@var{pc}) @@ -3750,8 +3692,8 @@ function. A zero value indicates that it is not important or necessary to set a breakpoint to get through the dynamic linker and that single stepping will suffice. -@item INTEGER_TO_ADDRESS (@var{type}, @var{buf}) -@findex INTEGER_TO_ADDRESS +@item CORE_ADDR gdbarch_integer_to_address (@var{gdbarch}, @var{type}, @var{buf}) +@findex gdbarch_integer_to_address @cindex converting integers to addresses Define this when the architecture needs to handle non-pointer to address conversions specially. Converts that value to an address according to @@ -3767,40 +3709,25 @@ conversions in clever and useful ways. It has, however, been pointed out that users aren't complaining about how @value{GDBN} casts integers to pointers; they are complaining that they can't take an address from a disassembly listing and give it to @code{x/i}. Adding an architecture -method like @code{INTEGER_TO_ADDRESS} certainly makes it possible for +method like @code{gdbarch_integer_to_address} certainly makes it possible for @value{GDBN} to ``get it right'' in all circumstances.} @xref{Target Architecture Definition, , Pointers Are Not Always Addresses}. -@item NO_HIF_SUPPORT -@findex NO_HIF_SUPPORT -(Specific to the a29k.) - -@item POINTER_TO_ADDRESS (@var{type}, @var{buf}) -@findex POINTER_TO_ADDRESS +@item CORE_ADDR gdbarch_pointer_to_address (@var{gdbarch}, @var{type}, @var{buf}) +@findex gdbarch_pointer_to_address Assume that @var{buf} holds a pointer of type @var{type}, in the appropriate format for the current architecture. Return the byte address the pointer refers to. @xref{Target Architecture Definition, , Pointers Are Not Always Addresses}. -@item REGISTER_CONVERTIBLE (@var{reg}) -@findex REGISTER_CONVERTIBLE -Return non-zero if @var{reg} uses different raw and virtual formats. -@xref{Target Architecture Definition, , Raw and Virtual Register Representations}. - -@item REGISTER_TO_VALUE(@var{regnum}, @var{type}, @var{from}, @var{to}) -@findex REGISTER_TO_VALUE +@item void gdbarch_register_to_value(@var{gdbarch}, @var{frame}, @var{regnum}, @var{type}, @var{fur}) +@findex gdbarch_register_to_value Convert the raw contents of register @var{regnum} into a value of type @var{type}. @xref{Target Architecture Definition, , Using Different Register and Memory Data Representations}. -@item DEPRECATED_REGISTER_RAW_SIZE (@var{reg}) -@findex DEPRECATED_REGISTER_RAW_SIZE -Return the raw size of @var{reg}; defaults to the size of the register's -virtual type. -@xref{Target Architecture Definition, , Raw and Virtual Register Representations}. - @item register_reggroup_p (@var{gdbarch}, @var{regnum}, @var{reggroup}) @findex register_reggroup_p @cindex register groups @@ -3907,25 +3834,20 @@ them. If defined, print information about the load segment for the program counter. (Defined only for the RS/6000.) -@item PC_REGNUM -@findex PC_REGNUM -If the program counter is kept in a register, then define this macro to -be the number (greater than or equal to zero) of that register. - -This should only need to be defined if @code{TARGET_READ_PC} and -@code{TARGET_WRITE_PC} are not defined. +@item int gdbarch_pc_regnum (@var{gdbarch}) +@findex gdbarch_pc_regnum +If the program counter is kept in a register, then let this function return +the number (greater than or equal to zero) of that register. -@item PARM_BOUNDARY -@findex PARM_BOUNDARY -If non-zero, round arguments to a boundary of this many bits before -pushing them on the stack. +This should only need to be defined if @code{gdbarch_read_pc} and +@code{gdbarch_write_pc} are not defined. -@item stabs_argument_has_addr (@var{gdbarch}, @var{type}) -@findex stabs_argument_has_addr +@item int gdbarch_stabs_argument_has_addr (@var{gdbarch}, @var{type}) +@findex gdbarch_stabs_argument_has_addr @findex DEPRECATED_REG_STRUCT_HAS_ADDR -@anchor{stabs_argument_has_addr} Define this to return nonzero if a -function argument of type @var{type} is passed by reference instead of -value. +@anchor{gdbarch_stabs_argument_has_addr} Define this function to return +nonzero if a function argument of type @var{type} is passed by reference +instead of value. This method replaces @code{DEPRECATED_REG_STRUCT_HAS_ADDR} (@pxref{DEPRECATED_REG_STRUCT_HAS_ADDR}). @@ -3934,28 +3856,19 @@ This method replaces @code{DEPRECATED_REG_STRUCT_HAS_ADDR} @findex PROCESS_LINENUMBER_HOOK A hook defined for XCOFF reading. -@item PROLOGUE_FIRSTLINE_OVERLAP -@findex PROLOGUE_FIRSTLINE_OVERLAP -(Only used in unsupported Convex configuration.) - -@item PS_REGNUM -@findex PS_REGNUM -If defined, this is the number of the processor status register. (This -definition is only used in generic code when parsing "$ps".) - -@item DEPRECATED_POP_FRAME -@findex DEPRECATED_POP_FRAME -@findex frame_pop -If defined, used by @code{frame_pop} to remove a stack frame. This -method has been superseded by generic code. +@item gdbarch_ps_regnum (@var{gdbarch} +@findex gdbarch_ps_regnum +If defined, this function returns the number of the processor status +register. +(This definition is only used in generic code when parsing "$ps".) -@item push_dummy_call (@var{gdbarch}, @var{function}, @var{regcache}, @var{pc_addr}, @var{nargs}, @var{args}, @var{sp}, @var{struct_return}, @var{struct_addr}) -@findex push_dummy_call +@item CORE_ADDR gdbarch_push_dummy_call (@var{gdbarch}, @var{function}, @var{regcache}, @var{bp_addr}, @var{nargs}, @var{args}, @var{sp}, @var{struct_return}, @var{struct_addr}) +@findex gdbarch_push_dummy_call @findex DEPRECATED_PUSH_ARGUMENTS. -@anchor{push_dummy_call} Define this to push the dummy frame's call to -the inferior function onto the stack. In addition to pushing -@var{nargs}, the code should push @var{struct_addr} (when -@var{struct_return}), and the return address (@var{bp_addr}). +@anchor{gdbarch_push_dummy_call} Define this to push the dummy frame's call to +the inferior function onto the stack. In addition to pushing @var{nargs}, the +code should push @var{struct_addr} (when @var{struct_return} is non-zero), and +the return address (@var{bp_addr}). @var{function} is a pointer to a @code{struct value}; on architectures that use function descriptors, this contains the function descriptor value. @@ -3964,9 +3877,9 @@ Returns the updated top-of-stack pointer. This method replaces @code{DEPRECATED_PUSH_ARGUMENTS}. -@item CORE_ADDR push_dummy_code (@var{gdbarch}, @var{sp}, @var{funaddr}, @var{using_gcc}, @var{args}, @var{nargs}, @var{value_type}, @var{real_pc}, @var{bp_addr}) -@findex push_dummy_code -@anchor{push_dummy_code} Given a stack based call dummy, push the +@item CORE_ADDR gdbarch_push_dummy_code (@var{gdbarch}, @var{sp}, @var{funaddr}, @var{using_gcc}, @var{args}, @var{nargs}, @var{value_type}, @var{real_pc}, @var{bp_addr}, @var{regcache}) +@findex gdbarch_push_dummy_code +@anchor{gdbarch_push_dummy_code} Given a stack based call dummy, push the instruction sequence (including space for a breakpoint) to which the called function should return. @@ -3978,21 +3891,21 @@ By default, the stack is grown sufficient to hold a frame-aligned (@pxref{frame_align}) breakpoint, @var{bp_addr} is set to the address reserved for that breakpoint, and @var{real_pc} set to @var{funaddr}. -This method replaces @code{CALL_DUMMY_LOCATION}, +This method replaces @w{@code{gdbarch_call_dummy_location (@var{gdbarch})}} and @code{DEPRECATED_REGISTER_SIZE}. -@item REGISTER_NAME(@var{i}) -@findex REGISTER_NAME -Return the name of register @var{i} as a string. May return @code{NULL} -or @code{NUL} to indicate that register @var{i} is not valid. +@item const char *gdbarch_register_name (@var{gdbarch}, @var{regnr}) +@findex gdbarch_register_name +Return the name of register @var{regnr} as a string. May return @code{NULL} +to indicate that @var{regnr} is not a valid register. @item DEPRECATED_REG_STRUCT_HAS_ADDR (@var{gcc_p}, @var{type}) @findex DEPRECATED_REG_STRUCT_HAS_ADDR @anchor{DEPRECATED_REG_STRUCT_HAS_ADDR}Define this to return 1 if the given type will be passed by pointer rather than directly. -This method has been replaced by @code{stabs_argument_has_addr} -(@pxref{stabs_argument_has_addr}). +This method has been replaced by @code{gdbarch_stabs_argument_has_addr} +(@pxref{gdbarch_stabs_argument_has_addr}). @item SAVE_DUMMY_FRAME_TOS (@var{sp}) @findex SAVE_DUMMY_FRAME_TOS @@ -4000,12 +3913,12 @@ This method has been replaced by @code{stabs_argument_has_addr} notify the target dependent code of the top-of-stack value that will be passed to the inferior code. This is the value of the @code{SP} after both the dummy frame and space for parameters/results have been -allocated on the stack. @xref{unwind_dummy_id}. +allocated on the stack. @xref{gdbarch_unwind_dummy_id}. -@item SDB_REG_TO_REGNUM -@findex SDB_REG_TO_REGNUM -Define this to convert sdb register numbers into @value{GDBN} regnums. If not -defined, no conversion will be done. +@item int gdbarch_sdb_reg_to_regnum (@var{gdbarch}, @var{sdb_regnr}) +@findex gdbarch_sdb_reg_to_regnum +Use this function to convert sdb register @var{sdb_regnr} into @value{GDBN} +regnum. If not defined, no conversion will be done. @item enum return_value_convention gdbarch_return_value (struct gdbarch *@var{gdbarch}, struct type *@var{valtype}, struct regcache *@var{regcache}, void *@var{readbuf}, const void *@var{writebuf}) @findex gdbarch_return_value @@ -4049,61 +3962,42 @@ to the inner most frame. While replacing @var{regcache} with a @code{struct frame_info} @var{frame} parameter would remove that limitation there has yet to be a demonstrated need for such a change.} -@item SKIP_PERMANENT_BREAKPOINT -@findex SKIP_PERMANENT_BREAKPOINT +@item void gdbarch_skip_permanent_breakpoint (@var{gdbarch}, @var{regcache}) +@findex gdbarch_skip_permanent_breakpoint Advance the inferior's PC past a permanent breakpoint. @value{GDBN} normally steps over a breakpoint by removing it, stepping one instruction, and re-inserting the breakpoint. However, permanent breakpoints are hardwired into the inferior, and can't be removed, so this strategy -doesn't work. Calling @code{SKIP_PERMANENT_BREAKPOINT} adjusts the processor's -state so that execution will resume just after the breakpoint. This -macro does the right thing even when the breakpoint is in the delay slot +doesn't work. Calling @code{gdbarch_skip_permanent_breakpoint} adjusts the +processor's state so that execution will resume just after the breakpoint. +This function does the right thing even when the breakpoint is in the delay slot of a branch or jump. -@item SKIP_PROLOGUE (@var{pc}) -@findex SKIP_PROLOGUE -A C expression that returns the address of the ``real'' code beyond the -function entry prologue found at @var{pc}. +@item CORE_ADDR gdbarch_skip_prologue (@var{gdbarch}, @var{ip}) +@findex gdbarch_skip_prologue +A function that returns the address of the ``real'' code beyond the +function entry prologue found at @var{ip}. -@item SKIP_TRAMPOLINE_CODE (@var{pc}) -@findex SKIP_TRAMPOLINE_CODE +@item CORE_ADDR gdbarch_skip_trampoline_code (@var{gdbarch}, @var{frame}, @var{pc}) +@findex gdbarch_skip_trampoline_code If the target machine has trampoline code that sits between callers and -the functions being called, then define this macro to return a new PC +the functions being called, then define this function to return a new PC that is at the start of the real function. -@item SP_REGNUM -@findex SP_REGNUM -If the stack-pointer is kept in a register, then define this macro to be +@item int gdbarch_sp_regnum (@var{gdbarch}) +@findex gdbarch_sp_regnum +If the stack-pointer is kept in a register, then use this function to return the number (greater than or equal to zero) of that register, or -1 if there is no such register. -@item STAB_REG_TO_REGNUM -@findex STAB_REG_TO_REGNUM -Define this to convert stab register numbers (as gotten from `r' -declarations) into @value{GDBN} regnums. If not defined, no conversion will be -done. - -@item DEPRECATED_STACK_ALIGN (@var{addr}) -@anchor{DEPRECATED_STACK_ALIGN} -@findex DEPRECATED_STACK_ALIGN -Define this to increase @var{addr} so that it meets the alignment -requirements for the processor's stack. - -Unlike @ref{frame_align}, this function always adjusts @var{addr} -upwards. - -By default, no stack alignment is performed. - -@item STEP_SKIPS_DELAY (@var{addr}) -@findex STEP_SKIPS_DELAY -Define this to return true if the address is of an instruction with a -delay slot. If a breakpoint has been placed in the instruction's delay -slot, @value{GDBN} will single-step over that instruction before resuming -normally. Currently only defined for the Mips. - -@item STORE_RETURN_VALUE (@var{type}, @var{regcache}, @var{valbuf}) -@findex STORE_RETURN_VALUE -A C expression that writes the function return value, found in +@item int gdbarch_stab_reg_to_regnum (@var{gdbarch}, @var{stab_regnr}) +@findex gdbarch_stab_reg_to_regnum +Use this function to convert stab register @var{stab_regnr} into @value{GDBN} +regnum. If not defined, no conversion will be done. + +@item void gdbarch_store_return_value (@var{gdbarch}, @var{type}, @var{regcache}, @var{valbuf}) +@findex gdbarch_store_return_value +A function that writes the function return value, found in @var{valbuf}, into the @var{regcache}. @var{type} is the type of the value that is to be returned. @@ -4119,8 +4013,8 @@ current sources.) @findex TARGET_CHAR_BIT Number of bits in a char; defaults to 8. -@item TARGET_CHAR_SIGNED -@findex TARGET_CHAR_SIGNED +@item int gdbarch_char_signed (@var{gdbarch}) +@findex gdbarch_char_signed Non-zero if @code{char} is normally signed on this architecture; zero if it should be unsigned. @@ -4130,77 +4024,67 @@ character in the standard execution set is supposed to be positive. Most compilers treat @code{char} as signed, but @code{char} is unsigned on the IBM S/390, RS6000, and PowerPC targets. -@item TARGET_COMPLEX_BIT -@findex TARGET_COMPLEX_BIT -Number of bits in a complex number; defaults to @code{2 * TARGET_FLOAT_BIT}. - -At present this macro is not used. - -@item TARGET_DOUBLE_BIT -@findex TARGET_DOUBLE_BIT -Number of bits in a double float; defaults to @code{8 * TARGET_CHAR_BIT}. - -@item TARGET_DOUBLE_COMPLEX_BIT -@findex TARGET_DOUBLE_COMPLEX_BIT -Number of bits in a double complex; defaults to @code{2 * TARGET_DOUBLE_BIT}. +@item int gdbarch_double_bit (@var{gdbarch}) +@findex gdbarch_double_bit +Number of bits in a double float; defaults to @w{@code{8 * TARGET_CHAR_BIT}}. -At present this macro is not used. +@item int gdbarch_float_bit (@var{gdbarch}) +@findex gdbarch_float_bit +Number of bits in a float; defaults to @w{@code{4 * TARGET_CHAR_BIT}}. -@item TARGET_FLOAT_BIT -@findex TARGET_FLOAT_BIT -Number of bits in a float; defaults to @code{4 * TARGET_CHAR_BIT}. +@item int gdbarch_int_bit (@var{gdbarch}) +@findex gdbarch_int_bit +Number of bits in an integer; defaults to @w{@code{4 * TARGET_CHAR_BIT}}. -@item TARGET_INT_BIT -@findex TARGET_INT_BIT -Number of bits in an integer; defaults to @code{4 * TARGET_CHAR_BIT}. +@item int gdbarch_long_bit (@var{gdbarch}) +@findex gdbarch_long_bit +Number of bits in a long integer; defaults to @w{@code{4 * TARGET_CHAR_BIT}}. -@item TARGET_LONG_BIT -@findex TARGET_LONG_BIT -Number of bits in a long integer; defaults to @code{4 * TARGET_CHAR_BIT}. - -@item TARGET_LONG_DOUBLE_BIT -@findex TARGET_LONG_DOUBLE_BIT +@item int gdbarch_long_double_bit (@var{gdbarch}) +@findex gdbarch_long_double_bit Number of bits in a long double float; -defaults to @code{2 * TARGET_DOUBLE_BIT}. - -@item TARGET_LONG_LONG_BIT -@findex TARGET_LONG_LONG_BIT -Number of bits in a long long integer; defaults to @code{2 * TARGET_LONG_BIT}. - -@item TARGET_PTR_BIT -@findex TARGET_PTR_BIT -Number of bits in a pointer; defaults to @code{TARGET_INT_BIT}. - -@item TARGET_SHORT_BIT -@findex TARGET_SHORT_BIT -Number of bits in a short integer; defaults to @code{2 * TARGET_CHAR_BIT}. - -@item TARGET_READ_PC -@findex TARGET_READ_PC -@itemx TARGET_WRITE_PC (@var{val}, @var{pid}) -@findex TARGET_WRITE_PC -@anchor{TARGET_WRITE_PC} +defaults to @w{@code{2 * gdbarch_double_bit (@var{gdbarch})}}. + +@item int gdbarch_long_long_bit (@var{gdbarch}) +@findex gdbarch_long_long_bit +Number of bits in a long long integer; defaults to +@w{@code{2 * gdbarch_long_bit (@var{gdbarch})}}. + +@item int gdbarch_ptr_bit (@var{gdbarch}) +@findex gdbarch_ptr_bit +Number of bits in a pointer; defaults to +@w{@code{gdbarch_int_bit (@var{gdbarch})}}. + +@item int gdbarch_short_bit (@var{gdbarch}) +@findex gdbarch_short_bit +Number of bits in a short integer; defaults to @w{@code{2 * TARGET_CHAR_BIT}}. + +@item CORE_ADDR gdbarch_read_pc (@var{gdbarch}, @var{regcache}) +@findex gdbarch_read_pc +@itemx gdbarch_write_pc (@var{gdbarch}, @var{regcache}, @var{val}) +@findex gdbarch_write_pc +@anchor{gdbarch_write_pc} @itemx TARGET_READ_SP @findex TARGET_READ_SP @itemx TARGET_READ_FP @findex TARGET_READ_FP -@findex read_pc -@findex write_pc +@findex gdbarch_read_pc +@findex gdbarch_write_pc @findex read_sp @findex read_fp -@anchor{TARGET_READ_SP} These change the behavior of @code{read_pc}, -@code{write_pc}, and @code{read_sp}. For most targets, these may be +@anchor{TARGET_READ_SP} These change the behavior of @code{gdbarch_read_pc}, +@code{gdbarch_write_pc}, and @code{read_sp}. For most targets, these may be left undefined. @value{GDBN} will call the read and write register functions with the relevant @code{_REGNUM} argument. -These macros are useful when a target keeps one of these registers in a -hard to get at place; for example, part in a segment register and part -in an ordinary register. +These macros and functions are useful when a target keeps one of these +registers in a hard to get at place; for example, part in a segment register +and part in an ordinary register. -@xref{unwind_sp}, which replaces @code{TARGET_READ_SP}. +@xref{gdbarch_unwind_sp}, which replaces @code{TARGET_READ_SP}. -@item TARGET_VIRTUAL_FRAME_POINTER(@var{pc}, @var{regp}, @var{offsetp}) -@findex TARGET_VIRTUAL_FRAME_POINTER +@item void gdbarch_virtual_frame_pointer (@var{gdbarch}, @var{pc}, @var{frame_regnum}, @var{frame_offset}) +@findex gdbarch_virtual_frame_pointer Returns a @code{(register, offset)} pair representing the virtual frame pointer in use at the code address @var{pc}. If virtual frame pointers are not used, a default definition simply returns @@ -4211,10 +4095,10 @@ If non-zero, the target has support for hardware-assisted watchpoints. @xref{Algorithms, watchpoints}, for more details and other related macros. -@item TARGET_PRINT_INSN (@var{addr}, @var{info}) -@findex TARGET_PRINT_INSN +@item int gdbarch_print_insn (@var{gdbarch}, @var{vma}, @var{info}) +@findex gdbarch_print_insn This is the function used by @value{GDBN} to print an assembly -instruction. It prints the instruction at address @var{addr} in +instruction. It prints the instruction at address @var{vma} in debugged memory and returns the length of the instruction, in bytes. If a target doesn't define its own printing routine, it defaults to an accessor function for the global pointer @@ -4224,10 +4108,10 @@ the @code{opcodes} library (@pxref{Support Libraries, ,Opcodes}). @file{include/dis-asm.h} used to pass information to the instruction decoding routine. -@item struct frame_id unwind_dummy_id (struct frame_info *@var{frame}) -@findex unwind_dummy_id -@anchor{unwind_dummy_id} Given @var{frame} return a @code{struct -frame_id} that uniquely identifies an inferior function call's dummy +@item frame_id gdbarch_unwind_dummy_id (@var{gdbarch}, @var{frame}) +@findex gdbarch_unwind_dummy_id +@anchor{gdbarch_unwind_dummy_id} Given @var{frame} return a @w{@code{struct +frame_id}} that uniquely identifies an inferior function call's dummy frame. The value returned must match the dummy frame stack value previously saved using @code{SAVE_DUMMY_FRAME_TOS}. @xref{SAVE_DUMMY_FRAME_TOS}. @@ -4244,10 +4128,9 @@ other compilers. This method has been deprecated in favour of @code{gdbarch_return_value} (@pxref{gdbarch_return_value}). -@item VALUE_TO_REGISTER(@var{type}, @var{regnum}, @var{from}, @var{to}) -@findex VALUE_TO_REGISTER -Convert a value of type @var{type} into the raw contents of register -@var{regnum}'s. +@item void gdbarch_value_to_register (@var{gdbarch}, @var{frame}, @var{type}, @var{buf}) +@findex gdbarch_value_to_register +Convert a value of type @var{type} into the raw contents of a register. @xref{Target Architecture Definition, , Using Different Register and Memory Data Representations}. @item VARIABLES_INSIDE_BLOCK (@var{desc}, @var{gcc_p}) @@ -4259,9 +4142,6 @@ nonzero. @var{desc} is the value of @code{n_desc} from the presence of either the @code{GCC_COMPILED_SYMBOL} or the @code{GCC2_COMPILED_SYMBOL}. By default, this is 0. -@item OS9K_VARIABLES_INSIDE_BLOCK (@var{desc}, @var{gcc_p}) -@findex OS9K_VARIABLES_INSIDE_BLOCK -Similarly, for OS/9000. Defaults to 1. @end table Motorola M68K target conditionals. @@ -4274,8 +4154,8 @@ not defined, it will default to @code{0xf}. @item REMOTE_BPT_VECTOR Defaults to @code{1}. -@item NAME_OF_MALLOC -@findex NAME_OF_MALLOC +@item const char *gdbarch_name_of_malloc (@var{gdbarch}) +@findex gdbarch_name_of_malloc A string containing the name of the function to call in order to allocate some memory in the inferior. The default value is "malloc". @@ -4339,168 +4219,6 @@ instruction needed; etc.). Then write a @file{@var{arch}/tm-@var{os}.h} that just @code{#include}s @file{tm-@var{arch}.h} and @file{config/tm-@var{os}.h}. - -@node Converting Targets to Multi-arch -@section Converting an existing Target Architecture to Multi-arch -@cindex converting targets to multi-arch - -This section describes the current accepted best practice for converting -an existing target architecture to the multi-arch framework. - -The process consists of generating, testing, posting and committing a -sequence of patches. Each patch must contain a single change, for -instance: - -@itemize @bullet - -@item -Directly convert a group of functions into macros (the conversion does -not change the behavior of any of the functions). - -@item -Replace a non-multi-arch with a multi-arch mechanism (e.g., -@code{FRAME_INFO}). - -@item -Enable multi-arch level one. - -@item -Delete one or more files. - -@end itemize - -@noindent -There isn't a size limit on a patch, however, a developer is strongly -encouraged to keep the patch size down. - -Since each patch is well defined, and since each change has been tested -and shows no regressions, the patches are considered @emph{fairly} -obvious. Such patches, when submitted by developers listed in the -@file{MAINTAINERS} file, do not need approval. Occasional steps in the -process may be more complicated and less clear. The developer is -expected to use their judgment and is encouraged to seek advice as -needed. - -@subsection Preparation - -The first step is to establish control. Build (with @option{-Werror} -enabled) and test the target so that there is a baseline against which -the debugger can be compared. - -At no stage can the test results regress or @value{GDBN} stop compiling -with @option{-Werror}. - -@subsection Add the multi-arch initialization code - -The objective of this step is to establish the basic multi-arch -framework. It involves - -@itemize @bullet - -@item -The addition of a @code{@var{arch}_gdbarch_init} function@footnote{The -above is from the original example and uses K&R C. @value{GDBN} -has since converted to ISO C but lets ignore that.} that creates -the architecture: -@smallexample -static struct gdbarch * -d10v_gdbarch_init (info, arches) - struct gdbarch_info info; - struct gdbarch_list *arches; -@{ - struct gdbarch *gdbarch; - /* there is only one d10v architecture */ - if (arches != NULL) - return arches->gdbarch; - gdbarch = gdbarch_alloc (&info, NULL); - return gdbarch; -@} -@end smallexample -@noindent -@emph{} - -@item -A per-architecture dump function to print any architecture specific -information: -@smallexample -static void -mips_dump_tdep (struct gdbarch *current_gdbarch, - struct ui_file *file) -@{ - @dots{} code to print architecture specific info @dots{} -@} -@end smallexample - -@item -A change to @code{_initialize_@var{arch}_tdep} to register this new -architecture: -@smallexample -void -_initialize_mips_tdep (void) -@{ - gdbarch_register (bfd_arch_mips, mips_gdbarch_init, - mips_dump_tdep); -@end smallexample - -@item -Add the macro @code{GDB_MULTI_ARCH}, defined as 0 (zero), to the file@* -@file{config/@var{arch}/tm-@var{arch}.h}. - -@end itemize - -@subsection Update multi-arch incompatible mechanisms - -Some mechanisms do not work with multi-arch. They include: - -@table @code -@item FRAME_FIND_SAVED_REGS -Replaced with @code{DEPRECATED_FRAME_INIT_SAVED_REGS} -@end table - -@noindent -At this stage you could also consider converting the macros into -functions. - -@subsection Prepare for multi-arch level to one - -Temporally set @code{GDB_MULTI_ARCH} to @code{GDB_MULTI_ARCH_PARTIAL} -and then build and start @value{GDBN} (the change should not be -committed). @value{GDBN} may not build, and once built, it may die with -an internal error listing the architecture methods that must be -provided. - -Fix any build problems (patch(es)). - -Convert all the architecture methods listed, which are only macros, into -functions (patch(es)). - -Update @code{@var{arch}_gdbarch_init} to set all the missing -architecture methods and wrap the corresponding macros in @code{#if -!GDB_MULTI_ARCH} (patch(es)). - -@subsection Set multi-arch level one - -Change the value of @code{GDB_MULTI_ARCH} to GDB_MULTI_ARCH_PARTIAL (a -single patch). - -Any problems with throwing ``the switch'' should have been fixed -already. - -@subsection Convert remaining macros - -Suggest converting macros into functions (and setting the corresponding -architecture method) in small batches. - -@subsection Set multi-arch level to two - -This should go smoothly. - -@subsection Delete the TM file - -The @file{tm-@var{arch}.h} can be deleted. @file{@var{arch}.mt} and -@file{configure.in} updated. - - @node Target Descriptions @chapter Target Descriptions @cindex target descriptions @@ -4901,20 +4619,20 @@ Define this if the native-dependent code will provide its own routines @file{infptrace.c} is included in this configuration, the default routines in @file{infptrace.c} are used for these functions. -@item FP0_REGNUM -@findex FP0_REGNUM -This macro is normally defined to be the number of the first floating +@item int gdbarch_fp0_regnum (@var{gdbarch}) +@findex gdbarch_fp0_regnum +This functions normally returns the number of the first floating point register, if the machine has such registers. As such, it would appear only in target-specific code. However, @file{/proc} support uses this to decide whether floats are in use on this target. -@item GET_LONGJMP_TARGET -@findex GET_LONGJMP_TARGET +@item int gdbarch_get_longjmp_target (@var{gdbarch}) +@findex gdbarch_get_longjmp_target For most machines, this is a target-dependent parameter. On the DECstation and the Iris, this is a native-dependent parameter, since @file{setjmp.h} is needed to define it. -This macro determines the target PC address that @code{longjmp} will jump to, +This function determines the target PC address that @code{longjmp} will jump to, assuming that we have just stopped at a longjmp breakpoint. It takes a @code{CORE_ADDR *} as argument, and stores the target PC value through this pointer. It examines the current state of the machine as needed. @@ -4923,20 +4641,6 @@ pointer. It examines the current state of the machine as needed. An x86-based machine can define this to use the generic x86 watchpoint support; see @ref{Algorithms, I386_USE_GENERIC_WATCHPOINTS}. -@item KERNEL_U_ADDR -@findex KERNEL_U_ADDR -Define this to the address of the @code{u} structure (the ``user -struct'', also known as the ``u-page'') in kernel virtual memory. @value{GDBN} -needs to know this so that it can subtract this address from absolute -addresses in the upage, that are obtained via ptrace or from core files. -On systems that don't need this value, set it to zero. - -@item KERNEL_U_ADDR_HPUX -@findex KERNEL_U_ADDR_HPUX -Define this to cause @value{GDBN} to determine the address of @code{u} at -runtime, by using HP-style @code{nlist} on the kernel's image in the -root directory. - @item ONE_PROCESS_WRITETEXT @findex ONE_PROCESS_WRITETEXT Define this to be able to, when a breakpoint insertion fails, warn the @@ -4948,10 +4652,6 @@ Defines the format for the name of a @file{/proc} device. Should be defined in @file{nm.h} @emph{only} in order to override the default definition in @file{procfs.c}. -@item REGISTER_U_ADDR -@findex REGISTER_U_ADDR -Defines the offset of the registers in the ``u area''. - @item SHELL_COMMAND_CONCAT @findex SHELL_COMMAND_CONCAT If defined, is a string to prefix on the shell command used to start the @@ -4982,29 +4682,12 @@ the shell execs, and once when the program itself execs. If the actual number of traps is something other than 2, then define this macro to expand into the number expected. -@item U_REGS_OFFSET -@findex U_REGS_OFFSET -This is the offset of the registers in the upage. It need only be -defined if the generic ptrace register access routines in -@file{infptrace.c} are being used (that is, @file{infptrace.c} is -configured in, and @code{FETCH_INFERIOR_REGISTERS} is not defined). If -the default value from @file{infptrace.c} is good enough, leave it -undefined. - -The default value means that u.u_ar0 @emph{points to} the location of -the registers. I'm guessing that @code{#define U_REGS_OFFSET 0} means -that @code{u.u_ar0} @emph{is} the location of the registers. - @item CLEAR_SOLIB @findex CLEAR_SOLIB See @file{objfiles.c}. -@item DEBUG_PTRACE -@findex DEBUG_PTRACE -Define this to debug @code{ptrace} calls. @end table - @node Support Libraries @chapter Support Libraries |