diff options
| -rw-r--r-- | gas/NEWS | 2 | ||||
| -rw-r--r-- | gas/config/tc-aarch64.c | 1 | ||||
| -rw-r--r-- | gas/doc/c-aarch64.texi | 2 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 3 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 3 |
5 files changed, 9 insertions, 2 deletions
@@ -19,7 +19,7 @@ Extension) and BRBE (Branch Record Buffer Extension) system registers for AArch64. -* Add support for Armv8-R AArch64. +* Add support for Armv8-R and Armv8.7-A AArch64. * Add support for Intel TDX instructions. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index fac571e..d17d118 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -9033,6 +9033,7 @@ static const struct aarch64_arch_option_table aarch64_archs[] = { {"armv8.4-a", AARCH64_ARCH_V8_4}, {"armv8.5-a", AARCH64_ARCH_V8_5}, {"armv8.6-a", AARCH64_ARCH_V8_6}, + {"armv8.7-a", AARCH64_ARCH_V8_7}, {"armv8-r", AARCH64_ARCH_V8_R}, {NULL, AARCH64_ARCH_NONE} }; diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 3dc9828..526e808 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -106,7 +106,7 @@ issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized: @code{armv8-a}, @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a} -@code{armv8.5-a}, @code{armv8.6-a}, and @code{armv8-r}. +@code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, and @code{armv8-r}. If both @option{-mcpu} and @option{-march} are specified, the assembler will use the setting for @option{-mcpu}. If neither are diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 4462648..a5f9e71 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -50,6 +50,7 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10) #define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */ #define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */ +#define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */ #define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */ #define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */ #define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */ @@ -128,6 +129,8 @@ typedef uint32_t aarch64_insn; AARCH64_FEATURE_V8_6 \ | AARCH64_FEATURE_BFLOAT16 \ | AARCH64_FEATURE_I8MM) +#define AARCH64_ARCH_V8_7 AARCH64_FEATURE (AARCH64_ARCH_V8_6, \ + AARCH64_FEATURE_V8_7) #define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \ AARCH64_FEATURE_V8_R) \ & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR)) diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 1cecaea..16d008d 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2395,6 +2395,8 @@ static const aarch64_feature_set aarch64_feature_sve2bitperm = AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0); static const aarch64_feature_set aarch64_feature_v8_6 = AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0); +static const aarch64_feature_set aarch64_feature_v8_7 = + AARCH64_FEATURE (AARCH64_FEATURE_V8_7, 0); static const aarch64_feature_set aarch64_feature_i8mm = AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_I8MM, 0); static const aarch64_feature_set aarch64_feature_i8mm_sve = @@ -2453,6 +2455,7 @@ static const aarch64_feature_set aarch64_feature_v8_r = #define F64MM_SVE &aarch64_feature_f64mm_sve #define I8MM &aarch64_feature_i8mm #define ARMV8_R &aarch64_feature_v8_r +#define ARMV8_7 &aarch64_feature_v8_7 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } |