diff options
| -rw-r--r-- | sim/arm/ChangeLog | 31 | ||||
| -rw-r--r-- | sim/arm/armcopro.c | 8 | ||||
| -rw-r--r-- | sim/arm/armdefs.h | 6 | ||||
| -rw-r--r-- | sim/arm/armfpe.h | 11 | ||||
| -rw-r--r-- | sim/arm/arminit.c | 6 | ||||
| -rw-r--r-- | sim/arm/armopts.h | 8 | ||||
| -rw-r--r-- | sim/arm/armos.c | 22 | ||||
| -rw-r--r-- | sim/arm/armos.h | 6 | ||||
| -rw-r--r-- | sim/arm/armrdi.c | 6 | ||||
| -rw-r--r-- | sim/arm/armsupp.c | 14 | ||||
| -rw-r--r-- | sim/arm/armvirt.c | 18 | ||||
| -rw-r--r-- | sim/arm/bag.c | 6 | ||||
| -rw-r--r-- | sim/arm/bag.h | 6 | ||||
| -rw-r--r-- | sim/arm/communicate.c | 6 | ||||
| -rw-r--r-- | sim/arm/communicate.h | 6 | ||||
| -rw-r--r-- | sim/arm/dbg_conf.h | 7 | ||||
| -rw-r--r-- | sim/arm/dbg_cp.h | 6 | ||||
| -rw-r--r-- | sim/arm/dbg_hif.h | 6 | ||||
| -rw-r--r-- | sim/arm/dbg_rdi.h | 6 | ||||
| -rw-r--r-- | sim/arm/gdbhost.c | 6 | ||||
| -rw-r--r-- | sim/arm/gdbhost.h | 6 | ||||
| -rw-r--r-- | sim/arm/iwmmxt.c | 160 | ||||
| -rw-r--r-- | sim/arm/iwmmxt.h | 2 | ||||
| -rw-r--r-- | sim/arm/kid.c | 6 | ||||
| -rw-r--r-- | sim/arm/main.c | 6 | ||||
| -rw-r--r-- | sim/arm/maverick.c | 184 | ||||
| -rw-r--r-- | sim/arm/parent.c | 8 | ||||
| -rw-r--r-- | sim/arm/thumbemu.c | 90 | ||||
| -rw-r--r-- | sim/arm/wrapper.c | 15 |
29 files changed, 348 insertions, 320 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog index acdb659..cdeef1a 100644 --- a/sim/arm/ChangeLog +++ b/sim/arm/ChangeLog @@ -1,3 +1,34 @@ +2015-07-14 Nick Clifton <nickc@redhat.com> + + * armcopro.c: Remove extraneous whitespace. + * armdefs.h: Likewise. + * armfpe.h: Likewise. + * arminit.c: Likewise. + * armopts.h: Likewise. + * armos.c: Likewise. + * armos.h: Likewise. + * armrdi.c: Likewise. + * armsupp.c: Likewise. + * armvirt.c: Likewise. + * bag.c: Likewise. + * bag.h: Likewise. + * communicate.c: Likewise. + * communicate.h: Likewise. + * dbg_conf.h: Likewise. + * dbg_cp.h: Likewise. + * dbg_hif.h: Likewise. + * dbg_rdi.h: Likewise. + * gdbhost.c: Likewise. + * gdbhost.h: Likewise. + * iwmmxt.c: Likewise. + * iwmmxt.h: Likewise. + * kid.c: Likewise. + * main.c: Likewise. + * maverick.c: Likewise. + * parent.c: Likewise. + * thumbemu.c: Likewise. + * wrapper.c: Likewise. + 2015-07-02 Nick Clifton <nickc@redhat.com> * Makefile.in (SIM_EXTRA_CFLAGS): Revert previous delta. diff --git a/sim/arm/armcopro.c b/sim/arm/armcopro.c index 4c5da24..9227fc0 100644 --- a/sim/arm/armcopro.c +++ b/sim/arm/armcopro.c @@ -1,16 +1,16 @@ /* armcopro.c -- co-processor interface: ARM6 Instruction Emulator. Copyright (C) 1994, 2000 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -114,7 +114,7 @@ check_cp15_access (ARMul_State * state, /* CRm must be 0. Opcode_2 can be anything. */ if (CRm != 0) return ARMul_CANT; - break; + break; case 2: case 3: /* CRm must be 0. Opcode_2 must be zero. */ diff --git a/sim/arm/armdefs.h b/sim/arm/armdefs.h index 4e19a62..4595e56 100644 --- a/sim/arm/armdefs.h +++ b/sim/arm/armdefs.h @@ -1,16 +1,16 @@ /* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/armfpe.h b/sim/arm/armfpe.h index c38ca80..c9e9f86 100644 --- a/sim/arm/armfpe.h +++ b/sim/arm/armfpe.h @@ -1,23 +1,22 @@ /* armfpe.h -- ARMulator pre-compiled FPE: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ /* Array containing the Floating Point Emualtor (FPE). */ - - -unsigned long fpecode[] = { +unsigned long fpecode[] = +{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/sim/arm/arminit.c b/sim/arm/arminit.c index 38b8f40..dd7808a 100644 --- a/sim/arm/arminit.c +++ b/sim/arm/arminit.c @@ -1,16 +1,16 @@ /* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/armopts.h b/sim/arm/armopts.h index 53946fc..57dc749 100644 --- a/sim/arm/armopts.h +++ b/sim/arm/armopts.h @@ -1,20 +1,20 @@ /* armopts.h -- ARMulator configuration options: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ -/* Define one of ARM60 or ARM61 */ +/* Define one of ARM60 or ARM61. */ #ifndef ARM60 #ifndef ARM61 #define ARM60 diff --git a/sim/arm/armos.c b/sim/arm/armos.c index c222e2e..6adfd94 100644 --- a/sim/arm/armos.c +++ b/sim/arm/armos.c @@ -1,16 +1,16 @@ /* armos.c -- ARMulator OS interface: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -157,7 +157,7 @@ ARMul_OSInit (ARMul_State * state) exit (15); } } - + OSptr = (struct OSblock *) state->OSptr; OSptr->ErrorP = 0; state->Reg[13] = ADDRSUPERSTACK; /* Set up a stack for the current mode... */ @@ -166,11 +166,11 @@ ARMul_OSInit (ARMul_State * state) ARMul_SetReg (state, UNDEF32MODE, 13, ADDRSUPERSTACK);/* ...and for undef 32 mode... */ ARMul_SetReg (state, SYSTEMMODE, 13, ADDRSUPERSTACK);/* ...and for system mode. */ instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8); /* Load pc from soft vector */ - + for (i = ARMul_ResetV; i <= ARMFIQV; i += 4) /* Write hardware vectors. */ ARMul_WriteWord (state, i, instr); - + SWI_vector_installed = 0; for (i = ARMul_ResetV; i <= ARMFIQV + 4; i += 4) @@ -626,7 +626,7 @@ ARMul_OSHandleSWI (ARMul_State * state, ARMword number) returning -1 in r0 to the caller. If GDB is then used to resume the system call the reason code will now be -1. */ return TRUE; - + /* Unimplemented reason codes. */ case AngelSWI_Reason_ReadC: case AngelSWI_Reason_TmpNam: @@ -777,7 +777,7 @@ ARMul_OSHandleSWI (ARMul_State * state, ARMword number) state->EndCondition = RDIError_SoftwareInterrupt; state->Emulate = FALSE; return FALSE; - } + } case 0x90: /* Reset. */ case 0x92: /* SWI. */ @@ -799,7 +799,7 @@ ARMul_OSHandleSWI (ARMul_State * state, ARMword number) returning -1 in r0 to the caller. If GDB is then used to resume the system call the reason code will now be -1. */ return TRUE; - + case 0x180001: /* RedBoot's Syscall SWI in ARM mode. */ if (swi_mask & SWI_MASK_REDBOOT) { @@ -887,11 +887,11 @@ ARMul_OSHandleSWI (ARMul_State * state, ARMword number) } break; } - + default: unhandled = TRUE; } - + if (unhandled) { if (SWI_vector_installed) diff --git a/sim/arm/armos.h b/sim/arm/armos.h index bcd5e57..393ee50 100644 --- a/sim/arm/armos.h +++ b/sim/arm/armos.h @@ -1,16 +1,16 @@ /* armos.h -- ARMulator OS definitions: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/armrdi.c b/sim/arm/armrdi.c index 5cdd4dd..e9ef77d 100644 --- a/sim/arm/armrdi.c +++ b/sim/arm/armrdi.c @@ -1,16 +1,16 @@ /* armrdi.c -- ARMulator RDI interface: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/armsupp.c b/sim/arm/armsupp.c index e2bbf53..3ff4bf9 100644 --- a/sim/arm/armsupp.c +++ b/sim/arm/armsupp.c @@ -1134,7 +1134,7 @@ handle_VFP_op (ARMul_State * state, ARMword instr) { if (trace) fprintf (stderr, " VFP: VMLS: %g = %g - %g * %g\n", - VFP_dval (dest) - val, + VFP_dval (dest) - val, VFP_dval (dest), VFP_dval (srcN), VFP_dval (srcM)); VFP_dval (dest) -= val; } @@ -1142,7 +1142,7 @@ handle_VFP_op (ARMul_State * state, ARMword instr) { if (trace) fprintf (stderr, " VFP: VMLA: %g = %g + %g * %g\n", - VFP_dval (dest) + val, + VFP_dval (dest) + val, VFP_dval (dest), VFP_dval (srcN), VFP_dval (srcM)); VFP_dval (dest) += val; } @@ -1155,7 +1155,7 @@ handle_VFP_op (ARMul_State * state, ARMword instr) { if (trace) fprintf (stderr, " VFP: VMLS: %g = %g - %g * %g\n", - VFP_fval (dest) - val, + VFP_fval (dest) - val, VFP_fval (dest), VFP_fval (srcN), VFP_fval (srcM)); VFP_fval (dest) -= val; } @@ -1163,7 +1163,7 @@ handle_VFP_op (ARMul_State * state, ARMword instr) { if (trace) fprintf (stderr, " VFP: VMLA: %g = %g + %g * %g\n", - VFP_fval (dest) + val, + VFP_fval (dest) + val, VFP_fval (dest), VFP_fval (srcN), VFP_fval (srcM)); VFP_fval (dest) += val; } @@ -1345,7 +1345,7 @@ handle_VFP_op (ARMul_State * state, ARMword instr) if (BIT (8)) { ARMdval src = VFP_dval (srcM); - + VFP_dval (dest) = fabs (src); if (trace) fprintf (stderr, " VFP: VABS (%g) = %g\n", src, VFP_dval (dest)); @@ -1402,7 +1402,7 @@ handle_VFP_op (ARMul_State * state, ARMword instr) if (BIT (16) == 0) { ARMdval src = VFP_dval (srcM); - + if (isinf (res) && isinf (src)) { if (res > 0.0 && src > 0.0) @@ -1442,7 +1442,7 @@ handle_VFP_op (ARMul_State * state, ARMword instr) if (BIT (16) == 0) { ARMfval src = VFP_fval (srcM); - + if (isinf (res) && isinf (src)) { if (res > 0.0 && src > 0.0) diff --git a/sim/arm/armvirt.c b/sim/arm/armvirt.c index 31ff8d8..c5af8d6 100644 --- a/sim/arm/armvirt.c +++ b/sim/arm/armvirt.c @@ -1,26 +1,26 @@ /* armvirt.c -- ARMulator virtual memory interace: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ /* This file contains a complete ARMulator memory model, modelling a -"virtual memory" system. A much simpler model can be found in armfast.c, -and that model goes faster too, but has a fixed amount of memory. This -model's memory has 64K pages, allocated on demand from a 64K entry page -table. The routines PutWord and GetWord implement this. Pages are never -freed as they might be needed again. A single area of memory may be -defined to generate aborts. */ + "virtual memory" system. A much simpler model can be found in armfast.c, + and that model goes faster too, but has a fixed amount of memory. This + model's memory has 64K pages, allocated on demand from a 64K entry page + table. The routines PutWord and GetWord implement this. Pages are never + freed as they might be needed again. A single area of memory may be + defined to generate aborts. */ #include "armopts.h" #include "armos.h" diff --git a/sim/arm/bag.c b/sim/arm/bag.c index 35f2953..f1b6a2c 100644 --- a/sim/arm/bag.c +++ b/sim/arm/bag.c @@ -1,16 +1,16 @@ /* bag.c -- ARMulator support code: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/bag.h b/sim/arm/bag.h index 83bb530..6a237c2 100644 --- a/sim/arm/bag.h +++ b/sim/arm/bag.h @@ -1,16 +1,16 @@ /* bag.h -- ARMulator support code: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/communicate.c b/sim/arm/communicate.c index e00b3cf..4d97647 100644 --- a/sim/arm/communicate.c +++ b/sim/arm/communicate.c @@ -1,16 +1,16 @@ /* communicate.c -- ARMulator RDP comms code: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/communicate.h b/sim/arm/communicate.h index 4ab676b..e234246 100644 --- a/sim/arm/communicate.h +++ b/sim/arm/communicate.h @@ -1,16 +1,16 @@ /* communicate.h -- ARMulator comms support defns: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/dbg_conf.h b/sim/arm/dbg_conf.h index 39c0a40..27c486c 100644 --- a/sim/arm/dbg_conf.h +++ b/sim/arm/dbg_conf.h @@ -1,21 +1,20 @@ /* dbg_conf.h -- ARMulator debug interface: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ #ifndef Dbg_Conf__h - #define Dbg_Conf__h typedef struct Dbg_ConfigBlock diff --git a/sim/arm/dbg_cp.h b/sim/arm/dbg_cp.h index 05638e2..640d1f2 100644 --- a/sim/arm/dbg_cp.h +++ b/sim/arm/dbg_cp.h @@ -1,16 +1,16 @@ /* dbg_cp.h -- ARMulator debug interface: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/dbg_hif.h b/sim/arm/dbg_hif.h index 686ed30..a4c48c2 100644 --- a/sim/arm/dbg_hif.h +++ b/sim/arm/dbg_hif.h @@ -1,16 +1,16 @@ /* dbg_hif.h -- ARMulator debug interface: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/dbg_rdi.h b/sim/arm/dbg_rdi.h index d7a3862..34e4354 100644 --- a/sim/arm/dbg_rdi.h +++ b/sim/arm/dbg_rdi.h @@ -1,16 +1,16 @@ /* dbg_rdi.h -- ARMulator RDI interface: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/gdbhost.c b/sim/arm/gdbhost.c index 5fca60d..aacaacc 100644 --- a/sim/arm/gdbhost.c +++ b/sim/arm/gdbhost.c @@ -1,16 +1,16 @@ /* gdbhost.c -- ARMulator RDP to gdb comms code: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/gdbhost.h b/sim/arm/gdbhost.h index c38c971..f24fb60 100644 --- a/sim/arm/gdbhost.h +++ b/sim/arm/gdbhost.h @@ -1,16 +1,16 @@ /* gdbhost.h -- ARMulator to gdb interface: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/iwmmxt.c b/sim/arm/iwmmxt.c index fd94d00..50a22a7 100644 --- a/sim/arm/iwmmxt.c +++ b/sim/arm/iwmmxt.c @@ -1,7 +1,7 @@ /* iwmmxt.c -- Intel(r) Wireless MMX(tm) technology co-processor interface. Copyright (C) 2002-2015 Free Software Foundation, Inc. Contributed by matthew green (mrg@redhat.com). - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or @@ -25,7 +25,7 @@ /* #define DEBUG 1 */ -/* Intel(r) Wireless MMX(tm) technology co-processor. +/* Intel(r) Wireless MMX(tm) technology co-processor. It uses co-processor numbers (0 and 1). There are 16 vector registers wRx and 16 control registers wCx. Co-processors 0 and 1 are used in MCR/MRC to access wRx and wCx respectively. */ @@ -231,7 +231,7 @@ Add32 (ARMword a1, same sign, but the result is a different sign. */ * overflow_ptr = ( ( (result & sign_mask) && !(a1 & sign_mask) && !(a2 & sign_mask)) || (!(result & sign_mask) && (a1 & sign_mask) && (a2 & sign_mask))); - + return result; } @@ -495,7 +495,7 @@ static signed short IwmmxtSaturateS16 (signed int val, int * sat) { signed short rv; - + if (val < -0x8000) { rv = - 0x8000; @@ -541,7 +541,7 @@ static signed long IwmmxtSaturateS32 (signed long long val, int * sat) { signed long rv; - + if (val < -0x80000000LL) { rv = -0x80000000; @@ -616,7 +616,7 @@ TANDC (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "tandc\n"); -#endif +#endif /* The Rd field must be r15. */ if (BITS (12, 15) != 15) @@ -654,7 +654,7 @@ TANDC (ARMul_State * state, ARMword instr) ARMul_UndefInstr (state, instr); return ARMul_DONE; } - + ARMul_SetCPSR (state, cpsr); return ARMul_DONE; @@ -671,7 +671,7 @@ TBCST (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "tbcst\n"); -#endif +#endif Rn = state->Reg [BITS (12, 15)]; if (BITS (12, 15) == 15) @@ -717,7 +717,7 @@ TEXTRC (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "textrc\n"); -#endif +#endif /* The Rd field must be r15. */ if (BITS (12, 15) != 15) @@ -744,7 +744,7 @@ TEXTRC (ARMul_State * state, ARMword instr) ARMul_UndefInstr (state, instr); return ARMul_DONE; } - + cpsr |= wCBITS (wCASF, selector, selector + 3) << 28; ARMul_SetCPSR (state, cpsr); @@ -764,12 +764,12 @@ TEXTRM (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "textrm\n"); -#endif +#endif wRn = BITS (16, 19); sign = BIT (3); offset = BITS (0, 2); - + switch (BITS (22, 23)) { case Bqual: @@ -844,7 +844,7 @@ TINSR (ARMul_State * state, ARMword instr) switch (offset & 3) { - case 0: wR [wRd] = data | (wRBITS (wRd, 16, 63) << 16); break; + case 0: wR [wRd] = data | (wRBITS (wRd, 16, 63) << 16); break; case 1: wR [wRd] = wRBITS (wRd, 0, 15) | (data << 16) | (wRBITS (wRd, 32, 63) << 32); break; case 2: wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32) | (wRBITS (wRd, 48, 63) << 48); break; case 3: wR [wRd] = wRBITS (wRd, 0, 47) | (data << 48); break; @@ -878,7 +878,7 @@ TMCR (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "tmcr\n"); -#endif +#endif if (BITS (0, 3) != 0) return ARMul_CANT; @@ -899,14 +899,14 @@ TMCR (ARMul_State * state, ARMword instr) /* Writing to the MUP or CUP bits clears them. */ wC [wCon] &= ~ (val & 0x3); break; - + case wCSSF: /* Only the bottom 8 bits can be written to. The higher bits write as zero. */ wC [wCSSF] = (val & 0xff); wC [wCon] |= WCON_CUP; break; - + default: wC [wCreg] = val; wC [wCon] |= WCON_CUP; @@ -927,7 +927,7 @@ TMCRR (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "tmcrr\n"); -#endif +#endif if ((BITS (16, 19) == 15) || (BITS (12, 15) == 15)) return ARMul_CANT; @@ -949,7 +949,7 @@ TMIA (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "tmia\n"); -#endif +#endif if ((BITS (0, 3) == 15) || (BITS (12, 15) == 15)) { @@ -976,13 +976,13 @@ TMIAPH (ARMul_State * state, ARMword instr) signed long long r; ARMword Rm = state->Reg [BITS (0, 3)]; ARMword Rs = state->Reg [BITS (12, 15)]; - + if ((read_cp15_reg (15, 0, 1) & 3) != 3) return ARMul_CANT; #ifdef DEBUG fprintf (stderr, "tmiaph\n"); -#endif +#endif if (BITS (0, 3) == 15 || BITS (12, 15) == 15) { @@ -1000,7 +1000,7 @@ TMIAPH (ARMul_State * state, ARMword instr) r = result; r = EXTEND32 (r); - + wR [BITS (5, 8)] += r; a = SUBSTR (Rs, ARMword, 0, 15); @@ -1013,7 +1013,7 @@ TMIAPH (ARMul_State * state, ARMword instr) r = result; r = EXTEND32 (r); - + wR [BITS (5, 8)] += r; wC [wCon] |= WCON_MUP; @@ -1026,13 +1026,13 @@ TMIAxy (ARMul_State * state, ARMword instr) ARMword Rm; ARMword Rs; long long temp; - + if ((read_cp15_reg (15, 0, 1) & 3) != 3) return ARMul_CANT; #ifdef DEBUG fprintf (stderr, "tmiaxy\n"); -#endif +#endif if (BITS (0, 3) == 15 || BITS (12, 15) == 15) { @@ -1081,7 +1081,7 @@ TMOVMSK (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "tmovmsk\n"); -#endif +#endif /* The CRm field must be r0. */ if (BITS (0, 3) != 0) @@ -1133,7 +1133,7 @@ TMRC (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "tmrc\n"); -#endif +#endif if (BITS (0, 3) != 0) return ARMul_CANT; @@ -1154,7 +1154,7 @@ TMRRC (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "tmrrc\n"); -#endif +#endif if ((BITS (16, 19) == 15) || (BITS (12, 15) == 15) || (BITS (4, 11) != 0)) ARMul_UndefInstr (state, instr); @@ -1177,16 +1177,16 @@ TORC (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "torc\n"); -#endif +#endif /* The Rd field must be r15. */ if (BITS (12, 15) != 15) return ARMul_CANT; - + /* The CRn field must be r3. */ if (BITS (16, 19) != 3) return ARMul_CANT; - + /* The CRm field must be r0. */ if (BITS (0, 3) != 0) return ARMul_CANT; @@ -1215,7 +1215,7 @@ TORC (ARMul_State * state, ARMword instr) ARMul_UndefInstr (state, instr); return ARMul_DONE; } - + ARMul_SetCPSR (state, cpsr); return ARMul_DONE; @@ -1231,7 +1231,7 @@ WACC (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wacc\n"); -#endif +#endif wRn = BITS (16, 19); @@ -1281,7 +1281,7 @@ WADD (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wadd\n"); -#endif +#endif /* Add two numbers using the specified function, leaving setting the carry bit as required. */ @@ -1450,7 +1450,7 @@ WADD (ARMul_State * state, ARMword instr) wC [wCon] |= (WCON_MUP | WCON_CUP); SET_wCSSFvec (satrv); - + #undef ADDx return ARMul_DONE; @@ -1466,7 +1466,7 @@ WALIGNI (ARMword instr) #ifdef DEBUG fprintf (stderr, "waligni\n"); -#endif +#endif if (shift) wR [BITS (12, 15)] = @@ -1474,7 +1474,7 @@ WALIGNI (ARMword instr) | (wRBITS (BITS (0, 3), 0, shift) << ((64 - shift))); else wR [BITS (12, 15)] = wR [BITS (16, 19)]; - + wC [wCon] |= WCON_MUP; return ARMul_DONE; } @@ -1489,7 +1489,7 @@ WALIGNR (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "walignr\n"); -#endif +#endif if (shift) wR [BITS (12, 15)] = @@ -1513,14 +1513,14 @@ WAND (ARMword instr) #ifdef DEBUG fprintf (stderr, "wand\n"); -#endif +#endif result = wR [BITS (16, 19)] & wR [BITS (0, 3)]; wR [BITS (12, 15)] = result; SIMD64_SET (psr, (result == 0), SIMD_ZBIT); SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT); - + wC [wCASF] = psr; wC [wCon] |= (WCON_CUP | WCON_MUP); @@ -1538,14 +1538,14 @@ WANDN (ARMword instr) #ifdef DEBUG fprintf (stderr, "wandn\n"); -#endif +#endif result = wR [BITS (16, 19)] & ~ wR [BITS (0, 3)]; wR [BITS (12, 15)] = result; SIMD64_SET (psr, (result == 0), SIMD_ZBIT); SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT); - + wC [wCASF] = psr; wC [wCon] |= (WCON_CUP | WCON_MUP); @@ -1566,7 +1566,7 @@ WAVG2 (ARMword instr) #ifdef DEBUG fprintf (stderr, "wavg2\n"); -#endif +#endif #define AVG2x(x, y, m) (((wRBITS (BITS (16, 19), (x), (y)) & (m)) \ + (wRBITS (BITS ( 0, 3), (x), (y)) & (m)) \ @@ -1611,7 +1611,7 @@ WCMPEQ (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wcmpeq\n"); -#endif +#endif switch (BITS (22, 23)) { @@ -1670,7 +1670,7 @@ WCMPGT (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wcmpgt\n"); -#endif +#endif switch (BITS (22, 23)) { @@ -1681,7 +1681,7 @@ WCMPGT (ARMul_State * state, ARMword instr) for (i = 0; i < 8; i++) { signed char a, b; - + a = wRBYTE (BITS (16, 19), i); b = wRBYTE (BITS (0, 3), i); @@ -1826,7 +1826,7 @@ Compute_Iwmmxt_Address (ARMul_State * state, ARMword instr, int * pFailed) /* Writeback into R15 is UNPREDICTABLE. */ #ifdef DEBUG fprintf (stderr, "iWMMXt: writeback into r15\n"); -#endif +#endif * pFailed = 1; } else @@ -1848,7 +1848,7 @@ Compute_Iwmmxt_Address (ARMul_State * state, ARMword instr, int * pFailed) { #ifdef DEBUG fprintf (stderr, "iWMMXt: undefined addressing mode\n"); -#endif +#endif * pFailed = 1; } } @@ -1861,7 +1861,7 @@ static ARMdword Iwmmxt_Load_Double_Word (ARMul_State * state, ARMword address) { ARMdword value; - + /* The address must be aligned on a 8 byte boundary. */ if (address & 0x7) { @@ -1911,7 +1911,7 @@ Iwmmxt_Load_Word (ARMul_State * state, ARMword address) else address &= ~ 3; } - + value = ARMul_LoadWordN (state, address); if (state->Aborted) @@ -2052,7 +2052,7 @@ WLDR (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wldr\n"); -#endif +#endif address = Compute_Iwmmxt_Address (state, instr, & failed); if (failed) @@ -2099,7 +2099,7 @@ WMAC (ARMword instr) #ifdef DEBUG fprintf (stderr, "wmac\n"); -#endif +#endif for (i = 0; i < 4; i++) { @@ -2154,7 +2154,7 @@ WMADD (ARMword instr) #ifdef DEBUG fprintf (stderr, "wmadd\n"); -#endif +#endif for (i = 0; i < 2; i++) { @@ -2216,7 +2216,7 @@ WMAX (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wmax\n"); -#endif +#endif switch (BITS (22, 23)) { @@ -2345,7 +2345,7 @@ WMIN (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wmin\n"); -#endif +#endif switch (BITS (22, 23)) { @@ -2459,7 +2459,7 @@ WMIN (ARMul_State * state, ARMword instr) wR [BITS (12, 15)] = r; wC [wCon] |= WCON_MUP; - + return ARMul_DONE; } @@ -2475,7 +2475,7 @@ WMUL (ARMword instr) #ifdef DEBUG fprintf (stderr, "wmul\n"); -#endif +#endif for (i = 0; i < 4; i++) if (BIT (21)) /* Signed. */ @@ -2527,14 +2527,14 @@ WOR (ARMword instr) #ifdef DEBUG fprintf (stderr, "wor\n"); -#endif +#endif result = wR [BITS (16, 19)] | wR [BITS (0, 3)]; wR [BITS (12, 15)] = result; SIMD64_SET (psr, (result == 0), SIMD_ZBIT); SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT); - + wC [wCASF] = psr; wC [wCon] |= (WCON_CUP | WCON_MUP); @@ -2556,8 +2556,8 @@ WPACK (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wpack\n"); -#endif - +#endif + switch (BITS (22, 23)) { case Hqual: @@ -2669,7 +2669,7 @@ WROR (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wror\n"); -#endif +#endif DECODE_G_BIT (state, instr, shift); @@ -2732,7 +2732,7 @@ WSAD (ARMword instr) #ifdef DEBUG fprintf (stderr, "wsad\n"); -#endif +#endif /* Z bit. */ r = BIT (20) ? 0 : (wR [BITS (12, 15)] & 0xffffffff); @@ -2772,7 +2772,7 @@ WSHUFH (ARMword instr) #ifdef DEBUG fprintf (stderr, "wshufh\n"); -#endif +#endif imm8 = (BITS (20, 23) << 4) | BITS (0, 3); @@ -2805,7 +2805,7 @@ WSLL (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wsll\n"); -#endif +#endif DECODE_G_BIT (state, instr, shift); @@ -2874,7 +2874,7 @@ WSRA (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wsra\n"); -#endif +#endif DECODE_G_BIT (state, instr, shift); @@ -2915,7 +2915,7 @@ WSRA (ARMul_State * state, ARMword instr) SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i); } break; - + case Dqual: if (shift > 63) r = (wR [BITS (16, 19)] & 0x8000000000000000ULL) ? 0xffffffffffffffffULL : 0; @@ -3020,7 +3020,7 @@ WSTR (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wstr\n"); #endif - + address = Compute_Iwmmxt_Address (state, instr, & failed); if (failed) return ARMul_CANT; @@ -3069,7 +3069,7 @@ WSUB (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wsub\n"); -#endif +#endif /* Subtract two numbers using the specified function, leaving setting the carry bit as required. */ @@ -3255,7 +3255,7 @@ WUNPCKEH (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wunpckeh\n"); -#endif +#endif switch (BITS (22, 23)) { @@ -3322,7 +3322,7 @@ WUNPCKEL (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wunpckel\n"); -#endif +#endif switch (BITS (22, 23)) { @@ -3390,7 +3390,7 @@ WUNPCKIH (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wunpckih\n"); -#endif +#endif switch (BITS (22, 23)) { @@ -3407,7 +3407,7 @@ WUNPCKIH (ARMul_State * state, ARMword instr) SIMD8_SET (psr, ZBIT8 (b), SIMD_ZBIT, (i * 2) + 1); } break; - + case Hqual: for (i = 0; i < 2; i++) { @@ -3459,7 +3459,7 @@ WUNPCKIL (ARMul_State * state, ARMword instr) #ifdef DEBUG fprintf (stderr, "wunpckil\n"); -#endif +#endif switch (BITS (22, 23)) { @@ -3525,14 +3525,14 @@ WXOR (ARMword instr) #ifdef DEBUG fprintf (stderr, "wxor\n"); -#endif +#endif result = wR [BITS (16, 19)] ^ wR [BITS (0, 3)]; wR [BITS (12, 15)] = result; SIMD64_SET (psr, (result == 0), SIMD_ZBIT); SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT); - + wC [wCASF] = psr; wC [wCon] |= (WCON_CUP | WCON_MUP); @@ -3560,7 +3560,7 @@ Process_Instruction (ARMul_State * state, ARMword instr) status = WMADD (instr); break; case 0x10e: case 0x50e: case 0x90e: case 0xd0e: - status = WUNPCKIL (state, instr); break; + status = WUNPCKIL (state, instr); break; case 0x10c: case 0x50c: case 0x90c: case 0xd0c: status = WUNPCKIH (state, instr); break; case 0x012: case 0x112: case 0x412: case 0x512: @@ -3626,7 +3626,7 @@ Process_Instruction (ARMul_State * state, ARMword instr) case 0x81a: case 0x91a: case 0xa1a: case 0xb1a: case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a: status = WSUB (state, instr); break; - case 0x01e: case 0x11e: case 0x21e: case 0x31e: + case 0x01e: case 0x11e: case 0x21e: case 0x31e: case 0x41e: case 0x51e: case 0x61e: case 0x71e: case 0x81e: case 0x91e: case 0xa1e: case 0xb1e: case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e: @@ -3643,8 +3643,8 @@ Process_Instruction (ARMul_State * state, ARMword instr) status = WPACK (state, instr); break; case 0x201: case 0x203: case 0x205: case 0x207: case 0x209: case 0x20b: case 0x20d: case 0x20f: - case 0x211: case 0x213: case 0x215: case 0x217: - case 0x219: case 0x21b: case 0x21d: case 0x21f: + case 0x211: case 0x213: case 0x215: case 0x217: + case 0x219: case 0x21b: case 0x21d: case 0x21f: switch (BITS (16, 19)) { case 0x0: status = TMIA (state, instr); break; @@ -3667,7 +3667,7 @@ Process_Instruction (ARMul_State * state, ARMword instr) int ARMul_HandleIwmmxt (ARMul_State * state, ARMword instr) -{ +{ int status = ARMul_BUSY; if (BITS (24, 27) == 0xe) diff --git a/sim/arm/iwmmxt.h b/sim/arm/iwmmxt.h index eab596b..aeb7f50 100644 --- a/sim/arm/iwmmxt.h +++ b/sim/arm/iwmmxt.h @@ -1,7 +1,7 @@ /* iwmmxt.h -- Intel(r) Wireless MMX(tm) technology co-processor interface. Copyright (C) 2002-2015 Free Software Foundation, Inc. Contributed by matthew green (mrg@redhat.com). - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or diff --git a/sim/arm/kid.c b/sim/arm/kid.c index 491f6c8..340b999 100644 --- a/sim/arm/kid.c +++ b/sim/arm/kid.c @@ -1,16 +1,16 @@ /* kid.c -- ARMulator RDP/RDI interface: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/main.c b/sim/arm/main.c index b63b371..2ce1af1 100644 --- a/sim/arm/main.c +++ b/sim/arm/main.c @@ -1,16 +1,16 @@ /* main.c -- top level of ARMulator: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ diff --git a/sim/arm/maverick.c b/sim/arm/maverick.c index 1b0dca9..9c3ea08 100644 --- a/sim/arm/maverick.c +++ b/sim/arm/maverick.c @@ -1,7 +1,7 @@ /* maverick.c -- Cirrus/DSP co-processor interface. Copyright (C) 2003-2015 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldyh@redhat.com). - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or @@ -47,7 +47,7 @@ struct maverick_regs int i; float f; } upper; - + union { int i; @@ -93,7 +93,7 @@ cirrus_not_implemented (char * insn) { fprintf (stderr, "Cirrus instruction '%s' not implemented.\n", insn); fprintf (stderr, "aborting!\n"); - + exit (1); } @@ -110,19 +110,19 @@ DSPMRC4 (ARMul_State * state ATTRIBUTE_UNUSED, printfdbg ("cfmvrdl\n"); printfdbg ("\tlower half=0x%x\n", DSPregs[SRC1_REG].lower.i); printfdbg ("\tentire thing=%g\n", mv_getRegDouble (SRC1_REG)); - + *value = (ARMword) DSPregs[SRC1_REG].lower.i; break; - + case 1: /* cfmvrdh */ /* Move upper half of a DF stored in a DSP reg into an Arm reg. */ printfdbg ("cfmvrdh\n"); printfdbg ("\tupper half=0x%x\n", DSPregs[SRC1_REG].upper.i); printfdbg ("\tentire thing=%g\n", mv_getRegDouble (SRC1_REG)); - + *value = (ARMword) DSPregs[SRC1_REG].upper.i; break; - + case 2: /* cfmvrs */ /* Move SF from upper half of a DSP register to an Arm register. */ *value = (ARMword) DSPregs[SRC1_REG].upper.i; @@ -130,7 +130,7 @@ DSPMRC4 (ARMul_State * state ATTRIBUTE_UNUSED, SRC1_REG, DSPregs[SRC1_REG].upper.f); break; - + #ifdef doesnt_work case 4: /* cfcmps */ { @@ -150,7 +150,7 @@ DSPMRC4 (ARMul_State * state ATTRIBUTE_UNUSED, *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); break; } - + case 5: /* cfcmpd */ { double a, b; @@ -177,7 +177,7 @@ DSPMRC4 (ARMul_State * state ATTRIBUTE_UNUSED, a = DSPregs[SRC1_REG].upper.f; b = DSPregs[SRC2_REG].upper.f; - + printfdbg ("cfcmps\n"); printfdbg ("\tcomparing %f and %f\n", a, b); @@ -197,10 +197,10 @@ DSPMRC4 (ARMul_State * state ATTRIBUTE_UNUSED, a = mv_getRegDouble (SRC1_REG); b = mv_getRegDouble (SRC2_REG); - + printfdbg ("cfcmpd\n"); printfdbg ("\tcomparing %g and %g\n", a, b); - + z = a == b; /* zero */ n = a < b; /* negative */ c = a > b; /* carry */ @@ -233,13 +233,13 @@ DSPMRC5 (ARMul_State * state ATTRIBUTE_UNUSED, DEST_REG, (int) *value); break; - + case 1: /* cfmvr64h */ /* Move upper half of 64bit int from Cirrus to Arm. */ *value = (ARMword) DSPregs[SRC1_REG].upper.i; printfdbg ("cfmvr64h <-- %d\n", (int) *value); break; - + case 4: /* cfcmp32 */ { int res; @@ -270,7 +270,7 @@ DSPMRC5 (ARMul_State * state ATTRIBUTE_UNUSED, *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); break; } - + case 5: /* cfcmp64 */ { long long res; @@ -302,7 +302,7 @@ DSPMRC5 (ARMul_State * state ATTRIBUTE_UNUSED, *value = (n << 31) | (z << 30) | (c << 29) | (v << 28); break; } - + default: fprintf (stderr, "unknown opcode in DSPMRC5 0x%x\n", instr); cirrus_not_implemented ("unknown"); @@ -323,27 +323,27 @@ DSPMRC6 (ARMul_State * state ATTRIBUTE_UNUSED, case 0: /* cfmval32 */ cirrus_not_implemented ("cfmval32"); break; - + case 1: /* cfmvam32 */ cirrus_not_implemented ("cfmvam32"); break; - + case 2: /* cfmvah32 */ cirrus_not_implemented ("cfmvah32"); break; - + case 3: /* cfmva32 */ cirrus_not_implemented ("cfmva32"); break; - + case 4: /* cfmva64 */ cirrus_not_implemented ("cfmva64"); break; - + case 5: /* cfmvsc32 */ cirrus_not_implemented ("cfmvsc32"); break; - + default: fprintf (stderr, "unknown opcode in DSPMRC6 0x%x\n", instr); cirrus_not_implemented ("unknown"); @@ -367,20 +367,20 @@ DSPMCR4 (ARMul_State * state, printfdbg ("cfmvdlr <-- 0x%x\n", (int) value); DSPregs[SRC1_REG].lower.i = (int) value; break; - + case 1: /* cfmvdhr */ /* Move the upper half of a DF value from an Arm register into the upper half of a Cirrus register. */ printfdbg ("cfmvdhr <-- 0x%x\n", (int) value); DSPregs[SRC1_REG].upper.i = (int) value; break; - + case 2: /* cfmvsr */ /* Move SF from Arm register into upper half of Cirrus register. */ printfdbg ("cfmvsr <-- 0x%x\n", (int) value); DSPregs[SRC1_REG].upper.i = (int) value; break; - + default: fprintf (stderr, "unknown opcode in DSPMCR4 0x%x\n", instr); cirrus_not_implemented ("unknown"); @@ -410,7 +410,7 @@ DSPMCR5 (ARMul_State * state, printfdbg ("cfmv64lr mvdx%d <-- 0x%x\n", SRC1_REG, (int) value); DSPregs[SRC1_REG].lower.i = (int) value; break; - + case 1: /* cfmv64hr */ /* Move upper half of a 64bit int from an ARM register into the upper half of a DSP register. */ @@ -419,7 +419,7 @@ DSPMCR5 (ARMul_State * state, (int) value); DSPregs[SRC1_REG].upper.i = (int) value; break; - + case 2: /* cfrshl32 */ printfdbg ("cfrshl32\n"); val.us = value; @@ -428,7 +428,7 @@ DSPMCR5 (ARMul_State * state, else DSPregs[SRC2_REG].lower.i = DSPregs[SRC1_REG].lower.i >> -value; break; - + case 3: /* cfrshl64 */ printfdbg ("cfrshl64\n"); val.us = value; @@ -437,7 +437,7 @@ DSPMCR5 (ARMul_State * state, else mv_setReg64int (SRC2_REG, mv_getReg64int (SRC1_REG) >> -value); break; - + default: fprintf (stderr, "unknown opcode in DSPMCR5 0x%x\n", instr); cirrus_not_implemented ("unknown"); @@ -458,27 +458,27 @@ DSPMCR6 (ARMul_State * state, case 0: /* cfmv32al */ cirrus_not_implemented ("cfmv32al"); break; - + case 1: /* cfmv32am */ cirrus_not_implemented ("cfmv32am"); break; - + case 2: /* cfmv32ah */ cirrus_not_implemented ("cfmv32ah"); break; - + case 3: /* cfmv32a */ cirrus_not_implemented ("cfmv32a"); break; - + case 4: /* cfmv64a */ cirrus_not_implemented ("cfmv64a"); break; - + case 5: /* cfmv32sc */ cirrus_not_implemented ("cfmv32sc"); break; - + default: fprintf (stderr, "unknown opcode in DSPMCR6 0x%x\n", instr); cirrus_not_implemented ("unknown"); @@ -501,14 +501,14 @@ DSPLDC4 (ARMul_State * state ATTRIBUTE_UNUSED, words = 0; return ARMul_DONE; } - + if (BIT (22)) { /* it's a long access, get two words */ /* cfldrd */ printfdbg ("cfldrd: %x (words = %d) (bigend = %d) DESTREG = %d\n", data, words, state->bigendSig, DEST_REG); - + if (words == 0) { if (state->bigendSig) @@ -523,14 +523,14 @@ DSPLDC4 (ARMul_State * state ATTRIBUTE_UNUSED, else DSPregs[DEST_REG].upper.i = (int) data; } - + ++ words; - + if (words == 2) { printfdbg ("\tmvd%d <-- mem = %g\n", DEST_REG, mv_getRegDouble (DEST_REG)); - + return ARMul_DONE; } else @@ -539,7 +539,7 @@ DSPLDC4 (ARMul_State * state ATTRIBUTE_UNUSED, else { /* Get just one word. */ - + /* cfldrs */ printfdbg ("cfldrs\n"); @@ -565,11 +565,11 @@ DSPLDC5 (ARMul_State * state ATTRIBUTE_UNUSED, words = 0; return ARMul_DONE; } - + if (BIT (22)) { /* It's a long access, get two words. */ - + /* cfldr64 */ printfdbg ("cfldr64: %d\n", data); @@ -587,14 +587,14 @@ DSPLDC5 (ARMul_State * state ATTRIBUTE_UNUSED, else DSPregs[DEST_REG].upper.i = (int) data; } - + ++ words; - + if (words == 2) { printfdbg ("\tmvdx%d <-- mem = %lld\n", DEST_REG, mv_getReg64int (DEST_REG)); - + return ARMul_DONE; } else @@ -603,10 +603,10 @@ DSPLDC5 (ARMul_State * state ATTRIBUTE_UNUSED, else { /* Get just one word. */ - + /* cfldr32 */ printfdbg ("cfldr32 mvfx%d <-- %d\n", DEST_REG, (int) data); - + /* 32bit ints should be sign extended to 64bits when loaded. */ mv_setReg64int (DEST_REG, (long long) data); @@ -627,7 +627,7 @@ DSPSTC4 (ARMul_State * state ATTRIBUTE_UNUSED, words = 0; return ARMul_DONE; } - + if (BIT (22)) { /* It's a long access, get two words. */ @@ -648,14 +648,14 @@ DSPSTC4 (ARMul_State * state ATTRIBUTE_UNUSED, else *data = (ARMword) DSPregs[DEST_REG].upper.i; } - + ++ words; - + if (words == 2) { printfdbg ("\tmem = mvd%d = %g\n", DEST_REG, mv_getRegDouble (DEST_REG)); - + return ARMul_DONE; } else @@ -687,7 +687,7 @@ DSPSTC5 (ARMul_State * state ATTRIBUTE_UNUSED, words = 0; return ARMul_DONE; } - + if (BIT (22)) { /* It's a long access, store two words. */ @@ -708,14 +708,14 @@ DSPSTC5 (ARMul_State * state ATTRIBUTE_UNUSED, else *data = (ARMword) DSPregs[DEST_REG].upper.i; } - + ++ words; - + if (words == 2) { printfdbg ("\tmem = mvd%d = %lld\n", DEST_REG, mv_getReg64int (DEST_REG)); - + return ARMul_DONE; } else @@ -726,7 +726,7 @@ DSPSTC5 (ARMul_State * state ATTRIBUTE_UNUSED, /* Store just one word. */ /* cfstr32 */ *data = (ARMword) DSPregs[DEST_REG].lower.i; - + printfdbg ("cfstr32 MEM = %d\n", (int) *data); return ARMul_DONE; @@ -754,7 +754,7 @@ DSPCDP4 (ARMul_State * state, DSPregs[SRC1_REG].upper.f); DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f; break; - + case 1: /* cfcpyd */ printfdbg ("cfcpyd mvd%d = mvd%d = %g\n", DEST_REG, @@ -762,7 +762,7 @@ DSPCDP4 (ARMul_State * state, mv_getRegDouble (SRC1_REG)); mv_setRegDouble (DEST_REG, mv_getRegDouble (SRC1_REG)); break; - + case 2: /* cfcvtds */ printfdbg ("cfcvtds mvf%d = (float) mvd%d = %f\n", DEST_REG, @@ -770,7 +770,7 @@ DSPCDP4 (ARMul_State * state, (float) mv_getRegDouble (SRC1_REG)); DSPregs[DEST_REG].upper.f = (float) mv_getRegDouble (SRC1_REG); break; - + case 3: /* cfcvtsd */ printfdbg ("cfcvtsd mvd%d = mvf%d = %g\n", DEST_REG, @@ -778,7 +778,7 @@ DSPCDP4 (ARMul_State * state, (double) DSPregs[SRC1_REG].upper.f); mv_setRegDouble (DEST_REG, (double) DSPregs[SRC1_REG].upper.f); break; - + case 4: /* cfcvt32s */ printfdbg ("cfcvt32s mvf%d = mvfx%d = %f\n", DEST_REG, @@ -786,7 +786,7 @@ DSPCDP4 (ARMul_State * state, (float) DSPregs[SRC1_REG].lower.i); DSPregs[DEST_REG].upper.f = (float) DSPregs[SRC1_REG].lower.i; break; - + case 5: /* cfcvt32d */ printfdbg ("cfcvt32d mvd%d = mvfx%d = %g\n", DEST_REG, @@ -794,7 +794,7 @@ DSPCDP4 (ARMul_State * state, (double) DSPregs[SRC1_REG].lower.i); mv_setRegDouble (DEST_REG, (double) DSPregs[SRC1_REG].lower.i); break; - + case 6: /* cfcvt64s */ printfdbg ("cfcvt64s mvf%d = mvdx%d = %f\n", DEST_REG, @@ -802,7 +802,7 @@ DSPCDP4 (ARMul_State * state, (float) mv_getReg64int (SRC1_REG)); DSPregs[DEST_REG].upper.f = (float) mv_getReg64int (SRC1_REG); break; - + case 7: /* cfcvt64d */ printfdbg ("cfcvt64d mvd%d = mvdx%d = %g\n", DEST_REG, @@ -821,11 +821,11 @@ DSPCDP4 (ARMul_State * state, DEST_REG, SRC1_REG, DSPregs[SRC1_REG].upper.f * DSPregs[SRC2_REG].upper.f); - + DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f * DSPregs[SRC2_REG].upper.f; break; - + case 1: /* cfmuld */ printfdbg ("cfmuld mvd%d = mvd%d = %g\n", DEST_REG, @@ -836,7 +836,7 @@ DSPCDP4 (ARMul_State * state, mv_getRegDouble (SRC1_REG) * mv_getRegDouble (SRC2_REG)); break; - + default: fprintf (stderr, "unknown opcode in DSPCDP4 0x%x\n", instr); cirrus_not_implemented ("unknown"); @@ -856,7 +856,7 @@ DSPCDP4 (ARMul_State * state, SRC1_REG, DSPregs[DEST_REG].upper.f); break; - + case 1: /* cfabsd */ mv_setRegDouble (DEST_REG, (mv_getRegDouble (SRC1_REG) < 0.0 ? @@ -867,7 +867,7 @@ DSPCDP4 (ARMul_State * state, SRC1_REG, mv_getRegDouble (DEST_REG)); break; - + case 2: /* cfnegs */ DSPregs[DEST_REG].upper.f = -DSPregs[SRC1_REG].upper.f; printfdbg ("cfnegs mvf%d = -mvf%d = %f\n", @@ -875,7 +875,7 @@ DSPCDP4 (ARMul_State * state, SRC1_REG, DSPregs[DEST_REG].upper.f); break; - + case 3: /* cfnegd */ mv_setRegDouble (DEST_REG, -mv_getRegDouble (SRC1_REG)); @@ -883,7 +883,7 @@ DSPCDP4 (ARMul_State * state, DEST_REG, mv_getRegDouble (DEST_REG)); break; - + case 4: /* cfadds */ DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f + DSPregs[SRC2_REG].upper.f; @@ -893,7 +893,7 @@ DSPCDP4 (ARMul_State * state, SRC2_REG, DSPregs[DEST_REG].upper.f); break; - + case 5: /* cfaddd */ mv_setRegDouble (DEST_REG, mv_getRegDouble (SRC1_REG) @@ -904,7 +904,7 @@ DSPCDP4 (ARMul_State * state, SRC2_REG, mv_getRegDouble (DEST_REG)); break; - + case 6: /* cfsubs */ DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f - DSPregs[SRC2_REG].upper.f; @@ -914,7 +914,7 @@ DSPCDP4 (ARMul_State * state, SRC2_REG, DSPregs[DEST_REG].upper.f); break; - + case 7: /* cfsubd */ mv_setRegDouble (DEST_REG, mv_getRegDouble (SRC1_REG) @@ -978,7 +978,7 @@ DSPCDP5 (ARMul_State * state, SRC2_REG, DSPregs[DEST_REG].lower.i); break; - + case 1: /* cfmul64 */ mv_setReg64int (DEST_REG, mv_getReg64int (SRC1_REG) @@ -989,7 +989,7 @@ DSPCDP5 (ARMul_State * state, SRC2_REG, mv_getReg64int (DEST_REG)); break; - + case 2: /* cfmac32 */ DSPregs[DEST_REG].lower.i += DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i; @@ -999,7 +999,7 @@ DSPCDP5 (ARMul_State * state, SRC2_REG, DSPregs[DEST_REG].lower.i); break; - + case 3: /* cfmsc32 */ DSPregs[DEST_REG].lower.i -= DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i; @@ -1009,7 +1009,7 @@ DSPCDP5 (ARMul_State * state, SRC2_REG, DSPregs[DEST_REG].lower.i); break; - + case 4: /* cfcvts32 */ /* fixme: this should round */ DSPregs[DEST_REG].lower.i = (int) DSPregs[SRC1_REG].upper.f; @@ -1018,7 +1018,7 @@ DSPCDP5 (ARMul_State * state, SRC1_REG, DSPregs[DEST_REG].lower.i); break; - + case 5: /* cfcvtd32 */ /* fixme: this should round */ DSPregs[DEST_REG].lower.i = (int) mv_getRegDouble (SRC1_REG); @@ -1027,7 +1027,7 @@ DSPCDP5 (ARMul_State * state, SRC1_REG, DSPregs[DEST_REG].lower.i); break; - + case 6: /* cftruncs32 */ DSPregs[DEST_REG].lower.i = (int) DSPregs[SRC1_REG].upper.f; printfdbg ("cftruncs32 mvfx%d = mvf%d = %d\n", @@ -1035,7 +1035,7 @@ DSPCDP5 (ARMul_State * state, SRC1_REG, DSPregs[DEST_REG].lower.i); break; - + case 7: /* cftruncd32 */ DSPregs[DEST_REG].lower.i = (int) mv_getRegDouble (SRC1_REG); printfdbg ("cftruncd32 mvfx%d = mvd%d = %d\n", @@ -1049,7 +1049,7 @@ DSPCDP5 (ARMul_State * state, case 2: /* cfsh64 */ printfdbg ("cfsh64\n"); - + if (shift < 0) /* Negative shift is a right shift. */ mv_setReg64int (DEST_REG, @@ -1073,7 +1073,7 @@ DSPCDP5 (ARMul_State * state, SRC2_REG, DSPregs[DEST_REG].lower.i); break; - + case 1: /* cfabs64 */ mv_setReg64int (DEST_REG, (mv_getReg64int (SRC1_REG) < 0 @@ -1085,7 +1085,7 @@ DSPCDP5 (ARMul_State * state, SRC2_REG, mv_getReg64int (DEST_REG)); break; - + case 2: /* cfneg32 */ DSPregs[DEST_REG].lower.i = -DSPregs[SRC1_REG].lower.i; printfdbg ("cfneg32 mvfx%d = -mvfx%d = %d\n", @@ -1094,7 +1094,7 @@ DSPCDP5 (ARMul_State * state, SRC2_REG, DSPregs[DEST_REG].lower.i); break; - + case 3: /* cfneg64 */ mv_setReg64int (DEST_REG, -mv_getReg64int (SRC1_REG)); printfdbg ("cfneg64 mvdx%d = -mvdx%d = %lld\n", @@ -1103,7 +1103,7 @@ DSPCDP5 (ARMul_State * state, SRC2_REG, mv_getReg64int (DEST_REG)); break; - + case 4: /* cfadd32 */ DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i + DSPregs[SRC2_REG].lower.i; @@ -1113,7 +1113,7 @@ DSPCDP5 (ARMul_State * state, SRC2_REG, DSPregs[DEST_REG].lower.i); break; - + case 5: /* cfadd64 */ mv_setReg64int (DEST_REG, mv_getReg64int (SRC1_REG) @@ -1124,7 +1124,7 @@ DSPCDP5 (ARMul_State * state, SRC2_REG, mv_getReg64int (DEST_REG)); break; - + case 6: /* cfsub32 */ DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i - DSPregs[SRC2_REG].lower.i; @@ -1134,7 +1134,7 @@ DSPCDP5 (ARMul_State * state, SRC2_REG, DSPregs[DEST_REG].lower.i); break; - + case 7: /* cfsub64 */ mv_setReg64int (DEST_REG, mv_getReg64int (SRC1_REG) @@ -1168,17 +1168,17 @@ DSPCDP6 (ARMul_State * state, /* cfmadd32 */ cirrus_not_implemented ("cfmadd32"); break; - + case 1: /* cfmsub32 */ cirrus_not_implemented ("cfmsub32"); break; - + case 2: /* cfmadda32 */ cirrus_not_implemented ("cfmadda32"); break; - + case 3: /* cfmsuba32 */ cirrus_not_implemented ("cfmsuba32"); diff --git a/sim/arm/parent.c b/sim/arm/parent.c index 4a052d7..ef33d3f 100644 --- a/sim/arm/parent.c +++ b/sim/arm/parent.c @@ -1,16 +1,16 @@ /* parent.c -- ARMulator RDP comms code: ARM6 Instruction Emulator. Copyright (C) 1994 Advanced RISC Machines Ltd. - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -102,7 +102,7 @@ panic_error: fprintf (stderr, "->debugger\n"); #endif - /* Inside this rather large if statement with simply pass on a complete + /* Inside this rather large if statement with simply pass on a complete message to the ARMulator. The reason we need to pass messages on one at a time is that we have to know whether the message is an OSOpReply or an info(stop), so that we can take different action in those diff --git a/sim/arm/thumbemu.c b/sim/arm/thumbemu.c index 40c365e..2d26bf6 100644 --- a/sim/arm/thumbemu.c +++ b/sim/arm/thumbemu.c @@ -137,7 +137,7 @@ ThumbExpandImm (ARMword tinstr) else { int ror = tBITS (7, 11); - + val = (1 << 7) | tBITS (0, 6); val = (val >> ror) | (val << (32 - ror)); } @@ -207,7 +207,7 @@ handle_T2_insn (ARMul_State * state, simm32 |= (-1 << 20); break; } - + case 1: /* B.W */ { ARMword imm10 = tBITS (0, 9); @@ -220,7 +220,7 @@ handle_T2_insn (ARMul_State * state, simm32 |= (-1 << 24); break; } - + case 2: /* BLX <label> */ { ARMword imm10h = tBITS (0, 9); @@ -258,7 +258,7 @@ handle_T2_insn (ARMul_State * state, fprintf (stderr, " pc changed to %x\n", state->Reg[15]); return; } - + switch (tBITS (5,12)) { case 0x29: // TST<c>.W <Rn>,<Rm>{,<shift>} @@ -400,7 +400,7 @@ handle_T2_insn (ARMul_State * state, break; } - case 0x50: + case 0x50: { ARMword Rd = ntBITS (8, 11); ARMword Rn = tBITS (0, 3); @@ -436,7 +436,7 @@ handle_T2_insn (ARMul_State * state, * pvalid = t_decoded; break; } - + case 0x51: // BIC{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>} { ARMword Rn = tBITS (0, 3); @@ -458,8 +458,8 @@ handle_T2_insn (ARMul_State * state, * pvalid = t_decoded; break; } - - case 0x52: + + case 0x52: { ARMword Rn = tBITS (0, 3); ARMword Rd = ntBITS (8, 11); @@ -539,7 +539,7 @@ handle_T2_insn (ARMul_State * state, break; } - case 0x54: + case 0x54: { ARMword Rn = tBITS (0, 3); ARMword Rd = ntBITS (8, 11); @@ -611,7 +611,7 @@ handle_T2_insn (ARMul_State * state, * ainstr |= ntBITS (0, 3); // Rm * pvalid = t_decoded; break; - + case 0x5B: // SBC{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>} { ARMword Rn = tBITS (0, 3); @@ -636,7 +636,7 @@ handle_T2_insn (ARMul_State * state, * pvalid = t_decoded; break; } - + case 0x5E: // RSB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} case 0x5D: // SUB{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>} { @@ -669,13 +669,13 @@ handle_T2_insn (ARMul_State * state, * pvalid = t_decoded; break; } - + case 0x9D: // NOP.W tASSERT (tBITS (0, 15) == 0xF3AF); tASSERT (ntBITS (0, 15) == 0x8000); * pvalid = t_branch; break; - + case 0x80: // AND case 0xA0: // TST { @@ -697,7 +697,7 @@ handle_T2_insn (ARMul_State * state, { // AND{S}<c> <Rd>,<Rn>,#<const> if (in_IT_block ()) - S = 0; + S = 0; state->Reg[Rd] = val; } @@ -726,7 +726,7 @@ handle_T2_insn (ARMul_State * state, * pvalid = t_resolved; break; } - + case 0xA2: case 0x82: // MOV{S}<c>.W <Rd>,#<const> { @@ -783,13 +783,13 @@ handle_T2_insn (ARMul_State * state, if (in_IT_block ()) S = 0; } - + if (S) ARMul_NegZero (state, result); * pvalid = t_resolved; break; } - + case 0xA8: // CMN case 0x88: // ADD { @@ -838,7 +838,7 @@ handle_T2_insn (ARMul_State * state, break; } - case 0xAA: + case 0xAA: case 0x8A: // ADC{S}<c> <Rd>,<Rn>,#<const> { ARMword Rn = tBITS (0, 3); @@ -879,7 +879,7 @@ handle_T2_insn (ARMul_State * state, * pvalid = t_branch; break; } - + case 0xAB: case 0x8B: // SBC{S}<c> <Rd>,<Rn>,#<const> { @@ -940,7 +940,7 @@ handle_T2_insn (ARMul_State * state, } else { - // SUB{S}<c>.W <Rd>,<Rn>,#<const> + // SUB{S}<c>.W <Rd>,<Rn>,#<const> if (in_IT_block ()) S = 0; @@ -997,7 +997,7 @@ handle_T2_insn (ARMul_State * state, CLEARV; } } - + * pvalid = t_branch; break; } @@ -1038,7 +1038,7 @@ handle_T2_insn (ARMul_State * state, tASSERT (tBIT (4) == 0); tASSERT (ntBIT (15) == 0); - + /* Note the ARM ARM indicates special cases for Rn == 15 (ADR) and Rn == 13 (SUB SP minus immediate), but these are implemented in exactly the same way as the normal SUBW insn. */ @@ -1047,7 +1047,7 @@ handle_T2_insn (ARMul_State * state, * pvalid = t_resolved; break; } - + case 0xB6: case 0x96: // MOVT<c> <Rd>,#<imm16> { @@ -1098,7 +1098,7 @@ handle_T2_insn (ARMul_State * state, // BFI<c> <Rd>,<Rn>,#<lsb>,#<width> ARMword val = state->Reg[Rn] & (mask >> lsbit); - val <<= lsbit; + val <<= lsbit; state->Reg[Rd] &= ~ mask; state->Reg[Rd] |= val; } @@ -1118,7 +1118,7 @@ handle_T2_insn (ARMul_State * state, * ainstr |= tBITS (0, 3); // Rn * pvalid = t_decoded; break; - + case 0xC0: // STRB case 0xC4: // LDRB { @@ -1157,7 +1157,7 @@ handle_T2_insn (ARMul_State * state, tASSERT (! (Rt == 15 && P && !U && !W)); tASSERT (! (P && U && !W)); - + /* LDRB<c> <Rt>,[<Rn>,#-<imm8>] => 1111 1000 0001 rrrr LDRB<c> <Rt>,[<Rn>],#+/-<imm8> => 1111 1000 0001 rrrr LDRB<c> <Rt>,[<Rn>,#+/-<imm8>]! => 1111 1000 0001 rrrr */ @@ -1239,7 +1239,7 @@ handle_T2_insn (ARMul_State * state, tASSERT (! (P && U && ! W)); tASSERT (! (!P && U && W && Rn == 13 && imm8 == 4 && ntBIT (11) == 0)); tASSERT (! (P && !U && W && Rn == 13 && imm8 == 4 && ntBIT (11))); - + // LDR<c> <Rt>,[<Rn>,#-<imm8>] // LDR<c> <Rt>,[<Rn>],#+/-<imm8> // LDR<c> <Rt>,[<Rn>,#+/-<imm8>]! @@ -1275,7 +1275,7 @@ handle_T2_insn (ARMul_State * state, * ainstr = 0xE92D0000; * ainstr |= (1 << Rt); - + Rt = Rn = 0; } else @@ -1412,7 +1412,7 @@ handle_T2_insn (ARMul_State * state, * pvalid = t_branch; break; } - + case 0xC6: // LDR.W/STR.W { ARMword Rn = tBITS (0, 3); @@ -1453,7 +1453,7 @@ handle_T2_insn (ARMul_State * state, // LDRSB<c> <Rt>,<label> ARMword imm12 = ntBITS (0, 11); address += (U ? imm12 : - imm12); - } + } else if (U) { // LDRSB<c> <Rt>,[<Rn>,#<imm12>] @@ -1494,7 +1494,7 @@ handle_T2_insn (ARMul_State * state, * pvalid = t_resolved; break; } - + case 0xC9: case 0xCD:// LDRSH { @@ -1548,7 +1548,7 @@ handle_T2_insn (ARMul_State * state, break; } - case 0x0D0: + case 0x0D0: { ARMword Rm = ntBITS (0, 3); ARMword Rd = ntBITS (8, 11); @@ -1598,7 +1598,7 @@ handle_T2_insn (ARMul_State * state, break; } - case 0xD2: + case 0xD2: tASSERT (ntBITS (12, 15) == 15); if (ntBIT (7)) { @@ -1622,7 +1622,7 @@ handle_T2_insn (ARMul_State * state, * ainstr |= (ntBITS (8, 11) << 12); // Rd * pvalid = t_decoded; break; - + case 0xD3: // ROR{S}<c>.W <Rd>,<Rn>,<Rm> tASSERT (ntBITS (12, 15) == 15); tASSERT (ntBITS (4, 7) == 0); @@ -1634,7 +1634,7 @@ handle_T2_insn (ARMul_State * state, * ainstr |= (tBITS (0, 3) << 0); // Rn * pvalid = t_decoded; break; - + case 0xD4: { ARMword Rn = tBITS (0, 3); @@ -1647,9 +1647,9 @@ handle_T2_insn (ARMul_State * state, { // REV<c>.W <Rd>,<Rm> ARMword val = state->Reg[Rm]; - + tASSERT (Rm == Rn); - + state->Reg [Rd] = (val >> 24) | ((val >> 8) & 0xFF00) @@ -1741,7 +1741,7 @@ handle_T2_insn (ARMul_State * state, if (ntBITS (4, 7) == 1) { // MLS<c> <Rd>,<Rn>,<Rm>,<Ra> - state->Reg[Rd] = state->Reg[Ra] - (state->Reg[Rn] * state->Reg[Rm]); + state->Reg[Rd] = state->Reg[Ra] - (state->Reg[Rn] * state->Reg[Rm]); } else { @@ -1769,7 +1769,7 @@ handle_T2_insn (ARMul_State * state, * ainstr |= tBITS (0, 3); // Rn * pvalid = t_decoded; break; - + case 0xDD: // UMULL tASSERT (tBIT (4) == 0); tASSERT (ntBITS (4, 7) == 0); @@ -1780,7 +1780,7 @@ handle_T2_insn (ARMul_State * state, * ainstr |= tBITS (0, 3); // Rn * pvalid = t_decoded; break; - + case 0xDF: // UMLAL tASSERT (tBIT (4) == 0); tASSERT (ntBITS (4, 7) == 0); @@ -1792,7 +1792,7 @@ handle_T2_insn (ARMul_State * state, * pvalid = t_decoded; break; - default: + default: fprintf (stderr, "(op = %x) ", tBITS (5,12)); tASSERT (0); return; @@ -1860,7 +1860,7 @@ handle_v6_thumb_insn (ARMul_State * state, state->Reg[Rd] += state->Reg[Rm]; break; } - + case 0x4600: // MOV<c> <Rd>,<Rm> { // instr [15, 8] = 0100 0110 @@ -1916,7 +1916,7 @@ handle_v6_thumb_insn (ARMul_State * state, state->Reg [tBITS (0, 2)] = (val >> 16) | (val << 16); break; } - + case 0xb660: /* cpsie */ case 0xb670: /* cpsid */ case 0xbac0: /* revsh */ @@ -2017,7 +2017,7 @@ ARMul_ThumbDecode (ARMul_State * state, return t_branch; } - + old_tinstr = tinstr; if (trace) fprintf (stderr, "pc: %x, Thumb instr: %x", pc & ~1, tinstr); @@ -2072,7 +2072,7 @@ ARMul_ThumbDecode (ARMul_State * state, * ainstr |= tBITS (8, 10) << 16; * ainstr |= tBITS (0, 7); break; - + case 6: case 7: * ainstr = tBIT (11) diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c index b494354..b9b4a0b 100644 --- a/sim/arm/wrapper.c +++ b/sim/arm/wrapper.c @@ -114,7 +114,7 @@ struct maverick_regs int i; float f; } upper; - + union { int i; @@ -664,7 +664,7 @@ sim_fetch_register (SIM_DESC sd ATTRIBUTE_UNUSED, len -= 4; memory += 4; regval = 0; - } + } return length; } @@ -710,7 +710,7 @@ sim_target_parse_command_line (int argc, char ** argv) trace = 1; continue; } - + if (strcmp (ptr, "-z") == 0) { /* Remove this option from the argv array. */ @@ -721,7 +721,7 @@ sim_target_parse_command_line (int argc, char ** argv) trace_funcs = 1; continue; } - + if (strcmp (ptr, "-d") == 0) { /* Remove this option from the argv array. */ @@ -742,14 +742,14 @@ sim_target_parse_command_line (int argc, char ** argv) for (arg = i; arg < argc; arg ++) argv[arg] = argv[arg + 1]; argc --; - + ptr = argv[i]; } else ptr += sizeof SWI_SWITCH; swi_mask = 0; - + while (* ptr) { int i; @@ -773,7 +773,7 @@ sim_target_parse_command_line (int argc, char ** argv) if (* ptr != 0) fprintf (stderr, "Ignoring swi options: %s\n", ptr); - + /* Remove this option from the argv array. */ for (arg = i; arg < argc; arg ++) argv[arg] = argv[arg + 1]; @@ -907,7 +907,6 @@ sim_open (SIM_OPEN_KIND kind, "Missing argument to -m option\n"); return NULL; } - } } |