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-rw-r--r--gdb/ChangeLog13
-rw-r--r--gdb/config/mips/tm-mips.h5
-rw-r--r--gdb/config/mips/tm-tx39.h2
-rw-r--r--gdb/config/mips/tm-tx39l.h2
-rw-r--r--gdb/config/mips/tm-vr4100.h1
-rw-r--r--gdb/config/mips/tm-vr4xxx.h1
-rw-r--r--gdb/config/mips/tm-vr4xxxel.h1
-rw-r--r--gdb/mips-tdep.c9
8 files changed, 24 insertions, 10 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index a6ac185..e5f23c2 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,16 @@
+Thu Jun 8 14:23:12 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * config/mips/tm-vr4xxxel.h, config/mips/tm-vr4xxx.h,
+ config/mips/tm-vr4100.h, config/mips/tm-tx39l.h,
+ config/mips/tm-tx39.h: Delete definition of
+ MIPS_DEFAULT_FPU. Enable multi-arch.
+ * mips-tdep.c: (mips_gdbarch_init): The bfd_mach_mips3900 has no
+ FPU.
+
+ * config/mips/tm-mips.h (MIPS_FPU_SINGLE_REGSIZE):
+ (MIPS_FPU_DOUBLE_REGSIZE): Move from here.
+ * mips-tdep.c: To here. Change to an enum.
+
Wed Jun 7 18:27:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
* configure.in (DEFAULT_BFD_ARCH, DEFAULT_BFD_VEC): Use config.bfd
diff --git a/gdb/config/mips/tm-mips.h b/gdb/config/mips/tm-mips.h
index 4aa77f3..ff95113 100644
--- a/gdb/config/mips/tm-mips.h
+++ b/gdb/config/mips/tm-mips.h
@@ -129,11 +129,6 @@ extern breakpoint_from_pc_fn mips_breakpoint_from_pc;
#define MIPS_REGSIZE 4
#endif
-/* The sizes of floating point registers. */
-
-#define MIPS_FPU_SINGLE_REGSIZE 4
-#define MIPS_FPU_DOUBLE_REGSIZE 8
-
/* Number of machine registers */
#ifndef NUM_REGS
diff --git a/gdb/config/mips/tm-tx39.h b/gdb/config/mips/tm-tx39.h
index 520db7b..c1d9cf7 100644
--- a/gdb/config/mips/tm-tx39.h
+++ b/gdb/config/mips/tm-tx39.h
@@ -17,8 +17,8 @@
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
+#define GDB_MULTI_ARCH 1
#define MIPS_EABI 1
-#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_NONE
#include "mips/tm-bigmips.h"
diff --git a/gdb/config/mips/tm-tx39l.h b/gdb/config/mips/tm-tx39l.h
index 30ba78a..802e41b 100644
--- a/gdb/config/mips/tm-tx39l.h
+++ b/gdb/config/mips/tm-tx39l.h
@@ -17,8 +17,8 @@
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
+#define GDB_MULTI_ARCH 1
#define MIPS_EABI 1
-#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_NONE
#include "mips/tm-mips.h"
diff --git a/gdb/config/mips/tm-vr4100.h b/gdb/config/mips/tm-vr4100.h
index 9c87619..faf0a96 100644
--- a/gdb/config/mips/tm-vr4100.h
+++ b/gdb/config/mips/tm-vr4100.h
@@ -18,7 +18,6 @@
Boston, MA 02111-1307, USA. */
#define MIPS_EABI 1
-#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_NONE
#define TARGET_PTR_BIT 64
#include "mips/tm-bigmips64.h"
diff --git a/gdb/config/mips/tm-vr4xxx.h b/gdb/config/mips/tm-vr4xxx.h
index 2878227..7d2a78a 100644
--- a/gdb/config/mips/tm-vr4xxx.h
+++ b/gdb/config/mips/tm-vr4xxx.h
@@ -18,6 +18,5 @@
Boston, MA 02111-1307, USA. */
#define GDB_MULTI_ARCH 1
-#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
#include "mips/tm-bigmips64.h"
diff --git a/gdb/config/mips/tm-vr4xxxel.h b/gdb/config/mips/tm-vr4xxxel.h
index c9eedc3..1347af7 100644
--- a/gdb/config/mips/tm-vr4xxxel.h
+++ b/gdb/config/mips/tm-vr4xxxel.h
@@ -18,6 +18,5 @@
Boston, MA 02111-1307, USA. */
#define GDB_MULTI_ARCH 1
-#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
#include "mips/tm-mips64.h"
diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c
index cf9ac59..971b04a 100644
--- a/gdb/mips-tdep.c
+++ b/gdb/mips-tdep.c
@@ -40,6 +40,14 @@
#include "elf-bfd.h"
+/* The sizes of floating point registers. */
+
+enum
+{
+ MIPS_FPU_SINGLE_REGSIZE = 4,
+ MIPS_FPU_DOUBLE_REGSIZE = 8
+};
+
/* All the possible MIPS ABIs. */
enum mips_abi
@@ -4030,6 +4038,7 @@ mips_gdbarch_init (info, arches)
&& info.bfd_arch_info->arch == bfd_arch_mips)
switch (info.bfd_arch_info->mach)
{
+ case bfd_mach_mips3900:
case bfd_mach_mips4100:
case bfd_mach_mips4111:
tdep->mips_fpu_type = MIPS_FPU_NONE;