diff options
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 10 |
2 files changed, 10 insertions, 5 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 85a2842..6b55f5c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2019-07-10 Hans-Peter Nilsson <hp@bitrange.com> + + * arm-dis.c (print_insn_coprocessor): Rename index to + index_operand. + 2019-07-05 Kito Cheng <kito.cheng@sifive.com> * riscv-opc.c (riscv_insn_types): Add r4 type. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 03aebb5..f3b1cc3 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -6767,23 +6767,23 @@ print_mve_vmov_index (struct disassemble_info *info, unsigned long given) unsigned long op1 = arm_decode_field (given, 21, 22); unsigned long op2 = arm_decode_field (given, 5, 6); unsigned long h = arm_decode_field (given, 16, 16); - unsigned long index, esize, targetBeat, idx; + unsigned long index_operand, esize, targetBeat, idx; void *stream = info->stream; fprintf_ftype func = info->fprintf_func; if ((op1 & 0x2) == 0x2) { - index = op2; + index_operand = op2; esize = 8; } else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1)) { - index = op2 >> 1; + index_operand = op2 >> 1; esize = 16; } else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0)) { - index = 0; + index_operand = 0; esize = 32; } else @@ -6793,7 +6793,7 @@ print_mve_vmov_index (struct disassemble_info *info, unsigned long given) } targetBeat = (op1 & 0x1) | (h << 1); - idx = index + targetBeat * (32/esize); + idx = index_operand + targetBeat * (32/esize); func (stream, "%lu", idx); } |