diff options
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/config/tc-arm.c | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/dfb.d | 15 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/dfb.s | 14 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 8 |
6 files changed, 55 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 3ad6f6e..149d896 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2020-06-08 Alex Coplan <alex.coplan@arm.com> + + * config/tc-arm.c (insns): Add dfb. + * testsuite/gas/arm/dfb.d: New test. + * testsuite/gas/arm/dfb.s: Input for test. + 2020-06-08 Nick Clifton <nickc@redhat.com> * testsuite/gas/cfi/cfi-i386-2.d: Skip for PE based targets. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index a693006..00fa2c7 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -24950,6 +24950,13 @@ static const struct asm_opcode insns[] = ldrexd, t_ldrexd), TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v8r +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v8r + +/* ARMv8-R instructions. */ + TUF("dfb", 57ff04c, f3bf8f4c, 0, (), noargs, noargs), /* Defined in V8 but is in undefined encoding space for earlier architectures. However earlier architectures are required to treat diff --git a/gas/testsuite/gas/arm/dfb.d b/gas/testsuite/gas/arm/dfb.d new file mode 100644 index 0000000..3cc434c --- /dev/null +++ b/gas/testsuite/gas/arm/dfb.d @@ -0,0 +1,15 @@ +#objdump: -dr + +.*: file format .* + +Disassembly of section .text: + +[0-9a-f]+ <f_a32>: +.*: f57ff04c dfb + +[0-9a-f]+ <f_t32>: +.*: f3bf 8f4c dfb +.*: bf18 it ne +.*: f3bf 8f4c dfbne +.*: bf08 it eq +.*: f3bf 8f4c dfbeq diff --git a/gas/testsuite/gas/arm/dfb.s b/gas/testsuite/gas/arm/dfb.s new file mode 100644 index 0000000..22e89b0 --- /dev/null +++ b/gas/testsuite/gas/arm/dfb.s @@ -0,0 +1,14 @@ +// Test file for ARMv8-R dfb. +.arch armv8-r +.syntax unified + +f_a32: + dfb + +.thumb +f_t32: + dfb + it ne + dfbne + it eq + dfbeq diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index d405787..e8714ed 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2020-06-08 Alex Coplan <alex.coplan@arm.com> + + * arm-dis.c (arm_opcodes): Add dfb. + (thumb32_opcodes): Add dfb. + 2020-06-08 Jan Beulich <jbeulich@suse.com> * i386-opc.h (reg_entry): Const-qualify reg_name field. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 79a3dc6..de62328 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -3685,6 +3685,10 @@ static const struct opcode32 arm_opcodes[] = {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 0xe320f010, 0xffffffff, "esb"}, + /* V8-R instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R), + 0xf57ff04c, 0xffffffff, "dfb"}, + /* V8 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0x0320f005, 0x0fffffff, "sevl"}, @@ -4735,6 +4739,10 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, + /* V8-R instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R), + 0xf3bf8f4c, 0xffffffff, "dfb%c"}, + /* CRC32 instructions. */ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"}, |