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-rw-r--r--sim/m32r/ChangeLog10
-rw-r--r--sim/m32r/cpu.h719
-rw-r--r--sim/m32r/cpux.h716
-rw-r--r--sim/m32r/tconfig.in46
4 files changed, 811 insertions, 680 deletions
diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog
index 26e9f8a..18ff93d 100644
--- a/sim/m32r/ChangeLog
+++ b/sim/m32r/ChangeLog
@@ -1,3 +1,13 @@
+Wed Nov 4 23:55:37 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * sim-main.h: Delete inclusion of config.h, include sim-basics.h
+ before cgen-types.h.
+ * tconfig.in: Guard against multiple inclusion.
+ * cpu.h: Delete decls moved to genmloop.sh.
+start-sanitize-m32rx
+ * cpux.h: Ditto.
+end-sanitize-m32rx
+
Mon Oct 19 14:13:05 1998 Doug Evans <devans@seba.cygnus.com>
* sim-main.h: #include cpu-opc.h.
diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h
index c48cee2..8636b40 100644
--- a/sim/m32r/cpu.h
+++ b/sim/m32r/cpu.h
@@ -1,6 +1,6 @@
-/* CPU family header for m32r.
+/* CPU family header for m32rbf.
-This file is machine generated with CGEN.
+THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
@@ -22,8 +22,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
*/
-#ifndef CPU_M32R_H
-#define CPU_M32R_H
+#ifndef CPU_M32RBF_H
+#define CPU_M32RBF_H
/* Maximum number of instructions that are fetched at a time.
This is for LIW type instructions sets (e.g. m32r). */
@@ -45,7 +45,7 @@ typedef struct {
#define GET_H_GR(a1) CPU (h_gr)[a1]
#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
/* control registers */
- USI h_cr[7];
+ USI h_cr[16];
#define GET_H_CR(a1) CPU (h_cr)[a1]
#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
/* accumulator */
@@ -58,363 +58,434 @@ typedef struct {
/* end-sanitize-m32rx */
#define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
#define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
-/* start-sanitize-m32rx */
- /* abort flag */
- UBI h_abort;
-/* end-sanitize-m32rx */
-#define GET_H_ABORT() CPU (h_abort)
-#define SET_H_ABORT(x) (CPU (h_abort) = (x))
/* condition bit */
- UBI h_cond;
+ BI h_cond;
#define GET_H_COND() CPU (h_cond)
#define SET_H_COND(x) (CPU (h_cond) = (x))
- /* sm */
- UBI h_sm;
-#define GET_H_SM() CPU (h_sm)
-#define SET_H_SM(x) (CPU (h_sm) = (x))
- /* bsm */
- UBI h_bsm;
-#define GET_H_BSM() CPU (h_bsm)
-#define SET_H_BSM(x) (CPU (h_bsm) = (x))
- /* ie */
- UBI h_ie;
-#define GET_H_IE() CPU (h_ie)
-#define SET_H_IE(x) (CPU (h_ie) = (x))
- /* bie */
- UBI h_bie;
-#define GET_H_BIE() CPU (h_bie)
-#define SET_H_BIE(x) (CPU (h_bie) = (x))
- /* bcond */
- UBI h_bcond;
-#define GET_H_BCOND() CPU (h_bcond)
-#define SET_H_BCOND(x) (CPU (h_bcond) = (x))
- /* bpc */
- SI h_bpc;
-#define GET_H_BPC() CPU (h_bpc)
-#define SET_H_BPC(x) (CPU (h_bpc) = (x))
+ /* psw part of psw */
+ UQI h_psw;
+#define GET_H_PSW() CPU (h_psw)
+#define SET_H_PSW(x) (CPU (h_psw) = (x))
+ /* backup psw */
+ UQI h_bpsw;
+#define GET_H_BPSW() CPU (h_bpsw)
+#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
+ /* backup bpsw */
+ UQI h_bbpsw;
+#define GET_H_BBPSW() CPU (h_bbpsw)
+#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
/* lock */
- UBI h_lock;
+ BI h_lock;
#define GET_H_LOCK() CPU (h_lock)
#define SET_H_LOCK(x) (CPU (h_lock) = (x))
} hardware;
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
- /* CPU profiling state information. */
- struct {
- /* general registers */
- unsigned long h_gr;
- } profile;
-#define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
-} M32R_CPU_DATA;
-
-USI m32r_h_pc_get (SIM_CPU *);
-void m32r_h_pc_set (SIM_CPU *, USI);
-SI m32r_h_gr_get (SIM_CPU *, UINT);
-void m32r_h_gr_set (SIM_CPU *, UINT, SI);
-USI m32r_h_cr_get (SIM_CPU *, UINT);
-void m32r_h_cr_set (SIM_CPU *, UINT, USI);
-DI m32r_h_accum_get (SIM_CPU *);
-void m32r_h_accum_set (SIM_CPU *, DI);
-DI m32r_h_accums_get (SIM_CPU *, UINT);
-void m32r_h_accums_set (SIM_CPU *, UINT, DI);
-UBI m32r_h_abort_get (SIM_CPU *);
-void m32r_h_abort_set (SIM_CPU *, UBI);
-UBI m32r_h_cond_get (SIM_CPU *);
-void m32r_h_cond_set (SIM_CPU *, UBI);
-UBI m32r_h_sm_get (SIM_CPU *);
-void m32r_h_sm_set (SIM_CPU *, UBI);
-UBI m32r_h_bsm_get (SIM_CPU *);
-void m32r_h_bsm_set (SIM_CPU *, UBI);
-UBI m32r_h_ie_get (SIM_CPU *);
-void m32r_h_ie_set (SIM_CPU *, UBI);
-UBI m32r_h_bie_get (SIM_CPU *);
-void m32r_h_bie_set (SIM_CPU *, UBI);
-UBI m32r_h_bcond_get (SIM_CPU *);
-void m32r_h_bcond_set (SIM_CPU *, UBI);
-SI m32r_h_bpc_get (SIM_CPU *);
-void m32r_h_bpc_set (SIM_CPU *, SI);
-UBI m32r_h_lock_get (SIM_CPU *);
-void m32r_h_lock_set (SIM_CPU *, UBI);
-extern DECODE *m32r_decode (SIM_CPU *, PCADDR, insn_t);
+} M32RBF_CPU_DATA;
+
+/* Cover fns for register access. */
+USI m32rbf_h_pc_get (SIM_CPU *);
+void m32rbf_h_pc_set (SIM_CPU *, USI);
+SI m32rbf_h_gr_get (SIM_CPU *, UINT);
+void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
+USI m32rbf_h_cr_get (SIM_CPU *, UINT);
+void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
+DI m32rbf_h_accum_get (SIM_CPU *);
+void m32rbf_h_accum_set (SIM_CPU *, DI);
+DI m32rbf_h_accums_get (SIM_CPU *, UINT);
+void m32rbf_h_accums_set (SIM_CPU *, UINT, DI);
+BI m32rbf_h_cond_get (SIM_CPU *);
+void m32rbf_h_cond_set (SIM_CPU *, BI);
+UQI m32rbf_h_psw_get (SIM_CPU *);
+void m32rbf_h_psw_set (SIM_CPU *, UQI);
+UQI m32rbf_h_bpsw_get (SIM_CPU *);
+void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
+UQI m32rbf_h_bbpsw_get (SIM_CPU *);
+void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
+BI m32rbf_h_lock_get (SIM_CPU *);
+void m32rbf_h_lock_set (SIM_CPU *, BI);
+
+/* These must be hand-written. */
+extern CPUREG_FETCH_FN m32rbf_fetch_register;
+extern CPUREG_STORE_FN m32rbf_store_register;
+
+typedef struct {
+ UINT h_gr;
+} MODEL_M32R_D_DATA;
+
+typedef struct {
+ int empty;
+} MODEL_TEST_DATA;
/* The ARGBUF struct. */
struct argbuf {
/* These are the baseclass definitions. */
- unsigned int length;
PCADDR addr;
- const struct cgen_insn *opcode;
-#if ! defined (SCACHE_P)
- insn_t insn;
-#endif
+ const IDESC *idesc;
/* cpu specific data follows */
+ union sem semantic;
+ int written;
union {
struct { /* e.g. add $dr,$sr */
SI * f_r1;
SI * f_r2;
- } fmt_0_add;
- struct { /* e.g. add3 $dr,$sr,#$slo16 */
+ unsigned char in_dr;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_add;
+ struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
SI * f_r1;
SI * f_r2;
HI f_simm16;
- } fmt_1_add3;
- struct { /* e.g. and3 $dr,$sr,#$uimm16 */
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_add3;
+ struct { /* e.g. and3 $dr,$sr,$uimm16 */
SI * f_r1;
SI * f_r2;
USI f_uimm16;
- } fmt_2_and3;
- struct { /* e.g. or3 $dr,$sr,#$ulo16 */
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_and3;
+ struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
SI * f_r1;
SI * f_r2;
UHI f_uimm16;
- } fmt_3_or3;
- struct { /* e.g. addi $dr,#$simm8 */
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_or3;
+ struct { /* e.g. addi $dr,$simm8 */
SI * f_r1;
SI f_simm8;
- } fmt_4_addi;
+ unsigned char in_dr;
+ unsigned char out_dr;
+ } fmt_addi;
struct { /* e.g. addv $dr,$sr */
SI * f_r1;
SI * f_r2;
- } fmt_5_addv;
- struct { /* e.g. addv3 $dr,$sr,#$simm16 */
+ unsigned char in_dr;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_addv;
+ struct { /* e.g. addv3 $dr,$sr,$simm16 */
SI * f_r1;
SI * f_r2;
SI f_simm16;
- } fmt_6_addv3;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_addv3;
struct { /* e.g. addx $dr,$sr */
SI * f_r1;
SI * f_r2;
- } fmt_7_addx;
- struct { /* e.g. bc $disp8 */
- IADDR f_disp8;
- } fmt_8_bc8;
- struct { /* e.g. bc $disp24 */
- IADDR f_disp24;
- } fmt_9_bc24;
- struct { /* e.g. beq $src1,$src2,$disp16 */
- SI * f_r1;
- SI * f_r2;
- IADDR f_disp16;
- } fmt_10_beq;
- struct { /* e.g. beqz $src2,$disp16 */
- SI * f_r2;
- IADDR f_disp16;
- } fmt_11_beqz;
- struct { /* e.g. bl $disp8 */
- IADDR f_disp8;
- } fmt_12_bl8;
- struct { /* e.g. bl $disp24 */
- IADDR f_disp24;
- } fmt_13_bl24;
- struct { /* e.g. bra $disp8 */
- IADDR f_disp8;
- } fmt_14_bra8;
- struct { /* e.g. bra $disp24 */
- IADDR f_disp24;
- } fmt_15_bra24;
+ unsigned char in_dr;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_addx;
struct { /* e.g. cmp $src1,$src2 */
SI * f_r1;
SI * f_r2;
- } fmt_16_cmp;
- struct { /* e.g. cmpi $src2,#$simm16 */
+ unsigned char in_src1;
+ unsigned char in_src2;
+ } fmt_cmp;
+ struct { /* e.g. cmpi $src2,$simm16 */
SI * f_r2;
SI f_simm16;
- } fmt_17_cmpi;
- struct { /* e.g. cmpui $src2,#$uimm16 */
- SI * f_r2;
- USI f_uimm16;
- } fmt_18_cmpui;
+ unsigned char in_src2;
+ } fmt_cmpi;
struct { /* e.g. div $dr,$sr */
SI * f_r1;
SI * f_r2;
- } fmt_19_div;
- struct { /* e.g. jl $sr */
- SI * f_r2;
- } fmt_20_jl;
- struct { /* e.g. jmp $sr */
- SI * f_r2;
- } fmt_21_jmp;
+ unsigned char in_sr;
+ unsigned char in_dr;
+ unsigned char out_dr;
+ } fmt_div;
struct { /* e.g. ld $dr,@$sr */
SI * f_r1;
SI * f_r2;
- } fmt_22_ld;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_ld;
struct { /* e.g. ld $dr,@($slo16,$sr) */
SI * f_r1;
SI * f_r2;
HI f_simm16;
- } fmt_23_ld_d;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_ld_d;
struct { /* e.g. ldb $dr,@$sr */
SI * f_r1;
SI * f_r2;
- } fmt_24_ldb;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_ldb;
struct { /* e.g. ldb $dr,@($slo16,$sr) */
SI * f_r1;
SI * f_r2;
HI f_simm16;
- } fmt_25_ldb_d;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_ldb_d;
struct { /* e.g. ldh $dr,@$sr */
SI * f_r1;
SI * f_r2;
- } fmt_26_ldh;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_ldh;
struct { /* e.g. ldh $dr,@($slo16,$sr) */
SI * f_r1;
SI * f_r2;
HI f_simm16;
- } fmt_27_ldh_d;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_ldh_d;
struct { /* e.g. ld $dr,@$sr+ */
SI * f_r1;
SI * f_r2;
- } fmt_28_ld_plus;
- struct { /* e.g. ld24 $dr,#$uimm24 */
+ unsigned char in_sr;
+ unsigned char out_dr;
+ unsigned char out_sr;
+ } fmt_ld_plus;
+ struct { /* e.g. ld24 $dr,$uimm24 */
SI * f_r1;
ADDR f_uimm24;
- } fmt_29_ld24;
- struct { /* e.g. ldi $dr,#$simm8 */
+ unsigned char out_dr;
+ } fmt_ld24;
+ struct { /* e.g. ldi8 $dr,$simm8 */
SI * f_r1;
SI f_simm8;
- } fmt_30_ldi8;
- struct { /* e.g. ldi $dr,$slo16 */
+ unsigned char out_dr;
+ } fmt_ldi8;
+ struct { /* e.g. ldi16 $dr,$hash$slo16 */
SI * f_r1;
HI f_simm16;
- } fmt_31_ldi16;
+ unsigned char out_dr;
+ } fmt_ldi16;
struct { /* e.g. lock $dr,@$sr */
SI * f_r1;
SI * f_r2;
- } fmt_32_lock;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_lock;
struct { /* e.g. machi $src1,$src2 */
SI * f_r1;
SI * f_r2;
- } fmt_33_machi;
+ unsigned char in_src1;
+ unsigned char in_src2;
+ } fmt_machi;
struct { /* e.g. mulhi $src1,$src2 */
SI * f_r1;
SI * f_r2;
- } fmt_34_mulhi;
+ unsigned char in_src1;
+ unsigned char in_src2;
+ } fmt_mulhi;
struct { /* e.g. mv $dr,$sr */
SI * f_r1;
SI * f_r2;
- } fmt_35_mv;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_mv;
struct { /* e.g. mvfachi $dr */
SI * f_r1;
- } fmt_36_mvfachi;
+ unsigned char out_dr;
+ } fmt_mvfachi;
struct { /* e.g. mvfc $dr,$scr */
SI * f_r1;
UINT f_r2;
- } fmt_37_mvfc;
+ unsigned char out_dr;
+ } fmt_mvfc;
struct { /* e.g. mvtachi $src1 */
SI * f_r1;
- } fmt_38_mvtachi;
+ unsigned char in_src1;
+ } fmt_mvtachi;
struct { /* e.g. mvtc $sr,$dcr */
UINT f_r1;
SI * f_r2;
- } fmt_39_mvtc;
+ unsigned char in_sr;
+ } fmt_mvtc;
struct { /* e.g. nop */
int empty;
- } fmt_40_nop;
+ } fmt_nop;
struct { /* e.g. rac */
int empty;
- } fmt_41_rac;
- struct { /* e.g. rte */
- int empty;
- } fmt_42_rte;
- struct { /* e.g. seth $dr,#$hi16 */
+ } fmt_rac;
+ struct { /* e.g. seth $dr,$hash$hi16 */
SI * f_r1;
UHI f_hi16;
- } fmt_43_seth;
- struct { /* e.g. sll3 $dr,$sr,#$simm16 */
+ unsigned char out_dr;
+ } fmt_seth;
+ struct { /* e.g. sll3 $dr,$sr,$simm16 */
SI * f_r1;
SI * f_r2;
SI f_simm16;
- } fmt_44_sll3;
- struct { /* e.g. slli $dr,#$uimm5 */
+ unsigned char in_sr;
+ unsigned char out_dr;
+ } fmt_sll3;
+ struct { /* e.g. slli $dr,$uimm5 */
SI * f_r1;
USI f_uimm5;
- } fmt_45_slli;
+ unsigned char in_dr;
+ unsigned char out_dr;
+ } fmt_slli;
struct { /* e.g. st $src1,@$src2 */
SI * f_r1;
SI * f_r2;
- } fmt_46_st;
+ unsigned char in_src2;
+ unsigned char in_src1;
+ } fmt_st;
struct { /* e.g. st $src1,@($slo16,$src2) */
SI * f_r1;
SI * f_r2;
HI f_simm16;
- } fmt_47_st_d;
+ unsigned char in_src2;
+ unsigned char in_src1;
+ } fmt_st_d;
struct { /* e.g. stb $src1,@$src2 */
SI * f_r1;
SI * f_r2;
- } fmt_48_stb;
+ unsigned char in_src2;
+ unsigned char in_src1;
+ } fmt_stb;
struct { /* e.g. stb $src1,@($slo16,$src2) */
SI * f_r1;
SI * f_r2;
HI f_simm16;
- } fmt_49_stb_d;
+ unsigned char in_src2;
+ unsigned char in_src1;
+ } fmt_stb_d;
struct { /* e.g. sth $src1,@$src2 */
SI * f_r1;
SI * f_r2;
- } fmt_50_sth;
+ unsigned char in_src2;
+ unsigned char in_src1;
+ } fmt_sth;
struct { /* e.g. sth $src1,@($slo16,$src2) */
SI * f_r1;
SI * f_r2;
HI f_simm16;
- } fmt_51_sth_d;
+ unsigned char in_src2;
+ unsigned char in_src1;
+ } fmt_sth_d;
struct { /* e.g. st $src1,@+$src2 */
SI * f_r1;
SI * f_r2;
- } fmt_52_st_plus;
- struct { /* e.g. trap #$uimm4 */
- USI f_uimm4;
- } fmt_53_trap;
+ unsigned char in_src2;
+ unsigned char in_src1;
+ unsigned char out_src2;
+ } fmt_st_plus;
struct { /* e.g. unlock $src1,@$src2 */
SI * f_r1;
SI * f_r2;
- } fmt_54_unlock;
- } fields;
-#if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
- unsigned long h_gr_get;
- unsigned long h_gr_set;
+ unsigned char in_src2;
+ unsigned char in_src1;
+ } fmt_unlock;
+ /* cti insns, kept separately so addr_cache is in fixed place */
+ struct {
+ union {
+ struct { /* e.g. bc.s $disp8 */
+ IADDR f_disp8;
+ } fmt_bc8;
+ struct { /* e.g. bc.l $disp24 */
+ IADDR f_disp24;
+ } fmt_bc24;
+ struct { /* e.g. beq $src1,$src2,$disp16 */
+ SI * f_r1;
+ SI * f_r2;
+ IADDR f_disp16;
+ unsigned char in_src1;
+ unsigned char in_src2;
+ } fmt_beq;
+ struct { /* e.g. beqz $src2,$disp16 */
+ SI * f_r2;
+ IADDR f_disp16;
+ unsigned char in_src2;
+ } fmt_beqz;
+ struct { /* e.g. bl.s $disp8 */
+ IADDR f_disp8;
+ unsigned char out_h_gr_14;
+ } fmt_bl8;
+ struct { /* e.g. bl.l $disp24 */
+ IADDR f_disp24;
+ unsigned char out_h_gr_14;
+ } fmt_bl24;
+ struct { /* e.g. bra.s $disp8 */
+ IADDR f_disp8;
+ } fmt_bra8;
+ struct { /* e.g. bra.l $disp24 */
+ IADDR f_disp24;
+ } fmt_bra24;
+ struct { /* e.g. jl $sr */
+ SI * f_r2;
+ unsigned char in_sr;
+ unsigned char out_h_gr_14;
+ } fmt_jl;
+ struct { /* e.g. jmp $sr */
+ SI * f_r2;
+ unsigned char in_sr;
+ } fmt_jmp;
+ struct { /* e.g. rte */
+ int empty;
+ } fmt_rte;
+ struct { /* e.g. trap $uimm4 */
+ USI f_uimm4;
+ } fmt_trap;
+ } fields;
+#if WITH_SCACHE_PBB_M32RBF
+ SEM_PC addr_cache;
#endif
+ } cti;
+#if WITH_SCACHE_PBB_M32RBF
+ /* Writeback handler. */
+ struct {
+ /* Pointer to argbuf entry for insn whose results need writing back. */
+ const struct argbuf *abuf;
+ } write;
+ /* x-before handler */
+ struct {
+ /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+ int first_p;
+ } before;
+ /* x-after handler */
+ struct {
+ int empty;
+ } after;
+ /* This entry is used to terminate each pbb. */
+ struct {
+ /* Number of insns in pbb. */
+ int insn_count;
+ /* Next pbb to execute. */
+ SCACHE *next;
+ } chain;
+#endif
+ } fields;
};
/* A cached insn.
- This is currently also used in the non-scache case. In this situation we
- assume the cache size is 1, and do a few things a little differently. */
-/* FIXME: non-scache version to be redone. */
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
struct scache {
- IADDR next;
- union {
-#if ! WITH_SEM_SWITCH_FULL
- SEMANTIC_FN *sem_fn;
-#endif
-#if ! WITH_SEM_SWITCH_FAST
- SEMANTIC_FN *sem_fast_fn;
-#endif
-#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
-#ifdef __GNUC__
- void *sem_case;
-#else
- int sem_case;
-#endif
-#endif
- } semantic;
struct argbuf argbuf;
};
/* Macros to simplify extraction, reading and semantic code.
These define and assign the local vars that contain the insn's fields. */
-#define EXTRACT_FMT_0_ADD_VARS \
+#define EXTRACT_FMT_ADD_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_0_ADD_CODE \
+#define EXTRACT_FMT_ADD_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_1_ADD3_VARS \
+#define EXTRACT_FMT_ADD3_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -422,7 +493,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_1_ADD3_CODE \
+#define EXTRACT_FMT_ADD3_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -430,7 +501,7 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_2_AND3_VARS \
+#define EXTRACT_FMT_AND3_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -438,7 +509,7 @@ struct scache {
UINT f_r2; \
UINT f_uimm16; \
unsigned int length;
-#define EXTRACT_FMT_2_AND3_CODE \
+#define EXTRACT_FMT_AND3_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -446,7 +517,7 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_3_OR3_VARS \
+#define EXTRACT_FMT_OR3_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -454,7 +525,7 @@ struct scache {
UINT f_r2; \
UINT f_uimm16; \
unsigned int length;
-#define EXTRACT_FMT_3_OR3_CODE \
+#define EXTRACT_FMT_OR3_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -462,33 +533,33 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_4_ADDI_VARS \
+#define EXTRACT_FMT_ADDI_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_simm8; \
unsigned int length;
-#define EXTRACT_FMT_4_ADDI_CODE \
+#define EXTRACT_FMT_ADDI_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
-#define EXTRACT_FMT_5_ADDV_VARS \
+#define EXTRACT_FMT_ADDV_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_5_ADDV_CODE \
+#define EXTRACT_FMT_ADDV_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_6_ADDV3_VARS \
+#define EXTRACT_FMT_ADDV3_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -496,7 +567,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_6_ADDV3_CODE \
+#define EXTRACT_FMT_ADDV3_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -504,45 +575,45 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_7_ADDX_VARS \
+#define EXTRACT_FMT_ADDX_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_7_ADDX_CODE \
+#define EXTRACT_FMT_ADDX_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_8_BC8_VARS \
+#define EXTRACT_FMT_BC8_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_disp8; \
unsigned int length;
-#define EXTRACT_FMT_8_BC8_CODE \
+#define EXTRACT_FMT_BC8_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
+ f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
-#define EXTRACT_FMT_9_BC24_VARS \
+#define EXTRACT_FMT_BC24_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_disp24; \
unsigned int length;
-#define EXTRACT_FMT_9_BC24_CODE \
+#define EXTRACT_FMT_BC24_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
+ f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
-#define EXTRACT_FMT_10_BEQ_VARS \
+#define EXTRACT_FMT_BEQ_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -550,15 +621,15 @@ struct scache {
UINT f_r2; \
int f_disp16; \
unsigned int length;
-#define EXTRACT_FMT_10_BEQ_CODE \
+#define EXTRACT_FMT_BEQ_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_disp16 = ((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2)); \
+ f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
-#define EXTRACT_FMT_11_BEQZ_VARS \
+#define EXTRACT_FMT_BEQZ_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -566,77 +637,77 @@ struct scache {
UINT f_r2; \
int f_disp16; \
unsigned int length;
-#define EXTRACT_FMT_11_BEQZ_CODE \
+#define EXTRACT_FMT_BEQZ_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_disp16 = ((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2)); \
+ f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
-#define EXTRACT_FMT_12_BL8_VARS \
+#define EXTRACT_FMT_BL8_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_disp8; \
unsigned int length;
-#define EXTRACT_FMT_12_BL8_CODE \
+#define EXTRACT_FMT_BL8_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
+ f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
-#define EXTRACT_FMT_13_BL24_VARS \
+#define EXTRACT_FMT_BL24_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_disp24; \
unsigned int length;
-#define EXTRACT_FMT_13_BL24_CODE \
+#define EXTRACT_FMT_BL24_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
+ f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
-#define EXTRACT_FMT_14_BRA8_VARS \
+#define EXTRACT_FMT_BRA8_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_disp8; \
unsigned int length;
-#define EXTRACT_FMT_14_BRA8_CODE \
+#define EXTRACT_FMT_BRA8_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
- f_disp8 = ((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2)); \
+ f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
-#define EXTRACT_FMT_15_BRA24_VARS \
+#define EXTRACT_FMT_BRA24_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_disp24; \
unsigned int length;
-#define EXTRACT_FMT_15_BRA24_CODE \
+#define EXTRACT_FMT_BRA24_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_disp24 = ((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2)); \
+ f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
-#define EXTRACT_FMT_16_CMP_VARS \
+#define EXTRACT_FMT_CMP_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_16_CMP_CODE \
+#define EXTRACT_FMT_CMP_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_17_CMPI_VARS \
+#define EXTRACT_FMT_CMPI_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -644,7 +715,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_17_CMPI_CODE \
+#define EXTRACT_FMT_CMPI_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -652,23 +723,7 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_18_CMPUI_VARS \
- /* Instruction fields. */ \
- UINT f_op1; \
- UINT f_r1; \
- UINT f_op2; \
- UINT f_r2; \
- UINT f_uimm16; \
- unsigned int length;
-#define EXTRACT_FMT_18_CMPUI_CODE \
- length = 4; \
- f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
- f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
- f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
- f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
- f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
-
-#define EXTRACT_FMT_19_DIV_VARS \
+#define EXTRACT_FMT_DIV_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -676,7 +731,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_19_DIV_CODE \
+#define EXTRACT_FMT_DIV_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -684,49 +739,49 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_20_JL_VARS \
+#define EXTRACT_FMT_JL_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_20_JL_CODE \
+#define EXTRACT_FMT_JL_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_21_JMP_VARS \
+#define EXTRACT_FMT_JMP_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_21_JMP_CODE \
+#define EXTRACT_FMT_JMP_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_22_LD_VARS \
+#define EXTRACT_FMT_LD_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_22_LD_CODE \
+#define EXTRACT_FMT_LD_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_23_LD_D_VARS \
+#define EXTRACT_FMT_LD_D_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -734,7 +789,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_23_LD_D_CODE \
+#define EXTRACT_FMT_LD_D_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -742,21 +797,21 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_24_LDB_VARS \
+#define EXTRACT_FMT_LDB_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_24_LDB_CODE \
+#define EXTRACT_FMT_LDB_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_25_LDB_D_VARS \
+#define EXTRACT_FMT_LDB_D_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -764,7 +819,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_25_LDB_D_CODE \
+#define EXTRACT_FMT_LDB_D_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -772,21 +827,21 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_26_LDH_VARS \
+#define EXTRACT_FMT_LDH_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_26_LDH_CODE \
+#define EXTRACT_FMT_LDH_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_27_LDH_D_VARS \
+#define EXTRACT_FMT_LDH_D_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -794,7 +849,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_27_LDH_D_CODE \
+#define EXTRACT_FMT_LDH_D_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -802,45 +857,45 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_28_LD_PLUS_VARS \
+#define EXTRACT_FMT_LD_PLUS_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_28_LD_PLUS_CODE \
+#define EXTRACT_FMT_LD_PLUS_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_29_LD24_VARS \
+#define EXTRACT_FMT_LD24_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_uimm24; \
unsigned int length;
-#define EXTRACT_FMT_29_LD24_CODE \
+#define EXTRACT_FMT_LD24_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
-#define EXTRACT_FMT_30_LDI8_VARS \
+#define EXTRACT_FMT_LDI8_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
int f_simm8; \
unsigned int length;
-#define EXTRACT_FMT_30_LDI8_CODE \
+#define EXTRACT_FMT_LDI8_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
-#define EXTRACT_FMT_31_LDI16_VARS \
+#define EXTRACT_FMT_LDI16_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -848,7 +903,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_31_LDI16_CODE \
+#define EXTRACT_FMT_LDI16_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -856,161 +911,161 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_32_LOCK_VARS \
+#define EXTRACT_FMT_LOCK_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_32_LOCK_CODE \
+#define EXTRACT_FMT_LOCK_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_33_MACHI_VARS \
+#define EXTRACT_FMT_MACHI_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_33_MACHI_CODE \
+#define EXTRACT_FMT_MACHI_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_34_MULHI_VARS \
+#define EXTRACT_FMT_MULHI_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_34_MULHI_CODE \
+#define EXTRACT_FMT_MULHI_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_35_MV_VARS \
+#define EXTRACT_FMT_MV_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_35_MV_CODE \
+#define EXTRACT_FMT_MV_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_36_MVFACHI_VARS \
+#define EXTRACT_FMT_MVFACHI_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_36_MVFACHI_CODE \
+#define EXTRACT_FMT_MVFACHI_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_37_MVFC_VARS \
+#define EXTRACT_FMT_MVFC_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_37_MVFC_CODE \
+#define EXTRACT_FMT_MVFC_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_38_MVTACHI_VARS \
+#define EXTRACT_FMT_MVTACHI_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_38_MVTACHI_CODE \
+#define EXTRACT_FMT_MVTACHI_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_39_MVTC_VARS \
+#define EXTRACT_FMT_MVTC_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_39_MVTC_CODE \
+#define EXTRACT_FMT_MVTC_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_40_NOP_VARS \
+#define EXTRACT_FMT_NOP_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_40_NOP_CODE \
+#define EXTRACT_FMT_NOP_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_41_RAC_VARS \
+#define EXTRACT_FMT_RAC_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_41_RAC_CODE \
+#define EXTRACT_FMT_RAC_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_42_RTE_VARS \
+#define EXTRACT_FMT_RTE_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_42_RTE_CODE \
+#define EXTRACT_FMT_RTE_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_43_SETH_VARS \
+#define EXTRACT_FMT_SETH_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -1018,7 +1073,7 @@ struct scache {
UINT f_r2; \
UINT f_hi16; \
unsigned int length;
-#define EXTRACT_FMT_43_SETH_CODE \
+#define EXTRACT_FMT_SETH_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1026,7 +1081,7 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_44_SLL3_VARS \
+#define EXTRACT_FMT_SLL3_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -1034,7 +1089,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_44_SLL3_CODE \
+#define EXTRACT_FMT_SLL3_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1042,35 +1097,35 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_45_SLLI_VARS \
+#define EXTRACT_FMT_SLLI_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_shift_op2; \
UINT f_uimm5; \
unsigned int length;
-#define EXTRACT_FMT_45_SLLI_CODE \
+#define EXTRACT_FMT_SLLI_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
-#define EXTRACT_FMT_46_ST_VARS \
+#define EXTRACT_FMT_ST_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_46_ST_CODE \
+#define EXTRACT_FMT_ST_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_47_ST_D_VARS \
+#define EXTRACT_FMT_ST_D_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -1078,7 +1133,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_47_ST_D_CODE \
+#define EXTRACT_FMT_ST_D_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1086,21 +1141,21 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_48_STB_VARS \
+#define EXTRACT_FMT_STB_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_48_STB_CODE \
+#define EXTRACT_FMT_STB_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_49_STB_D_VARS \
+#define EXTRACT_FMT_STB_D_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -1108,7 +1163,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_49_STB_D_CODE \
+#define EXTRACT_FMT_STB_D_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1116,21 +1171,21 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_50_STH_VARS \
+#define EXTRACT_FMT_STH_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_50_STH_CODE \
+#define EXTRACT_FMT_STH_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_51_STH_D_VARS \
+#define EXTRACT_FMT_STH_D_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
@@ -1138,7 +1193,7 @@ struct scache {
UINT f_r2; \
int f_simm16; \
unsigned int length;
-#define EXTRACT_FMT_51_STH_D_CODE \
+#define EXTRACT_FMT_STH_D_CODE \
length = 4; \
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1146,46 +1201,46 @@ struct scache {
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
-#define EXTRACT_FMT_52_ST_PLUS_VARS \
+#define EXTRACT_FMT_ST_PLUS_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_52_ST_PLUS_CODE \
+#define EXTRACT_FMT_ST_PLUS_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_53_TRAP_VARS \
+#define EXTRACT_FMT_TRAP_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_uimm4; \
unsigned int length;
-#define EXTRACT_FMT_53_TRAP_CODE \
+#define EXTRACT_FMT_TRAP_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#define EXTRACT_FMT_54_UNLOCK_VARS \
+#define EXTRACT_FMT_UNLOCK_VARS \
/* Instruction fields. */ \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
-#define EXTRACT_FMT_54_UNLOCK_CODE \
+#define EXTRACT_FMT_UNLOCK_CODE \
length = 2; \
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-#endif /* CPU_M32R_H */
+#endif /* CPU_M32RBF_H */
diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h
index ff2d4da..fb1ac9c 100644
--- a/sim/m32r/cpux.h
+++ b/sim/m32r/cpux.h
@@ -1,4 +1,4 @@
-/* CPU family header for m32rx.
+/* CPU family header for m32rxf.
THIS FILE IS MACHINE GENERATED WITH CGEN.
@@ -22,8 +22,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
*/
-#ifndef CPU_M32RX_H
-#define CPU_M32RX_H
+#ifndef CPU_M32RXF_H
+#define CPU_M32RXF_H
/* Maximum number of instructions that are fetched at a time.
This is for LIW type instructions sets (e.g. m32r). */
@@ -59,257 +59,251 @@ typedef struct {
#define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
#define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
/* condition bit */
- UBI h_cond;
+ BI h_cond;
#define GET_H_COND() CPU (h_cond)
#define SET_H_COND(x) (CPU (h_cond) = (x))
- /* sm */
- UBI h_sm;
-#define GET_H_SM() CPU (h_sm)
-#define SET_H_SM(x) (CPU (h_sm) = (x))
- /* bsm */
- UBI h_bsm;
-#define GET_H_BSM() CPU (h_bsm)
-#define SET_H_BSM(x) (CPU (h_bsm) = (x))
- /* ie */
- UBI h_ie;
-#define GET_H_IE() CPU (h_ie)
-#define SET_H_IE(x) (CPU (h_ie) = (x))
- /* bie */
- UBI h_bie;
-#define GET_H_BIE() CPU (h_bie)
-#define SET_H_BIE(x) (CPU (h_bie) = (x))
- /* bcond */
- UBI h_bcond;
-#define GET_H_BCOND() CPU (h_bcond)
-#define SET_H_BCOND(x) (CPU (h_bcond) = (x))
- /* bpc */
- SI h_bpc;
-#define GET_H_BPC() CPU (h_bpc)
-#define SET_H_BPC(x) (CPU (h_bpc) = (x))
+ /* psw part of psw */
+ UQI h_psw;
+#define GET_H_PSW() CPU (h_psw)
+#define SET_H_PSW(x) (CPU (h_psw) = (x))
+ /* backup psw */
+ UQI h_bpsw;
+#define GET_H_BPSW() CPU (h_bpsw)
+#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
+ /* backup bpsw */
+ UQI h_bbpsw;
+#define GET_H_BBPSW() CPU (h_bbpsw)
+#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
/* lock */
- UBI h_lock;
+ BI h_lock;
#define GET_H_LOCK() CPU (h_lock)
#define SET_H_LOCK(x) (CPU (h_lock) = (x))
} hardware;
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
- /* CPU profiling state information. */
- struct {
- /* general registers */
- unsigned long h_gr;
- } profile;
-#define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
-} M32RX_CPU_DATA;
+} M32RXF_CPU_DATA;
/* Cover fns for register access. */
-USI m32rx_h_pc_get (SIM_CPU *);
-void m32rx_h_pc_set (SIM_CPU *, USI);
-SI m32rx_h_gr_get (SIM_CPU *, UINT);
-void m32rx_h_gr_set (SIM_CPU *, UINT, SI);
-USI m32rx_h_cr_get (SIM_CPU *, UINT);
-void m32rx_h_cr_set (SIM_CPU *, UINT, USI);
-DI m32rx_h_accum_get (SIM_CPU *);
-void m32rx_h_accum_set (SIM_CPU *, DI);
-DI m32rx_h_accums_get (SIM_CPU *, UINT);
-void m32rx_h_accums_set (SIM_CPU *, UINT, DI);
-UBI m32rx_h_cond_get (SIM_CPU *);
-void m32rx_h_cond_set (SIM_CPU *, UBI);
-UBI m32rx_h_sm_get (SIM_CPU *);
-void m32rx_h_sm_set (SIM_CPU *, UBI);
-UBI m32rx_h_bsm_get (SIM_CPU *);
-void m32rx_h_bsm_set (SIM_CPU *, UBI);
-UBI m32rx_h_ie_get (SIM_CPU *);
-void m32rx_h_ie_set (SIM_CPU *, UBI);
-UBI m32rx_h_bie_get (SIM_CPU *);
-void m32rx_h_bie_set (SIM_CPU *, UBI);
-UBI m32rx_h_bcond_get (SIM_CPU *);
-void m32rx_h_bcond_set (SIM_CPU *, UBI);
-SI m32rx_h_bpc_get (SIM_CPU *);
-void m32rx_h_bpc_set (SIM_CPU *, SI);
-UBI m32rx_h_lock_get (SIM_CPU *);
-void m32rx_h_lock_set (SIM_CPU *, UBI);
+USI m32rxf_h_pc_get (SIM_CPU *);
+void m32rxf_h_pc_set (SIM_CPU *, USI);
+SI m32rxf_h_gr_get (SIM_CPU *, UINT);
+void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
+USI m32rxf_h_cr_get (SIM_CPU *, UINT);
+void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
+DI m32rxf_h_accum_get (SIM_CPU *);
+void m32rxf_h_accum_set (SIM_CPU *, DI);
+DI m32rxf_h_accums_get (SIM_CPU *, UINT);
+void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
+BI m32rxf_h_cond_get (SIM_CPU *);
+void m32rxf_h_cond_set (SIM_CPU *, BI);
+UQI m32rxf_h_psw_get (SIM_CPU *);
+void m32rxf_h_psw_set (SIM_CPU *, UQI);
+UQI m32rxf_h_bpsw_get (SIM_CPU *);
+void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
+UQI m32rxf_h_bbpsw_get (SIM_CPU *);
+void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
+BI m32rxf_h_lock_get (SIM_CPU *);
+void m32rxf_h_lock_set (SIM_CPU *, BI);
/* These must be hand-written. */
-extern CPUREG_FETCH_FN m32rx_fetch_register;
-extern CPUREG_STORE_FN m32rx_store_register;
+extern CPUREG_FETCH_FN m32rxf_fetch_register;
+extern CPUREG_STORE_FN m32rxf_store_register;
+
+typedef struct {
+ int empty;
+} MODEL_M32RX_DATA;
/* The ARGBUF struct. */
struct argbuf {
/* These are the baseclass definitions. */
- unsigned int length;
PCADDR addr;
const IDESC *idesc;
/* cpu specific data follows */
- insn_t insn;
+ union sem semantic;
+ int written;
union {
struct { /* e.g. add $dr,$sr */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_dr;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_add;
struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
HI f_simm16;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_add3;
struct { /* e.g. and3 $dr,$sr,$uimm16 */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
USI f_uimm16;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_and3;
struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
UHI f_uimm16;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_or3;
struct { /* e.g. addi $dr,$simm8 */
- UINT f_r1;
+ SI * f_r1;
SI f_simm8;
+ unsigned char in_dr;
+ unsigned char out_dr;
} fmt_addi;
struct { /* e.g. addv $dr,$sr */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_dr;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_addv;
struct { /* e.g. addv3 $dr,$sr,$simm16 */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
SI f_simm16;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_addv3;
struct { /* e.g. addx $dr,$sr */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_dr;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_addx;
- struct { /* e.g. bc.s $disp8 */
- IADDR f_disp8;
- } fmt_bc8;
- struct { /* e.g. bc.l $disp24 */
- IADDR f_disp24;
- } fmt_bc24;
- struct { /* e.g. beq $src1,$src2,$disp16 */
- UINT f_r1;
- UINT f_r2;
- IADDR f_disp16;
- } fmt_beq;
- struct { /* e.g. beqz $src2,$disp16 */
- UINT f_r2;
- IADDR f_disp16;
- } fmt_beqz;
- struct { /* e.g. bl.s $disp8 */
- IADDR f_disp8;
- } fmt_bl8;
- struct { /* e.g. bl.l $disp24 */
- IADDR f_disp24;
- } fmt_bl24;
- struct { /* e.g. bcl.s $disp8 */
- IADDR f_disp8;
- } fmt_bcl8;
- struct { /* e.g. bcl.l $disp24 */
- IADDR f_disp24;
- } fmt_bcl24;
- struct { /* e.g. bra.s $disp8 */
- IADDR f_disp8;
- } fmt_bra8;
- struct { /* e.g. bra.l $disp24 */
- IADDR f_disp24;
- } fmt_bra24;
struct { /* e.g. cmp $src1,$src2 */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_src1;
+ unsigned char in_src2;
} fmt_cmp;
struct { /* e.g. cmpi $src2,$simm16 */
- UINT f_r2;
+ SI * f_r2;
SI f_simm16;
+ unsigned char in_src2;
} fmt_cmpi;
struct { /* e.g. cmpz $src2 */
- UINT f_r2;
+ SI * f_r2;
+ unsigned char in_src2;
} fmt_cmpz;
struct { /* e.g. div $dr,$sr */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_sr;
+ unsigned char in_dr;
+ unsigned char out_dr;
} fmt_div;
- struct { /* e.g. jc $sr */
- UINT f_r2;
- } fmt_jc;
- struct { /* e.g. jl $sr */
- UINT f_r2;
- } fmt_jl;
- struct { /* e.g. jmp $sr */
- UINT f_r2;
- } fmt_jmp;
struct { /* e.g. ld $dr,@$sr */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_ld;
struct { /* e.g. ld $dr,@($slo16,$sr) */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
HI f_simm16;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_ld_d;
struct { /* e.g. ldb $dr,@$sr */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_ldb;
struct { /* e.g. ldb $dr,@($slo16,$sr) */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
HI f_simm16;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_ldb_d;
struct { /* e.g. ldh $dr,@$sr */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_ldh;
struct { /* e.g. ldh $dr,@($slo16,$sr) */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
HI f_simm16;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_ldh_d;
struct { /* e.g. ld $dr,@$sr+ */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_sr;
+ unsigned char out_dr;
+ unsigned char out_sr;
} fmt_ld_plus;
struct { /* e.g. ld24 $dr,$uimm24 */
- UINT f_r1;
+ SI * f_r1;
ADDR f_uimm24;
+ unsigned char out_dr;
} fmt_ld24;
struct { /* e.g. ldi8 $dr,$simm8 */
- UINT f_r1;
+ SI * f_r1;
SI f_simm8;
+ unsigned char out_dr;
} fmt_ldi8;
struct { /* e.g. ldi16 $dr,$hash$slo16 */
- UINT f_r1;
+ SI * f_r1;
HI f_simm16;
+ unsigned char out_dr;
} fmt_ldi16;
struct { /* e.g. lock $dr,@$sr */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_lock;
struct { /* e.g. machi $src1,$src2,$acc */
- UINT f_r1;
+ SI * f_r1;
UINT f_acc;
- UINT f_r2;
+ SI * f_r2;
+ unsigned char in_src1;
+ unsigned char in_src2;
} fmt_machi_a;
struct { /* e.g. mulhi $src1,$src2,$acc */
- UINT f_r1;
+ SI * f_r1;
UINT f_acc;
- UINT f_r2;
+ SI * f_r2;
+ unsigned char in_src1;
+ unsigned char in_src2;
} fmt_mulhi_a;
struct { /* e.g. mv $dr,$sr */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_mv;
struct { /* e.g. mvfachi $dr,$accs */
- UINT f_r1;
+ SI * f_r1;
UINT f_accs;
+ unsigned char out_dr;
} fmt_mvfachi_a;
struct { /* e.g. mvfc $dr,$scr */
- UINT f_r1;
+ SI * f_r1;
UINT f_r2;
+ unsigned char out_dr;
} fmt_mvfc;
struct { /* e.g. mvtachi $src1,$accs */
- UINT f_r1;
+ SI * f_r1;
UINT f_accs;
+ unsigned char in_src1;
} fmt_mvtachi_a;
struct { /* e.g. mvtc $sr,$dcr */
UINT f_r1;
- UINT f_r2;
+ SI * f_r2;
+ unsigned char in_sr;
} fmt_mvtc;
struct { /* e.g. nop */
int empty;
@@ -319,115 +313,212 @@ struct argbuf {
UINT f_accs;
USI f_imm1;
} fmt_rac_dsi;
- struct { /* e.g. rte */
- int empty;
- } fmt_rte;
struct { /* e.g. seth $dr,$hash$hi16 */
- UINT f_r1;
+ SI * f_r1;
UHI f_hi16;
+ unsigned char out_dr;
} fmt_seth;
struct { /* e.g. sll3 $dr,$sr,$simm16 */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
SI f_simm16;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_sll3;
struct { /* e.g. slli $dr,$uimm5 */
- UINT f_r1;
+ SI * f_r1;
USI f_uimm5;
+ unsigned char in_dr;
+ unsigned char out_dr;
} fmt_slli;
struct { /* e.g. st $src1,@$src2 */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_src2;
+ unsigned char in_src1;
} fmt_st;
struct { /* e.g. st $src1,@($slo16,$src2) */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
HI f_simm16;
+ unsigned char in_src2;
+ unsigned char in_src1;
} fmt_st_d;
struct { /* e.g. stb $src1,@$src2 */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_src2;
+ unsigned char in_src1;
} fmt_stb;
struct { /* e.g. stb $src1,@($slo16,$src2) */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
HI f_simm16;
+ unsigned char in_src2;
+ unsigned char in_src1;
} fmt_stb_d;
struct { /* e.g. sth $src1,@$src2 */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_src2;
+ unsigned char in_src1;
} fmt_sth;
struct { /* e.g. sth $src1,@($slo16,$src2) */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
HI f_simm16;
+ unsigned char in_src2;
+ unsigned char in_src1;
} fmt_sth_d;
struct { /* e.g. st $src1,@+$src2 */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_src2;
+ unsigned char in_src1;
+ unsigned char out_src2;
} fmt_st_plus;
- struct { /* e.g. trap $uimm4 */
- USI f_uimm4;
- } fmt_trap;
struct { /* e.g. unlock $src1,@$src2 */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_src2;
+ unsigned char in_src1;
} fmt_unlock;
struct { /* e.g. satb $dr,$sr */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_satb;
struct { /* e.g. sat $dr,$sr */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_sr;
+ unsigned char out_dr;
} fmt_sat;
struct { /* e.g. sadd */
int empty;
} fmt_sadd;
struct { /* e.g. macwu1 $src1,$src2 */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_src1;
+ unsigned char in_src2;
} fmt_macwu1;
struct { /* e.g. msblo $src1,$src2 */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_src1;
+ unsigned char in_src2;
} fmt_msblo;
struct { /* e.g. mulwu1 $src1,$src2 */
- UINT f_r1;
- UINT f_r2;
+ SI * f_r1;
+ SI * f_r2;
+ unsigned char in_src1;
+ unsigned char in_src2;
} fmt_mulwu1;
struct { /* e.g. sc */
int empty;
} fmt_sc;
- } fields;
-#if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
- unsigned long h_gr_get;
- unsigned long h_gr_set;
+ /* cti insns, kept separately so addr_cache is in fixed place */
+ struct {
+ union {
+ struct { /* e.g. bc.s $disp8 */
+ IADDR f_disp8;
+ } fmt_bc8;
+ struct { /* e.g. bc.l $disp24 */
+ IADDR f_disp24;
+ } fmt_bc24;
+ struct { /* e.g. beq $src1,$src2,$disp16 */
+ SI * f_r1;
+ SI * f_r2;
+ IADDR f_disp16;
+ unsigned char in_src1;
+ unsigned char in_src2;
+ } fmt_beq;
+ struct { /* e.g. beqz $src2,$disp16 */
+ SI * f_r2;
+ IADDR f_disp16;
+ unsigned char in_src2;
+ } fmt_beqz;
+ struct { /* e.g. bl.s $disp8 */
+ IADDR f_disp8;
+ unsigned char out_h_gr_14;
+ } fmt_bl8;
+ struct { /* e.g. bl.l $disp24 */
+ IADDR f_disp24;
+ unsigned char out_h_gr_14;
+ } fmt_bl24;
+ struct { /* e.g. bcl.s $disp8 */
+ IADDR f_disp8;
+ unsigned char out_h_gr_14;
+ } fmt_bcl8;
+ struct { /* e.g. bcl.l $disp24 */
+ IADDR f_disp24;
+ unsigned char out_h_gr_14;
+ } fmt_bcl24;
+ struct { /* e.g. bra.s $disp8 */
+ IADDR f_disp8;
+ } fmt_bra8;
+ struct { /* e.g. bra.l $disp24 */
+ IADDR f_disp24;
+ } fmt_bra24;
+ struct { /* e.g. jc $sr */
+ SI * f_r2;
+ unsigned char in_sr;
+ } fmt_jc;
+ struct { /* e.g. jl $sr */
+ SI * f_r2;
+ unsigned char in_sr;
+ unsigned char out_h_gr_14;
+ } fmt_jl;
+ struct { /* e.g. jmp $sr */
+ SI * f_r2;
+ unsigned char in_sr;
+ } fmt_jmp;
+ struct { /* e.g. rte */
+ int empty;
+ } fmt_rte;
+ struct { /* e.g. trap $uimm4 */
+ USI f_uimm4;
+ } fmt_trap;
+ } fields;
+#if WITH_SCACHE_PBB_M32RXF
+ SEM_PC addr_cache;
+#endif
+ } cti;
+#if WITH_SCACHE_PBB_M32RXF
+ /* Writeback handler. */
+ struct {
+ /* Pointer to argbuf entry for insn whose results need writing back. */
+ const struct argbuf *abuf;
+ } write;
+ /* x-before handler */
+ struct {
+ /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+ int first_p;
+ } before;
+ /* x-after handler */
+ struct {
+ int empty;
+ } after;
+ /* This entry is used to terminate each pbb. */
+ struct {
+ /* Number of insns in pbb. */
+ int insn_count;
+ /* Next pbb to execute. */
+ SCACHE *next;
+ } chain;
#endif
+ } fields;
};
/* A cached insn.
- This is currently also used in the non-scache case. In this situation we
- assume the cache size is 1, and do a few things a little differently. */
-/* FIXME: non-scache version to be redone. */
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
struct scache {
- IADDR next;
- union {
-#if ! WITH_SEM_SWITCH_FULL
- SEMANTIC_FN *sem_full;
-#endif
-#if ! WITH_SEM_SWITCH_FAST
- SEMANTIC_FN *sem_fast;
-#endif
-#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
-#ifdef __GNUC__
- void *sem_case;
-#else
- int sem_case;
-#endif
-#endif
- } semantic;
struct argbuf argbuf;
};
@@ -1374,273 +1465,236 @@ struct scache {
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-/* Fetched input values of an instruction. */
+/* Queued output values of an instruction. */
struct parexec {
union {
struct { /* e.g. add $dr,$sr */
SI dr;
- SI sr;
} fmt_add;
struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
- SI sr;
- HI slo16;
+ SI dr;
} fmt_add3;
struct { /* e.g. and3 $dr,$sr,$uimm16 */
- SI sr;
- USI uimm16;
+ SI dr;
} fmt_and3;
struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
- SI sr;
- UHI ulo16;
+ SI dr;
} fmt_or3;
struct { /* e.g. addi $dr,$simm8 */
SI dr;
- SI simm8;
} fmt_addi;
struct { /* e.g. addv $dr,$sr */
SI dr;
- SI sr;
+ BI condbit;
} fmt_addv;
struct { /* e.g. addv3 $dr,$sr,$simm16 */
- SI sr;
- SI simm16;
+ SI dr;
+ BI condbit;
} fmt_addv3;
struct { /* e.g. addx $dr,$sr */
SI dr;
- SI sr;
- UBI condbit;
+ BI condbit;
} fmt_addx;
struct { /* e.g. bc.s $disp8 */
- UBI condbit;
- USI disp8;
+ USI pc;
} fmt_bc8;
struct { /* e.g. bc.l $disp24 */
- UBI condbit;
- USI disp24;
+ USI pc;
} fmt_bc24;
struct { /* e.g. beq $src1,$src2,$disp16 */
- SI src1;
- SI src2;
- USI disp16;
+ USI pc;
} fmt_beq;
struct { /* e.g. beqz $src2,$disp16 */
- SI src2;
- USI disp16;
+ USI pc;
} fmt_beqz;
struct { /* e.g. bl.s $disp8 */
+ SI h_gr_14;
USI pc;
- USI disp8;
} fmt_bl8;
struct { /* e.g. bl.l $disp24 */
+ SI h_gr_14;
USI pc;
- USI disp24;
} fmt_bl24;
struct { /* e.g. bcl.s $disp8 */
- UBI condbit;
+ SI h_gr_14;
USI pc;
- USI disp8;
} fmt_bcl8;
struct { /* e.g. bcl.l $disp24 */
- UBI condbit;
+ SI h_gr_14;
USI pc;
- USI disp24;
} fmt_bcl24;
struct { /* e.g. bra.s $disp8 */
- USI disp8;
+ USI pc;
} fmt_bra8;
struct { /* e.g. bra.l $disp24 */
- USI disp24;
+ USI pc;
} fmt_bra24;
struct { /* e.g. cmp $src1,$src2 */
- SI src1;
- SI src2;
+ BI condbit;
} fmt_cmp;
struct { /* e.g. cmpi $src2,$simm16 */
- SI src2;
- SI simm16;
+ BI condbit;
} fmt_cmpi;
struct { /* e.g. cmpz $src2 */
- SI src2;
+ BI condbit;
} fmt_cmpz;
struct { /* e.g. div $dr,$sr */
SI dr;
- SI sr;
} fmt_div;
struct { /* e.g. jc $sr */
- UBI condbit;
- SI sr;
+ USI pc;
} fmt_jc;
struct { /* e.g. jl $sr */
+ SI h_gr_14;
USI pc;
- SI sr;
} fmt_jl;
struct { /* e.g. jmp $sr */
- SI sr;
+ USI pc;
} fmt_jmp;
struct { /* e.g. ld $dr,@$sr */
- SI h_memory_sr;
- USI sr;
+ SI dr;
} fmt_ld;
struct { /* e.g. ld $dr,@($slo16,$sr) */
- SI h_memory_add__VM_sr_slo16;
- SI sr;
- HI slo16;
+ SI dr;
} fmt_ld_d;
struct { /* e.g. ldb $dr,@$sr */
- QI h_memory_sr;
- USI sr;
+ SI dr;
} fmt_ldb;
struct { /* e.g. ldb $dr,@($slo16,$sr) */
- QI h_memory_add__VM_sr_slo16;
- SI sr;
- HI slo16;
+ SI dr;
} fmt_ldb_d;
struct { /* e.g. ldh $dr,@$sr */
- HI h_memory_sr;
- USI sr;
+ SI dr;
} fmt_ldh;
struct { /* e.g. ldh $dr,@($slo16,$sr) */
- HI h_memory_add__VM_sr_slo16;
- SI sr;
- HI slo16;
+ SI dr;
} fmt_ldh_d;
struct { /* e.g. ld $dr,@$sr+ */
- SI h_memory_sr;
+ SI dr;
SI sr;
} fmt_ld_plus;
struct { /* e.g. ld24 $dr,$uimm24 */
- USI uimm24;
+ SI dr;
} fmt_ld24;
struct { /* e.g. ldi8 $dr,$simm8 */
- SI simm8;
+ SI dr;
} fmt_ldi8;
struct { /* e.g. ldi16 $dr,$hash$slo16 */
- HI slo16;
+ SI dr;
} fmt_ldi16;
struct { /* e.g. lock $dr,@$sr */
- SI h_memory_sr;
- USI sr;
+ BI h_lock_0;
+ SI dr;
} fmt_lock;
struct { /* e.g. machi $src1,$src2,$acc */
DI acc;
- SI src1;
- SI src2;
} fmt_machi_a;
struct { /* e.g. mulhi $src1,$src2,$acc */
- SI src1;
- SI src2;
+ DI acc;
} fmt_mulhi_a;
struct { /* e.g. mv $dr,$sr */
- SI sr;
+ SI dr;
} fmt_mv;
struct { /* e.g. mvfachi $dr,$accs */
- DI accs;
+ SI dr;
} fmt_mvfachi_a;
struct { /* e.g. mvfc $dr,$scr */
- USI scr;
+ SI dr;
} fmt_mvfc;
struct { /* e.g. mvtachi $src1,$accs */
DI accs;
- SI src1;
} fmt_mvtachi_a;
struct { /* e.g. mvtc $sr,$dcr */
- SI sr;
+ USI dcr;
} fmt_mvtc;
struct { /* e.g. nop */
int empty;
} fmt_nop;
struct { /* e.g. rac $accd,$accs,$imm1 */
- DI accs;
- USI imm1;
+ DI accd;
} fmt_rac_dsi;
struct { /* e.g. rte */
- UBI h_bsm_0;
- UBI h_bie_0;
- UBI h_bcond_0;
- SI h_bpc_0;
+ USI pc;
+ USI h_cr_6;
+ UQI h_psw_0;
+ UQI h_bpsw_0;
} fmt_rte;
struct { /* e.g. seth $dr,$hash$hi16 */
- SI hi16;
+ SI dr;
} fmt_seth;
struct { /* e.g. sll3 $dr,$sr,$simm16 */
- SI sr;
- SI simm16;
+ SI dr;
} fmt_sll3;
struct { /* e.g. slli $dr,$uimm5 */
SI dr;
- USI uimm5;
} fmt_slli;
struct { /* e.g. st $src1,@$src2 */
- USI src2;
- SI src1;
+ SI h_memory_src2;
+ USI h_memory_src2_idx;
} fmt_st;
struct { /* e.g. st $src1,@($slo16,$src2) */
- SI src2;
- HI slo16;
- SI src1;
+ SI h_memory_add__VM_src2_slo16;
+ USI h_memory_add__VM_src2_slo16_idx;
} fmt_st_d;
struct { /* e.g. stb $src1,@$src2 */
- USI src2;
- QI src1;
+ QI h_memory_src2;
+ USI h_memory_src2_idx;
} fmt_stb;
struct { /* e.g. stb $src1,@($slo16,$src2) */
- SI src2;
- HI slo16;
- QI src1;
+ QI h_memory_add__VM_src2_slo16;
+ USI h_memory_add__VM_src2_slo16_idx;
} fmt_stb_d;
struct { /* e.g. sth $src1,@$src2 */
- USI src2;
- HI src1;
+ HI h_memory_src2;
+ USI h_memory_src2_idx;
} fmt_sth;
struct { /* e.g. sth $src1,@($slo16,$src2) */
- SI src2;
- HI slo16;
- HI src1;
+ HI h_memory_add__VM_src2_slo16;
+ USI h_memory_add__VM_src2_slo16_idx;
} fmt_sth_d;
struct { /* e.g. st $src1,@+$src2 */
+ SI h_memory_new_src2;
+ USI h_memory_new_src2_idx;
SI src2;
- SI src1;
} fmt_st_plus;
struct { /* e.g. trap $uimm4 */
- USI h_cr_0;
+ USI h_cr_14;
+ USI h_cr_6;
+ UQI h_bbpsw_0;
+ UQI h_bpsw_0;
+ UQI h_psw_0;
SI pc;
- SI uimm4;
} fmt_trap;
struct { /* e.g. unlock $src1,@$src2 */
- UBI h_lock_0;
- USI src2;
- SI src1;
+ SI h_memory_src2;
+ USI h_memory_src2_idx;
+ BI h_lock_0;
} fmt_unlock;
struct { /* e.g. satb $dr,$sr */
- SI sr;
+ SI dr;
} fmt_satb;
struct { /* e.g. sat $dr,$sr */
- UBI condbit;
- SI sr;
+ SI dr;
} fmt_sat;
struct { /* e.g. sadd */
- DI h_accums_1;
DI h_accums_0;
} fmt_sadd;
struct { /* e.g. macwu1 $src1,$src2 */
DI h_accums_1;
- SI src1;
- SI src2;
} fmt_macwu1;
struct { /* e.g. msblo $src1,$src2 */
DI accum;
- SI src1;
- SI src2;
} fmt_msblo;
struct { /* e.g. mulwu1 $src1,$src2 */
- SI src1;
- SI src2;
+ DI h_accums_1;
} fmt_mulwu1;
struct { /* e.g. sc */
- UBI condbit;
+ int empty;
} fmt_sc;
} operands;
+ /* For conditionally written operands, bitmask of which ones were. */
+ int written;
};
-#endif /* CPU_M32RX_H */
+#endif /* CPU_M32RXF_H */
diff --git a/sim/m32r/tconfig.in b/sim/m32r/tconfig.in
index b6f03d7..ddeafd4 100644
--- a/sim/m32r/tconfig.in
+++ b/sim/m32r/tconfig.in
@@ -1,5 +1,8 @@
/* M32R target configuration file. -*- C -*- */
+#ifndef M32R_TCONFIG_H
+#define M32R_TCONFIG_H
+
/* Define this if the simulator can vary the size of memory.
See the xxx simulator for an example.
This enables the `-m size' option.
@@ -7,29 +10,38 @@
/* Not used for M32R since we use the memory module. */
/* #define SIM_HAVE_MEM_SIZE */
+/* See sim-hload.c. We properly handle LMA. */
+#define SIM_HANDLES_LMA 1
+
/* For MSPR support. FIXME: revisit. */
#define WITH_DEVICES 1
-/* The semantic code should probably always use a switch().
- However, in case that's not possible in some circumstance, we allow
- the target to choose. Perhaps this can be autoconf'd on whether the
- switch is too big? I can't (yet) think of a reason for allowing the
- user to choose, though the developer may certainly wish to. */
-#ifdef WANT_CPU_M32R
-#define WITH_FAST 1
-#define WITH_SEM_SWITCH_FULL 0
-#define WITH_SEM_SWITCH_FAST 1
+/* FIXME: Revisit. */
+#ifdef HAVE_DV_SOCKSER
+MODULE_INSTALL_FN dv_sockser_install;
+#define MODULE_LIST dv_sockser_install,
#endif
-#ifdef WANT_CPU_M32RX
-#define HAVE_PARALLEL_EXEC
-#define WITH_FAST 0
-#define WITH_SEM_SWITCH_FULL 1
-#define WITH_SEM_SWITCH_FAST 0
-/* The m32rx currently never uses the scache. So hardcode this off. */
-#undef WITH_SCACHE
-#define WITH_SCACHE 0
+#if 0
+/* Enable watchpoints. */
+#define WITH_WATCHPOINTS 1
#endif
/* ??? Temporary hack until model support unified. */
#define SIM_HAVE_MODEL
+
+/* Define this to enable the intrinsic breakpoint mechanism. */
+/* FIXME: may be able to remove SIM_HAVE_BREAKPOINT since it essentially
+ duplicates ifdef SIM_BREAKPOINT (right?) */
+#if 0
+#define SIM_HAVE_BREAKPOINTS
+#define SIM_BREAKPOINT { 0x10, 0xf1 }
+#define SIM_BREAKPOINT_SIZE 2
+#endif
+
+/* This is a global setting. Different cpu families can't mix-n-match -scache
+ and -bb. However some cpu families may use -simple while others use
+ one of -scache/-bb. */
+#define WITH_SCACHE_PBB 1
+
+#endif /* M32R_TCONFIG_H */
generated by cgit v1.1 at 2024-12-03 19:56:13 +0000