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-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/testsuite/gas/aarch64/addsub.d159
-rw-r--r--gas/testsuite/gas/aarch64/addsub.s16
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/aarch64-asm-2.c2
-rw-r--r--opcodes/aarch64-dis-2.c6
-rw-r--r--opcodes/aarch64-tbl.h2
7 files changed, 191 insertions, 5 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 6ec557d..bf3efdd 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2018-06-22 Tamar Christina <tamar.christina@arm.com>
+
+ * testsuite/gas/aarch64/addsub.s: Add negs to zero reg test.
+ * testsuite/gas/aarch64/addsub.d: Likewise.
+
2018-06-21 Alan Modra <amodra@gmail.com>
* doc/Makefile.am (AUTOMAKE_OPTIONS): Add "foreign".
diff --git a/gas/testsuite/gas/aarch64/addsub.d b/gas/testsuite/gas/aarch64/addsub.d
index 3d25d10..4611220 100644
--- a/gas/testsuite/gas/aarch64/addsub.d
+++ b/gas/testsuite/gas/aarch64/addsub.d
@@ -2369,3 +2369,162 @@ Disassembly of section \.text:
24e4: eb8143e7 negs x7, x1, asr #16
24e8: eb817fe7 negs x7, x1, asr #31
24ec: eb81ffe7 negs x7, x1, asr #63
+ 24f0: 6b0103ff cmp wzr, w1
+ 24f4: 6b0103ff cmp wzr, w1
+ 24f8: 6b0107ff cmp wzr, w1, lsl #1
+ 24fc: 6b010bff cmp wzr, w1, lsl #2
+ 2500: 6b010fff cmp wzr, w1, lsl #3
+ 2504: 6b0113ff cmp wzr, w1, lsl #4
+ 2508: 6b0117ff cmp wzr, w1, lsl #5
+ 250c: 6b0143ff cmp wzr, w1, lsl #16
+ 2510: 6b017fff cmp wzr, w1, lsl #31
+ 2514: 6b4103ff cmp wzr, w1, lsr #0
+ 2518: 6b4107ff cmp wzr, w1, lsr #1
+ 251c: 6b410bff cmp wzr, w1, lsr #2
+ 2520: 6b410fff cmp wzr, w1, lsr #3
+ 2524: 6b4113ff cmp wzr, w1, lsr #4
+ 2528: 6b4117ff cmp wzr, w1, lsr #5
+ 252c: 6b4143ff cmp wzr, w1, lsr #16
+ 2530: 6b417fff cmp wzr, w1, lsr #31
+ 2534: 6b8103ff cmp wzr, w1, asr #0
+ 2538: 6b8107ff cmp wzr, w1, asr #1
+ 253c: 6b810bff cmp wzr, w1, asr #2
+ 2540: 6b810fff cmp wzr, w1, asr #3
+ 2544: 6b8113ff cmp wzr, w1, asr #4
+ 2548: 6b8117ff cmp wzr, w1, asr #5
+ 254c: 6b8143ff cmp wzr, w1, asr #16
+ 2550: 6b817fff cmp wzr, w1, asr #31
+ 2554: eb0103ff cmp xzr, x1
+ 2558: eb0103ff cmp xzr, x1
+ 255c: eb0107ff cmp xzr, x1, lsl #1
+ 2560: eb010bff cmp xzr, x1, lsl #2
+ 2564: eb010fff cmp xzr, x1, lsl #3
+ 2568: eb0113ff cmp xzr, x1, lsl #4
+ 256c: eb0117ff cmp xzr, x1, lsl #5
+ 2570: eb0143ff cmp xzr, x1, lsl #16
+ 2574: eb017fff cmp xzr, x1, lsl #31
+ 2578: eb01ffff cmp xzr, x1, lsl #63
+ 257c: eb4103ff cmp xzr, x1, lsr #0
+ 2580: eb4107ff cmp xzr, x1, lsr #1
+ 2584: eb410bff cmp xzr, x1, lsr #2
+ 2588: eb410fff cmp xzr, x1, lsr #3
+ 258c: eb4113ff cmp xzr, x1, lsr #4
+ 2590: eb4117ff cmp xzr, x1, lsr #5
+ 2594: eb4143ff cmp xzr, x1, lsr #16
+ 2598: eb417fff cmp xzr, x1, lsr #31
+ 259c: eb41ffff cmp xzr, x1, lsr #63
+ 25a0: eb8103ff cmp xzr, x1, asr #0
+ 25a4: eb8107ff cmp xzr, x1, asr #1
+ 25a8: eb810bff cmp xzr, x1, asr #2
+ 25ac: eb810fff cmp xzr, x1, asr #3
+ 25b0: eb8113ff cmp xzr, x1, asr #4
+ 25b4: eb8117ff cmp xzr, x1, asr #5
+ 25b8: eb8143ff cmp xzr, x1, asr #16
+ 25bc: eb817fff cmp xzr, x1, asr #31
+ 25c0: eb81ffff cmp xzr, x1, asr #63
+ 25c4: 6b0103e7 negs w7, w1
+ 25c8: 6b0103e7 negs w7, w1
+ 25cc: 6b0107e7 negs w7, w1, lsl #1
+ 25d0: 6b010be7 negs w7, w1, lsl #2
+ 25d4: 6b010fe7 negs w7, w1, lsl #3
+ 25d8: 6b0113e7 negs w7, w1, lsl #4
+ 25dc: 6b0117e7 negs w7, w1, lsl #5
+ 25e0: 6b0143e7 negs w7, w1, lsl #16
+ 25e4: 6b017fe7 negs w7, w1, lsl #31
+ 25e8: 6b4103e7 negs w7, w1, lsr #0
+ 25ec: 6b4107e7 negs w7, w1, lsr #1
+ 25f0: 6b410be7 negs w7, w1, lsr #2
+ 25f4: 6b410fe7 negs w7, w1, lsr #3
+ 25f8: 6b4113e7 negs w7, w1, lsr #4
+ 25fc: 6b4117e7 negs w7, w1, lsr #5
+ 2600: 6b4143e7 negs w7, w1, lsr #16
+ 2604: 6b417fe7 negs w7, w1, lsr #31
+ 2608: 6b8103e7 negs w7, w1, asr #0
+ 260c: 6b8107e7 negs w7, w1, asr #1
+ 2610: 6b810be7 negs w7, w1, asr #2
+ 2614: 6b810fe7 negs w7, w1, asr #3
+ 2618: 6b8113e7 negs w7, w1, asr #4
+ 261c: 6b8117e7 negs w7, w1, asr #5
+ 2620: 6b8143e7 negs w7, w1, asr #16
+ 2624: 6b817fe7 negs w7, w1, asr #31
+ 2628: eb0103e7 negs x7, x1
+ 262c: eb0103e7 negs x7, x1
+ 2630: eb0107e7 negs x7, x1, lsl #1
+ 2634: eb010be7 negs x7, x1, lsl #2
+ 2638: eb010fe7 negs x7, x1, lsl #3
+ 263c: eb0113e7 negs x7, x1, lsl #4
+ 2640: eb0117e7 negs x7, x1, lsl #5
+ 2644: eb0143e7 negs x7, x1, lsl #16
+ 2648: eb017fe7 negs x7, x1, lsl #31
+ 264c: eb01ffe7 negs x7, x1, lsl #63
+ 2650: eb4103e7 negs x7, x1, lsr #0
+ 2654: eb4107e7 negs x7, x1, lsr #1
+ 2658: eb410be7 negs x7, x1, lsr #2
+ 265c: eb410fe7 negs x7, x1, lsr #3
+ 2660: eb4113e7 negs x7, x1, lsr #4
+ 2664: eb4117e7 negs x7, x1, lsr #5
+ 2668: eb4143e7 negs x7, x1, lsr #16
+ 266c: eb417fe7 negs x7, x1, lsr #31
+ 2670: eb41ffe7 negs x7, x1, lsr #63
+ 2674: eb8103e7 negs x7, x1, asr #0
+ 2678: eb8107e7 negs x7, x1, asr #1
+ 267c: eb810be7 negs x7, x1, asr #2
+ 2680: eb810fe7 negs x7, x1, asr #3
+ 2684: eb8113e7 negs x7, x1, asr #4
+ 2688: eb8117e7 negs x7, x1, asr #5
+ 268c: eb8143e7 negs x7, x1, asr #16
+ 2690: eb817fe7 negs x7, x1, asr #31
+ 2694: eb81ffe7 negs x7, x1, asr #63
+ 2698: 6b0103f0 negs w16, w1
+ 269c: 6b0103f0 negs w16, w1
+ 26a0: 6b0107f0 negs w16, w1, lsl #1
+ 26a4: 6b010bf0 negs w16, w1, lsl #2
+ 26a8: 6b010ff0 negs w16, w1, lsl #3
+ 26ac: 6b0113f0 negs w16, w1, lsl #4
+ 26b0: 6b0117f0 negs w16, w1, lsl #5
+ 26b4: 6b0143f0 negs w16, w1, lsl #16
+ 26b8: 6b017ff0 negs w16, w1, lsl #31
+ 26bc: 6b4103f0 negs w16, w1, lsr #0
+ 26c0: 6b4107f0 negs w16, w1, lsr #1
+ 26c4: 6b410bf0 negs w16, w1, lsr #2
+ 26c8: 6b410ff0 negs w16, w1, lsr #3
+ 26cc: 6b4113f0 negs w16, w1, lsr #4
+ 26d0: 6b4117f0 negs w16, w1, lsr #5
+ 26d4: 6b4143f0 negs w16, w1, lsr #16
+ 26d8: 6b417ff0 negs w16, w1, lsr #31
+ 26dc: 6b8103f0 negs w16, w1, asr #0
+ 26e0: 6b8107f0 negs w16, w1, asr #1
+ 26e4: 6b810bf0 negs w16, w1, asr #2
+ 26e8: 6b810ff0 negs w16, w1, asr #3
+ 26ec: 6b8113f0 negs w16, w1, asr #4
+ 26f0: 6b8117f0 negs w16, w1, asr #5
+ 26f4: 6b8143f0 negs w16, w1, asr #16
+ 26f8: 6b817ff0 negs w16, w1, asr #31
+ 26fc: eb0103f0 negs x16, x1
+ 2700: eb0103f0 negs x16, x1
+ 2704: eb0107f0 negs x16, x1, lsl #1
+ 2708: eb010bf0 negs x16, x1, lsl #2
+ 270c: eb010ff0 negs x16, x1, lsl #3
+ 2710: eb0113f0 negs x16, x1, lsl #4
+ 2714: eb0117f0 negs x16, x1, lsl #5
+ 2718: eb0143f0 negs x16, x1, lsl #16
+ 271c: eb017ff0 negs x16, x1, lsl #31
+ 2720: eb01fff0 negs x16, x1, lsl #63
+ 2724: eb4103f0 negs x16, x1, lsr #0
+ 2728: eb4107f0 negs x16, x1, lsr #1
+ 272c: eb410bf0 negs x16, x1, lsr #2
+ 2730: eb410ff0 negs x16, x1, lsr #3
+ 2734: eb4113f0 negs x16, x1, lsr #4
+ 2738: eb4117f0 negs x16, x1, lsr #5
+ 273c: eb4143f0 negs x16, x1, lsr #16
+ 2740: eb417ff0 negs x16, x1, lsr #31
+ 2744: eb41fff0 negs x16, x1, lsr #63
+ 2748: eb8103f0 negs x16, x1, asr #0
+ 274c: eb8107f0 negs x16, x1, asr #1
+ 2750: eb810bf0 negs x16, x1, asr #2
+ 2754: eb810ff0 negs x16, x1, asr #3
+ 2758: eb8113f0 negs x16, x1, asr #4
+ 275c: eb8117f0 negs x16, x1, asr #5
+ 2760: eb8143f0 negs x16, x1, asr #16
+ 2764: eb817ff0 negs x16, x1, asr #31
+ 2768: eb81fff0 negs x16, x1, asr #63
diff --git a/gas/testsuite/gas/aarch64/addsub.s b/gas/testsuite/gas/aarch64/addsub.s
index 6eb2389..f610521 100644
--- a/gas/testsuite/gas/aarch64/addsub.s
+++ b/gas/testsuite/gas/aarch64/addsub.s
@@ -222,3 +222,19 @@ func:
do_shift 2, \op, W7, W
do_shift 2, \op, X7, X
.endr
+
+ /*
+ * Check for correct aliasing
+ */
+
+ .irp op, NEGS
+ do_shift 2, \op, WZR, W
+ do_shift 2, \op, XZR, X
+ .endr
+
+ .irp op, SUBS
+ do_shift 3, \op, W7, W
+ do_shift 3, \op, X7, X
+ do_shift 0, \op, WZR, W
+ do_shift 0, \op, XZR, X
+ .endr
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d455a38..2c2b975 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2018-06-19 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Likewise.
+
2018-06-21 Maciej W. Rozycki <macro@mips.com>
* mips-dis.c (print_mips_disassembler_options): Fix a typo in
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 01bc0e1..45b0085 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -66,8 +66,8 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 22: /* sub */
value = 22; /* --> sub. */
break;
- case 26: /* negs */
case 25: /* cmp */
+ case 26: /* negs */
case 24: /* subs */
value = 24; /* --> subs. */
break;
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index cf0288f..5218297 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -19404,7 +19404,7 @@ aarch64_find_alias_opcode (const aarch64_opcode *opcode)
case 17: value = 18; break; /* subs --> cmp. */
case 20: value = 21; break; /* adds --> cmn. */
case 22: value = 23; break; /* sub --> neg. */
- case 24: value = 26; break; /* subs --> negs. */
+ case 24: value = 25; break; /* subs --> cmp. */
case 150: value = 151; break; /* umov --> mov. */
case 152: value = 153; break; /* ins --> mov. */
case 154: value = 155; break; /* ins --> mov. */
@@ -19543,8 +19543,8 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode)
case 18: value = 17; break; /* cmp --> subs. */
case 21: value = 20; break; /* cmn --> adds. */
case 23: value = 22; break; /* neg --> sub. */
- case 26: value = 25; break; /* negs --> cmp. */
- case 25: value = 24; break; /* cmp --> subs. */
+ case 25: value = 26; break; /* cmp --> negs. */
+ case 26: value = 24; break; /* negs --> subs. */
case 151: value = 150; break; /* mov --> umov. */
case 153: value = 152; break; /* mov --> ins. */
case 155: value = 154; break; /* mov --> ins. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 1a35b3f..08eec60 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2266,7 +2266,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("sub", 0x4b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
CORE_INSN ("neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF),
CORE_INSN ("subs", 0x6b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
- CORE_INSN ("cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF),
+ CORE_INSN ("cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF | F_P1),
CORE_INSN ("negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF),
/* AdvSIMD across lanes. */
SIMD_INSN ("saddlv", 0x0e303800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ),
generated by cgit v1.1 at 2024-11-24 06:06:15 +0000