diff options
| -rw-r--r-- | sim/frv/ChangeLog | 34 | ||||
| -rw-r--r-- | sim/frv/arch.h | 51 | ||||
| -rw-r--r-- | sim/frv/cpu.h | 15 | ||||
| -rw-r--r-- | sim/frv/decode.c | 37 | ||||
| -rw-r--r-- | sim/frv/decode.h | 391 | ||||
| -rw-r--r-- | sim/frv/model.c | 133 | ||||
| -rw-r--r-- | sim/frv/profile-fr400.c | 49 | ||||
| -rw-r--r-- | sim/frv/profile-fr500.c | 190 | ||||
| -rw-r--r-- | sim/frv/profile.c | 99 | ||||
| -rw-r--r-- | sim/frv/profile.h | 4 | ||||
| -rw-r--r-- | sim/frv/sem.c | 33 |
11 files changed, 532 insertions, 504 deletions
diff --git a/sim/frv/ChangeLog b/sim/frv/ChangeLog index a5ce891..ff45fb1 100644 --- a/sim/frv/ChangeLog +++ b/sim/frv/ChangeLog @@ -1,3 +1,37 @@ +2003-09-24 Dave Brolley <brolley@redhat.com> + + * profile.h (update_FR_ptime): New prototype. + (update_FRdouble_ptime): Ditto. + (update_SPR_ptime): Ditto. + (increase_ACC_busy): Ditto. + (enforce_full_acc_latency): Ditto. + (post_wait_for_SPR): Ditto. + * profile.c (update_FR_ptime): Moved here from profile-fr500.c. + (update_FRdouble_ptime): Ditto. + (update_SPR_ptime): New function. + (increase_ACC_busy): Ditto. + (enforce_full_acc_latency): Ditto. + (vliw_wait_for_fdiv_resource): Correct resource name. + (vliw_wait_for_fsqrt_resource): Ditto. + (post_wait_for_SPR): New function. + * profile-fr500.c (frvbf_model_fr500_u_commit): New function. + (frvbf_model_fr500_u_gr2fr): Pass out_FRk as output register to + adjust_float_register_busy. + (frvbf_model_fr500_u_gr_load): Record latency of SPR registers. + (frvbf_model_fr500_u_fr_load): Wait for and record latency of SPR + registers. + (frvbf_model_fr500_u_float_arith): Ditto. + (frvbf_model_fr500_u_float_dual_arith): Ditto. + (frvbf_model_fr500_u_float_div): Ditto. + (frvbf_model_fr500_u_float_sqrt): Ditto. + (frvbf_model_fr500_u_float_convert): Ditto. + (update_FR_ptime): Moved to profile.c + (update_FRdouble_ptime): Moved to profile.c + * profile-fr400.c (update_FR_ptime): Removed. Identical to functions + for other machines. + (update_FRdouble_ptime): Ditto. + * arch.h,cpu.h,sem.c,decode.[ch],model.c,sem.c: Regenerated. + 2003-09-12 Dave Brolley <brolley@redhat.com> * registers.c (frv_check_spr_read_access): Check for access to diff --git a/sim/frv/arch.h b/sim/frv/arch.h index 99fb1b3..5a32e49 100644 --- a/sim/frv/arch.h +++ b/sim/frv/arch.h @@ -37,31 +37,32 @@ typedef enum model_type { /* Enum declaration for unit types. */ typedef enum unit_type { - UNIT_NONE, UNIT_FRV_U_EXEC, UNIT_FR500_U_DCUL, UNIT_FR500_U_ICUL - , UNIT_FR500_U_DCPL, UNIT_FR500_U_ICPL, UNIT_FR500_U_DCF, UNIT_FR500_U_DCI - , UNIT_FR500_U_ICI, UNIT_FR500_U_MEMBAR, UNIT_FR500_U_BARRIER, UNIT_FR500_U_MEDIA_DUAL_BTOHE - , UNIT_FR500_U_MEDIA_DUAL_HTOB, UNIT_FR500_U_MEDIA_DUAL_BTOH, UNIT_FR500_U_MEDIA_DUAL_UNPACK, UNIT_FR500_U_MEDIA_DUAL_EXPAND - , UNIT_FR500_U_MEDIA_QUAD_COMPLEX, UNIT_FR500_U_MEDIA_QUAD_MUL, UNIT_FR500_U_MEDIA_DUAL_MUL, UNIT_FR500_U_MEDIA_QUAD_ARITH - , UNIT_FR500_U_MEDIA, UNIT_FR500_U_FLOAT_DUAL_CONVERT, UNIT_FR500_U_FLOAT_CONVERT, UNIT_FR500_U_FLOAT_DUAL_COMPARE - , UNIT_FR500_U_FLOAT_COMPARE, UNIT_FR500_U_FLOAT_DUAL_SQRT, UNIT_FR500_U_FLOAT_SQRT, UNIT_FR500_U_FLOAT_DIV - , UNIT_FR500_U_FLOAT_DUAL_ARITH, UNIT_FR500_U_FLOAT_ARITH, UNIT_FR500_U_GR2SPR, UNIT_FR500_U_GR2FR - , UNIT_FR500_U_SPR2GR, UNIT_FR500_U_FR2GR, UNIT_FR500_U_FR2FR, UNIT_FR500_U_SWAP - , UNIT_FR500_U_FR_R_STORE, UNIT_FR500_U_FR_STORE, UNIT_FR500_U_FR_LOAD, UNIT_FR500_U_GR_R_STORE - , UNIT_FR500_U_GR_STORE, UNIT_FR500_U_GR_LOAD, UNIT_FR500_U_SET_HILO, UNIT_FR500_U_CLRFR - , UNIT_FR500_U_CLRGR, UNIT_FR500_U_CHECK, UNIT_FR500_U_TRAP, UNIT_FR500_U_BRANCH - , UNIT_FR500_U_IDIV, UNIT_FR500_U_IMUL, UNIT_FR500_U_INTEGER, UNIT_FR500_U_EXEC - , UNIT_TOMCAT_U_EXEC, UNIT_FR400_U_DCUL, UNIT_FR400_U_ICUL, UNIT_FR400_U_DCPL - , UNIT_FR400_U_ICPL, UNIT_FR400_U_DCF, UNIT_FR400_U_DCI, UNIT_FR400_U_ICI - , UNIT_FR400_U_MEMBAR, UNIT_FR400_U_BARRIER, UNIT_FR400_U_MEDIA_DUAL_HTOB, UNIT_FR400_U_MEDIA_DUAL_EXPAND - , UNIT_FR400_U_MEDIA_7, UNIT_FR400_U_MEDIA_6, UNIT_FR400_U_MEDIA_4_ACC_DUAL, UNIT_FR400_U_MEDIA_4_ACCG - , UNIT_FR400_U_MEDIA_4, UNIT_FR400_U_MEDIA_3_QUAD, UNIT_FR400_U_MEDIA_3_DUAL, UNIT_FR400_U_MEDIA_3 - , UNIT_FR400_U_MEDIA_2_ADD_SUB_DUAL, UNIT_FR400_U_MEDIA_2_ADD_SUB, UNIT_FR400_U_MEDIA_2_ACC_DUAL, UNIT_FR400_U_MEDIA_2_ACC - , UNIT_FR400_U_MEDIA_2_QUAD, UNIT_FR400_U_MEDIA_2, UNIT_FR400_U_MEDIA_HILO, UNIT_FR400_U_MEDIA_1_QUAD - , UNIT_FR400_U_MEDIA_1, UNIT_FR400_U_GR2SPR, UNIT_FR400_U_GR2FR, UNIT_FR400_U_SPR2GR - , UNIT_FR400_U_FR2GR, UNIT_FR400_U_SWAP, UNIT_FR400_U_FR_STORE, UNIT_FR400_U_FR_LOAD - , UNIT_FR400_U_GR_STORE, UNIT_FR400_U_GR_LOAD, UNIT_FR400_U_SET_HILO, UNIT_FR400_U_CHECK - , UNIT_FR400_U_TRAP, UNIT_FR400_U_BRANCH, UNIT_FR400_U_IDIV, UNIT_FR400_U_IMUL - , UNIT_FR400_U_INTEGER, UNIT_FR400_U_EXEC, UNIT_SIMPLE_U_EXEC, UNIT_MAX + UNIT_NONE, UNIT_FRV_U_EXEC, UNIT_FR500_U_COMMIT, UNIT_FR500_U_DCUL + , UNIT_FR500_U_ICUL, UNIT_FR500_U_DCPL, UNIT_FR500_U_ICPL, UNIT_FR500_U_DCF + , UNIT_FR500_U_DCI, UNIT_FR500_U_ICI, UNIT_FR500_U_MEMBAR, UNIT_FR500_U_BARRIER + , UNIT_FR500_U_MEDIA_DUAL_BTOHE, UNIT_FR500_U_MEDIA_DUAL_HTOB, UNIT_FR500_U_MEDIA_DUAL_BTOH, UNIT_FR500_U_MEDIA_DUAL_UNPACK + , UNIT_FR500_U_MEDIA_DUAL_EXPAND, UNIT_FR500_U_MEDIA_QUAD_COMPLEX, UNIT_FR500_U_MEDIA_QUAD_MUL, UNIT_FR500_U_MEDIA_DUAL_MUL + , UNIT_FR500_U_MEDIA_QUAD_ARITH, UNIT_FR500_U_MEDIA, UNIT_FR500_U_FLOAT_DUAL_CONVERT, UNIT_FR500_U_FLOAT_CONVERT + , UNIT_FR500_U_FLOAT_DUAL_COMPARE, UNIT_FR500_U_FLOAT_COMPARE, UNIT_FR500_U_FLOAT_DUAL_SQRT, UNIT_FR500_U_FLOAT_SQRT + , UNIT_FR500_U_FLOAT_DIV, UNIT_FR500_U_FLOAT_DUAL_ARITH, UNIT_FR500_U_FLOAT_ARITH, UNIT_FR500_U_GR2SPR + , UNIT_FR500_U_GR2FR, UNIT_FR500_U_SPR2GR, UNIT_FR500_U_FR2GR, UNIT_FR500_U_FR2FR + , UNIT_FR500_U_SWAP, UNIT_FR500_U_FR_R_STORE, UNIT_FR500_U_FR_STORE, UNIT_FR500_U_FR_LOAD + , UNIT_FR500_U_GR_R_STORE, UNIT_FR500_U_GR_STORE, UNIT_FR500_U_GR_LOAD, UNIT_FR500_U_SET_HILO + , UNIT_FR500_U_CLRFR, UNIT_FR500_U_CLRGR, UNIT_FR500_U_CHECK, UNIT_FR500_U_TRAP + , UNIT_FR500_U_BRANCH, UNIT_FR500_U_IDIV, UNIT_FR500_U_IMUL, UNIT_FR500_U_INTEGER + , UNIT_FR500_U_EXEC, UNIT_TOMCAT_U_EXEC, UNIT_FR400_U_DCUL, UNIT_FR400_U_ICUL + , UNIT_FR400_U_DCPL, UNIT_FR400_U_ICPL, UNIT_FR400_U_DCF, UNIT_FR400_U_DCI + , UNIT_FR400_U_ICI, UNIT_FR400_U_MEMBAR, UNIT_FR400_U_BARRIER, UNIT_FR400_U_MEDIA_DUAL_HTOB + , UNIT_FR400_U_MEDIA_DUAL_EXPAND, UNIT_FR400_U_MEDIA_7, UNIT_FR400_U_MEDIA_6, UNIT_FR400_U_MEDIA_4_ACC_DUAL + , UNIT_FR400_U_MEDIA_4_ACCG, UNIT_FR400_U_MEDIA_4, UNIT_FR400_U_MEDIA_3_QUAD, UNIT_FR400_U_MEDIA_3_DUAL + , UNIT_FR400_U_MEDIA_3, UNIT_FR400_U_MEDIA_2_ADD_SUB_DUAL, UNIT_FR400_U_MEDIA_2_ADD_SUB, UNIT_FR400_U_MEDIA_2_ACC_DUAL + , UNIT_FR400_U_MEDIA_2_ACC, UNIT_FR400_U_MEDIA_2_QUAD, UNIT_FR400_U_MEDIA_2, UNIT_FR400_U_MEDIA_HILO + , UNIT_FR400_U_MEDIA_1_QUAD, UNIT_FR400_U_MEDIA_1, UNIT_FR400_U_GR2SPR, UNIT_FR400_U_GR2FR + , UNIT_FR400_U_SPR2GR, UNIT_FR400_U_FR2GR, UNIT_FR400_U_SWAP, UNIT_FR400_U_FR_STORE + , UNIT_FR400_U_FR_LOAD, UNIT_FR400_U_GR_STORE, UNIT_FR400_U_GR_LOAD, UNIT_FR400_U_SET_HILO + , UNIT_FR400_U_CHECK, UNIT_FR400_U_TRAP, UNIT_FR400_U_BRANCH, UNIT_FR400_U_IDIV + , UNIT_FR400_U_IMUL, UNIT_FR400_U_INTEGER, UNIT_FR400_U_EXEC, UNIT_SIMPLE_U_EXEC + , UNIT_MAX } UNIT_TYPE; #define MAX_UNITS (1) diff --git a/sim/frv/cpu.h b/sim/frv/cpu.h index d2328fd..1b0a4fd 100644 --- a/sim/frv/cpu.h +++ b/sim/frv/cpu.h @@ -140,7 +140,7 @@ frvbf_h_spr_set_handler (current_cpu, (index), (x));\ UQI h_iccr[4]; #define GET_H_ICCR(a1) CPU (h_iccr)[a1] #define SET_H_ICCR(a1, x) (CPU (h_iccr)[a1] = (x)) - /* Integer condition code registers */ + /* Floating point condition code registers */ UQI h_fccr[4]; #define GET_H_FCCR(a1) CPU (h_fccr)[a1] #define SET_H_FCCR(a1, x) (CPU (h_fccr)[a1] = (x)) @@ -419,12 +419,6 @@ union sem_fields { unsigned char out_GRklo; } sfmt_setlo; struct { /* */ - UINT f_ACCGk; - UINT f_FRi; - unsigned char in_FRinti; - unsigned char out_ACCGk; - } sfmt_mwtaccg; - struct { /* */ UINT f_ACCGi; UINT f_FRk; unsigned char in_ACCGi; @@ -485,6 +479,13 @@ union sem_fields { unsigned char in_GRj; } sfmt_movgs; struct { /* */ + UINT f_ACCGk; + UINT f_FRi; + unsigned char in_ACCGk; + unsigned char in_FRinti; + unsigned char out_ACCGk; + } sfmt_mwtaccg; + struct { /* */ INT f_s6; UINT f_ACC40Si; UINT f_FRk; diff --git a/sim/frv/decode.c b/sim/frv/decode.c index e018efc..0fe1a17 100644 --- a/sim/frv/decode.c +++ b/sim/frv/decode.c @@ -208,7 +208,6 @@ static const struct insn_sem frvbf_insn_sem[] = { FRV_INSN_NLDDFI, FRVBF_INSN_NLDDFI, FRVBF_SFMT_NLDDFI }, { FRV_INSN_LDQI, FRVBF_INSN_LDQI, FRVBF_SFMT_LDQI }, { FRV_INSN_LDQFI, FRVBF_INSN_LDQFI, FRVBF_SFMT_LDQFI }, - { FRV_INSN_NLDQI, FRVBF_INSN_NLDQI, FRVBF_SFMT_NLDQI }, { FRV_INSN_NLDQFI, FRVBF_INSN_NLDQFI, FRVBF_SFMT_NLDQFI }, { FRV_INSN_STB, FRVBF_INSN_STB, FRVBF_SFMT_STB }, { FRV_INSN_STH, FRVBF_INSN_STH, FRVBF_SFMT_STB }, @@ -1409,7 +1408,6 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, case 67 : itype = FRVBF_INSN_NLDUHI; goto extract_sfmt_nldsbi; case 68 : itype = FRVBF_INSN_NLDI; goto extract_sfmt_nldsbi; case 69 : itype = FRVBF_INSN_NLDDI; goto extract_sfmt_nlddi; - case 70 : itype = FRVBF_INSN_NLDQI; goto extract_sfmt_nldqi; case 71 : itype = FRVBF_INSN_SCANI; goto extract_sfmt_addi; case 72 : itype = FRVBF_INSN_NLDBFI; goto extract_sfmt_nldbfi; case 73 : itype = FRVBF_INSN_NLDHFI; goto extract_sfmt_nldbfi; @@ -4383,36 +4381,6 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_sfmt_nldqi: - { - const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_stdi.f - UINT f_GRk; - UINT f_GRi; - INT f_d12; - - f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); - f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); - f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12); - - /* Record the fields for the semantic handler. */ - FLD (f_GRi) = f_GRi; - FLD (f_d12) = f_d12; - FLD (f_GRk) = f_GRk; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldqi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_GRi) = f_GRi; - } -#endif -#undef FLD - return idesc; - } - extract_sfmt_nldqfi: { const IDESC *idesc = &frvbf_insn_data[itype]; @@ -10999,14 +10967,15 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); /* Record the fields for the semantic handler. */ - FLD (f_FRi) = f_FRi; FLD (f_ACCGk) = f_ACCGk; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mwtaccg", "f_FRi 0x%x", 'x', f_FRi, "f_ACCGk 0x%x", 'x', f_ACCGk, (char *) 0)); + FLD (f_FRi) = f_FRi; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mwtaccg", "f_ACCGk 0x%x", 'x', f_ACCGk, "f_FRi 0x%x", 'x', f_FRi, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { + FLD (in_ACCGk) = f_ACCGk; FLD (in_FRinti) = f_FRi; FLD (out_ACCGk) = f_ACCGk; } diff --git a/sim/frv/decode.h b/sim/frv/decode.h index 9544b12..93d2367 100644 --- a/sim/frv/decode.h +++ b/sim/frv/decode.h @@ -76,151 +76,151 @@ typedef enum frvbf_insn_type { , FRVBF_INSN_NLDSHI, FRVBF_INSN_NLDUHI, FRVBF_INSN_NLDI, FRVBF_INSN_NLDBFI , FRVBF_INSN_NLDHFI, FRVBF_INSN_NLDFI, FRVBF_INSN_LDDI, FRVBF_INSN_LDDFI , FRVBF_INSN_NLDDI, FRVBF_INSN_NLDDFI, FRVBF_INSN_LDQI, FRVBF_INSN_LDQFI - , FRVBF_INSN_NLDQI, FRVBF_INSN_NLDQFI, FRVBF_INSN_STB, FRVBF_INSN_STH - , FRVBF_INSN_ST, FRVBF_INSN_STBF, FRVBF_INSN_STHF, FRVBF_INSN_STF - , FRVBF_INSN_STC, FRVBF_INSN_RSTB, FRVBF_INSN_RSTH, FRVBF_INSN_RST - , FRVBF_INSN_RSTBF, FRVBF_INSN_RSTHF, FRVBF_INSN_RSTF, FRVBF_INSN_STD - , FRVBF_INSN_STDF, FRVBF_INSN_STDC, FRVBF_INSN_RSTD, FRVBF_INSN_RSTDF - , FRVBF_INSN_STQ, FRVBF_INSN_STQF, FRVBF_INSN_STQC, FRVBF_INSN_RSTQ - , FRVBF_INSN_RSTQF, FRVBF_INSN_STBU, FRVBF_INSN_STHU, FRVBF_INSN_STU - , FRVBF_INSN_STBFU, FRVBF_INSN_STHFU, FRVBF_INSN_STFU, FRVBF_INSN_STCU - , FRVBF_INSN_STDU, FRVBF_INSN_STDFU, FRVBF_INSN_STDCU, FRVBF_INSN_STQU - , FRVBF_INSN_STQFU, FRVBF_INSN_STQCU, FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB - , FRVBF_INSN_CLDSH, FRVBF_INSN_CLDUH, FRVBF_INSN_CLD, FRVBF_INSN_CLDBF - , FRVBF_INSN_CLDHF, FRVBF_INSN_CLDF, FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF - , FRVBF_INSN_CLDQ, FRVBF_INSN_CLDSBU, FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU - , FRVBF_INSN_CLDUHU, FRVBF_INSN_CLDU, FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU - , FRVBF_INSN_CLDFU, FRVBF_INSN_CLDDU, FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU - , FRVBF_INSN_CSTB, FRVBF_INSN_CSTH, FRVBF_INSN_CST, FRVBF_INSN_CSTBF - , FRVBF_INSN_CSTHF, FRVBF_INSN_CSTF, FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF - , FRVBF_INSN_CSTQ, FRVBF_INSN_CSTBU, FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU - , FRVBF_INSN_CSTBFU, FRVBF_INSN_CSTHFU, FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU - , FRVBF_INSN_CSTDFU, FRVBF_INSN_STBI, FRVBF_INSN_STHI, FRVBF_INSN_STI - , FRVBF_INSN_STBFI, FRVBF_INSN_STHFI, FRVBF_INSN_STFI, FRVBF_INSN_STDI - , FRVBF_INSN_STDFI, FRVBF_INSN_STQI, FRVBF_INSN_STQFI, FRVBF_INSN_SWAP - , FRVBF_INSN_SWAPI, FRVBF_INSN_CSWAP, FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG - , FRVBF_INSN_MOVGFD, FRVBF_INSN_MOVFGD, FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ - , FRVBF_INSN_CMOVGF, FRVBF_INSN_CMOVFG, FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD - , FRVBF_INSN_MOVGS, FRVBF_INSN_MOVSG, FRVBF_INSN_BRA, FRVBF_INSN_BNO - , FRVBF_INSN_BEQ, FRVBF_INSN_BNE, FRVBF_INSN_BLE, FRVBF_INSN_BGT - , FRVBF_INSN_BLT, FRVBF_INSN_BGE, FRVBF_INSN_BLS, FRVBF_INSN_BHI - , FRVBF_INSN_BC, FRVBF_INSN_BNC, FRVBF_INSN_BN, FRVBF_INSN_BP - , FRVBF_INSN_BV, FRVBF_INSN_BNV, FRVBF_INSN_FBRA, FRVBF_INSN_FBNO - , FRVBF_INSN_FBNE, FRVBF_INSN_FBEQ, FRVBF_INSN_FBLG, FRVBF_INSN_FBUE - , FRVBF_INSN_FBUL, FRVBF_INSN_FBGE, FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE - , FRVBF_INSN_FBUG, FRVBF_INSN_FBLE, FRVBF_INSN_FBGT, FRVBF_INSN_FBULE - , FRVBF_INSN_FBU, FRVBF_INSN_FBO, FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR - , FRVBF_INSN_BNOLR, FRVBF_INSN_BEQLR, FRVBF_INSN_BNELR, FRVBF_INSN_BLELR - , FRVBF_INSN_BGTLR, FRVBF_INSN_BLTLR, FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR - , FRVBF_INSN_BHILR, FRVBF_INSN_BCLR, FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR - , FRVBF_INSN_BPLR, FRVBF_INSN_BVLR, FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR - , FRVBF_INSN_FBNOLR, FRVBF_INSN_FBEQLR, FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR - , FRVBF_INSN_FBUELR, FRVBF_INSN_FBULLR, FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR - , FRVBF_INSN_FBUGELR, FRVBF_INSN_FBUGLR, FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR - , FRVBF_INSN_FBULELR, FRVBF_INSN_FBULR, FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR - , FRVBF_INSN_BCNOLR, FRVBF_INSN_BCEQLR, FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR - , FRVBF_INSN_BCGTLR, FRVBF_INSN_BCLTLR, FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR - , FRVBF_INSN_BCHILR, FRVBF_INSN_BCCLR, FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR - , FRVBF_INSN_BCPLR, FRVBF_INSN_BCVLR, FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR - , FRVBF_INSN_FCBNOLR, FRVBF_INSN_FCBEQLR, FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR - , FRVBF_INSN_FCBUELR, FRVBF_INSN_FCBULLR, FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR - , FRVBF_INSN_FCBUGELR, FRVBF_INSN_FCBUGLR, FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR - , FRVBF_INSN_FCBULELR, FRVBF_INSN_FCBULR, FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL - , FRVBF_INSN_CALLL, FRVBF_INSN_JMPIL, FRVBF_INSN_CALLIL, FRVBF_INSN_CALL - , FRVBF_INSN_RETT, FRVBF_INSN_REI, FRVBF_INSN_TRA, FRVBF_INSN_TNO - , FRVBF_INSN_TEQ, FRVBF_INSN_TNE, FRVBF_INSN_TLE, FRVBF_INSN_TGT - , FRVBF_INSN_TLT, FRVBF_INSN_TGE, FRVBF_INSN_TLS, FRVBF_INSN_THI - , FRVBF_INSN_TC, FRVBF_INSN_TNC, FRVBF_INSN_TN, FRVBF_INSN_TP - , FRVBF_INSN_TV, FRVBF_INSN_TNV, FRVBF_INSN_FTRA, FRVBF_INSN_FTNO - , FRVBF_INSN_FTNE, FRVBF_INSN_FTEQ, FRVBF_INSN_FTLG, FRVBF_INSN_FTUE - , FRVBF_INSN_FTUL, FRVBF_INSN_FTGE, FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE - , FRVBF_INSN_FTUG, FRVBF_INSN_FTLE, FRVBF_INSN_FTGT, FRVBF_INSN_FTULE - , FRVBF_INSN_FTU, FRVBF_INSN_FTO, FRVBF_INSN_TIRA, FRVBF_INSN_TINO - , FRVBF_INSN_TIEQ, FRVBF_INSN_TINE, FRVBF_INSN_TILE, FRVBF_INSN_TIGT - , FRVBF_INSN_TILT, FRVBF_INSN_TIGE, FRVBF_INSN_TILS, FRVBF_INSN_TIHI - , FRVBF_INSN_TIC, FRVBF_INSN_TINC, FRVBF_INSN_TIN, FRVBF_INSN_TIP - , FRVBF_INSN_TIV, FRVBF_INSN_TINV, FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO - , FRVBF_INSN_FTINE, FRVBF_INSN_FTIEQ, FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE - , FRVBF_INSN_FTIUL, FRVBF_INSN_FTIGE, FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE - , FRVBF_INSN_FTIUG, FRVBF_INSN_FTILE, FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE - , FRVBF_INSN_FTIU, FRVBF_INSN_FTIO, FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP - , FRVBF_INSN_ANDCR, FRVBF_INSN_ORCR, FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR - , FRVBF_INSN_NORCR, FRVBF_INSN_ANDNCR, FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR - , FRVBF_INSN_NORNCR, FRVBF_INSN_NOTCR, FRVBF_INSN_CKRA, FRVBF_INSN_CKNO - , FRVBF_INSN_CKEQ, FRVBF_INSN_CKNE, FRVBF_INSN_CKLE, FRVBF_INSN_CKGT - , FRVBF_INSN_CKLT, FRVBF_INSN_CKGE, FRVBF_INSN_CKLS, FRVBF_INSN_CKHI - , FRVBF_INSN_CKC, FRVBF_INSN_CKNC, FRVBF_INSN_CKN, FRVBF_INSN_CKP - , FRVBF_INSN_CKV, FRVBF_INSN_CKNV, FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO - , FRVBF_INSN_FCKNE, FRVBF_INSN_FCKEQ, FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE - , FRVBF_INSN_FCKUL, FRVBF_INSN_FCKGE, FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE - , FRVBF_INSN_FCKUG, FRVBF_INSN_FCKLE, FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE - , FRVBF_INSN_FCKU, FRVBF_INSN_FCKO, FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO - , FRVBF_INSN_CCKEQ, FRVBF_INSN_CCKNE, FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT - , FRVBF_INSN_CCKLT, FRVBF_INSN_CCKGE, FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI - , FRVBF_INSN_CCKC, FRVBF_INSN_CCKNC, FRVBF_INSN_CCKN, FRVBF_INSN_CCKP - , FRVBF_INSN_CCKV, FRVBF_INSN_CCKNV, FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO - , FRVBF_INSN_CFCKNE, FRVBF_INSN_CFCKEQ, FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE - , FRVBF_INSN_CFCKUL, FRVBF_INSN_CFCKGE, FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE - , FRVBF_INSN_CFCKUG, FRVBF_INSN_CFCKLE, FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE - , FRVBF_INSN_CFCKU, FRVBF_INSN_CFCKO, FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL - , FRVBF_INSN_ICI, FRVBF_INSN_DCI, FRVBF_INSN_ICEI, FRVBF_INSN_DCEI - , FRVBF_INSN_DCF, FRVBF_INSN_DCEF, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB - , FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL - , FRVBF_INSN_ICUL, FRVBF_INSN_DCUL, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR - , FRVBF_INSN_COP1, FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR - , FRVBF_INSN_CLRGA, FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR - , FRVBF_INSN_COMMITGA, FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI - , FRVBF_INSN_FITOD, FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI - , FRVBF_INSN_NFDITOS, FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI - , FRVBF_INSN_NFITOS, FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD - , FRVBF_INSN_FDMOVS, FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD - , FRVBF_INSN_FDNEGS, FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD - , FRVBF_INSN_FDABSS, FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS - , FRVBF_INSN_NFDSQRTS, FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS - , FRVBF_INSN_FADDS, FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS - , FRVBF_INSN_FADDD, FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD - , FRVBF_INSN_CFADDS, FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS - , FRVBF_INSN_NFADDS, FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS - , FRVBF_INSN_FCMPS, FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS - , FRVBF_INSN_FMADDS, FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD - , FRVBF_INSN_FDMADDS, FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS - , FRVBF_INSN_NFMADDS, FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS - , FRVBF_INSN_FDMAS, FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS - , FRVBF_INSN_CFMAS, FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD - , FRVBF_INSN_NFMAS, FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS - , FRVBF_INSN_FDMULS, FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS - , FRVBF_INSN_NFDMULCS, FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS - , FRVBF_INSN_NFDDIVS, FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS - , FRVBF_INSN_MHSETHIS, FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH - , FRVBF_INSN_MHDSETH, FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR - , FRVBF_INSN_CMAND, FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT - , FRVBF_INSN_CMNOT, FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT - , FRVBF_INSN_MWCUTI, FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS - , FRVBF_INSN_MCUTSSI, FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI - , FRVBF_INSN_MSRLHI, FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI - , FRVBF_INSN_MCPLI, FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU - , FRVBF_INSN_MCMPSH, FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS - , FRVBF_INSN_MADDHUS, FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS - , FRVBF_INSN_CMADDHUS, FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS - , FRVBF_INSN_MQADDHUS, FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS - , FRVBF_INSN_CMQADDHUS, FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS - , FRVBF_INSN_MSUBACCS, FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS - , FRVBF_INSN_MDASACCS, FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS - , FRVBF_INSN_MMULXHU, FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS - , FRVBF_INSN_MQMULHU, FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS - , FRVBF_INSN_CMQMULHU, FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS - , FRVBF_INSN_MMRDHU, FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS - , FRVBF_INSN_MQMACHU, FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS - , FRVBF_INSN_MQXMACXHS, FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU - , FRVBF_INSN_MCPXIS, FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU - , FRVBF_INSN_CMCPXIS, FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU - , FRVBF_INSN_MQCPXIS, FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW - , FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH - , FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH - , FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE - , FRVBF_INSN_MNOP, FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC - , FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1 - , FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP, FRVBF_INSN__MAX + , FRVBF_INSN_NLDQFI, FRVBF_INSN_STB, FRVBF_INSN_STH, FRVBF_INSN_ST + , FRVBF_INSN_STBF, FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC + , FRVBF_INSN_RSTB, FRVBF_INSN_RSTH, FRVBF_INSN_RST, FRVBF_INSN_RSTBF + , FRVBF_INSN_RSTHF, FRVBF_INSN_RSTF, FRVBF_INSN_STD, FRVBF_INSN_STDF + , FRVBF_INSN_STDC, FRVBF_INSN_RSTD, FRVBF_INSN_RSTDF, FRVBF_INSN_STQ + , FRVBF_INSN_STQF, FRVBF_INSN_STQC, FRVBF_INSN_RSTQ, FRVBF_INSN_RSTQF + , FRVBF_INSN_STBU, FRVBF_INSN_STHU, FRVBF_INSN_STU, FRVBF_INSN_STBFU + , FRVBF_INSN_STHFU, FRVBF_INSN_STFU, FRVBF_INSN_STCU, FRVBF_INSN_STDU + , FRVBF_INSN_STDFU, FRVBF_INSN_STDCU, FRVBF_INSN_STQU, FRVBF_INSN_STQFU + , FRVBF_INSN_STQCU, FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB, FRVBF_INSN_CLDSH + , FRVBF_INSN_CLDUH, FRVBF_INSN_CLD, FRVBF_INSN_CLDBF, FRVBF_INSN_CLDHF + , FRVBF_INSN_CLDF, FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF, FRVBF_INSN_CLDQ + , FRVBF_INSN_CLDSBU, FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU, FRVBF_INSN_CLDUHU + , FRVBF_INSN_CLDU, FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU, FRVBF_INSN_CLDFU + , FRVBF_INSN_CLDDU, FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU, FRVBF_INSN_CSTB + , FRVBF_INSN_CSTH, FRVBF_INSN_CST, FRVBF_INSN_CSTBF, FRVBF_INSN_CSTHF + , FRVBF_INSN_CSTF, FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF, FRVBF_INSN_CSTQ + , FRVBF_INSN_CSTBU, FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU, FRVBF_INSN_CSTBFU + , FRVBF_INSN_CSTHFU, FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU, FRVBF_INSN_CSTDFU + , FRVBF_INSN_STBI, FRVBF_INSN_STHI, FRVBF_INSN_STI, FRVBF_INSN_STBFI + , FRVBF_INSN_STHFI, FRVBF_INSN_STFI, FRVBF_INSN_STDI, FRVBF_INSN_STDFI + , FRVBF_INSN_STQI, FRVBF_INSN_STQFI, FRVBF_INSN_SWAP, FRVBF_INSN_SWAPI + , FRVBF_INSN_CSWAP, FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG, FRVBF_INSN_MOVGFD + , FRVBF_INSN_MOVFGD, FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ, FRVBF_INSN_CMOVGF + , FRVBF_INSN_CMOVFG, FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD, FRVBF_INSN_MOVGS + , FRVBF_INSN_MOVSG, FRVBF_INSN_BRA, FRVBF_INSN_BNO, FRVBF_INSN_BEQ + , FRVBF_INSN_BNE, FRVBF_INSN_BLE, FRVBF_INSN_BGT, FRVBF_INSN_BLT + , FRVBF_INSN_BGE, FRVBF_INSN_BLS, FRVBF_INSN_BHI, FRVBF_INSN_BC + , FRVBF_INSN_BNC, FRVBF_INSN_BN, FRVBF_INSN_BP, FRVBF_INSN_BV + , FRVBF_INSN_BNV, FRVBF_INSN_FBRA, FRVBF_INSN_FBNO, FRVBF_INSN_FBNE + , FRVBF_INSN_FBEQ, FRVBF_INSN_FBLG, FRVBF_INSN_FBUE, FRVBF_INSN_FBUL + , FRVBF_INSN_FBGE, FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE, FRVBF_INSN_FBUG + , FRVBF_INSN_FBLE, FRVBF_INSN_FBGT, FRVBF_INSN_FBULE, FRVBF_INSN_FBU + , FRVBF_INSN_FBO, FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR, FRVBF_INSN_BNOLR + , FRVBF_INSN_BEQLR, FRVBF_INSN_BNELR, FRVBF_INSN_BLELR, FRVBF_INSN_BGTLR + , FRVBF_INSN_BLTLR, FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR, FRVBF_INSN_BHILR + , FRVBF_INSN_BCLR, FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR, FRVBF_INSN_BPLR + , FRVBF_INSN_BVLR, FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR, FRVBF_INSN_FBNOLR + , FRVBF_INSN_FBEQLR, FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR, FRVBF_INSN_FBUELR + , FRVBF_INSN_FBULLR, FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR, FRVBF_INSN_FBUGELR + , FRVBF_INSN_FBUGLR, FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR, FRVBF_INSN_FBULELR + , FRVBF_INSN_FBULR, FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR, FRVBF_INSN_BCNOLR + , FRVBF_INSN_BCEQLR, FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR, FRVBF_INSN_BCGTLR + , FRVBF_INSN_BCLTLR, FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR, FRVBF_INSN_BCHILR + , FRVBF_INSN_BCCLR, FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR, FRVBF_INSN_BCPLR + , FRVBF_INSN_BCVLR, FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR, FRVBF_INSN_FCBNOLR + , FRVBF_INSN_FCBEQLR, FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR, FRVBF_INSN_FCBUELR + , FRVBF_INSN_FCBULLR, FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR, FRVBF_INSN_FCBUGELR + , FRVBF_INSN_FCBUGLR, FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR, FRVBF_INSN_FCBULELR + , FRVBF_INSN_FCBULR, FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL, FRVBF_INSN_CALLL + , FRVBF_INSN_JMPIL, FRVBF_INSN_CALLIL, FRVBF_INSN_CALL, FRVBF_INSN_RETT + , FRVBF_INSN_REI, FRVBF_INSN_TRA, FRVBF_INSN_TNO, FRVBF_INSN_TEQ + , FRVBF_INSN_TNE, FRVBF_INSN_TLE, FRVBF_INSN_TGT, FRVBF_INSN_TLT + , FRVBF_INSN_TGE, FRVBF_INSN_TLS, FRVBF_INSN_THI, FRVBF_INSN_TC + , FRVBF_INSN_TNC, FRVBF_INSN_TN, FRVBF_INSN_TP, FRVBF_INSN_TV + , FRVBF_INSN_TNV, FRVBF_INSN_FTRA, FRVBF_INSN_FTNO, FRVBF_INSN_FTNE + , FRVBF_INSN_FTEQ, FRVBF_INSN_FTLG, FRVBF_INSN_FTUE, FRVBF_INSN_FTUL + , FRVBF_INSN_FTGE, FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE, FRVBF_INSN_FTUG + , FRVBF_INSN_FTLE, FRVBF_INSN_FTGT, FRVBF_INSN_FTULE, FRVBF_INSN_FTU + , FRVBF_INSN_FTO, FRVBF_INSN_TIRA, FRVBF_INSN_TINO, FRVBF_INSN_TIEQ + , FRVBF_INSN_TINE, FRVBF_INSN_TILE, FRVBF_INSN_TIGT, FRVBF_INSN_TILT + , FRVBF_INSN_TIGE, FRVBF_INSN_TILS, FRVBF_INSN_TIHI, FRVBF_INSN_TIC + , FRVBF_INSN_TINC, FRVBF_INSN_TIN, FRVBF_INSN_TIP, FRVBF_INSN_TIV + , FRVBF_INSN_TINV, FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO, FRVBF_INSN_FTINE + , FRVBF_INSN_FTIEQ, FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE, FRVBF_INSN_FTIUL + , FRVBF_INSN_FTIGE, FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE, FRVBF_INSN_FTIUG + , FRVBF_INSN_FTILE, FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE, FRVBF_INSN_FTIU + , FRVBF_INSN_FTIO, FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP, FRVBF_INSN_ANDCR + , FRVBF_INSN_ORCR, FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR, FRVBF_INSN_NORCR + , FRVBF_INSN_ANDNCR, FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR, FRVBF_INSN_NORNCR + , FRVBF_INSN_NOTCR, FRVBF_INSN_CKRA, FRVBF_INSN_CKNO, FRVBF_INSN_CKEQ + , FRVBF_INSN_CKNE, FRVBF_INSN_CKLE, FRVBF_INSN_CKGT, FRVBF_INSN_CKLT + , FRVBF_INSN_CKGE, FRVBF_INSN_CKLS, FRVBF_INSN_CKHI, FRVBF_INSN_CKC + , FRVBF_INSN_CKNC, FRVBF_INSN_CKN, FRVBF_INSN_CKP, FRVBF_INSN_CKV + , FRVBF_INSN_CKNV, FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO, FRVBF_INSN_FCKNE + , FRVBF_INSN_FCKEQ, FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE, FRVBF_INSN_FCKUL + , FRVBF_INSN_FCKGE, FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE, FRVBF_INSN_FCKUG + , FRVBF_INSN_FCKLE, FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE, FRVBF_INSN_FCKU + , FRVBF_INSN_FCKO, FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO, FRVBF_INSN_CCKEQ + , FRVBF_INSN_CCKNE, FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT, FRVBF_INSN_CCKLT + , FRVBF_INSN_CCKGE, FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI, FRVBF_INSN_CCKC + , FRVBF_INSN_CCKNC, FRVBF_INSN_CCKN, FRVBF_INSN_CCKP, FRVBF_INSN_CCKV + , FRVBF_INSN_CCKNV, FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO, FRVBF_INSN_CFCKNE + , FRVBF_INSN_CFCKEQ, FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE, FRVBF_INSN_CFCKUL + , FRVBF_INSN_CFCKGE, FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE, FRVBF_INSN_CFCKUG + , FRVBF_INSN_CFCKLE, FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE, FRVBF_INSN_CFCKU + , FRVBF_INSN_CFCKO, FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL, FRVBF_INSN_ICI + , FRVBF_INSN_DCI, FRVBF_INSN_ICEI, FRVBF_INSN_DCEI, FRVBF_INSN_DCF + , FRVBF_INSN_DCEF, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB, FRVBF_INSN_ITLBI + , FRVBF_INSN_DTLBI, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL, FRVBF_INSN_ICUL + , FRVBF_INSN_DCUL, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR, FRVBF_INSN_COP1 + , FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA + , FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA + , FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD + , FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS + , FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS + , FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS + , FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS + , FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS + , FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS + , FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS + , FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD + , FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS + , FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS + , FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS + , FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS + , FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS + , FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS + , FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS + , FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS + , FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS + , FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS + , FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS + , FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS + , FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS + , FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH + , FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND + , FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT + , FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI + , FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI + , FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI + , FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI + , FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH + , FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS + , FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS + , FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS + , FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS + , FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS + , FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS + , FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU + , FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU + , FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU + , FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU + , FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU + , FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS + , FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS + , FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS + , FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS + , FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD + , FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH + , FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB + , FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP + , FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG + , FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2 + , FRVBF_INSN_FNOP, FRVBF_INSN__MAX } FRVBF_INSN_TYPE; /* Enum declaration for semantic formats in cpu family frvbf. */ @@ -241,61 +241,62 @@ typedef enum frvbf_sfmt_type { , FRVBF_SFMT_NLDQU, FRVBF_SFMT_LDQFU, FRVBF_SFMT_LDQCU, FRVBF_SFMT_NLDQFU , FRVBF_SFMT_LDSBI, FRVBF_SFMT_LDBFI, FRVBF_SFMT_NLDSBI, FRVBF_SFMT_NLDBFI , FRVBF_SFMT_LDDI, FRVBF_SFMT_LDDFI, FRVBF_SFMT_NLDDI, FRVBF_SFMT_NLDDFI - , FRVBF_SFMT_LDQI, FRVBF_SFMT_LDQFI, FRVBF_SFMT_NLDQI, FRVBF_SFMT_NLDQFI - , FRVBF_SFMT_STB, FRVBF_SFMT_STBF, FRVBF_SFMT_STC, FRVBF_SFMT_RSTB - , FRVBF_SFMT_RSTBF, FRVBF_SFMT_STD, FRVBF_SFMT_STDF, FRVBF_SFMT_STDC - , FRVBF_SFMT_RSTD, FRVBF_SFMT_RSTDF, FRVBF_SFMT_STBU, FRVBF_SFMT_STBFU - , FRVBF_SFMT_STCU, FRVBF_SFMT_STDU, FRVBF_SFMT_STDFU, FRVBF_SFMT_STDCU - , FRVBF_SFMT_STQU, FRVBF_SFMT_CLDSB, FRVBF_SFMT_CLDBF, FRVBF_SFMT_CLDD - , FRVBF_SFMT_CLDDF, FRVBF_SFMT_CLDQ, FRVBF_SFMT_CLDSBU, FRVBF_SFMT_CLDBFU - , FRVBF_SFMT_CLDDU, FRVBF_SFMT_CLDDFU, FRVBF_SFMT_CLDQU, FRVBF_SFMT_CSTB - , FRVBF_SFMT_CSTBF, FRVBF_SFMT_CSTD, FRVBF_SFMT_CSTDF, FRVBF_SFMT_CSTBU - , FRVBF_SFMT_CSTBFU, FRVBF_SFMT_CSTDU, FRVBF_SFMT_CSTDFU, FRVBF_SFMT_STBI - , FRVBF_SFMT_STBFI, FRVBF_SFMT_STDI, FRVBF_SFMT_STDFI, FRVBF_SFMT_SWAP - , FRVBF_SFMT_SWAPI, FRVBF_SFMT_CSWAP, FRVBF_SFMT_MOVGF, FRVBF_SFMT_MOVFG - , FRVBF_SFMT_MOVGFD, FRVBF_SFMT_MOVFGD, FRVBF_SFMT_MOVGFQ, FRVBF_SFMT_MOVFGQ - , FRVBF_SFMT_CMOVGF, FRVBF_SFMT_CMOVFG, FRVBF_SFMT_CMOVGFD, FRVBF_SFMT_CMOVFGD - , FRVBF_SFMT_MOVGS, FRVBF_SFMT_MOVSG, FRVBF_SFMT_BRA, FRVBF_SFMT_BNO - , FRVBF_SFMT_BEQ, FRVBF_SFMT_FBNE, FRVBF_SFMT_BCTRLR, FRVBF_SFMT_BRALR - , FRVBF_SFMT_BNOLR, FRVBF_SFMT_BEQLR, FRVBF_SFMT_FBEQLR, FRVBF_SFMT_BCRALR - , FRVBF_SFMT_BCNOLR, FRVBF_SFMT_BCEQLR, FRVBF_SFMT_FCBEQLR, FRVBF_SFMT_JMPL - , FRVBF_SFMT_JMPIL, FRVBF_SFMT_CALL, FRVBF_SFMT_RETT, FRVBF_SFMT_REI - , FRVBF_SFMT_TRA, FRVBF_SFMT_TEQ, FRVBF_SFMT_FTNE, FRVBF_SFMT_TIRA - , FRVBF_SFMT_TIEQ, FRVBF_SFMT_FTINE, FRVBF_SFMT_BREAK, FRVBF_SFMT_ANDCR - , FRVBF_SFMT_NOTCR, FRVBF_SFMT_CKRA, FRVBF_SFMT_CKEQ, FRVBF_SFMT_FCKRA - , FRVBF_SFMT_FCKNE, FRVBF_SFMT_CCKRA, FRVBF_SFMT_CCKEQ, FRVBF_SFMT_CFCKRA - , FRVBF_SFMT_CFCKNE, FRVBF_SFMT_CJMPL, FRVBF_SFMT_ICI, FRVBF_SFMT_ICEI - , FRVBF_SFMT_ICPL, FRVBF_SFMT_ICUL, FRVBF_SFMT_CLRGR, FRVBF_SFMT_CLRFR - , FRVBF_SFMT_COMMITGR, FRVBF_SFMT_COMMITFR, FRVBF_SFMT_FITOS, FRVBF_SFMT_FSTOI - , FRVBF_SFMT_FITOD, FRVBF_SFMT_FDTOI, FRVBF_SFMT_FDITOS, FRVBF_SFMT_FDSTOI - , FRVBF_SFMT_CFITOS, FRVBF_SFMT_CFSTOI, FRVBF_SFMT_NFITOS, FRVBF_SFMT_NFSTOI - , FRVBF_SFMT_FMOVS, FRVBF_SFMT_FMOVD, FRVBF_SFMT_FDMOVS, FRVBF_SFMT_CFMOVS - , FRVBF_SFMT_NFSQRTS, FRVBF_SFMT_FADDS, FRVBF_SFMT_FADDD, FRVBF_SFMT_CFADDS - , FRVBF_SFMT_NFADDS, FRVBF_SFMT_FCMPS, FRVBF_SFMT_FCMPD, FRVBF_SFMT_CFCMPS - , FRVBF_SFMT_FDCMPS, FRVBF_SFMT_FMADDS, FRVBF_SFMT_FMADDD, FRVBF_SFMT_FDMADDS - , FRVBF_SFMT_CFMADDS, FRVBF_SFMT_NFMADDS, FRVBF_SFMT_FMAS, FRVBF_SFMT_FDMAS - , FRVBF_SFMT_CFMAS, FRVBF_SFMT_NFDCMPS, FRVBF_SFMT_MHSETLOS, FRVBF_SFMT_MHSETHIS - , FRVBF_SFMT_MHDSETS, FRVBF_SFMT_MHSETLOH, FRVBF_SFMT_MHSETHIH, FRVBF_SFMT_MHDSETH - , FRVBF_SFMT_MAND, FRVBF_SFMT_CMAND, FRVBF_SFMT_MNOT, FRVBF_SFMT_CMNOT - , FRVBF_SFMT_MROTLI, FRVBF_SFMT_MWCUT, FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT - , FRVBF_SFMT_MCUTI, FRVBF_SFMT_MDCUTSSI, FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI - , FRVBF_SFMT_MCPLHI, FRVBF_SFMT_MCPLI, FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS - , FRVBF_SFMT_MCMPSH, FRVBF_SFMT_MABSHS, FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS - , FRVBF_SFMT_MADDACCS, FRVBF_SFMT_MDADDACCS, FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS - , FRVBF_SFMT_MMULHS, FRVBF_SFMT_CMMULHS, FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS - , FRVBF_SFMT_MMACHS, FRVBF_SFMT_MMACHU, FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU - , FRVBF_SFMT_MQMACHS, FRVBF_SFMT_MQMACHU, FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU - , FRVBF_SFMT_MCPXRS, FRVBF_SFMT_CMCPXRS, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW - , FRVBF_SFMT_CMEXPDHW, FRVBF_SFMT_MEXPDHD, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH - , FRVBF_SFMT_MDPACKH, FRVBF_SFMT_MUNPACKH, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH - , FRVBF_SFMT_CMBTOH, FRVBF_SFMT_MHTOB, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE - , FRVBF_SFMT_CMBTOHE, FRVBF_SFMT_MCLRACC_0, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG - , FRVBF_SFMT_MWTACC, FRVBF_SFMT_MWTACCG + , FRVBF_SFMT_LDQI, FRVBF_SFMT_LDQFI, FRVBF_SFMT_NLDQFI, FRVBF_SFMT_STB + , FRVBF_SFMT_STBF, FRVBF_SFMT_STC, FRVBF_SFMT_RSTB, FRVBF_SFMT_RSTBF + , FRVBF_SFMT_STD, FRVBF_SFMT_STDF, FRVBF_SFMT_STDC, FRVBF_SFMT_RSTD + , FRVBF_SFMT_RSTDF, FRVBF_SFMT_STBU, FRVBF_SFMT_STBFU, FRVBF_SFMT_STCU + , FRVBF_SFMT_STDU, FRVBF_SFMT_STDFU, FRVBF_SFMT_STDCU, FRVBF_SFMT_STQU + , FRVBF_SFMT_CLDSB, FRVBF_SFMT_CLDBF, FRVBF_SFMT_CLDD, FRVBF_SFMT_CLDDF + , FRVBF_SFMT_CLDQ, FRVBF_SFMT_CLDSBU, FRVBF_SFMT_CLDBFU, FRVBF_SFMT_CLDDU + , FRVBF_SFMT_CLDDFU, FRVBF_SFMT_CLDQU, FRVBF_SFMT_CSTB, FRVBF_SFMT_CSTBF + , FRVBF_SFMT_CSTD, FRVBF_SFMT_CSTDF, FRVBF_SFMT_CSTBU, FRVBF_SFMT_CSTBFU + , FRVBF_SFMT_CSTDU, FRVBF_SFMT_CSTDFU, FRVBF_SFMT_STBI, FRVBF_SFMT_STBFI + , FRVBF_SFMT_STDI, FRVBF_SFMT_STDFI, FRVBF_SFMT_SWAP, FRVBF_SFMT_SWAPI + , FRVBF_SFMT_CSWAP, FRVBF_SFMT_MOVGF, FRVBF_SFMT_MOVFG, FRVBF_SFMT_MOVGFD + , FRVBF_SFMT_MOVFGD, FRVBF_SFMT_MOVGFQ, FRVBF_SFMT_MOVFGQ, FRVBF_SFMT_CMOVGF + , FRVBF_SFMT_CMOVFG, FRVBF_SFMT_CMOVGFD, FRVBF_SFMT_CMOVFGD, FRVBF_SFMT_MOVGS + , FRVBF_SFMT_MOVSG, FRVBF_SFMT_BRA, FRVBF_SFMT_BNO, FRVBF_SFMT_BEQ + , FRVBF_SFMT_FBNE, FRVBF_SFMT_BCTRLR, FRVBF_SFMT_BRALR, FRVBF_SFMT_BNOLR + , FRVBF_SFMT_BEQLR, FRVBF_SFMT_FBEQLR, FRVBF_SFMT_BCRALR, FRVBF_SFMT_BCNOLR + , FRVBF_SFMT_BCEQLR, FRVBF_SFMT_FCBEQLR, FRVBF_SFMT_JMPL, FRVBF_SFMT_JMPIL + , FRVBF_SFMT_CALL, FRVBF_SFMT_RETT, FRVBF_SFMT_REI, FRVBF_SFMT_TRA + , FRVBF_SFMT_TEQ, FRVBF_SFMT_FTNE, FRVBF_SFMT_TIRA, FRVBF_SFMT_TIEQ + , FRVBF_SFMT_FTINE, FRVBF_SFMT_BREAK, FRVBF_SFMT_ANDCR, FRVBF_SFMT_NOTCR + , FRVBF_SFMT_CKRA, FRVBF_SFMT_CKEQ, FRVBF_SFMT_FCKRA, FRVBF_SFMT_FCKNE + , FRVBF_SFMT_CCKRA, FRVBF_SFMT_CCKEQ, FRVBF_SFMT_CFCKRA, FRVBF_SFMT_CFCKNE + , FRVBF_SFMT_CJMPL, FRVBF_SFMT_ICI, FRVBF_SFMT_ICEI, FRVBF_SFMT_ICPL + , FRVBF_SFMT_ICUL, FRVBF_SFMT_CLRGR, FRVBF_SFMT_CLRFR, FRVBF_SFMT_COMMITGR + , FRVBF_SFMT_COMMITFR, FRVBF_SFMT_FITOS, FRVBF_SFMT_FSTOI, FRVBF_SFMT_FITOD + , FRVBF_SFMT_FDTOI, FRVBF_SFMT_FDITOS, FRVBF_SFMT_FDSTOI, FRVBF_SFMT_CFITOS + , FRVBF_SFMT_CFSTOI, FRVBF_SFMT_NFITOS, FRVBF_SFMT_NFSTOI, FRVBF_SFMT_FMOVS + , FRVBF_SFMT_FMOVD, FRVBF_SFMT_FDMOVS, FRVBF_SFMT_CFMOVS, FRVBF_SFMT_NFSQRTS + , FRVBF_SFMT_FADDS, FRVBF_SFMT_FADDD, FRVBF_SFMT_CFADDS, FRVBF_SFMT_NFADDS + , FRVBF_SFMT_FCMPS, FRVBF_SFMT_FCMPD, FRVBF_SFMT_CFCMPS, FRVBF_SFMT_FDCMPS + , FRVBF_SFMT_FMADDS, FRVBF_SFMT_FMADDD, FRVBF_SFMT_FDMADDS, FRVBF_SFMT_CFMADDS + , FRVBF_SFMT_NFMADDS, FRVBF_SFMT_FMAS, FRVBF_SFMT_FDMAS, FRVBF_SFMT_CFMAS + , FRVBF_SFMT_NFDCMPS, FRVBF_SFMT_MHSETLOS, FRVBF_SFMT_MHSETHIS, FRVBF_SFMT_MHDSETS + , FRVBF_SFMT_MHSETLOH, FRVBF_SFMT_MHSETHIH, FRVBF_SFMT_MHDSETH, FRVBF_SFMT_MAND + , FRVBF_SFMT_CMAND, FRVBF_SFMT_MNOT, FRVBF_SFMT_CMNOT, FRVBF_SFMT_MROTLI + , FRVBF_SFMT_MWCUT, FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT, FRVBF_SFMT_MCUTI + , FRVBF_SFMT_MDCUTSSI, FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI, FRVBF_SFMT_MCPLHI + , FRVBF_SFMT_MCPLI, FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS, FRVBF_SFMT_MCMPSH + , FRVBF_SFMT_MABSHS, FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MADDACCS + , FRVBF_SFMT_MDADDACCS, FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS + , FRVBF_SFMT_CMMULHS, FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS + , FRVBF_SFMT_MMACHU, FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS + , FRVBF_SFMT_MQMACHU, FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS + , FRVBF_SFMT_CMCPXRS, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW + , FRVBF_SFMT_MEXPDHD, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH + , FRVBF_SFMT_MUNPACKH, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH + , FRVBF_SFMT_MHTOB, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE + , FRVBF_SFMT_MCLRACC_0, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC + , FRVBF_SFMT_MWTACCG } FRVBF_SFMT_TYPE; /* Function unit handlers (user written). */ extern int frvbf_model_frv_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr500_u_commit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRk*/, INT /*FRk*/); extern int frvbf_model_fr500_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); extern int frvbf_model_fr500_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); extern int frvbf_model_fr500_u_dcpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); diff --git a/sim/frv/model.c b/sim/frv/model.c index b5cde2f..cca2f22 100644 --- a/sim/frv/model.c +++ b/sim/frv/model.c @@ -2627,22 +2627,6 @@ model_frv_ldqfi (SIM_CPU *current_cpu, void *sem_arg) } static int -model_frv_nldqi (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_stdi.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_frv_nldqfi (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_stdfi.f @@ -15913,28 +15897,6 @@ model_fr500_ldqfi (SIM_CPU *current_cpu, void *sem_arg) } static int -model_fr500_nldqi (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_stdi.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT out_GRk = -1; - INT out_GRdoublek = -1; - in_GRi = FLD (in_GRi); - if (insn_referenced & (1 << 0)) referenced |= 1 << 0; - cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); - } - return cycles; -#undef FLD -} - -static int model_fr500_nldqfi (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_stdfi.f @@ -24215,7 +24177,9 @@ model_fr500_commitgr (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + INT in_GRk = -1; + INT in_FRk = -1; + cycles += frvbf_model_fr500_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk); } return cycles; #undef FLD @@ -24231,7 +24195,9 @@ model_fr500_commitfr (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + INT in_GRk = -1; + INT in_FRk = -1; + cycles += frvbf_model_fr500_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk); } return cycles; #undef FLD @@ -24247,7 +24213,9 @@ model_fr500_commitga (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + INT in_GRk = -1; + INT in_FRk = -1; + cycles += frvbf_model_fr500_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk); } return cycles; #undef FLD @@ -24263,7 +24231,9 @@ model_fr500_commitfa (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + INT in_GRk = -1; + INT in_FRk = -1; + cycles += frvbf_model_fr500_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk); } return cycles; #undef FLD @@ -25316,17 +25286,14 @@ model_fr500_cfdivs (SIM_CPU *current_cpu, void *sem_arg) int UNUSED insn_referenced = abuf->written; INT in_FRi = -1; INT in_FRj = -1; - INT in_FRdoublei = -1; - INT in_FRdoublej = -1; INT out_FRk = -1; - INT out_FRdoublek = -1; in_FRi = FLD (in_FRi); in_FRj = FLD (in_FRj); out_FRk = FLD (out_FRk); if (insn_referenced & (1 << 1)) referenced |= 1 << 0; if (insn_referenced & (1 << 2)) referenced |= 1 << 1; - if (insn_referenced & (1 << 4)) referenced |= 1 << 4; - cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_float_div (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FRk); } return cycles; #undef FLD @@ -25428,17 +25395,14 @@ model_fr500_nfdivs (SIM_CPU *current_cpu, void *sem_arg) int UNUSED insn_referenced = abuf->written; INT in_FRi = -1; INT in_FRj = -1; - INT in_FRdoublei = -1; - INT in_FRdoublej = -1; INT out_FRk = -1; - INT out_FRdoublek = -1; in_FRi = FLD (in_FRi); in_FRj = FLD (in_FRj); out_FRk = FLD (out_FRk); referenced |= 1 << 0; referenced |= 1 << 1; - referenced |= 1 << 4; - cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek); + referenced |= 1 << 2; + cycles += frvbf_model_fr500_u_float_div (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FRk); } return cycles; #undef FLD @@ -31870,22 +31834,6 @@ model_tomcat_ldqfi (SIM_CPU *current_cpu, void *sem_arg) } static int -model_tomcat_nldqi (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_stdi.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_tomcat_nldqfi (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_stdfi.f @@ -44820,22 +44768,6 @@ model_fr400_ldqfi (SIM_CPU *current_cpu, void *sem_arg) } static int -model_fr400_nldqi (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_stdi.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_fr400_nldqfi (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_stdfi.f @@ -59685,22 +59617,6 @@ model_simple_ldqfi (SIM_CPU *current_cpu, void *sem_arg) } static int -model_simple_nldqi (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_stdi.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int model_simple_nldqfi (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_stdfi.f @@ -69106,7 +69022,6 @@ static const INSN_TIMING frv_timing[] = { { FRVBF_INSN_NLDDFI, model_frv_nlddfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_LDQI, model_frv_ldqi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_LDQFI, model_frv_ldqfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_NLDQI, model_frv_nldqi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_NLDQFI, model_frv_nldqfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STB, model_frv_stb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STH, model_frv_sth, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, @@ -69857,7 +69772,6 @@ static const INSN_TIMING fr500_timing[] = { { FRVBF_INSN_NLDDFI, model_fr500_nlddfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, { FRVBF_INSN_LDQI, model_fr500_ldqi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, { FRVBF_INSN_LDQFI, model_fr500_ldqfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, - { FRVBF_INSN_NLDQI, model_fr500_nldqi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } }, { FRVBF_INSN_NLDQFI, model_fr500_nldqfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } }, { FRVBF_INSN_STB, model_fr500_stb, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STH, model_fr500_sth, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, @@ -70227,10 +70141,10 @@ static const INSN_TIMING fr500_timing[] = { { FRVBF_INSN_CLRFR, model_fr500_clrfr, { { (int) UNIT_FR500_U_CLRFR, 1, 1 } } }, { FRVBF_INSN_CLRGA, model_fr500_clrga, { { (int) UNIT_FR500_U_CLRGR, 1, 1 } } }, { FRVBF_INSN_CLRFA, model_fr500_clrfa, { { (int) UNIT_FR500_U_CLRFR, 1, 1 } } }, - { FRVBF_INSN_COMMITGR, model_fr500_commitgr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_COMMITFR, model_fr500_commitfr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_COMMITGA, model_fr500_commitga, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_COMMITFA, model_fr500_commitfa, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITGR, model_fr500_commitgr, { { (int) UNIT_FR500_U_COMMIT, 1, 1 } } }, + { FRVBF_INSN_COMMITFR, model_fr500_commitfr, { { (int) UNIT_FR500_U_COMMIT, 1, 1 } } }, + { FRVBF_INSN_COMMITGA, model_fr500_commitga, { { (int) UNIT_FR500_U_COMMIT, 1, 1 } } }, + { FRVBF_INSN_COMMITFA, model_fr500_commitfa, { { (int) UNIT_FR500_U_COMMIT, 1, 1 } } }, { FRVBF_INSN_FITOS, model_fr500_fitos, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } }, { FRVBF_INSN_FSTOI, model_fr500_fstoi, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } }, { FRVBF_INSN_FITOD, model_fr500_fitod, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } }, @@ -70272,11 +70186,11 @@ static const INSN_TIMING fr500_timing[] = { { FRVBF_INSN_CFADDS, model_fr500_cfadds, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, { FRVBF_INSN_CFSUBS, model_fr500_cfsubs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, { FRVBF_INSN_CFMULS, model_fr500_cfmuls, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, - { FRVBF_INSN_CFDIVS, model_fr500_cfdivs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_CFDIVS, model_fr500_cfdivs, { { (int) UNIT_FR500_U_FLOAT_DIV, 1, 1 } } }, { FRVBF_INSN_NFADDS, model_fr500_nfadds, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, { FRVBF_INSN_NFSUBS, model_fr500_nfsubs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, { FRVBF_INSN_NFMULS, model_fr500_nfmuls, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, - { FRVBF_INSN_NFDIVS, model_fr500_nfdivs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } }, + { FRVBF_INSN_NFDIVS, model_fr500_nfdivs, { { (int) UNIT_FR500_U_FLOAT_DIV, 1, 1 } } }, { FRVBF_INSN_FCMPS, model_fr500_fcmps, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } }, { FRVBF_INSN_FCMPD, model_fr500_fcmpd, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } }, { FRVBF_INSN_CFCMPS, model_fr500_cfcmps, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } }, @@ -70608,7 +70522,6 @@ static const INSN_TIMING tomcat_timing[] = { { FRVBF_INSN_NLDDFI, model_tomcat_nlddfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_LDQI, model_tomcat_ldqi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_LDQFI, model_tomcat_ldqfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_NLDQI, model_tomcat_nldqi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_NLDQFI, model_tomcat_nldqfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STB, model_tomcat_stb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STH, model_tomcat_sth, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, @@ -71359,7 +71272,6 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_NLDDFI, model_fr400_nlddfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_LDQI, model_fr400_ldqi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_LDQFI, model_fr400_ldqfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_NLDQI, model_fr400_nldqi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_NLDQFI, model_fr400_nldqfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STB, model_fr400_stb, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STH, model_fr400_sth, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, @@ -72110,7 +72022,6 @@ static const INSN_TIMING simple_timing[] = { { FRVBF_INSN_NLDDFI, model_simple_nlddfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_LDQI, model_simple_ldqi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_LDQFI, model_simple_ldqfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_NLDQI, model_simple_nldqi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_NLDQFI, model_simple_nldqfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STB, model_simple_stb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STH, model_simple_sth, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, diff --git a/sim/frv/profile-fr400.c b/sim/frv/profile-fr400.c index 9baddd1..698e06e 100644 --- a/sim/frv/profile-fr400.c +++ b/sim/frv/profile-fr400.c @@ -621,55 +621,6 @@ frvbf_model_fr400_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc, in_GRj, out_spr); } -/* Top up the post-processing time of the given FR by the given number of - cycles. */ -static void -update_FR_ptime (SIM_CPU *cpu, INT out_FR, int cycles) -{ - if (out_FR >= 0) - { - FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); - /* If a load is pending on this register, then add the cycles to - the post processing time for this register. Otherwise apply it - directly to the latency of the register. */ - if (! load_pending_for_register (cpu, out_FR, 1, REGTYPE_FR)) - { - int *fr = ps->fr_latency; - fr[out_FR] += cycles; - } - else - ps->fr_ptime[out_FR] += cycles; - } -} - -static void -update_FRdouble_ptime (SIM_CPU *cpu, INT out_FR, int cycles) -{ - if (out_FR >= 0) - { - FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); - /* If a load is pending on this register, then add the cycles to - the post processing time for this register. Otherwise apply it - directly to the latency of the register. */ - if (! load_pending_for_register (cpu, out_FR, 2, REGTYPE_FR)) - { - int *fr = ps->fr_latency; - fr[out_FR] += cycles; - if (out_FR < 63) - fr[out_FR + 1] += cycles; - } - else - { - /* On the fr400, loads are available to media insns one cycle early, - so knock one cycle off the post processing time to account for - this. */ - ps->fr_ptime[out_FR] += cycles - 1; - if (out_FR < 63) - ps->fr_ptime[out_FR + 1] += cycles - 1; - } - } -} - int frvbf_model_fr400_u_media_1 (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, diff --git a/sim/frv/profile-fr500.c b/sim/frv/profile-fr500.c index 7591d1f..610927c 100644 --- a/sim/frv/profile-fr500.c +++ b/sim/frv/profile-fr500.c @@ -580,6 +580,41 @@ frvbf_model_fr500_u_clrfr (SIM_CPU *cpu, const IDESC *idesc, } int +frvbf_model_fr500_u_commit (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRk, INT in_FRk) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* If GR is specified, then FR is not and vice-versa. If neither is + then it's a commitga or commitfa. Check the insn attribute to + figure out which. */ + if (in_GRk != -1) + vliw_wait_for_SPR (cpu, GNER_FOR_GR (in_GRk)); + else if (in_FRk != -1) + vliw_wait_for_SPR (cpu, FNER_FOR_FR (in_FRk)); + else if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_FR_ACCESS)) + { + vliw_wait_for_SPR (cpu, H_SPR_FNER0); + vliw_wait_for_SPR (cpu, H_SPR_FNER1); + } + else + { + vliw_wait_for_SPR (cpu, H_SPR_GNER0); + vliw_wait_for_SPR (cpu, H_SPR_GNER1); + } + handle_resource_wait (cpu); + trace_vliw_wait_cycles (cpu); + return 0; + } + + cycles = idesc->timing->units[unit_num].done; + return cycles; +} + +int frvbf_model_fr500_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, INT out_GRkhi, INT out_GRklo) @@ -656,9 +691,20 @@ frvbf_model_fr500_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, update_GR_latency_for_load (cpu, out_GRk, cycles); update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles); - set_use_is_gr_complex (cpu, out_GRk); - set_use_is_gr_complex (cpu, out_GRdoublek); - set_use_is_gr_complex (cpu, out_GRdoublek + 1); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* GNER has a latency of 2 cycles. */ + update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2); + update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2); + } + + if (out_GRk >= 0) + set_use_is_gr_complex (cpu, out_GRk); + if (out_GRdoublek != -1) + { + set_use_is_gr_complex (cpu, out_GRdoublek); + set_use_is_gr_complex (cpu, out_GRdoublek + 1); + } return cycles; } @@ -786,6 +832,11 @@ frvbf_model_fr500_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, vliw_wait_for_GR (cpu, in_GRj); vliw_wait_for_FR (cpu, out_FRk); vliw_wait_for_FRdouble (cpu, out_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); + } handle_resource_wait (cpu); load_wait_for_GR (cpu, in_GRi); load_wait_for_GR (cpu, in_GRj); @@ -802,6 +853,13 @@ frvbf_model_fr500_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, update_FR_latency_for_load (cpu, out_FRk, cycles); update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* FNER has a latency of 3 cycles. */ + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), cycles + 3); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), cycles + 3); + } + fr500_reset_fr_flags (cpu, out_FRk); return cycles; @@ -1061,7 +1119,7 @@ frvbf_model_fr500_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc, if (use_is_media (cpu, out_FRk)) decrease_FR_busy (cpu, out_FRk, 1); else - adjust_float_register_busy (cpu, -1, out_FRk, -1, 1); + adjust_float_register_busy (cpu, -1, -1, out_FRk, 1); } vliw_wait_for_GR (cpu, in_GRj); vliw_wait_for_FR (cpu, out_FRk); @@ -1385,52 +1443,6 @@ frvbf_model_fr500_u_dcul (SIM_CPU *cpu, const IDESC *idesc, return cycles; } -/* Top up the post-processing time of the given FR by the given number of - cycles. */ -static void -update_FR_ptime (SIM_CPU *cpu, INT out_FR, int cycles) -{ - if (out_FR >= 0) - { - FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); - /* If a load is pending on this register, then add the cycles to - the post processing time for this register. Otherwise apply it - directly to the latency of the register. */ - if (! load_pending_for_register (cpu, out_FR, 1, REGTYPE_FR)) - { - int *fr = ps->fr_latency; - fr[out_FR] += cycles; - } - else - ps->fr_ptime[out_FR] += cycles; - } -} - -static void -update_FRdouble_ptime (SIM_CPU *cpu, INT out_FR, int cycles) -{ - if (out_FR >= 0) - { - FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); - /* If a load is pending on this register, then add the cycles to - the post processing time for this register. Otherwise apply it - directly to the latency of the register. */ - if (! load_pending_for_register (cpu, out_FR, 2, REGTYPE_FR)) - { - int *fr = ps->fr_latency; - fr[out_FR] += cycles; - if (out_FR < 63) - fr[out_FR + 1] += cycles; - } - else - { - ps->fr_ptime[out_FR] += cycles; - if (out_FR < 63) - ps->fr_ptime[out_FR + 1] += cycles; - } - } -} - int frvbf_model_fr500_u_float_arith (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced, @@ -1460,6 +1472,11 @@ frvbf_model_fr500_u_float_arith (SIM_CPU *cpu, const IDESC *idesc, post_wait_for_FRdouble (cpu, in_FRdoublei); post_wait_for_FRdouble (cpu, in_FRdoublej); post_wait_for_FRdouble (cpu, out_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); + } restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek, 1); @@ -1468,10 +1485,22 @@ frvbf_model_fr500_u_float_arith (SIM_CPU *cpu, const IDESC *idesc, update_FR_latency (cpu, out_FRk, ps->post_wait); update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); + } + /* Once initiated, post-processing will take 3 cycles. */ update_FR_ptime (cpu, out_FRk, 3); update_FRdouble_ptime (cpu, out_FRdoublek, 3); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3); + } + /* Mark this use of the register as a floating point op. */ if (out_FRk >= 0) set_use_is_fpop (cpu, out_FRk); @@ -1536,6 +1565,13 @@ frvbf_model_fr500_u_float_dual_arith (SIM_CPU *cpu, const IDESC *idesc, post_wait_for_FRdouble (cpu, dual_FRdoublei); post_wait_for_FRdouble (cpu, dual_FRdoublej); post_wait_for_FRdouble (cpu, dual_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); + post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRdoublek)); + } restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1); restore_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1); restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek, @@ -1549,12 +1585,28 @@ frvbf_model_fr500_u_float_dual_arith (SIM_CPU *cpu, const IDESC *idesc, update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); update_FRdouble_latency (cpu, dual_FRdoublek, ps->post_wait); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (dual_FRk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (dual_FRdoublek), ps->post_wait); + } + /* Once initiated, post-processing will take 3 cycles. */ update_FR_ptime (cpu, out_FRk, 3); update_FR_ptime (cpu, dual_FRk, 3); update_FRdouble_ptime (cpu, out_FRdoublek, 3); update_FRdouble_ptime (cpu, dual_FRdoublek, 3); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRk), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRdoublek), 3); + } + /* Mark this use of the register as a floating point op. */ if (out_FRk >= 0) set_use_is_fpop (cpu, out_FRk); @@ -1599,6 +1651,8 @@ frvbf_model_fr500_u_float_div (SIM_CPU *cpu, const IDESC *idesc, post_wait_for_FR (cpu, in_FRi); post_wait_for_FR (cpu, in_FRj); post_wait_for_FR (cpu, out_FRk); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); vliw = CPU_VLIW (cpu); slot = vliw->next_slot - 1; slot = (*vliw->current_vliw)[slot] - UNIT_FM0; @@ -1610,6 +1664,13 @@ frvbf_model_fr500_u_float_div (SIM_CPU *cpu, const IDESC *idesc, update_FR_latency (cpu, out_FRk, ps->post_wait); update_FR_ptime (cpu, out_FRk, 10); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* FNER has a latency of 10 cycles. */ + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 10); + } + /* The latency of the fdiv unit will be at least the latency of the other inputs. Once initiated, post-processing will take 9 cycles. */ update_fdiv_resource_latency (cpu, slot, ps->post_wait + 9); @@ -1646,6 +1707,8 @@ frvbf_model_fr500_u_float_sqrt (SIM_CPU *cpu, const IDESC *idesc, post_wait_for_FR (cpu, out_FRk); post_wait_for_FRdouble (cpu, in_FRdoublej); post_wait_for_FRdouble (cpu, out_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); vliw = CPU_VLIW (cpu); slot = vliw->next_slot - 1; slot = (*vliw->current_vliw)[slot] - UNIT_FM0; @@ -1656,11 +1719,16 @@ frvbf_model_fr500_u_float_sqrt (SIM_CPU *cpu, const IDESC *idesc, /* The latency of FRk will be at least the latency of the other inputs. */ update_FR_latency (cpu, out_FRk, ps->post_wait); update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); /* Once initiated, post-processing will take 15 cycles. */ update_FR_ptime (cpu, out_FRk, 15); update_FRdouble_ptime (cpu, out_FRdoublek, 15); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 15); + /* The latency of the sqrt unit will be the latency of the other inputs plus 14 cycles. */ update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14); @@ -1844,6 +1912,12 @@ frvbf_model_fr500_u_float_convert (SIM_CPU *cpu, const IDESC *idesc, post_wait_for_FR (cpu, out_FRk); post_wait_for_FR (cpu, out_FRintk); post_wait_for_FRdouble (cpu, out_FRdoublek); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRintk)); + post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek)); + } restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1); restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1); restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1); @@ -1853,11 +1927,25 @@ frvbf_model_fr500_u_float_convert (SIM_CPU *cpu, const IDESC *idesc, update_FR_latency (cpu, out_FRintk, ps->post_wait); update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRintk), ps->post_wait); + update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait); + } + /* Once initiated, post-processing will take 3 cycles. */ update_FR_ptime (cpu, out_FRk, 3); update_FR_ptime (cpu, out_FRintk, 3); update_FRdouble_ptime (cpu, out_FRdoublek, 3); + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRintk), 3); + update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3); + } + /* Mark this use of the register as a floating point op. */ if (out_FRk >= 0) set_use_is_fpop (cpu, out_FRk); @@ -2632,7 +2720,7 @@ frvbf_model_fr500_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, if (dual_FRk >= 0) fr[dual_FRk] += busy_adjustment[2]; - /* The latency of tht output register will be at least the latency of the + /* The latency of the output register will be at least the latency of the other inputs. Once initiated, post-processing will take 3 cycles. */ update_FR_latency (cpu, out_FRk, ps->post_wait); update_FR_ptime (cpu, out_FRk, 3); diff --git a/sim/frv/profile.c b/sim/frv/profile.c index 6ef1e35..2eadef4 100644 --- a/sim/frv/profile.c +++ b/sim/frv/profile.c @@ -1155,6 +1155,52 @@ update_FRdouble_latency_for_load (SIM_CPU *cpu, INT out_FR, int cycles) /* Top up the post-processing time of the given FR by the given number of cycles. */ void +update_FR_ptime (SIM_CPU *cpu, INT out_FR, int cycles) +{ + if (out_FR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + /* If a load is pending on this register, then add the cycles to + the post processing time for this register. Otherwise apply it + directly to the latency of the register. */ + if (! load_pending_for_register (cpu, out_FR, 1, REGTYPE_FR)) + { + int *fr = ps->fr_latency; + fr[out_FR] += cycles; + } + else + ps->fr_ptime[out_FR] += cycles; + } +} + +void +update_FRdouble_ptime (SIM_CPU *cpu, INT out_FR, int cycles) +{ + if (out_FR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + /* If a load is pending on this register, then add the cycles to + the post processing time for this register. Otherwise apply it + directly to the latency of the register. */ + if (! load_pending_for_register (cpu, out_FR, 2, REGTYPE_FR)) + { + int *fr = ps->fr_latency; + fr[out_FR] += cycles; + if (out_FR < 63) + fr[out_FR + 1] += cycles; + } + else + { + ps->fr_ptime[out_FR] += cycles; + if (out_FR < 63) + ps->fr_ptime[out_FR + 1] += cycles; + } + } +} + +/* Top up the post-processing time of the given ACC by the given number of + cycles. */ +void update_ACC_ptime (SIM_CPU *cpu, INT out_ACC, int cycles) { if (out_ACC >= 0) @@ -1167,6 +1213,21 @@ update_ACC_ptime (SIM_CPU *cpu, INT out_ACC, int cycles) } } +/* Top up the post-processing time of the given SPR by the given number of + cycles. */ +void +update_SPR_ptime (SIM_CPU *cpu, INT out_SPR, int cycles) +{ + if (out_SPR >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + /* No load can be pending on this register. Apply the cycles + directly to the latency of the register. */ + int *spr = ps->spr_latency; + spr[out_SPR] += cycles; + } +} + void decrease_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles) { @@ -1181,6 +1242,26 @@ decrease_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles) } } +/* start-sanitize-frv */ +void +increase_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles) +{ + if (out_ACC >= 0) + { + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *acc = ps->acc_busy; + acc[out_ACC] += cycles; + } +} + +void +enforce_full_acc_latency (SIM_CPU *cpu, INT in_ACC) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + ps->acc_busy_adjust [in_ACC] = -1; +} + +/* end-sanitize-frv */ void decrease_FR_busy (SIM_CPU *cpu, INT out_FR, int cycles) { @@ -1465,7 +1546,7 @@ vliw_wait_for_fdiv_resource (SIM_CPU *cpu, INT in_resource) { if (TRACE_INSN_P (cpu)) { - sprintf (hazard_name, "Resource hazard for integer division in slot I%d:", in_resource); + sprintf (hazard_name, "Resource hazard for floating point division in slot F%d:", in_resource); } ps->vliw_wait = r[in_resource]; } @@ -1485,7 +1566,7 @@ vliw_wait_for_fsqrt_resource (SIM_CPU *cpu, INT in_resource) { if (TRACE_INSN_P (cpu)) { - sprintf (hazard_name, "Resource hazard for integer division in slot I%d:", in_resource); + sprintf (hazard_name, "Resource hazard for square root in slot F%d:", in_resource); } ps->vliw_wait = r[in_resource]; } @@ -1694,6 +1775,20 @@ post_wait_for_CCR (SIM_CPU *cpu, INT in_CCR) } int +post_wait_for_SPR (SIM_CPU *cpu, INT in_SPR) +{ + FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); + int *spr = ps->spr_busy; + + if (in_SPR >= 0 && spr[in_SPR] > ps->post_wait) + { + ps->post_wait = spr[in_SPR]; + if (TRACE_INSN_P (cpu)) + sprintf (hazard_name, "Data hazard for spr[%d]:", in_SPR); + } +} + +int post_wait_for_fdiv (SIM_CPU *cpu, INT slot) { FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); diff --git a/sim/frv/profile.h b/sim/frv/profile.h index ec36cf6..5570a5a 100644 --- a/sim/frv/profile.h +++ b/sim/frv/profile.h @@ -111,6 +111,8 @@ void update_FR_latency (SIM_CPU *, INT, int); void update_FRdouble_latency (SIM_CPU *, INT, int); void update_FR_latency_for_load (SIM_CPU *, INT, int); void update_FRdouble_latency_for_load (SIM_CPU *, INT, int); +void update_FR_ptime (SIM_CPU *, INT, int); +void update_FRdouble_ptime (SIM_CPU *, INT, int); void decrease_ACC_busy (SIM_CPU *, INT, int); void decrease_FR_busy (SIM_CPU *, INT, int); void decrease_GR_busy (SIM_CPU *, INT, int); @@ -123,6 +125,7 @@ void update_fdiv_resource_latency (SIM_CPU *, INT, int); void update_fsqrt_resource_latency (SIM_CPU *, INT, int); void update_branch_penalty (SIM_CPU *, int); void update_ACC_ptime (SIM_CPU *, INT, int); +void update_SPR_ptime (SIM_CPU *, INT, int); void vliw_wait_for_GR (SIM_CPU *, INT); void vliw_wait_for_GRdouble (SIM_CPU *, INT); void vliw_wait_for_FR (SIM_CPU *, INT); @@ -142,6 +145,7 @@ int post_wait_for_FR (SIM_CPU *, INT); int post_wait_for_FRdouble (SIM_CPU *, INT); int post_wait_for_ACC (SIM_CPU *, INT); int post_wait_for_CCR (SIM_CPU *, INT); +int post_wait_for_SPR (SIM_CPU *, INT); int post_wait_for_fdiv (SIM_CPU *, INT); int post_wait_for_fsqrt (SIM_CPU *, INT); diff --git a/sim/frv/sem.c b/sim/frv/sem.c index e76bea4..f6356c3 100644 --- a/sim/frv/sem.c +++ b/sim/frv/sem.c @@ -5317,35 +5317,6 @@ frvbf_load_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk)); #undef FLD } -/* nldqi: nldqi$pack @($GRi,$d12),$GRk */ - -static SEM_PC -SEM_FN_NAME (frvbf,nldqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_stdi.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; -{ - BI tmp_do_op; - tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 6, 0); -if (tmp_do_op) { -{ - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12)); -frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); -} -} -} -} - - return vpc; -#undef FLD -} - /* nldqfi: nldqfi$pack @($GRi,$d12),$FRintk */ static SEM_PC @@ -27777,11 +27748,14 @@ SEM_FN_NAME (frvbf,mwtaccg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +frv_ref_SI (GET_H_ACCG (FLD (f_ACCGk))); { USI opval = GET_H_FR_INT (FLD (f_FRi)); sim_queue_fn_si_write (current_cpu, frvbf_h_accg_set, FLD (f_ACCGk), opval); TRACE_RESULT (current_cpu, abuf, "accg", 'x', opval); } +} return vpc; #undef FLD @@ -28009,7 +27983,6 @@ static const struct sem_fn_desc sem_fns[] = { { FRVBF_INSN_NLDDFI, SEM_FN_NAME (frvbf,nlddfi) }, { FRVBF_INSN_LDQI, SEM_FN_NAME (frvbf,ldqi) }, { FRVBF_INSN_LDQFI, SEM_FN_NAME (frvbf,ldqfi) }, - { FRVBF_INSN_NLDQI, SEM_FN_NAME (frvbf,nldqi) }, { FRVBF_INSN_NLDQFI, SEM_FN_NAME (frvbf,nldqfi) }, { FRVBF_INSN_STB, SEM_FN_NAME (frvbf,stb) }, { FRVBF_INSN_STH, SEM_FN_NAME (frvbf,sth) }, |