diff options
| -rw-r--r-- | gas/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-by-element.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-by-element.l | 133 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-by-element.s | 62 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 8 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 52 |
6 files changed, 239 insertions, 26 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 821a706..5c561ca 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2018-07-12 Tamar Christina <tamar.christina@arm.com> + + PR binutils/23192 + * testsuite/gas/aarch64/illegal-by-element.s: New. + * testsuite/gas/aarch64/illegal-by-element.d: New. + * testsuite/gas/aarch64/illegal-by-element.l: New. + 2018-07-06 Tamar Christina <tamar.christina@arm.com> PR binutils/23369 diff --git a/gas/testsuite/gas/aarch64/illegal-by-element.d b/gas/testsuite/gas/aarch64/illegal-by-element.d new file mode 100644 index 0000000..5e9e5c2 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-by-element.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: illegal-by-element.s +#error-output: illegal-by-element.l diff --git a/gas/testsuite/gas/aarch64/illegal-by-element.l b/gas/testsuite/gas/aarch64/illegal-by-element.l new file mode 100644 index 0000000..467ccf6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-by-element.l @@ -0,0 +1,133 @@ +[^:]*: Assembler messages: +[^:]*:18: Error: register number out of range 0 to 15 at operand 3 -- `fmla v2.4h,v12.4h,v16.h\[0\]' +[^:]*:18: Error: register number out of range 0 to 15 at operand 3 -- `fmla v2.4h,v12.4h,v27.h\[0\]' +[^:]*:18: Error: register number out of range 0 to 15 at operand 3 -- `fmla v2.4h,v12.4h,v31.h\[0\]' +[^:]*:19: Error: register number out of range 0 to 15 at operand 3 -- `fmlal v2.4s,v12.4h,v16.h\[0\]' +[^:]*:19: Error: register number out of range 0 to 15 at operand 3 -- `fmlal v2.4s,v12.4h,v27.h\[0\]' +[^:]*:19: Error: register number out of range 0 to 15 at operand 3 -- `fmlal v2.4s,v12.4h,v31.h\[0\]' +[^:]*:20: Error: register number out of range 0 to 15 at operand 3 -- `fmlal2 v2.4s,v12.4h,v16.h\[0\]' +[^:]*:20: Error: register number out of range 0 to 15 at operand 3 -- `fmlal2 v2.4s,v12.4h,v27.h\[0\]' +[^:]*:20: Error: register number out of range 0 to 15 at operand 3 -- `fmlal2 v2.4s,v12.4h,v31.h\[0\]' +[^:]*:21: Error: register number out of range 0 to 15 at operand 3 -- `fmls v2.4h,v12.4h,v16.h\[0\]' +[^:]*:21: Error: register number out of range 0 to 15 at operand 3 -- `fmls v2.4h,v12.4h,v27.h\[0\]' +[^:]*:21: Error: register number out of range 0 to 15 at operand 3 -- `fmls v2.4h,v12.4h,v31.h\[0\]' +[^:]*:22: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl v2.4s,v12.4h,v16.h\[0\]' +[^:]*:22: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl v2.4s,v12.4h,v27.h\[0\]' +[^:]*:22: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl v2.4s,v12.4h,v31.h\[0\]' +[^:]*:23: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl2 v2.4s,v12.4h,v16.h\[0\]' +[^:]*:23: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl2 v2.4s,v12.4h,v27.h\[0\]' +[^:]*:23: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl2 v2.4s,v12.4h,v31.h\[0\]' +[^:]*:24: Error: register number out of range 0 to 15 at operand 3 -- `fmul v2.4h,v12.4h,v16.h\[0\]' +[^:]*:24: Error: register number out of range 0 to 15 at operand 3 -- `fmul v2.4h,v12.4h,v27.h\[0\]' +[^:]*:24: Error: register number out of range 0 to 15 at operand 3 -- `fmul v2.4h,v12.4h,v31.h\[0\]' +[^:]*:25: Error: register number out of range 0 to 15 at operand 3 -- `fmulx v2.4h,v12.4h,v16.h\[0\]' +[^:]*:25: Error: register number out of range 0 to 15 at operand 3 -- `fmulx v2.4h,v12.4h,v27.h\[0\]' +[^:]*:25: Error: register number out of range 0 to 15 at operand 3 -- `fmulx v2.4h,v12.4h,v31.h\[0\]' +[^:]*:26: Error: register number out of range 0 to 15 at operand 3 -- `mla v2.4h,v12.4h,v16.h\[0\]' +[^:]*:26: Error: register number out of range 0 to 15 at operand 3 -- `mla v2.4h,v12.4h,v27.h\[0\]' +[^:]*:26: Error: register number out of range 0 to 15 at operand 3 -- `mla v2.4h,v12.4h,v31.h\[0\]' +[^:]*:27: Error: register number out of range 0 to 15 at operand 3 -- `mls v2.4h,v12.4h,v16.h\[0\]' +[^:]*:27: Error: register number out of range 0 to 15 at operand 3 -- `mls v2.4h,v12.4h,v27.h\[0\]' +[^:]*:27: Error: register number out of range 0 to 15 at operand 3 -- `mls v2.4h,v12.4h,v31.h\[0\]' +[^:]*:28: Error: register number out of range 0 to 15 at operand 3 -- `mul v2.4h,v12.4h,v16.h\[0\]' +[^:]*:28: Error: register number out of range 0 to 15 at operand 3 -- `mul v2.4h,v12.4h,v27.h\[0\]' +[^:]*:28: Error: register number out of range 0 to 15 at operand 3 -- `mul v2.4h,v12.4h,v31.h\[0\]' +[^:]*:29: Error: register number out of range 0 to 15 at operand 3 -- `smlal v2.4s,v12.4h,v16.h\[0\]' +[^:]*:29: Error: register number out of range 0 to 15 at operand 3 -- `smlal v2.4s,v12.4h,v27.h\[0\]' +[^:]*:29: Error: register number out of range 0 to 15 at operand 3 -- `smlal v2.4s,v12.4h,v31.h\[0\]' +[^:]*:30: Error: register number out of range 0 to 15 at operand 3 -- `smlal2 v2.4s,v12.8h,v16.h\[0\]' +[^:]*:30: Error: register number out of range 0 to 15 at operand 3 -- `smlal2 v2.4s,v12.8h,v27.h\[0\]' +[^:]*:30: Error: register number out of range 0 to 15 at operand 3 -- `smlal2 v2.4s,v12.8h,v31.h\[0\]' +[^:]*:31: Error: register number out of range 0 to 15 at operand 3 -- `smlsl v2.4s,v12.4h,v16.h\[0\]' +[^:]*:31: Error: register number out of range 0 to 15 at operand 3 -- `smlsl v2.4s,v12.4h,v27.h\[0\]' +[^:]*:31: Error: register number out of range 0 to 15 at operand 3 -- `smlsl v2.4s,v12.4h,v31.h\[0\]' +[^:]*:32: Error: register number out of range 0 to 15 at operand 3 -- `smlsl2 v2.4s,v12.8h,v16.h\[0\]' +[^:]*:32: Error: register number out of range 0 to 15 at operand 3 -- `smlsl2 v2.4s,v12.8h,v27.h\[0\]' +[^:]*:32: Error: register number out of range 0 to 15 at operand 3 -- `smlsl2 v2.4s,v12.8h,v31.h\[0\]' +[^:]*:33: Error: register number out of range 0 to 15 at operand 3 -- `smull v2.4s,v12.4h,v16.h\[0\]' +[^:]*:33: Error: register number out of range 0 to 15 at operand 3 -- `smull v2.4s,v12.4h,v27.h\[0\]' +[^:]*:33: Error: register number out of range 0 to 15 at operand 3 -- `smull v2.4s,v12.4h,v31.h\[0\]' +[^:]*:34: Error: register number out of range 0 to 15 at operand 3 -- `smull2 v2.4s,v12.8h,v16.h\[0\]' +[^:]*:34: Error: register number out of range 0 to 15 at operand 3 -- `smull2 v2.4s,v12.8h,v27.h\[0\]' +[^:]*:34: Error: register number out of range 0 to 15 at operand 3 -- `smull2 v2.4s,v12.8h,v31.h\[0\]' +[^:]*:35: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal v2.4s,v12.4h,v16.h\[0\]' +[^:]*:35: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal v2.4s,v12.4h,v27.h\[0\]' +[^:]*:35: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal v2.4s,v12.4h,v31.h\[0\]' +[^:]*:36: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal2 v2.4s,v12.8h,v16.h\[0\]' +[^:]*:36: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal2 v2.4s,v12.8h,v27.h\[0\]' +[^:]*:36: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal2 v2.4s,v12.8h,v31.h\[0\]' +[^:]*:37: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl v2.4s,v12.4h,v16.h\[0\]' +[^:]*:37: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl v2.4s,v12.4h,v27.h\[0\]' +[^:]*:37: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl v2.4s,v12.4h,v31.h\[0\]' +[^:]*:38: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl2 v2.4s,v12.8h,v16.h\[0\]' +[^:]*:38: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl2 v2.4s,v12.8h,v27.h\[0\]' +[^:]*:38: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl2 v2.4s,v12.8h,v31.h\[0\]' +[^:]*:39: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh v2.4h,v12.4h,v16.h\[0\]' +[^:]*:39: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh v2.4h,v12.4h,v27.h\[0\]' +[^:]*:39: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh v2.4h,v12.4h,v31.h\[0\]' +[^:]*:40: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull v2.4s,v12.4h,v16.h\[0\]' +[^:]*:40: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull v2.4s,v12.4h,v27.h\[0\]' +[^:]*:40: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull v2.4s,v12.4h,v31.h\[0\]' +[^:]*:41: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull2 v2.4s,v12.8h,v16.h\[0\]' +[^:]*:41: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull2 v2.4s,v12.8h,v27.h\[0\]' +[^:]*:41: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull2 v2.4s,v12.8h,v31.h\[0\]' +[^:]*:42: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah v2.4h,v12.4h,v16.h\[0\]' +[^:]*:42: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah v2.4h,v12.4h,v27.h\[0\]' +[^:]*:42: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah v2.4h,v12.4h,v31.h\[0\]' +[^:]*:43: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh v2.4h,v12.4h,v16.h\[0\]' +[^:]*:43: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh v2.4h,v12.4h,v27.h\[0\]' +[^:]*:43: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh v2.4h,v12.4h,v31.h\[0\]' +[^:]*:44: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh v2.4h,v12.4h,v16.h\[0\]' +[^:]*:44: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh v2.4h,v12.4h,v27.h\[0\]' +[^:]*:44: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh v2.4h,v12.4h,v31.h\[0\]' +[^:]*:45: Error: register number out of range 0 to 15 at operand 3 -- `umlal v2.4s,v12.4h,v16.h\[0\]' +[^:]*:45: Error: register number out of range 0 to 15 at operand 3 -- `umlal v2.4s,v12.4h,v27.h\[0\]' +[^:]*:45: Error: register number out of range 0 to 15 at operand 3 -- `umlal v2.4s,v12.4h,v31.h\[0\]' +[^:]*:46: Error: register number out of range 0 to 15 at operand 3 -- `umlal2 v2.4s,v12.8h,v16.h\[0\]' +[^:]*:46: Error: register number out of range 0 to 15 at operand 3 -- `umlal2 v2.4s,v12.8h,v27.h\[0\]' +[^:]*:46: Error: register number out of range 0 to 15 at operand 3 -- `umlal2 v2.4s,v12.8h,v31.h\[0\]' +[^:]*:47: Error: register number out of range 0 to 15 at operand 3 -- `umlsl v2.4s,v12.4h,v16.h\[0\]' +[^:]*:47: Error: register number out of range 0 to 15 at operand 3 -- `umlsl v2.4s,v12.4h,v27.h\[0\]' +[^:]*:47: Error: register number out of range 0 to 15 at operand 3 -- `umlsl v2.4s,v12.4h,v31.h\[0\]' +[^:]*:48: Error: register number out of range 0 to 15 at operand 3 -- `umlsl2 v2.4s,v12.8h,v16.h\[0\]' +[^:]*:48: Error: register number out of range 0 to 15 at operand 3 -- `umlsl2 v2.4s,v12.8h,v27.h\[0\]' +[^:]*:48: Error: register number out of range 0 to 15 at operand 3 -- `umlsl2 v2.4s,v12.8h,v31.h\[0\]' +[^:]*:49: Error: register number out of range 0 to 15 at operand 3 -- `umull v2.4s,v12.4h,v16.h\[0\]' +[^:]*:49: Error: register number out of range 0 to 15 at operand 3 -- `umull v2.4s,v12.4h,v27.h\[0\]' +[^:]*:49: Error: register number out of range 0 to 15 at operand 3 -- `umull v2.4s,v12.4h,v31.h\[0\]' +[^:]*:50: Error: register number out of range 0 to 15 at operand 3 -- `umull2 v2.4s,v12.8h,v16.h\[0\]' +[^:]*:50: Error: register number out of range 0 to 15 at operand 3 -- `umull2 v2.4s,v12.8h,v27.h\[0\]' +[^:]*:50: Error: register number out of range 0 to 15 at operand 3 -- `umull2 v2.4s,v12.8h,v31.h\[0\]' +[^:]*:52: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal s2,h12,v16.h\[0\]' +[^:]*:52: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal s2,h12,v27.h\[0\]' +[^:]*:52: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal s2,h12,v31.h\[0\]' +[^:]*:53: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl s2,h12,v16.h\[0\]' +[^:]*:53: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl s2,h12,v27.h\[0\]' +[^:]*:53: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl s2,h12,v31.h\[0\]' +[^:]*:54: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull s2,h12,v16.h\[0\]' +[^:]*:54: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull s2,h12,v27.h\[0\]' +[^:]*:54: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull s2,h12,v31.h\[0\]' +[^:]*:55: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh h2,h12,v16.h\[0\]' +[^:]*:55: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh h2,h12,v27.h\[0\]' +[^:]*:55: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh h2,h12,v31.h\[0\]' +[^:]*:56: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh h2,h12,v16.h\[0\]' +[^:]*:56: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh h2,h12,v27.h\[0\]' +[^:]*:56: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh h2,h12,v31.h\[0\]' +[^:]*:57: Error: register number out of range 0 to 15 at operand 3 -- `fmla h2,h12,v16.h\[0\]' +[^:]*:57: Error: register number out of range 0 to 15 at operand 3 -- `fmla h2,h12,v27.h\[0\]' +[^:]*:57: Error: register number out of range 0 to 15 at operand 3 -- `fmla h2,h12,v31.h\[0\]' +[^:]*:58: Error: register number out of range 0 to 15 at operand 3 -- `fmls h2,h12,v16.h\[0\]' +[^:]*:58: Error: register number out of range 0 to 15 at operand 3 -- `fmls h2,h12,v27.h\[0\]' +[^:]*:58: Error: register number out of range 0 to 15 at operand 3 -- `fmls h2,h12,v31.h\[0\]' +[^:]*:59: Error: register number out of range 0 to 15 at operand 3 -- `fmul h2,h12,v16.h\[0\]' +[^:]*:59: Error: register number out of range 0 to 15 at operand 3 -- `fmul h2,h12,v27.h\[0\]' +[^:]*:59: Error: register number out of range 0 to 15 at operand 3 -- `fmul h2,h12,v31.h\[0\]' +[^:]*:60: Error: register number out of range 0 to 15 at operand 3 -- `fmulx h2,h12,v16.h\[0\]' +[^:]*:60: Error: register number out of range 0 to 15 at operand 3 -- `fmulx h2,h12,v27.h\[0\]' +[^:]*:60: Error: register number out of range 0 to 15 at operand 3 -- `fmulx h2,h12,v31.h\[0\]' +[^:]*:61: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah h2,h12,v16.h\[0\]' +[^:]*:61: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah h2,h12,v27.h\[0\]' +[^:]*:61: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah h2,h12,v31.h\[0\]' +[^:]*:62: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh h2,h12,v16.h\[0\]' +[^:]*:62: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh h2,h12,v27.h\[0\]' +[^:]*:62: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh h2,h12,v31.h\[0\]' diff --git a/gas/testsuite/gas/aarch64/illegal-by-element.s b/gas/testsuite/gas/aarch64/illegal-by-element.s new file mode 100644 index 0000000..99e7322 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-by-element.s @@ -0,0 +1,62 @@ +.text + .macro gen_illegal op, p1, p2, p3 + .irp w, v16.\p3, v27.\p3, v31.\p3 + \op v2.\p1, v12.\p2, \w[0] + .endr + .endm + + .macro gen_illegal2 op, p1, p2, p3 + .irp x, \p1\()2 + .irp y, \p2\()12 + .irp w, v16.\p3, v27.\p3, v31.\p3 + \op \x, \y, \w[0] + .endr + .endr + .endr + .endm + + gen_illegal fmla, 4h, 4h, h + gen_illegal fmlal, 4s, 4h, h + gen_illegal fmlal2, 4s, 4h, h + gen_illegal fmls, 4h, 4h, h + gen_illegal fmlsl, 4s, 4h, h + gen_illegal fmlsl2, 4s, 4h, h + gen_illegal fmul, 4h, 4h, h + gen_illegal fmulx, 4h, 4h, h + gen_illegal mla, 4h, 4h, h + gen_illegal mls, 4h, 4h, h + gen_illegal mul, 4h, 4h, h + gen_illegal smlal, 4s, 4h, h + gen_illegal smlal2, 4s, 8h, h + gen_illegal smlsl, 4s, 4h, h + gen_illegal smlsl2, 4s, 8h, h + gen_illegal smull, 4s, 4h, h + gen_illegal smull2, 4s, 8h, h + gen_illegal sqdmlal, 4s, 4h, h + gen_illegal sqdmlal2, 4s, 8h, h + gen_illegal sqdmlsl, 4s, 4h, h + gen_illegal sqdmlsl2, 4s, 8h, h + gen_illegal sqdmulh, 4h, 4h, h + gen_illegal sqdmull, 4s, 4h, h + gen_illegal sqdmull2, 4s, 8h, h + gen_illegal sqrdmlah, 4h, 4h, h + gen_illegal sqrdmlsh, 4h, 4h, h + gen_illegal sqrdmulh, 4h, 4h, h + gen_illegal umlal, 4s, 4h, h + gen_illegal umlal2, 4s, 8h, h + gen_illegal umlsl, 4s, 4h, h + gen_illegal umlsl2, 4s, 8h, h + gen_illegal umull, 4s, 4h, h + gen_illegal umull2, 4s, 8h, h + + gen_illegal2 sqdmlal, s, h, h + gen_illegal2 sqdmlsl, s, h, h + gen_illegal2 sqdmull, s, h, h + gen_illegal2 sqdmulh, h, h, h + gen_illegal2 sqrdmulh, h, h, h + gen_illegal2 fmla, h, h, h + gen_illegal2 fmls, h, h, h + gen_illegal2 fmul, h, h, h + gen_illegal2 fmulx, h, h, h + gen_illegal2 sqrdmlah, h, h, h + gen_illegal2 sqrdmlsh, h, h, h diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index cf1f052..6636bdf 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2018-07-12 Tamar Christina <tamar.christina@arm.com> + + PR binutils/23192 + * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2, + mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal, + umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull, + sqdmulh, sqrdmulh): Use Em16. + 2018-07-06 Tamar Christina <tamar.christina@arm.com> PR binutils/23242 diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 559efdb..39238cd 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2342,33 +2342,33 @@ struct aarch64_opcode aarch64_opcode_table[] = /* AdvSIMD vector x indexed element. */ SIMD_INSN ("smlal", 0x0f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), SIMD_INSN ("smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), - SIMD_INSN ("sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), - SIMD_INSN ("sqdmlal2",0x4f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), - SIMD_INSN ("smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), - SIMD_INSN ("smlsl2", 0x4f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), - SIMD_INSN ("sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), - SIMD_INSN ("sqdmlsl2",0x4f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), - SIMD_INSN ("mul", 0x0f008000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), - SIMD_INSN ("smull", 0x0f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), - SIMD_INSN ("smull2", 0x4f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), - SIMD_INSN ("sqdmull", 0x0f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), - SIMD_INSN ("sqdmull2",0x4f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), - SIMD_INSN ("sqdmulh", 0x0f00c000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), - SIMD_INSN ("sqrdmulh",0x0f00d000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), + SIMD_INSN ("sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), + SIMD_INSN ("sqdmlal2",0x4f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), + SIMD_INSN ("smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), + SIMD_INSN ("smlsl2", 0x4f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), + SIMD_INSN ("sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), + SIMD_INSN ("sqdmlsl2",0x4f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), + SIMD_INSN ("mul", 0x0f008000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), + SIMD_INSN ("smull", 0x0f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), + SIMD_INSN ("smull2", 0x4f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), + SIMD_INSN ("sqdmull", 0x0f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), + SIMD_INSN ("sqdmull2",0x4f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), + SIMD_INSN ("sqdmulh", 0x0f00c000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), + SIMD_INSN ("sqrdmulh",0x0f00d000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), SIMD_INSN ("fmla", 0x0f801000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), SF16_INSN ("fmla", 0x0f001000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), SIMD_INSN ("fmls", 0x0f805000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), SF16_INSN ("fmls", 0x0f005000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), SIMD_INSN ("fmul", 0x0f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), SF16_INSN ("fmul", 0x0f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), - SIMD_INSN ("mla", 0x2f000000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), - SIMD_INSN ("umlal", 0x2f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), - SIMD_INSN ("umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), - SIMD_INSN ("mls", 0x2f004000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ), - SIMD_INSN ("umlsl", 0x2f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), - SIMD_INSN ("umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), - SIMD_INSN ("umull", 0x2f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ), - SIMD_INSN ("umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ), + SIMD_INSN ("mla", 0x2f000000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), + SIMD_INSN ("umlal", 0x2f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), + SIMD_INSN ("umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), + SIMD_INSN ("mls", 0x2f004000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), + SIMD_INSN ("umlsl", 0x2f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), + SIMD_INSN ("umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), + SIMD_INSN ("umull", 0x2f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ), + SIMD_INSN ("umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ), SIMD_INSN ("fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ), SF16_INSN ("fmulx", 0x2f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ), RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ), @@ -2674,11 +2674,11 @@ struct aarch64_opcode aarch64_opcode_table[] = SIMD_INSN ("sqdmlsl", 0x5e20b000, 0xff20fc00, asisddiff, 0, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE), SIMD_INSN ("sqdmull", 0x5e20d000, 0xff20fc00, asisddiff, 0, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE), /* AdvSIMD scalar x indexed element. */ - SIMD_INSN ("sqdmlal", 0x5f003000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE), - SIMD_INSN ("sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE), - SIMD_INSN ("sqdmull", 0x5f00b000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE), - SIMD_INSN ("sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE), - SIMD_INSN ("sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE), + SIMD_INSN ("sqdmlal", 0x5f003000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE), + SIMD_INSN ("sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE), + SIMD_INSN ("sqdmull", 0x5f00b000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE), + SIMD_INSN ("sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), + SIMD_INSN ("sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE), SIMD_INSN ("fmla", 0x5f801000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE), SF16_INSN ("fmla", 0x5f001000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE), SIMD_INSN ("fmls", 0x5f805000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE), |