diff options
| -rw-r--r-- | sim/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/avr/interp.c | 36 |
2 files changed, 25 insertions, 16 deletions
diff --git a/sim/ChangeLog b/sim/ChangeLog index 18f555c..35055a9 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,5 +1,10 @@ 2009-11-12 Tristan Gingold <gingold@adacore.com> + * avr/interp.c (sim_write): Allow byte access. + (sim_read): Ditto. + +2009-11-12 Tristan Gingold <gingold@adacore.com> + * avr/interp.c (sim_load): Clear memory before loading. 2009-11-09 Tristan Gingold <gingold@adacore.com> diff --git a/sim/avr/interp.c b/sim/avr/interp.c index 8d267dd..109046b 100644 --- a/sim/avr/interp.c +++ b/sim/avr/interp.c @@ -1628,16 +1628,20 @@ sim_write (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size) if (addr >= 0 && addr < SRAM_VADDR) { - if (addr & 1) - return 0; - addr /= 2; - while (size > 1 && addr < MAX_AVR_FLASH) + while (size > 0 && addr < (MAX_AVR_FLASH << 1)) { - flash[addr].op = buffer[0] | (buffer[1] << 8); - flash[addr].code = OP_unknown; + word val = flash[addr >> 1].op; + + if (addr & 1) + val = (val & 0xff) | (buffer[0] << 8); + else + val = (val & 0xff00) | buffer[0]; + + flash[addr >> 1].op = val; + flash[addr >> 1].code = OP_unknown; addr++; - buffer += 2; - size -= 2; + buffer++; + size--; } return osize - size; } @@ -1660,16 +1664,16 @@ sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size) if (addr >= 0 && addr < SRAM_VADDR) { - if (addr & 1) - return 0; - addr /= 2; - while (size > 1 && addr < MAX_AVR_FLASH) + while (size > 0 && addr < (MAX_AVR_FLASH << 1)) { - buffer[0] = flash[addr].op; - buffer[1] = flash[addr].op >> 8; + word val = flash[addr >> 1].op; + + if (addr & 1) + val >>= 8; + + *buffer++ = val; addr++; - buffer += 2; - size -= 2; + size--; } return osize - size; } |