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| -rw-r--r-- | gas/doc/c-m32r.texi | 123 |
1 files changed, 122 insertions, 1 deletions
diff --git a/gas/doc/c-m32r.texi b/gas/doc/c-m32r.texi index f121ede..82b5456d 100644 --- a/gas/doc/c-m32r.texi +++ b/gas/doc/c-m32r.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc. +@c Copyright (C) 1991, 92-98, 1999 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC @@ -11,3 +11,124 @@ @chapter M32R Dependent Features @end ifclear +@cindex M32R support +@menu +* M32R-Opts:: M32R Options +* M32R-Warnings:: M32R Warnings +@end menu + +@node M32R-Opts +@section M32R Options + +@cindex options, M32R +@cindex M32R options + +The Mitsubishi M32R version of @code{@value{AS}} has a few machine +dependent options: + +@table @code +@item -m32rx +@cindex @samp{-m32rx} option, M32RX +@cindex architecture options, M32RX +@cindex M32R architecture options +@code{@value{AS}} can assemble code for several different members of the +Mitsubishi M32R family. Normally the default is to assemble code for +the M32R microprocessor. This option may be used to change the default +to the M32RX microprocessor, which adds some more instructions to the +basic M32R instruction set, and some additional parameters to some of +the original instructions. + +@item -warn-explicit-parallel-conflicts +@cindex @samp{-warn-explicit-parallel-conflicts} option, M32RX +Instructs @code{@value{AS}} to produce warning messages when +questionable parallel instructions are encountered. This option is +enabled by default, but @code{@value{GCC}} disables it when it invokes +@code{@value{AS}} directly. Questionable instructions are those whoes +behaviour would be different if they were executed sequentially. For +example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a +different result from @samp{mv r1, r2 \n mv r3, r1} since the former +moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 +and r3. + +@item -Wp +@cindex @samp{-Wp} option, M32RX +This is a shorter synonym for the @emph{-warn-explicit-parallel-conflicts} +option. + +@item -no-warn-explicit-parallel-conflicts +@cindex @samp{-no-warn-explicit-parallel-conflicts} option, M32RX +Instructs @code{@value{AS}} not to produce warning messages when +questionable parallel instructions are encountered. + +@item -Wnp +@cindex @samp{-Wnp} option, M32RX +This is a shorter synonym for the @emph{-no-warn-explicit-parallel-conflicts} +option. + +@end table + +@node M32R-Warnings +@section M32R Warnings + +@cindex warnings, M32R +@cindex M32R warnings + +There are several warning and error messages that can be produced by +@code{@value{AS}} which are specific to the M32R: + +@table @code + +@item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ? +This message is only produced if warnings for explicit parallel +conflicts have been enabled. It indicates that the assembler has +encountered a parallel instruction in which the destination register of +the left hand instruction is used as an input register in the right hand +instruction. For example in this code fragment +@samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the +move instruction and the input to the neg instruction. + +@item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ? +This message is only produced if warnings for explicit parallel +conflicts have been enabled. It indicates that the assembler has +encountered a parallel instruction in which the destination register of +the right hand instruction is used as an input register in the left hand +instruction. For example in this code fragment +@samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the +neg instruction and the input to the move instruction. + +@item instruction @samp{...} is for the M32RX only +This message is produced when the assembler encounters an instruction +which is only supported by the M32Rx processor, and the @samp{-m32rx} +command line flag has not been specified to allow assembly of such +instructions. + +@item unknown instruction @samp{...} +This message is produced when the assembler encounters an instruction +which it doe snot recognise. + +@item only the NOP instruction can be issued in parallel on the m32r +This message is produced when the assembler encounters a parallel +instruction which does not involve a NOP instruction and the +@samp{-m32rx} command line flag has not been specified. Only the M32Rx +processor is able to execute two instructions in parallel. + +@item instruction @samp{...} cannot be executed in parallel. +This message is produced when the assembler encounters a parallel +instruction which is made up of one or two instructions which cannot be +executed in parallel. + +@item Instructions share the same execution pipeline +This message is produced when the assembler encounters a parallel +instruction whoes components both use the same execution pipeline. + +@item Instructions write to the same destination register. +This message is produced when the assembler encounters a parallel +instruction where both components attempt to modify the same register. +For example these code fragments will produce this message: +@samp{mv r1, r2 || neg r1, r3} +@samp{jl r0 || mv r14, r1} +@samp{st r2, @@-r1 || mv r1, r3} +@samp{mv r1, r2 || ld r0, @@r1+} +@samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit) + +@end table |