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-rw-r--r--opcodes/ChangeLog25
-rw-r--r--opcodes/fr30-opc.c13
-rw-r--r--opcodes/i370-opc.c798
-rw-r--r--opcodes/i960-dis.c1469
-rw-r--r--opcodes/m32r-asm.c17
-rw-r--r--opcodes/m32r-desc.c7
-rw-r--r--opcodes/m32r-dis.c52
-rw-r--r--opcodes/m32r-ibld.c21
-rw-r--r--opcodes/m32r-opc.c13
-rw-r--r--opcodes/m32r-opinst.c6
-rw-r--r--opcodes/ns32k-dis.c12
-rw-r--r--opcodes/openrisc-asm.c13
-rw-r--r--opcodes/openrisc-desc.c7
-rw-r--r--opcodes/openrisc-dis.c14
-rw-r--r--opcodes/openrisc-ibld.c23
-rw-r--r--opcodes/openrisc-opc.c13
-rw-r--r--opcodes/pdp11-dis.c1
-rw-r--r--opcodes/tic54x-dis.c3
-rw-r--r--opcodes/v850-opc.c77
-rw-r--r--opcodes/vax-dis.c4
-rw-r--r--opcodes/w65-opc.h2
-rw-r--r--opcodes/z8k-opc.h2
-rw-r--r--opcodes/z8kgen.c2
23 files changed, 1360 insertions, 1234 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1dad511..5690d72 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,28 @@
+2001-09-20 Nick Clifton <nickc@cambridge.redhat.com>
+
+ * fr30-opc.c: Fix compile time warning messages.
+ * i370-opc.c: Fix compile time warning messages.
+ * i960-dis.c: Fix compile time warning messages.
+ * m32r-asm.c: Fix compile time warning messages.
+ * m32r-desc.c: Fix compile time warning messages.
+ * m32r-dis.c: Fix compile time warning messages.
+ * m32r-ibld.c: Fix compile time warning messages.
+ * m32r-opc.c: Fix compile time warning messages.
+ * m32r-opinst.c: Fix compile time warning messages.
+ * ns32k-dis.c: Fix compile time warning messages.
+ * openrisc-asm.c: Fix compile time warning messages.
+ * openrisc-desc.c: Fix compile time warning messages.
+ * openrisc-dis.c: Fix compile time warning messages.
+ * openrisc-ibld.c: Fix compile time warning messages.
+ * openrisc-opc.c: Fix compile time warning messages.
+ * pdp11-dis.c: Fix compile time warning messages.
+ * tic54x-dis.c: Fix compile time warning messages.
+ * v850-opc.c: Fix compile time warning messages.
+ * vax-dis.c: Fix compile time warning messages.
+ * w65-opc.h: Fix compile time warning messages.
+ * z8k-opc.h: Fix compile time warning messages.
+ * z8kgen.c: Fix compile time warning messages.
+
2001-09-19 Nick Clifton <nickc@cambridge.redhat.com>
* arm-dis.c: Fix compile time warning messages.
diff --git a/opcodes/fr30-opc.c b/opcodes/fr30-opc.c
index 877f26b..caa039a 100644
--- a/opcodes/fr30-opc.c
+++ b/opcodes/fr30-opc.c
@@ -33,10 +33,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int asm_hash_insn PARAMS ((const char *));
+static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
/* Instruction formats. */
@@ -1284,7 +1285,7 @@ static const CGEN_OPCODE fr30_cgen_macro_insn_opcode_table[] =
static int
asm_hash_insn_p (insn)
- const CGEN_INSN *insn;
+ const CGEN_INSN *insn ATTRIBUTE_UNUSED;
{
return CGEN_ASM_HASH_P (insn);
}
@@ -1335,7 +1336,7 @@ asm_hash_insn (mnem)
static unsigned int
dis_hash_insn (buf, value)
const char * buf;
- CGEN_INSN_INT value;
+ CGEN_INSN_INT value ATTRIBUTE_UNUSED;
{
return CGEN_DIS_HASH (buf, value);
}
diff --git a/opcodes/i370-opc.c b/opcodes/i370-opc.c
index 678f374..376dd0e 100644
--- a/opcodes/i370-opc.c
+++ b/opcodes/i370-opc.c
@@ -1,5 +1,5 @@
/* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list
- Copyright 1994, 1999, 2000 Free Software Foundation, Inc.
+ Copyright 1994, 1999, 2000, 2001 Free Software Foundation, Inc.
PowerPC version written by Ian Lance Taylor, Cygnus Support
Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999
@@ -199,7 +199,7 @@ const struct i370_operand i370_operands[] =
#define S_D2_MASK (0xfff)
{ 12, 0, 0, 0, I370_OPERAND_RELATIVE, "S D2" },
- /* The L length field in an SS form instruction. */
+ /* The L length field in an SS form instruction. */
#define SS_L (S_D2 + 1)
#define SS_L_MASK (0xffff<<16)
{ 8, 16, 0, 0, I370_OPERAND_RELATIVE | I370_OPERAND_LENGTH, "SS L" },
@@ -234,7 +234,7 @@ static i370_insn_t
insert_ss_b2 (insn, value, errmsg)
i370_insn_t insn;
long value;
- const char **errmsg;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
insn.i[1] |= (value & 0xf) << 28;
return insn;
@@ -244,7 +244,7 @@ static i370_insn_t
insert_ss_d2 (insn, value, errmsg)
i370_insn_t insn;
long value;
- const char **errmsg;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
insn.i[1] |= (value & 0xfff) << 16;
return insn;
@@ -254,7 +254,7 @@ static i370_insn_t
insert_rxf_r3 (insn, value, errmsg)
i370_insn_t insn;
long value;
- const char **errmsg;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
insn.i[1] |= (value & 0xf) << 28;
return insn;
@@ -263,7 +263,7 @@ insert_rxf_r3 (insn, value, errmsg)
static long
extract_ss_b2 (insn, invalid)
i370_insn_t insn;
- int *invalid;
+ int *invalid ATTRIBUTE_UNUSED;
{
return (insn.i[1] >>28) & 0xf;
}
@@ -271,7 +271,7 @@ extract_ss_b2 (insn, invalid)
static long
extract_ss_d2 (insn, invalid)
i370_insn_t insn;
- int *invalid;
+ int *invalid ATTRIBUTE_UNUSED;
{
return (insn.i[1] >>16) & 0xfff;
}
@@ -279,7 +279,7 @@ extract_ss_d2 (insn, invalid)
static long
extract_rxf_r3 (insn, invalid)
i370_insn_t insn;
- int *invalid;
+ int *invalid ATTRIBUTE_UNUSED;
{
return (insn.i[1] >>28) & 0xf;
}
@@ -341,7 +341,7 @@ extract_rxf_r3 (insn, invalid)
#define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0)
-/* An RX form instruction. */
+/* An RX form instruction. */
#define RX(op, r1, x2, b2, d2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(x2)) & 0xf) << 16) | \
@@ -350,7 +350,7 @@ extract_rxf_r3 (insn, invalid)
#define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0)
-/* An RXE form instruction high word. */
+/* An RXE form instruction high word. */
#define RXEH(op, r1, x2, b2, d2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(x2)) & 0xf) << 16) | \
@@ -359,13 +359,13 @@ extract_rxf_r3 (insn, invalid)
#define RXEH_MASK RXEH (0xff, 0, 0, 0, 0)
-/* An RXE form instruction low word. */
+/* An RXE form instruction low word. */
#define RXEL(op) \
((((unsigned short)(op)) & 0xff) << 16 )
#define RXEL_MASK RXEL (0xff)
-/* An RXF form instruction high word. */
+/* An RXF form instruction high word. */
#define RXFH(op, r1, x2, b2, d2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(x2)) & 0xf) << 16) | \
@@ -374,14 +374,14 @@ extract_rxf_r3 (insn, invalid)
#define RXFH_MASK RXFH (0xff, 0, 0, 0, 0)
-/* An RXF form instruction low word. */
+/* An RXF form instruction low word. */
#define RXFL(op, r3) \
(((((unsigned short)(r3)) & 0xf) << 28 ) | \
((((unsigned short)(op)) & 0xff) << 16 ))
#define RXFL_MASK RXFL (0xff, 0)
-/* An RS form instruction. */
+/* An RS form instruction. */
#define RS(op, r1, b3, b2, d2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(b3)) & 0xf) << 16) | \
@@ -390,7 +390,7 @@ extract_rxf_r3 (insn, invalid)
#define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0)
-/* An RSI form instruction. */
+/* An RSI form instruction. */
#define RSI(op, r1, r3, i2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(r3)) & 0xf) << 16) | \
@@ -398,14 +398,14 @@ extract_rxf_r3 (insn, invalid)
#define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0)
-/* An RI form instruction. */
+/* An RI form instruction. */
#define RI(op, r1, i2) \
(ROPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(i2)) & 0xffff)))
#define RI_MASK RI (0xfff, 0x0, 0x0)
-/* An SI form instruction. */
+/* An SI form instruction. */
#define SI(op, i2, b1, d1) \
(XOPS(op) | ((((unsigned short)(i2)) & 0xff) << 16) | \
((((unsigned short)(b1)) & 0xf) << 12) | \
@@ -413,32 +413,32 @@ extract_rxf_r3 (insn, invalid)
#define SI_MASK SI (0xff, 0x0, 0x0, 0x0)
-/* An S form instruction. */
+/* An S form instruction. */
#define S(op, b2, d2) \
(SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) | \
((((unsigned short)(d2)) & 0xfff)))
#define S_MASK S (0xffff, 0x0, 0x0)
-/* An SS form instruction high word. */
+/* An SS form instruction high word. */
#define SSH(op, l, b1, d1) \
(XOPS(op) | ((((unsigned short)(l)) & 0xff) << 16) | \
((((unsigned short)(b1)) & 0xf) << 12) | \
((((unsigned short)(d1)) & 0xfff)))
-/* An SS form instruction low word. */
+/* An SS form instruction low word. */
#define SSL(b2, d2) \
( ((((unsigned short)(b1)) & 0xf) << 28) | \
((((unsigned short)(d1)) & 0xfff) << 16 ))
#define SS_MASK SSH (0xff, 0x0, 0x0, 0x0)
-/* An SSE form instruction high word. */
+/* An SSE form instruction high word. */
#define SSEH(op, b1, d1) \
(SOPS(op) | ((((unsigned short)(b1)) & 0xf) << 12) | \
((((unsigned short)(d1)) & 0xfff)))
-/* An SSE form instruction low word. */
+/* An SSE form instruction low word. */
#define SSEL(b2, d2) \
( ((((unsigned short)(b1)) & 0xf) << 28) | \
((((unsigned short)(d1)) & 0xfff) << 16 ))
@@ -495,414 +495,414 @@ extract_rxf_r3 (insn, invalid)
const struct i370_opcode i370_opcodes[] = {
/* E form instructions */
-{ "pr", 2, {E(0x0101), 0}, {E_MASK, 0}, IESA, {0} },
+{ "pr", 2, {{E(0x0101), 0}}, {{E_MASK, 0}}, IESA, {0} },
-{ "trap2", 2, {E(0x01FF), 0}, {E_MASK, 0}, ITR, {0} },
-{ "upt", 2, {E(0x0102), 0}, {E_MASK, 0}, IXA, {0} },
+{ "trap2", 2, {{E(0x01FF), 0}}, {{E_MASK, 0}}, ITR, {0} },
+{ "upt", 2, {{E(0x0102), 0}}, {{E_MASK, 0}}, IXA, {0} },
/* RR form instructions */
-{ "ar", 2, {RR(0x1a,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "adr", 2, {RR(0x2a,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "aer", 2, {RR(0x3a,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "alr", 2, {RR(0x1e,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "aur", 2, {RR(0x2e,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "awr", 2, {RR(0x3e,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "axr", 2, {RR(0x36,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "balr", 2, {RR(0x05,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "basr", 2, {RR(0x0d,0,0), 0}, {RR_MASK, 0}, IXA, {RR_R1, RR_R2} },
-{ "bassm", 2, {RR(0x0c,0,0), 0}, {RR_MASK, 0}, IXA, {RR_R1, RR_R2} },
-{ "bsm", 2, {RR(0x0b,0,0), 0}, {RR_MASK, 0}, IXA, {RR_R1, RR_R2} },
-{ "bcr", 2, {RR(0x07,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "bctr", 2, {RR(0x06,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "cdr", 2, {RR(0x29,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "cer", 2, {RR(0x39,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "clr", 2, {RR(0x15,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "clcl", 2, {RR(0x0f,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "cr", 2, {RR(0x19,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "ddr", 2, {RR(0x2d,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "der", 2, {RR(0x3d,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "dr", 2, {RR(0x1d,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "hdr", 2, {RR(0x24,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "her", 2, {RR(0x34,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "lcdr", 2, {RR(0x23,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "lcer", 2, {RR(0x33,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "lcr", 2, {RR(0x13,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "ldr", 2, {RR(0x28,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "ler", 2, {RR(0x38,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "lndr", 2, {RR(0x21,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "lner", 2, {RR(0x31,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "lnr", 2, {RR(0x11,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "lpdr", 2, {RR(0x20,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "lper", 2, {RR(0x30,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "lpr", 2, {RR(0x10,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "lr", 2, {RR(0x18,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "lrdr", 2, {RR(0x25,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "lrer", 2, {RR(0x35,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "ltdr", 2, {RR(0x22,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "lter", 2, {RR(0x32,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "ltr", 2, {RR(0x12,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "mdr", 2, {RR(0x2c,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "mer", 2, {RR(0x3c,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "mr", 2, {RR(0x1c,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "mvcl", 2, {RR(0x0e,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "mxdr", 2, {RR(0x27,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "mxr", 2, {RR(0x26,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "nr", 2, {RR(0x14,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "or", 2, {RR(0x16,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "sdr", 2, {RR(0x2b,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "ser", 2, {RR(0x3b,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "slr", 2, {RR(0x1f,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "spm", 2, {RR(0x04,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1} },
-{ "sr", 2, {RR(0x1b,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "sur", 2, {RR(0x3f,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "swr", 2, {RR(0x2f,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "sxr", 2, {RR(0x37,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
-{ "xr", 2, {RR(0x17,0,0), 0}, {RR_MASK, 0}, I370, {RR_R1, RR_R2} },
+{ "ar", 2, {{RR(0x1a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "adr", 2, {{RR(0x2a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "aer", 2, {{RR(0x3a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "alr", 2, {{RR(0x1e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "aur", 2, {{RR(0x2e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "awr", 2, {{RR(0x3e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "axr", 2, {{RR(0x36,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "balr", 2, {{RR(0x05,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "basr", 2, {{RR(0x0d,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} },
+{ "bassm", 2, {{RR(0x0c,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} },
+{ "bsm", 2, {{RR(0x0b,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} },
+{ "bcr", 2, {{RR(0x07,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "bctr", 2, {{RR(0x06,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "cdr", 2, {{RR(0x29,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "cer", 2, {{RR(0x39,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "clr", 2, {{RR(0x15,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "clcl", 2, {{RR(0x0f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "cr", 2, {{RR(0x19,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "ddr", 2, {{RR(0x2d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "der", 2, {{RR(0x3d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "dr", 2, {{RR(0x1d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "hdr", 2, {{RR(0x24,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "her", 2, {{RR(0x34,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "lcdr", 2, {{RR(0x23,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "lcer", 2, {{RR(0x33,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "lcr", 2, {{RR(0x13,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "ldr", 2, {{RR(0x28,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "ler", 2, {{RR(0x38,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "lndr", 2, {{RR(0x21,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "lner", 2, {{RR(0x31,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "lnr", 2, {{RR(0x11,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "lpdr", 2, {{RR(0x20,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "lper", 2, {{RR(0x30,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "lpr", 2, {{RR(0x10,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "lr", 2, {{RR(0x18,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "lrdr", 2, {{RR(0x25,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "lrer", 2, {{RR(0x35,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "ltdr", 2, {{RR(0x22,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "lter", 2, {{RR(0x32,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "ltr", 2, {{RR(0x12,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "mdr", 2, {{RR(0x2c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "mer", 2, {{RR(0x3c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "mr", 2, {{RR(0x1c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "mvcl", 2, {{RR(0x0e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "mxdr", 2, {{RR(0x27,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "mxr", 2, {{RR(0x26,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "nr", 2, {{RR(0x14,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "or", 2, {{RR(0x16,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "sdr", 2, {{RR(0x2b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "ser", 2, {{RR(0x3b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "slr", 2, {{RR(0x1f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "spm", 2, {{RR(0x04,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1} },
+{ "sr", 2, {{RR(0x1b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "sur", 2, {{RR(0x3f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "swr", 2, {{RR(0x2f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "sxr", 2, {{RR(0x37,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
+{ "xr", 2, {{RR(0x17,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
/* unusual RR formats */
-{ "svc", 2, {SVC(0x0a,0), 0}, {SVC_MASK, 0}, I370, {RR_I} },
+{ "svc", 2, {{SVC(0x0a,0), 0}}, {{SVC_MASK, 0}}, I370, {RR_I} },
/* RRE form instructions */
-{ "adbr", 4, {RRE(0xb31a,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "aebr", 4, {RRE(0xb30a,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "axbr", 4, {RRE(0xb34a,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "bakr", 4, {RRE(0xb240,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
-{ "bsa", 4, {RRE(0xb25a,0,0), 0}, {RRE_MASK, 0}, IBS, {RRE_R1, RRE_R2} },
-{ "bsg", 4, {RRE(0xb258,0,0), 0}, {RRE_MASK, 0}, ISG, {RRE_R1, RRE_R2} },
-{ "cdbr", 4, {RRE(0xb319,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "cdfbr", 4, {RRE(0xb395,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "cdfr", 4, {RRE(0xb3b5,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "cebr", 4, {RRE(0xb309,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "cefbr", 4, {RRE(0xb394,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "cefr", 4, {RRE(0xb3b4,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "cksm", 4, {RRE(0xb241,0,0), 0}, {RRE_MASK, 0}, ICK, {RRE_R1, RRE_R2} },
-{ "clst", 4, {RRE(0xb25d,0,0), 0}, {RRE_MASK, 0}, ISR, {RRE_R1, RRE_R2} },
-{ "cpya", 4, {RRE(0xb24d,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
-{ "cuse", 4, {RRE(0xb257,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
-{ "cxbr", 4, {RRE(0xb349,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "cxfbr", 4, {RRE(0xb396,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "cxfr", 4, {RRE(0xb3b6,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "cxr", 4, {RRE(0xb369,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "ddbr", 4, {RRE(0xb31d,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "debr", 4, {RRE(0xb30d,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "dxbr", 4, {RRE(0xb34d,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "dxr", 4, {RRE(0xb22d,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} },
-{ "ear", 4, {RRE(0xb24f,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
-{ "efpc", 4, {RRE(0xb38c,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "epar", 4, {RRE(0xb226,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1} },
-{ "ereg", 4, {RRE(0xb249,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
-{ "esar", 4, {RRE(0xb227,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1} },
-{ "esta", 4, {RRE(0xb24a,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
-{ "fidr", 4, {RRE(0xb37f,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "fier", 4, {RRE(0xb377,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "fixr", 4, {RRE(0xb367,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "iac", 4, {RRE(0xb224,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1} },
-{ "ipm", 4, {RRE(0xb222,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1} },
-{ "ipte", 4, {RRE(0xb221,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} },
-{ "iske", 4, {RRE(0xb229,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} },
-{ "ivsk", 4, {RRE(0xb223,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} },
-{ "kdbr", 4, {RRE(0xb318,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "kebr", 4, {RRE(0xb308,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "kxbr", 4, {RRE(0xb348,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "lcdbr", 4, {RRE(0xb313,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "lcebr", 4, {RRE(0xb303,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "lcxbr", 4, {RRE(0xb343,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "lcxr", 4, {RRE(0xb363,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "lder", 4, {RRE(0xb324,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "ldxbr", 4, {RRE(0xb345,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "ledbr", 4, {RRE(0xb344,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "lexbr", 4, {RRE(0xb346,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "lexr", 4, {RRE(0xb366,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "lndbr", 4, {RRE(0xb311,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "lnebr", 4, {RRE(0xb301,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "lnxbr", 4, {RRE(0xb341,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "lnxr", 4, {RRE(0xb361,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "lpdbr", 4, {RRE(0xb310,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "lpebr", 4, {RRE(0xb300,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "lpxbr", 4, {RRE(0xb340,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "lpxr", 4, {RRE(0xb360,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "ltdbr", 4, {RRE(0xb312,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "ltebr", 4, {RRE(0xb302,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "ltxbr", 4, {RRE(0xb342,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "ltxr", 4, {RRE(0xb362,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "lura", 4, {RRE(0xb24b,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
-{ "lxdr", 4, {RRE(0xb325,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "lxer", 4, {RRE(0xb326,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "lxr", 4, {RRE(0xb365,0,0), 0}, {RRE_MASK, 0}, IFX, {RRE_R1, RRE_R2} },
-{ "lzdr", 4, {RRE(0xb375,0,0), 0}, {RRE_MASK, 0}, IFX, {RRE_R1, RRE_R2} },
-{ "lzer", 4, {RRE(0xb374,0,0), 0}, {RRE_MASK, 0}, IFX, {RRE_R1, RRE_R2} },
-{ "lzxr", 4, {RRE(0xb376,0,0), 0}, {RRE_MASK, 0}, IFX, {RRE_R1, RRE_R2} },
-{ "mdbr", 4, {RRE(0xb31c,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "mdebr", 4, {RRE(0xb30c,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "meebr", 4, {RRE(0xb317,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "meer", 4, {RRE(0xb337,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "msr", 4, {RRE(0xb252,0,0), 0}, {RRE_MASK, 0}, IIR, {RRE_R1, RRE_R2} },
-{ "msta", 4, {RRE(0xb247,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1} },
-{ "mvpg", 4, {RRE(0xb254,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
-{ "mvst", 4, {RRE(0xb255,0,0), 0}, {RRE_MASK, 0}, ISR, {RRE_R1, RRE_R2} },
-{ "mxbr", 4, {RRE(0xb34c,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "mxdbr", 4, {RRE(0xb307,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "palb", 4, {RRE(0xb248,0,0), 0}, {RRE_MASK, 0}, IESA, {0} },
-{ "prbe", 4, {RRE(0xb22a,0,0), 0}, {RRE_MASK, 0}, I370, {RRE_R1, RRE_R2} },
-{ "pt", 4, {RRE(0xb228,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} },
-{ "rrbe", 4, {RRE(0xb22a,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} },
-{ "sar", 4, {RRE(0xb24e,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
-{ "sdbr", 4, {RRE(0xb31b,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "sebr", 4, {RRE(0xb30b,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "servc", 4, {RRE(0xb220,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
-{ "sfpc", 4, {RRE(0xb384,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "sqdbr", 4, {RRE(0xb315,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "sqdr", 4, {RRE(0xb244,0,0), 0}, {RRE_MASK, 0}, IQR, {RRE_R1, RRE_R2} },
-{ "sqebr", 4, {RRE(0xb314,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "sqer", 4, {RRE(0xb245,0,0), 0}, {RRE_MASK, 0}, IQR, {RRE_R1, RRE_R2} },
-{ "sqxbr", 4, {RRE(0xb316,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "sqxr", 4, {RRE(0xb336,0,0), 0}, {RRE_MASK, 0}, IHX, {RRE_R1, RRE_R2} },
-{ "srst", 4, {RRE(0xb25e,0,0), 0}, {RRE_MASK, 0}, ISR, {RRE_R1, RRE_R2} },
-{ "ssar", 4, {RRE(0xb225,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1} },
-{ "sske", 4, {RRE(0xb22b,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} },
-{ "stura", 4, {RRE(0xb246,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
-{ "sxbr", 4, {RRE(0xb34b,0,0), 0}, {RRE_MASK, 0}, IBF, {RRE_R1, RRE_R2} },
-{ "tar", 4, {RRE(0xb24c,0,0), 0}, {RRE_MASK, 0}, IESA, {RRE_R1, RRE_R2} },
-{ "tb", 4, {RRE(0xb22c,0,0), 0}, {RRE_MASK, 0}, IXA, {RRE_R1, RRE_R2} },
-{ "thdr", 4, {RRE(0xb359,0,0), 0}, {RRE_MASK, 0}, IFX, {RRE_R1, RRE_R2} },
-{ "thder", 4, {RRE(0xb359,0,0), 0}, {RRE_MASK, 0}, IFX, {RRE_R1, RRE_R2} },
+{ "adbr", 4, {{RRE(0xb31a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "aebr", 4, {{RRE(0xb30a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "axbr", 4, {{RRE(0xb34a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "bakr", 4, {{RRE(0xb240,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
+{ "bsa", 4, {{RRE(0xb25a,0,0), 0}}, {{RRE_MASK, 0}}, IBS, {RRE_R1, RRE_R2} },
+{ "bsg", 4, {{RRE(0xb258,0,0), 0}}, {{RRE_MASK, 0}}, ISG, {RRE_R1, RRE_R2} },
+{ "cdbr", 4, {{RRE(0xb319,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "cdfbr", 4, {{RRE(0xb395,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "cdfr", 4, {{RRE(0xb3b5,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "cebr", 4, {{RRE(0xb309,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "cefbr", 4, {{RRE(0xb394,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "cefr", 4, {{RRE(0xb3b4,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "cksm", 4, {{RRE(0xb241,0,0), 0}}, {{RRE_MASK, 0}}, ICK, {RRE_R1, RRE_R2} },
+{ "clst", 4, {{RRE(0xb25d,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} },
+{ "cpya", 4, {{RRE(0xb24d,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
+{ "cuse", 4, {{RRE(0xb257,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
+{ "cxbr", 4, {{RRE(0xb349,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "cxfbr", 4, {{RRE(0xb396,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "cxfr", 4, {{RRE(0xb3b6,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "cxr", 4, {{RRE(0xb369,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "ddbr", 4, {{RRE(0xb31d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "debr", 4, {{RRE(0xb30d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "dxbr", 4, {{RRE(0xb34d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "dxr", 4, {{RRE(0xb22d,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
+{ "ear", 4, {{RRE(0xb24f,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
+{ "efpc", 4, {{RRE(0xb38c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "epar", 4, {{RRE(0xb226,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
+{ "ereg", 4, {{RRE(0xb249,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
+{ "esar", 4, {{RRE(0xb227,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
+{ "esta", 4, {{RRE(0xb24a,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
+{ "fidr", 4, {{RRE(0xb37f,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "fier", 4, {{RRE(0xb377,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "fixr", 4, {{RRE(0xb367,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "iac", 4, {{RRE(0xb224,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
+{ "ipm", 4, {{RRE(0xb222,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
+{ "ipte", 4, {{RRE(0xb221,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
+{ "iske", 4, {{RRE(0xb229,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
+{ "ivsk", 4, {{RRE(0xb223,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
+{ "kdbr", 4, {{RRE(0xb318,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "kebr", 4, {{RRE(0xb308,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "kxbr", 4, {{RRE(0xb348,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "lcdbr", 4, {{RRE(0xb313,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "lcebr", 4, {{RRE(0xb303,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "lcxbr", 4, {{RRE(0xb343,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "lcxr", 4, {{RRE(0xb363,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "lder", 4, {{RRE(0xb324,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "ldxbr", 4, {{RRE(0xb345,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "ledbr", 4, {{RRE(0xb344,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "lexbr", 4, {{RRE(0xb346,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "lexr", 4, {{RRE(0xb366,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "lndbr", 4, {{RRE(0xb311,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "lnebr", 4, {{RRE(0xb301,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "lnxbr", 4, {{RRE(0xb341,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "lnxr", 4, {{RRE(0xb361,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "lpdbr", 4, {{RRE(0xb310,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "lpebr", 4, {{RRE(0xb300,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "lpxbr", 4, {{RRE(0xb340,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "lpxr", 4, {{RRE(0xb360,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "ltdbr", 4, {{RRE(0xb312,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "ltebr", 4, {{RRE(0xb302,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "ltxbr", 4, {{RRE(0xb342,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "ltxr", 4, {{RRE(0xb362,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "lura", 4, {{RRE(0xb24b,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
+{ "lxdr", 4, {{RRE(0xb325,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "lxer", 4, {{RRE(0xb326,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "lxr", 4, {{RRE(0xb365,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
+{ "lzdr", 4, {{RRE(0xb375,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
+{ "lzer", 4, {{RRE(0xb374,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
+{ "lzxr", 4, {{RRE(0xb376,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
+{ "mdbr", 4, {{RRE(0xb31c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "mdebr", 4, {{RRE(0xb30c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "meebr", 4, {{RRE(0xb317,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "meer", 4, {{RRE(0xb337,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "msr", 4, {{RRE(0xb252,0,0), 0}}, {{RRE_MASK, 0}}, IIR, {RRE_R1, RRE_R2} },
+{ "msta", 4, {{RRE(0xb247,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1} },
+{ "mvpg", 4, {{RRE(0xb254,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
+{ "mvst", 4, {{RRE(0xb255,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} },
+{ "mxbr", 4, {{RRE(0xb34c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "mxdbr", 4, {{RRE(0xb307,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "palb", 4, {{RRE(0xb248,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {0} },
+{ "prbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, I370, {RRE_R1, RRE_R2} },
+{ "pt", 4, {{RRE(0xb228,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
+{ "rrbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
+{ "sar", 4, {{RRE(0xb24e,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
+{ "sdbr", 4, {{RRE(0xb31b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "sebr", 4, {{RRE(0xb30b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "servc", 4, {{RRE(0xb220,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
+{ "sfpc", 4, {{RRE(0xb384,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "sqdbr", 4, {{RRE(0xb315,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "sqdr", 4, {{RRE(0xb244,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} },
+{ "sqebr", 4, {{RRE(0xb314,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "sqer", 4, {{RRE(0xb245,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} },
+{ "sqxbr", 4, {{RRE(0xb316,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "sqxr", 4, {{RRE(0xb336,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
+{ "srst", 4, {{RRE(0xb25e,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} },
+{ "ssar", 4, {{RRE(0xb225,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
+{ "sske", 4, {{RRE(0xb22b,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
+{ "stura", 4, {{RRE(0xb246,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
+{ "sxbr", 4, {{RRE(0xb34b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
+{ "tar", 4, {{RRE(0xb24c,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
+{ "tb", 4, {{RRE(0xb22c,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
+{ "thdr", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
+{ "thder", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
/* RRF form instructions */
-{ "cfdbr", 4, {RRF(0xb399,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
-{ "cfdr", 4, {RRF(0xb3b9,0,0,0), 0}, {RRF_MASK, 0}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
-{ "cfebr", 4, {RRF(0xb398,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
-{ "cfer", 4, {RRF(0xb3b8,0,0,0), 0}, {RRF_MASK, 0}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
-{ "cfxbr", 4, {RRF(0xb39a,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
-{ "cfxr", 4, {RRF(0xb3ba,0,0,0), 0}, {RRF_MASK, 0}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
-{ "didbr", 4, {RRF(0xb35b,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
-{ "diebr", 4, {RRF(0xb353,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
-{ "fidbr", 4, {RRF(0xb35f,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
-{ "fiebr", 4, {RRF(0xb357,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
-{ "fixbr", 4, {RRF(0xb347,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
-{ "madbr", 4, {RRF(0xb31e,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
-{ "maebr", 4, {RRF(0xb30e,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
-{ "msdbr", 4, {RRF(0xb31f,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
-{ "msebr", 4, {RRF(0xb30f,0,0,0), 0}, {RRF_MASK, 0}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
-{ "tbdr", 4, {RRF(0xb351,0,0,0), 0}, {RRF_MASK, 0}, IFX, {RRF_R1, RRF_R3, RRF_R2} },
-{ "tbedr", 4, {RRF(0xb350,0,0,0), 0}, {RRF_MASK, 0}, IFX, {RRF_R1, RRF_R3, RRF_R2} },
+{ "cfdbr", 4, {{RRF(0xb399,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
+{ "cfdr", 4, {{RRF(0xb3b9,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
+{ "cfebr", 4, {{RRF(0xb398,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
+{ "cfer", 4, {{RRF(0xb3b8,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
+{ "cfxbr", 4, {{RRF(0xb39a,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
+{ "cfxr", 4, {{RRF(0xb3ba,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
+{ "didbr", 4, {{RRF(0xb35b,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
+{ "diebr", 4, {{RRF(0xb353,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
+{ "fidbr", 4, {{RRF(0xb35f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
+{ "fiebr", 4, {{RRF(0xb357,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
+{ "fixbr", 4, {{RRF(0xb347,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
+{ "madbr", 4, {{RRF(0xb31e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
+{ "maebr", 4, {{RRF(0xb30e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
+{ "msdbr", 4, {{RRF(0xb31f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
+{ "msebr", 4, {{RRF(0xb30f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
+{ "tbdr", 4, {{RRF(0xb351,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} },
+{ "tbedr", 4, {{RRF(0xb350,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} },
/* RX form instructions */
-{ "a", 4, {RX(0x5a,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "ad", 4, {RX(0x6a,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "ae", 4, {RX(0x7a,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "ah", 4, {RX(0x4a,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "al", 4, {RX(0x5e,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "au", 4, {RX(0x7e,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "aw", 4, {RX(0x6e,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "bal", 4, {RX(0x45,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "bas", 4, {RX(0x4d,0,0,0,0), 0}, {RX_MASK, 0}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "bc", 4, {RX(0x47,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "bct", 4, {RX(0x46,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "c", 4, {RX(0x59,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "cd", 4, {RX(0x69,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "ce", 4, {RX(0x79,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "ch", 4, {RX(0x49,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "cl", 4, {RX(0x55,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "cvb", 4, {RX(0x4f,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "cvd", 4, {RX(0x4e,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "d", 4, {RX(0x5d,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "dd", 4, {RX(0x6d,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "de", 4, {RX(0x7d,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "ex", 4, {RX(0x44,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "ic", 4, {RX(0x43,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "l", 4, {RX(0x58,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "la", 4, {RX(0x41,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "lae", 4, {RX(0x51,0,0,0,0), 0}, {RX_MASK, 0}, IESA, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "ld", 4, {RX(0x68,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "le", 4, {RX(0x78,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "lh", 4, {RX(0x48,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "lra", 4, {RX(0xb1,0,0,0,0), 0}, {RX_MASK, 0}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "m", 4, {RX(0x5c,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "md", 4, {RX(0x6c,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "me", 4, {RX(0x7c,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "mh", 4, {RX(0x4c,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "ms", 4, {RX(0x71,0,0,0,0), 0}, {RX_MASK, 0}, IIR, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "mxd", 4, {RX(0x67,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "n", 4, {RX(0x54,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "o", 4, {RX(0x56,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "s", 4, {RX(0x5b,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "sd", 4, {RX(0x6b,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "se", 4, {RX(0x7b,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "sh", 4, {RX(0x4b,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "sl", 4, {RX(0x5f,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "st", 4, {RX(0x50,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "stc", 4, {RX(0x42,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "std", 4, {RX(0x60,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "ste", 4, {RX(0x70,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "sth", 4, {RX(0x40,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "su", 4, {RX(0x7f,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "sw", 4, {RX(0x6f,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "x", 4, {RX(0x57,0,0,0,0), 0}, {RX_MASK, 0}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "a", 4, {{RX(0x5a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "ad", 4, {{RX(0x6a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "ae", 4, {{RX(0x7a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "ah", 4, {{RX(0x4a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "al", 4, {{RX(0x5e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "au", 4, {{RX(0x7e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "aw", 4, {{RX(0x6e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "bal", 4, {{RX(0x45,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "bas", 4, {{RX(0x4d,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "bc", 4, {{RX(0x47,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "bct", 4, {{RX(0x46,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "c", 4, {{RX(0x59,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "cd", 4, {{RX(0x69,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "ce", 4, {{RX(0x79,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "ch", 4, {{RX(0x49,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "cl", 4, {{RX(0x55,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "cvb", 4, {{RX(0x4f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "cvd", 4, {{RX(0x4e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "d", 4, {{RX(0x5d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "dd", 4, {{RX(0x6d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "de", 4, {{RX(0x7d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "ex", 4, {{RX(0x44,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "ic", 4, {{RX(0x43,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "l", 4, {{RX(0x58,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "la", 4, {{RX(0x41,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "lae", 4, {{RX(0x51,0,0,0,0), 0}}, {{RX_MASK, 0}}, IESA, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "ld", 4, {{RX(0x68,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "le", 4, {{RX(0x78,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "lh", 4, {{RX(0x48,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "lra", 4, {{RX(0xb1,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "m", 4, {{RX(0x5c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "md", 4, {{RX(0x6c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "me", 4, {{RX(0x7c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "mh", 4, {{RX(0x4c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "ms", 4, {{RX(0x71,0,0,0,0), 0}}, {{RX_MASK, 0}}, IIR, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "mxd", 4, {{RX(0x67,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "n", 4, {{RX(0x54,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "o", 4, {{RX(0x56,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "s", 4, {{RX(0x5b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "sd", 4, {{RX(0x6b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "se", 4, {{RX(0x7b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "sh", 4, {{RX(0x4b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "sl", 4, {{RX(0x5f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "st", 4, {{RX(0x50,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "stc", 4, {{RX(0x42,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "std", 4, {{RX(0x60,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "ste", 4, {{RX(0x70,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "sth", 4, {{RX(0x40,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "su", 4, {{RX(0x7f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "sw", 4, {{RX(0x6f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "x", 4, {{RX(0x57,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
/* RXE form instructions */
-{ "adb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x1a)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "aeb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x0a)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "cdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x19)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "ceb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x09)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "ddb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x1d)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "deb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x0d)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "kdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x18)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "keb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x08)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "lde", 6, {RXEH(0xed,0,0,0,0), RXEL(0x24)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "ldeb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x04)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "lxd", 6, {RXEH(0xed,0,0,0,0), RXEL(0x25)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "lxdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x05)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "lxe", 6, {RXEH(0xed,0,0,0,0), RXEL(0x26)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "lxeb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x06)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "mdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x1c)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "mdeb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x0c)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "mee", 6, {RXEH(0xed,0,0,0,0), RXEL(0x37)}, {RXEH_MASK, RXEL_MASK}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "meeb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x17)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "mxdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x07)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "sqd", 6, {RXEH(0xed,0,0,0,0), RXEL(0x35)}, {RXEH_MASK, RXEL_MASK}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "sqdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x15)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "sqe", 6, {RXEH(0xed,0,0,0,0), RXEL(0x34)}, {RXEH_MASK, RXEL_MASK}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "sqeb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x14)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "sdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x1b)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "seb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x0b)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "tcdb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x11)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "tceb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x10)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
-{ "tcxb", 6, {RXEH(0xed,0,0,0,0), RXEL(0x12)}, {RXEH_MASK, RXEL_MASK}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "adb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "aeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "cdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x19)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "ceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x09)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "ddb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "deb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "kdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x18)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "keb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x08)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "lde", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x24)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "ldeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x04)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "lxd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x25)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "lxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x05)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "lxe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x26)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "lxeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x06)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "mdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "mdeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "mee", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x37)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "meeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x17)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "mxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x07)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "sqd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x35)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "sqdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x15)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "sqe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x34)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "sqeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x14)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "sdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "seb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "tcdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x11)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "tceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x10)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
+{ "tcxb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x12)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
/* RXF form instructions */
-{ "madb", 6, {RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}, {RXFH_MASK, RXFL_MASK}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
-{ "maeb", 6, {RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}, {RXFH_MASK, RXFL_MASK}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
-{ "msdb", 6, {RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}, {RXFH_MASK, RXFL_MASK}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
-{ "mseb", 6, {RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}, {RXFH_MASK, RXFL_MASK}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
+{ "madb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
+{ "maeb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
+{ "msdb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
+{ "mseb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
/* RS form instructions */
-{ "bxh", 4, {RS(0x86,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "bxle", 4, {RS(0x87,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "cds", 4, {RS(0xbb,0,0,0,0), 0}, {RS_MASK, 0}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "clcle", 4, {RS(0xa9,0,0,0,0), 0}, {RS_MASK, 0}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "clm", 4, {RS(0xbd,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "cs", 4, {RS(0xba,0,0,0,0), 0}, {RS_MASK, 0}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "icm", 4, {RS(0xbf,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "lam", 4, {RS(0x9a,0,0,0,0), 0}, {RS_MASK, 0}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "lctl", 4, {RS(0xb7,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "lm", 4, {RS(0x98,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "mvcle", 4, {RS(0xa8,0,0,0,0), 0}, {RS_MASK, 0}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "sigp", 4, {RS(0xae,0,0,0,0), 0}, {RS_MASK, 0}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "stam", 4, {RS(0x9b,0,0,0,0), 0}, {RS_MASK, 0}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "stcm", 4, {RS(0xbe,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "stctl", 4, {RS(0xb6,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "stm", 4, {RS(0x90,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
-{ "trace", 4, {RS(0x99,0,0,0,0), 0}, {RS_MASK, 0}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "bxh", 4, {{RS(0x86,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "bxle", 4, {{RS(0x87,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "cds", 4, {{RS(0xbb,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "clcle", 4, {{RS(0xa9,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "clm", 4, {{RS(0xbd,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "cs", 4, {{RS(0xba,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "icm", 4, {{RS(0xbf,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "lam", 4, {{RS(0x9a,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "lctl", 4, {{RS(0xb7,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "lm", 4, {{RS(0x98,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "mvcle", 4, {{RS(0xa8,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "sigp", 4, {{RS(0xae,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "stam", 4, {{RS(0x9b,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "stcm", 4, {{RS(0xbe,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "stctl", 4, {{RS(0xb6,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "stm", 4, {{RS(0x90,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
+{ "trace", 4, {{RS(0x99,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
/* RS form instructions with blank R3 and optional B2 (shift left/right) */
-{ "sla", 4, {RS(0x8b,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
-{ "slda", 4, {RS(0x8f,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
-{ "sldl", 4, {RS(0x8d,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
-{ "sll", 4, {RS(0x89,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
-{ "sra", 4, {RS(0x8a,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
-{ "srda", 4, {RS(0x8e,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
-{ "srdl", 4, {RS(0x8c,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
-{ "srl", 4, {RS(0x88,0,0,0,0), 0}, {RS_MASK, 0}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
+{ "sla", 4, {{RS(0x8b,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
+{ "slda", 4, {{RS(0x8f,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
+{ "sldl", 4, {{RS(0x8d,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
+{ "sll", 4, {{RS(0x89,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
+{ "sra", 4, {{RS(0x8a,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
+{ "srda", 4, {{RS(0x8e,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
+{ "srdl", 4, {{RS(0x8c,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
+{ "srl", 4, {{RS(0x88,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
/* RSI form instructions */
-{ "brxh", 4, {RSI(0x84,0,0,0), 0}, {RSI_MASK, 0}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
-{ "brxle", 4, {RSI(0x85,0,0,0), 0}, {RSI_MASK, 0}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
+{ "brxh", 4, {{RSI(0x84,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
+{ "brxle", 4, {{RSI(0x85,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
/* RI form instructions */
-{ "ahi", 4, {RI(0xa7a,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} },
-{ "bras", 4, {RI(0xa75,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} },
-{ "brc", 4, {RI(0xa74,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} },
-{ "brct", 4, {RI(0xa76,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} },
-{ "chi", 4, {RI(0xa7e,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} },
-{ "lhi", 4, {RI(0xa78,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} },
-{ "mhi", 4, {RI(0xa7c,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} },
-{ "tmh", 4, {RI(0xa70,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} },
-{ "tml", 4, {RI(0xa71,0,0), 0}, {RI_MASK, 0}, IIR, {RI_R1, RI_I2} },
+{ "ahi", 4, {{RI(0xa7a,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
+{ "bras", 4, {{RI(0xa75,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
+{ "brc", 4, {{RI(0xa74,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
+{ "brct", 4, {{RI(0xa76,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
+{ "chi", 4, {{RI(0xa7e,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
+{ "lhi", 4, {{RI(0xa78,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
+{ "mhi", 4, {{RI(0xa7c,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
+{ "tmh", 4, {{RI(0xa70,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
+{ "tml", 4, {{RI(0xa71,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
/* SI form instructions */
-{ "cli", 4, {SI(0x95,0,0,0), 0}, {SI_MASK, 0}, I370, {SI_D1, SI_B1, SI_I2} },
-{ "mc", 4, {SI(0xaf,0,0,0), 0}, {SI_MASK, 0}, I370, {SI_D1, SI_B1, SI_I2} },
-{ "mvi", 4, {SI(0x92,0,0,0), 0}, {SI_MASK, 0}, I370, {SI_D1, SI_B1, SI_I2} },
-{ "ni", 4, {SI(0x94,0,0,0), 0}, {SI_MASK, 0}, I370, {SI_D1, SI_B1, SI_I2} },
-{ "oi", 4, {SI(0x96,0,0,0), 0}, {SI_MASK, 0}, I370, {SI_D1, SI_B1, SI_I2} },
-{ "stnsm", 4, {SI(0xac,0,0,0), 0}, {SI_MASK, 0}, IXA, {SI_D1, SI_B1, SI_I2} },
-{ "stosm", 4, {SI(0xad,0,0,0), 0}, {SI_MASK, 0}, IXA, {SI_D1, SI_B1, SI_I2} },
-{ "tm", 4, {SI(0x91,0,0,0), 0}, {SI_MASK, 0}, I370, {SI_D1, SI_B1, SI_I2} },
-{ "xi", 4, {SI(0x97,0,0,0), 0}, {SI_MASK, 0}, I370, {SI_D1, SI_B1, SI_I2} },
+{ "cli", 4, {{SI(0x95,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
+{ "mc", 4, {{SI(0xaf,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
+{ "mvi", 4, {{SI(0x92,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
+{ "ni", 4, {{SI(0x94,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
+{ "oi", 4, {{SI(0x96,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
+{ "stnsm", 4, {{SI(0xac,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} },
+{ "stosm", 4, {{SI(0xad,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} },
+{ "tm", 4, {{SI(0x91,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
+{ "xi", 4, {{SI(0x97,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
/* S form instructions */
-{ "cfc", 4, {S(0xb21a,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "csch", 4, {S(0xb230,0,0), 0}, {S_MASK, 0}, IXA, {0} },
-{ "hsch", 4, {S(0xb231,0,0), 0}, {S_MASK, 0}, IXA, {0} },
-{ "ipk", 4, {S(0xb20b,0,0), 0}, {S_MASK, 0}, IXA, {0} },
-{ "lfpc", 4, {S(0xb29d,0,0), 0}, {S_MASK, 0}, IBF, {S_D2, S_B2} },
-{ "lpsw", 4, {S(0x8200,0,0), 0}, {S_MASK, 0}, I370, {S_D2, S_B2} },
-{ "msch", 4, {S(0xb232,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "pc", 4, {S(0xb218,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "pcf", 4, {S(0xb218,0,0), 0}, {S_MASK, 0}, IPC, {S_D2, S_B2} },
-{ "ptlb", 4, {S(0xb20d,0,0), 0}, {S_MASK, 0}, IXA, {0} },
-{ "rchp", 4, {S(0xb23b,0,0), 0}, {S_MASK, 0}, IXA, {0} },
-{ "rp", 4, {S(0xb277,0,0), 0}, {S_MASK, 0}, IRP, {0} },
-{ "rsch", 4, {S(0xb238,0,0), 0}, {S_MASK, 0}, IXA, {0} },
-{ "sac", 4, {S(0xb219,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "sacf", 4, {S(0xb279,0,0), 0}, {S_MASK, 0}, ISA, {S_D2, S_B2} },
-{ "sal", 4, {S(0xb237,0,0), 0}, {S_MASK, 0}, IXA, {0} },
-{ "schm", 4, {S(0xb23c,0,0), 0}, {S_MASK, 0}, IXA, {0} },
-{ "sck", 4, {S(0xb204,0,0), 0}, {S_MASK, 0}, I370, {S_D2, S_B2} },
-{ "sckc", 4, {S(0xb206,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "spka", 4, {S(0xb20a,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "spt", 4, {S(0xb208,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "spx", 4, {S(0xb210,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "srnm", 4, {S(0xb299,0,0), 0}, {S_MASK, 0}, IBF, {S_D2, S_B2} },
-{ "ssch", 4, {S(0xb233,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "ssm", 4, {S(0x8000,0,0), 0}, {S_MASK, 0}, I370, {S_D2, S_B2} },
-{ "stap", 4, {S(0xb212,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "stck", 4, {S(0xb205,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "stckc", 4, {S(0xb207,0,0), 0}, {S_MASK, 0}, I370, {S_D2, S_B2} },
-{ "stcps", 4, {S(0xb23a,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "stcrw", 4, {S(0xb239,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "stfpc", 4, {S(0xb29c,0,0), 0}, {S_MASK, 0}, IBF, {S_D2, S_B2} },
-{ "stidp", 4, {S(0xb202,0,0), 0}, {S_MASK, 0}, I370, {S_D2, S_B2} },
-{ "stpt", 4, {S(0xb209,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "stpx", 4, {S(0xb211,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "stsch", 4, {S(0xb234,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "tpi", 4, {S(0xb236,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
-{ "trap4", 4, {S(0xb2ff,0,0), 0}, {S_MASK, 0}, ITR, {S_D2, S_B2} },
-{ "ts", 4, {S(0x9300,0,0), 0}, {S_MASK, 0}, I370, {S_D2, S_B2} },
-{ "tsch", 4, {S(0xb235,0,0), 0}, {S_MASK, 0}, IXA, {S_D2, S_B2} },
+{ "cfc", 4, {{S(0xb21a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "csch", 4, {{S(0xb230,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
+{ "hsch", 4, {{S(0xb231,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
+{ "ipk", 4, {{S(0xb20b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
+{ "lfpc", 4, {{S(0xb29d,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} },
+{ "lpsw", 4, {{S(0x8200,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
+{ "msch", 4, {{S(0xb232,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "pc", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "pcf", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IPC, {S_D2, S_B2} },
+{ "ptlb", 4, {{S(0xb20d,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
+{ "rchp", 4, {{S(0xb23b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
+{ "rp", 4, {{S(0xb277,0,0), 0}}, {{S_MASK, 0}}, IRP, {0} },
+{ "rsch", 4, {{S(0xb238,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
+{ "sac", 4, {{S(0xb219,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "sacf", 4, {{S(0xb279,0,0), 0}}, {{S_MASK, 0}}, ISA, {S_D2, S_B2} },
+{ "sal", 4, {{S(0xb237,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
+{ "schm", 4, {{S(0xb23c,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
+{ "sck", 4, {{S(0xb204,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
+{ "sckc", 4, {{S(0xb206,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "spka", 4, {{S(0xb20a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "spt", 4, {{S(0xb208,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "spx", 4, {{S(0xb210,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "srnm", 4, {{S(0xb299,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} },
+{ "ssch", 4, {{S(0xb233,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "ssm", 4, {{S(0x8000,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
+{ "stap", 4, {{S(0xb212,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "stck", 4, {{S(0xb205,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "stckc", 4, {{S(0xb207,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
+{ "stcps", 4, {{S(0xb23a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "stcrw", 4, {{S(0xb239,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "stfpc", 4, {{S(0xb29c,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} },
+{ "stidp", 4, {{S(0xb202,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
+{ "stpt", 4, {{S(0xb209,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "stpx", 4, {{S(0xb211,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "stsch", 4, {{S(0xb234,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "tpi", 4, {{S(0xb236,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
+{ "trap4", 4, {{S(0xb2ff,0,0), 0}}, {{S_MASK, 0}}, ITR, {S_D2, S_B2} },
+{ "ts", 4, {{S(0x9300,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
+{ "tsch", 4, {{S(0xb235,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
/* SS form instructions */
-{ "ap", 6, {SSH(0xfa,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "clc", 6, {SSH(0xd5,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "cp", 6, {SSH(0xf9,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "dp", 6, {SSH(0xfd,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "ed", 6, {SSH(0xde,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "edmk", 6, {SSH(0xdf,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "mvc", 6, {SSH(0xd2,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "mvcin", 6, {SSH(0xe8,0,0,0), 0}, {SS_MASK, 0}, IMI, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "mvck", 6, {SSH(0xd9,0,0,0), 0}, {SS_MASK, 0}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "mvcp", 6, {SSH(0xda,0,0,0), 0}, {SS_MASK, 0}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "mvcs", 6, {SSH(0xdb,0,0,0), 0}, {SS_MASK, 0}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "mvn", 6, {SSH(0xd1,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "mvo", 6, {SSH(0xf1,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "mvz", 6, {SSH(0xd3,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "nc", 6, {SSH(0xd4,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "oc", 6, {SSH(0xd6,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "pack", 6, {SSH(0xf2,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "plo", 6, {SSH(0xee,0,0,0), 0}, {SS_MASK, 0}, IPL, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "sp", 6, {SSH(0xfb,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "srp", 6, {SSH(0xf0,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "tr", 6, {SSH(0xdc,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "trt", 6, {SSH(0xdd,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "unpk", 6, {SSH(0xf3,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "xc", 6, {SSH(0xd7,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
-{ "zap", 6, {SSH(0xf8,0,0,0), 0}, {SS_MASK, 0}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "ap", 6, {{SSH(0xfa,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "clc", 6, {{SSH(0xd5,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "cp", 6, {{SSH(0xf9,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "dp", 6, {{SSH(0xfd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "ed", 6, {{SSH(0xde,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "edmk", 6, {{SSH(0xdf,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "mvc", 6, {{SSH(0xd2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "mvcin", 6, {{SSH(0xe8,0,0,0), 0}}, {{SS_MASK, 0}}, IMI, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "mvck", 6, {{SSH(0xd9,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "mvcp", 6, {{SSH(0xda,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "mvcs", 6, {{SSH(0xdb,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "mvn", 6, {{SSH(0xd1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "mvo", 6, {{SSH(0xf1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "mvz", 6, {{SSH(0xd3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "nc", 6, {{SSH(0xd4,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "oc", 6, {{SSH(0xd6,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "pack", 6, {{SSH(0xf2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "plo", 6, {{SSH(0xee,0,0,0), 0}}, {{SS_MASK, 0}}, IPL, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "sp", 6, {{SSH(0xfb,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "srp", 6, {{SSH(0xf0,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "tr", 6, {{SSH(0xdc,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "trt", 6, {{SSH(0xdd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "unpk", 6, {{SSH(0xf3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "xc", 6, {{SSH(0xd7,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
+{ "zap", 6, {{SSH(0xf8,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
/* SSE form instructions */
-{ "lasp", 6, {SSEH(0xe500,0,0), 0}, {SSE_MASK, 0}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} },
-{ "mvcdk", 6, {SSEH(0xe50f,0,0), 0}, {SSE_MASK, 0}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
-{ "mvcsk", 6, {SSEH(0xe50e,0,0), 0}, {SSE_MASK, 0}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
-{ "tprot", 6, {SSEH(0xe501,0,0), 0}, {SSE_MASK, 0}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} },
+{ "lasp", 6, {{SSEH(0xe500,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} },
+{ "mvcdk", 6, {{SSEH(0xe50f,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
+{ "mvcsk", 6, {{SSEH(0xe50e,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
+{ "tprot", 6, {{SSEH(0xe501,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} },
/* */
};
diff --git a/opcodes/i960-dis.c b/opcodes/i960-dis.c
index b2a8378..9210d02 100644
--- a/opcodes/i960-dis.c
+++ b/opcodes/i960-dis.c
@@ -36,7 +36,7 @@ static void ctrl PARAMS ((bfd_vma, unsigned long, unsigned long));
static void cobr PARAMS ((bfd_vma, unsigned long, unsigned long));
static void reg PARAMS ((unsigned long));
static int mem PARAMS ((bfd_vma, unsigned long, unsigned long, int));
-static void ea PARAMS ((bfd_vma, int, char *, char *, int, unsigned int));
+static void ea PARAMS ((bfd_vma, int, const char *, const char *, int, unsigned int));
static void dstop PARAMS ((int, int, int));
static void regop PARAMS ((int, int, int, int));
static void invalid PARAMS ((int));
@@ -118,802 +118,839 @@ struct sparse_tabent {
};
static int
-pinsn( memaddr, word1, word2 )
- bfd_vma memaddr;
- unsigned long word1, word2;
+pinsn (memaddr, word1, word2)
+ bfd_vma memaddr;
+ unsigned long word1, word2;
{
- int instr_len;
-
- instr_len = 4;
- put_abs( word1, word2 );
-
- /* Divide instruction set into classes based on high 4 bits of opcode*/
- switch ( (word1 >> 28) & 0xf ){
- case 0x0:
- case 0x1:
- ctrl( memaddr, word1, word2 );
- break;
- case 0x2:
- case 0x3:
- cobr( memaddr, word1, word2 );
- break;
- case 0x5:
- case 0x6:
- case 0x7:
- reg( word1 );
- break;
- case 0x8:
- case 0x9:
- case 0xa:
- case 0xb:
- case 0xc:
- instr_len = mem( memaddr, word1, word2, 0 );
- break;
- default:
- /* invalid instruction, print as data word */
- invalid( word1 );
- break;
- }
- return instr_len;
+ int instr_len;
+
+ instr_len = 4;
+ put_abs (word1, word2);
+
+ /* Divide instruction set into classes based on high 4 bits of opcode. */
+ switch ((word1 >> 28) & 0xf)
+ {
+ case 0x0:
+ case 0x1:
+ ctrl (memaddr, word1, word2);
+ break;
+ case 0x2:
+ case 0x3:
+ cobr (memaddr, word1, word2);
+ break;
+ case 0x5:
+ case 0x6:
+ case 0x7:
+ reg (word1);
+ break;
+ case 0x8:
+ case 0x9:
+ case 0xa:
+ case 0xb:
+ case 0xc:
+ instr_len = mem (memaddr, word1, word2, 0);
+ break;
+ default:
+ /* Invalid instruction, print as data word. */
+ invalid (word1);
+ break;
+ }
+ return instr_len;
}
-/****************************************/
-/* CTRL format */
-/****************************************/
+/* CTRL format.. */
+
static void
-ctrl( memaddr, word1, word2 )
- bfd_vma memaddr;
- unsigned long word1;
- unsigned long word2 ATTRIBUTE_UNUSED;
+ctrl (memaddr, word1, word2)
+ bfd_vma memaddr;
+ unsigned long word1;
+ unsigned long word2 ATTRIBUTE_UNUSED;
{
- int i;
- static const struct tabent ctrl_tab[] = {
- { NULL, 0, }, /* 0x00 */
- { NULL, 0, }, /* 0x01 */
- { NULL, 0, }, /* 0x02 */
- { NULL, 0, }, /* 0x03 */
- { NULL, 0, }, /* 0x04 */
- { NULL, 0, }, /* 0x05 */
- { NULL, 0, }, /* 0x06 */
- { NULL, 0, }, /* 0x07 */
- { "b", 1, }, /* 0x08 */
- { "call", 1, }, /* 0x09 */
- { "ret", 0, }, /* 0x0a */
- { "bal", 1, }, /* 0x0b */
- { NULL, 0, }, /* 0x0c */
- { NULL, 0, }, /* 0x0d */
- { NULL, 0, }, /* 0x0e */
- { NULL, 0, }, /* 0x0f */
- { "bno", 1, }, /* 0x10 */
- { "bg", 1, }, /* 0x11 */
- { "be", 1, }, /* 0x12 */
- { "bge", 1, }, /* 0x13 */
- { "bl", 1, }, /* 0x14 */
- { "bne", 1, }, /* 0x15 */
- { "ble", 1, }, /* 0x16 */
- { "bo", 1, }, /* 0x17 */
- { "faultno", 0, }, /* 0x18 */
- { "faultg", 0, }, /* 0x19 */
- { "faulte", 0, }, /* 0x1a */
- { "faultge", 0, }, /* 0x1b */
- { "faultl", 0, }, /* 0x1c */
- { "faultne", 0, }, /* 0x1d */
- { "faultle", 0, }, /* 0x1e */
- { "faulto", 0, }, /* 0x1f */
- };
-
- i = (word1 >> 24) & 0xff;
- if ( (ctrl_tab[i].name == NULL) || ((word1 & 1) != 0) ){
- invalid( word1 );
- return;
- }
+ int i;
+ static const struct tabent ctrl_tab[] = {
+ { NULL, 0, }, /* 0x00 */
+ { NULL, 0, }, /* 0x01 */
+ { NULL, 0, }, /* 0x02 */
+ { NULL, 0, }, /* 0x03 */
+ { NULL, 0, }, /* 0x04 */
+ { NULL, 0, }, /* 0x05 */
+ { NULL, 0, }, /* 0x06 */
+ { NULL, 0, }, /* 0x07 */
+ { "b", 1, }, /* 0x08 */
+ { "call", 1, }, /* 0x09 */
+ { "ret", 0, }, /* 0x0a */
+ { "bal", 1, }, /* 0x0b */
+ { NULL, 0, }, /* 0x0c */
+ { NULL, 0, }, /* 0x0d */
+ { NULL, 0, }, /* 0x0e */
+ { NULL, 0, }, /* 0x0f */
+ { "bno", 1, }, /* 0x10 */
+ { "bg", 1, }, /* 0x11 */
+ { "be", 1, }, /* 0x12 */
+ { "bge", 1, }, /* 0x13 */
+ { "bl", 1, }, /* 0x14 */
+ { "bne", 1, }, /* 0x15 */
+ { "ble", 1, }, /* 0x16 */
+ { "bo", 1, }, /* 0x17 */
+ { "faultno", 0, }, /* 0x18 */
+ { "faultg", 0, }, /* 0x19 */
+ { "faulte", 0, }, /* 0x1a */
+ { "faultge", 0, }, /* 0x1b */
+ { "faultl", 0, }, /* 0x1c */
+ { "faultne", 0, }, /* 0x1d */
+ { "faultle", 0, }, /* 0x1e */
+ { "faulto", 0, }, /* 0x1f */
+ };
+
+ i = (word1 >> 24) & 0xff;
+ if ((ctrl_tab[i].name == NULL) || ((word1 & 1) != 0))
+ {
+ invalid (word1);
+ return;
+ }
- (*info->fprintf_func) ( stream, ctrl_tab[i].name );
- if ( word1 & 2 ){ /* Predicts branch not taken */
- (*info->fprintf_func) ( stream, ".f" );
- }
+ (*info->fprintf_func) (stream, ctrl_tab[i].name);
+ if (word1 & 2)
+ /* Predicts branch not taken. */
+ (*info->fprintf_func) (stream, ".f");
- if ( ctrl_tab[i].numops == 1 ){
- /* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */
- word1 &= 0x00ffffff;
- if ( word1 & 0x00800000 ){ /* Sign bit is set */
- word1 |= (-1 & ~0xffffff); /* Sign extend */
- }
- (*info->fprintf_func)( stream, "\t" );
- print_addr( word1 + memaddr );
+ if (ctrl_tab[i].numops == 1)
+ {
+ /* Extract displacement and convert to address. */
+ word1 &= 0x00ffffff;
+
+ if (word1 & 0x00800000)
+ {
+ /* Sign bit is set. */
+ word1 |= (-1 & ~0xffffff); /* Sign extend. */
}
+
+ (*info->fprintf_func) (stream, "\t");
+ print_addr (word1 + memaddr);
+ }
}
-/****************************************/
-/* COBR format */
-/****************************************/
+/* COBR format. */
+
static void
-cobr( memaddr, word1, word2 )
- bfd_vma memaddr;
- unsigned long word1;
- unsigned long word2 ATTRIBUTE_UNUSED;
+cobr (memaddr, word1, word2)
+ bfd_vma memaddr;
+ unsigned long word1;
+ unsigned long word2 ATTRIBUTE_UNUSED;
{
- int src1;
- int src2;
- int i;
-
- static const struct tabent cobr_tab[] = {
- { "testno", 1, }, /* 0x20 */
- { "testg", 1, }, /* 0x21 */
- { "teste", 1, }, /* 0x22 */
- { "testge", 1, }, /* 0x23 */
- { "testl", 1, }, /* 0x24 */
- { "testne", 1, }, /* 0x25 */
- { "testle", 1, }, /* 0x26 */
- { "testo", 1, }, /* 0x27 */
- { NULL, 0, }, /* 0x28 */
- { NULL, 0, }, /* 0x29 */
- { NULL, 0, }, /* 0x2a */
- { NULL, 0, }, /* 0x2b */
- { NULL, 0, }, /* 0x2c */
- { NULL, 0, }, /* 0x2d */
- { NULL, 0, }, /* 0x2e */
- { NULL, 0, }, /* 0x2f */
- { "bbc", 3, }, /* 0x30 */
- { "cmpobg", 3, }, /* 0x31 */
- { "cmpobe", 3, }, /* 0x32 */
- { "cmpobge", 3, }, /* 0x33 */
- { "cmpobl", 3, }, /* 0x34 */
- { "cmpobne", 3, }, /* 0x35 */
- { "cmpoble", 3, }, /* 0x36 */
- { "bbs", 3, }, /* 0x37 */
- { "cmpibno", 3, }, /* 0x38 */
- { "cmpibg", 3, }, /* 0x39 */
- { "cmpibe", 3, }, /* 0x3a */
- { "cmpibge", 3, }, /* 0x3b */
- { "cmpibl", 3, }, /* 0x3c */
- { "cmpibne", 3, }, /* 0x3d */
- { "cmpible", 3, }, /* 0x3e */
- { "cmpibo", 3, }, /* 0x3f */
- };
-
- i = ((word1 >> 24) & 0xff) - 0x20;
- if ( cobr_tab[i].name == NULL ){
- invalid( word1 );
- return;
- }
+ int src1;
+ int src2;
+ int i;
+
+ static const struct tabent cobr_tab[] = {
+ { "testno", 1, }, /* 0x20 */
+ { "testg", 1, }, /* 0x21 */
+ { "teste", 1, }, /* 0x22 */
+ { "testge", 1, }, /* 0x23 */
+ { "testl", 1, }, /* 0x24 */
+ { "testne", 1, }, /* 0x25 */
+ { "testle", 1, }, /* 0x26 */
+ { "testo", 1, }, /* 0x27 */
+ { NULL, 0, }, /* 0x28 */
+ { NULL, 0, }, /* 0x29 */
+ { NULL, 0, }, /* 0x2a */
+ { NULL, 0, }, /* 0x2b */
+ { NULL, 0, }, /* 0x2c */
+ { NULL, 0, }, /* 0x2d */
+ { NULL, 0, }, /* 0x2e */
+ { NULL, 0, }, /* 0x2f */
+ { "bbc", 3, }, /* 0x30 */
+ { "cmpobg", 3, }, /* 0x31 */
+ { "cmpobe", 3, }, /* 0x32 */
+ { "cmpobge",3, }, /* 0x33 */
+ { "cmpobl", 3, }, /* 0x34 */
+ { "cmpobne",3, }, /* 0x35 */
+ { "cmpoble",3, }, /* 0x36 */
+ { "bbs", 3, }, /* 0x37 */
+ { "cmpibno",3, }, /* 0x38 */
+ { "cmpibg", 3, }, /* 0x39 */
+ { "cmpibe", 3, }, /* 0x3a */
+ { "cmpibge",3, }, /* 0x3b */
+ { "cmpibl", 3, }, /* 0x3c */
+ { "cmpibne",3, }, /* 0x3d */
+ { "cmpible",3, }, /* 0x3e */
+ { "cmpibo", 3, }, /* 0x3f */
+ };
+
+ i = ((word1 >> 24) & 0xff) - 0x20;
+ if (cobr_tab[i].name == NULL)
+ {
+ invalid (word1);
+ return;
+ }
- (*info->fprintf_func) ( stream, cobr_tab[i].name );
- if ( word1 & 2 ){ /* Predicts branch not taken */
- (*info->fprintf_func) ( stream, ".f" );
- }
- (*info->fprintf_func)( stream, "\t" );
+ (*info->fprintf_func) (stream, cobr_tab[i].name);
- src1 = (word1 >> 19) & 0x1f;
- src2 = (word1 >> 14) & 0x1f;
+ /* Predicts branch not taken. */
+ if (word1 & 2)
+ (*info->fprintf_func) (stream, ".f");
- if ( word1 & 0x02000 ){ /* M1 is 1 */
- (*info->fprintf_func)( stream, "%d", src1 );
- } else { /* M1 is 0 */
- (*info->fprintf_func)( stream, reg_names[src1] );
- }
+ (*info->fprintf_func) (stream, "\t");
- if ( cobr_tab[i].numops > 1 ){
- if ( word1 & 1 ){ /* S2 is 1 */
- (*info->fprintf_func)( stream, ",sf%d,", src2 );
- } else { /* S1 is 0 */
- (*info->fprintf_func)( stream, ",%s,", reg_names[src2] );
- }
-
- /* Extract displacement and convert to address
- */
- word1 &= 0x00001ffc;
- if ( word1 & 0x00001000 ){ /* Negative displacement */
- word1 |= (-1 & ~0x1fff); /* Sign extend */
- }
- print_addr( memaddr + word1 );
- }
+ src1 = (word1 >> 19) & 0x1f;
+ src2 = (word1 >> 14) & 0x1f;
+
+ if (word1 & 0x02000)
+ /* M1 is 1 */
+ (*info->fprintf_func) (stream, "%d", src1);
+ else
+ (*info->fprintf_func) (stream, reg_names[src1]);
+
+ if (cobr_tab[i].numops > 1)
+ {
+ if (word1 & 1)
+ /* S2 is 1. */
+ (*info->fprintf_func) (stream, ",sf%d,", src2);
+ else
+ /* S1 is 0. */
+ (*info->fprintf_func) (stream, ",%s,", reg_names[src2]);
+
+ /* Extract displacement and convert to address. */
+ word1 &= 0x00001ffc;
+ if (word1 & 0x00001000)
+ /* Negative displacement. */
+ word1 |= (-1 & ~0x1fff); /* Sign extend. */
+
+ print_addr (memaddr + word1);
+ }
}
-/****************************************/
-/* MEM format */
-/****************************************/
-static int /* returns instruction length: 4 or 8 */
-mem( memaddr, word1, word2, noprint )
- bfd_vma memaddr;
- unsigned long word1, word2;
- int noprint; /* If TRUE, return instruction length, but
- * don't output any text.
- */
+/* MEM format. */
+/* Returns instruction length: 4 or 8. */
+
+static int
+mem (memaddr, word1, word2, noprint)
+ bfd_vma memaddr;
+ unsigned long word1, word2;
+ int noprint; /* If TRUE, return instruction length, but
+ don't output any text. */
{
- int i, j;
- int len;
- int mode;
- int offset;
- const char *reg1, *reg2, *reg3;
-
- /* This lookup table is too sparse to make it worth typing in, but not
- so large as to make a sparse array necessary. We create the table
- at runtime. */
-
- /*
- * NOTE: In this table, the meaning of 'numops' is:
- * 1: single operand
- * 2: 2 operands, load instruction
- * -2: 2 operands, store instruction
- */
- static struct tabent *mem_tab;
-/* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */
+ int i, j;
+ int len;
+ int mode;
+ int offset;
+ const char *reg1, *reg2, *reg3;
+
+ /* This lookup table is too sparse to make it worth typing in, but not
+ so large as to make a sparse array necessary. We create the table
+ at runtime. */
+
+ /* NOTE: In this table, the meaning of 'numops' is:
+ 1: single operand
+ 2: 2 operands, load instruction
+ -2: 2 operands, store instruction. */
+ static struct tabent *mem_tab;
+ /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */
#define MEM_MIN 0x80
#define MEM_MAX 0xcf
#define MEM_SIZ ( * sizeof(struct tabent))
- static const struct sparse_tabent mem_init[] = {
- { 0x80, "ldob", 2 },
- { 0x82, "stob", -2 },
- { 0x84, "bx", 1 },
- { 0x85, "balx", 2 },
- { 0x86, "callx", 1 },
- { 0x88, "ldos", 2 },
- { 0x8a, "stos", -2 },
- { 0x8c, "lda", 2 },
- { 0x90, "ld", 2 },
- { 0x92, "st", -2 },
- { 0x98, "ldl", 2 },
- { 0x9a, "stl", -2 },
- { 0xa0, "ldt", 2 },
- { 0xa2, "stt", -2 },
- { 0xac, "dcinva", 1 },
- { 0xb0, "ldq", 2 },
- { 0xb2, "stq", -2 },
- { 0xc0, "ldib", 2 },
- { 0xc2, "stib", -2 },
- { 0xc8, "ldis", 2 },
- { 0xca, "stis", -2 },
- { 0, NULL, 0 }
- };
- static struct tabent mem_tab_buf[MEM_MAX - MEM_MIN + 1];
-
- if ( mem_tab == NULL ){
- mem_tab = mem_tab_buf;
- for ( i = 0; mem_init[i].opcode != 0; i++ ){
- j = mem_init[i].opcode - MEM_MIN;
- mem_tab[j].name = mem_init[i].name;
- mem_tab[j].numops = mem_init[i].numops;
- }
+ static const struct sparse_tabent mem_init[] = {
+ { 0x80, "ldob", 2 },
+ { 0x82, "stob", -2 },
+ { 0x84, "bx", 1 },
+ { 0x85, "balx", 2 },
+ { 0x86, "callx", 1 },
+ { 0x88, "ldos", 2 },
+ { 0x8a, "stos", -2 },
+ { 0x8c, "lda", 2 },
+ { 0x90, "ld", 2 },
+ { 0x92, "st", -2 },
+ { 0x98, "ldl", 2 },
+ { 0x9a, "stl", -2 },
+ { 0xa0, "ldt", 2 },
+ { 0xa2, "stt", -2 },
+ { 0xac, "dcinva", 1 },
+ { 0xb0, "ldq", 2 },
+ { 0xb2, "stq", -2 },
+ { 0xc0, "ldib", 2 },
+ { 0xc2, "stib", -2 },
+ { 0xc8, "ldis", 2 },
+ { 0xca, "stis", -2 },
+ { 0, NULL, 0 }
+ };
+ static struct tabent mem_tab_buf[MEM_MAX - MEM_MIN + 1];
+
+ if (mem_tab == NULL)
+ {
+ mem_tab = mem_tab_buf;
+
+ for (i = 0; mem_init[i].opcode != 0; i++)
+ {
+ j = mem_init[i].opcode - MEM_MIN;
+ mem_tab[j].name = mem_init[i].name;
+ mem_tab[j].numops = mem_init[i].numops;
}
+ }
- i = ((word1 >> 24) & 0xff) - MEM_MIN;
- mode = (word1 >> 10) & 0xf;
+ i = ((word1 >> 24) & 0xff) - MEM_MIN;
+ mode = (word1 >> 10) & 0xf;
- if ( (mem_tab[i].name != NULL) /* Valid instruction */
- && ((mode == 5) || (mode >=12)) ){ /* With 32-bit displacement */
- len = 8;
- } else {
- len = 4;
+ if ((mem_tab[i].name != NULL) /* Valid instruction */
+ && ((mode == 5) || (mode >= 12)))
+ /* With 32-bit displacement. */
+ len = 8;
+ else
+ len = 4;
+
+ if (noprint)
+ return len;
+
+ if ((mem_tab[i].name == NULL) || (mode == 6))
+ {
+ invalid (word1);
+ return len;
+ }
+
+ (*info->fprintf_func) (stream, "%s\t", mem_tab[i].name);
+
+ reg1 = reg_names[ (word1 >> 19) & 0x1f ]; /* MEMB only */
+ reg2 = reg_names[ (word1 >> 14) & 0x1f ];
+ reg3 = reg_names[ word1 & 0x1f ]; /* MEMB only */
+ offset = word1 & 0xfff; /* MEMA only */
+
+ switch (mem_tab[i].numops)
+ {
+ case 2: /* LOAD INSTRUCTION */
+ if (mode & 4)
+ { /* MEMB FORMAT */
+ ea (memaddr, mode, reg2, reg3, word1, word2);
+ (*info->fprintf_func) (stream, ",%s", reg1);
}
+ else
+ { /* MEMA FORMAT */
+ (*info->fprintf_func) (stream, "0x%x", (unsigned) offset);
- if ( noprint ){
- return len;
+ if (mode & 8)
+ (*info->fprintf_func) (stream, "(%s)", reg2);
+
+ (*info->fprintf_func)(stream, ",%s", reg1);
+ }
+ break;
+
+ case -2: /* STORE INSTRUCTION */
+ if (mode & 4)
+ {
+ /* MEMB FORMAT */
+ (*info->fprintf_func) (stream, "%s,", reg1);
+ ea (memaddr, mode, reg2, reg3, word1, word2);
}
+ else
+ {
+ /* MEMA FORMAT */
+ (*info->fprintf_func) (stream, "%s,0x%x", reg1, (unsigned) offset);
- if ( (mem_tab[i].name == NULL) || (mode == 6) ){
- invalid( word1 );
- return len;
+ if (mode & 8)
+ (*info->fprintf_func) (stream, "(%s)", reg2);
}
+ break;
- (*info->fprintf_func)( stream, "%s\t", mem_tab[i].name );
-
- reg1 = reg_names[ (word1 >> 19) & 0x1f ]; /* MEMB only */
- reg2 = reg_names[ (word1 >> 14) & 0x1f ];
- reg3 = reg_names[ word1 & 0x1f ]; /* MEMB only */
- offset = word1 & 0xfff; /* MEMA only */
-
- switch ( mem_tab[i].numops ){
-
- case 2: /* LOAD INSTRUCTION */
- if ( mode & 4 ){ /* MEMB FORMAT */
- ea( memaddr, mode, reg2, reg3, word1, word2 );
- (*info->fprintf_func)( stream, ",%s", reg1 );
- } else { /* MEMA FORMAT */
- (*info->fprintf_func)( stream, "0x%x", (unsigned) offset );
- if (mode & 8) {
- (*info->fprintf_func)( stream, "(%s)", reg2 );
- }
- (*info->fprintf_func)( stream, ",%s", reg1 );
- }
- break;
-
- case -2: /* STORE INSTRUCTION */
- if ( mode & 4 ){ /* MEMB FORMAT */
- (*info->fprintf_func)( stream, "%s,", reg1 );
- ea( memaddr, mode, reg2, reg3, word1, word2 );
- } else { /* MEMA FORMAT */
- (*info->fprintf_func)( stream, "%s,0x%x", reg1, (unsigned) offset );
- if (mode & 8) {
- (*info->fprintf_func)( stream, "(%s)", reg2 );
- }
- }
- break;
-
- case 1: /* BX/CALLX INSTRUCTION */
- if ( mode & 4 ){ /* MEMB FORMAT */
- ea( memaddr, mode, reg2, reg3, word1, word2 );
- } else { /* MEMA FORMAT */
- (*info->fprintf_func)( stream, "0x%x", (unsigned) offset );
- if (mode & 8) {
- (*info->fprintf_func)( stream, "(%s)", reg2 );
- }
- }
- break;
+ case 1: /* BX/CALLX INSTRUCTION */
+ if (mode & 4)
+ {
+ /* MEMB FORMAT */
+ ea (memaddr, mode, reg2, reg3, word1, word2);
}
+ else
+ {
+ /* MEMA FORMAT */
+ (*info->fprintf_func) (stream, "0x%x", (unsigned) offset);
+ if (mode & 8)
+ (*info->fprintf_func) (stream, "(%s)", reg2);
+ }
+ break;
+ }
- return len;
+ return len;
}
-/****************************************/
-/* REG format */
-/****************************************/
+/* REG format. */
+
static void
-reg( word1 )
- unsigned long word1;
+reg (word1)
+ unsigned long word1;
{
- int i, j;
- int opcode;
- int fp;
- int m1, m2, m3;
- int s1, s2;
- int src, src2, dst;
- char *mnemp;
-
- /* This lookup table is too sparse to make it worth typing in, but not
- so large as to make a sparse array necessary. We create the table
- at runtime. */
-
- /*
- * NOTE: In this table, the meaning of 'numops' is:
- * 1: single operand, which is NOT a destination.
- * -1: single operand, which IS a destination.
- * 2: 2 operands, the 2nd of which is NOT a destination.
- * -2: 2 operands, the 2nd of which IS a destination.
- * 3: 3 operands
- *
- * If an opcode mnemonic begins with "F", it is a floating-point
- * opcode (the "F" is not printed).
- */
-
- static struct tabent *reg_tab;
- static const struct sparse_tabent reg_init[] = {
+ int i, j;
+ int opcode;
+ int fp;
+ int m1, m2, m3;
+ int s1, s2;
+ int src, src2, dst;
+ char *mnemp;
+
+ /* This lookup table is too sparse to make it worth typing in, but not
+ so large as to make a sparse array necessary. We create the table
+ at runtime. */
+
+ /* NOTE: In this table, the meaning of 'numops' is:
+ 1: single operand, which is NOT a destination.
+ -1: single operand, which IS a destination.
+ 2: 2 operands, the 2nd of which is NOT a destination.
+ -2: 2 operands, the 2nd of which IS a destination.
+ 3: 3 operands
+
+ If an opcode mnemonic begins with "F", it is a floating-point
+ opcode (the "F" is not printed). */
+
+ static struct tabent *reg_tab;
+ static const struct sparse_tabent reg_init[] =
+ {
#define REG_MIN 0x580
- { 0x580, "notbit", 3 },
- { 0x581, "and", 3 },
- { 0x582, "andnot", 3 },
- { 0x583, "setbit", 3 },
- { 0x584, "notand", 3 },
- { 0x586, "xor", 3 },
- { 0x587, "or", 3 },
- { 0x588, "nor", 3 },
- { 0x589, "xnor", 3 },
- { 0x58a, "not", -2 },
- { 0x58b, "ornot", 3 },
- { 0x58c, "clrbit", 3 },
- { 0x58d, "notor", 3 },
- { 0x58e, "nand", 3 },
- { 0x58f, "alterbit", 3 },
- { 0x590, "addo", 3 },
- { 0x591, "addi", 3 },
- { 0x592, "subo", 3 },
- { 0x593, "subi", 3 },
- { 0x594, "cmpob", 2 },
- { 0x595, "cmpib", 2 },
- { 0x596, "cmpos", 2 },
- { 0x597, "cmpis", 2 },
- { 0x598, "shro", 3 },
- { 0x59a, "shrdi", 3 },
- { 0x59b, "shri", 3 },
- { 0x59c, "shlo", 3 },
- { 0x59d, "rotate", 3 },
- { 0x59e, "shli", 3 },
- { 0x5a0, "cmpo", 2 },
- { 0x5a1, "cmpi", 2 },
- { 0x5a2, "concmpo", 2 },
- { 0x5a3, "concmpi", 2 },
- { 0x5a4, "cmpinco", 3 },
- { 0x5a5, "cmpinci", 3 },
- { 0x5a6, "cmpdeco", 3 },
- { 0x5a7, "cmpdeci", 3 },
- { 0x5ac, "scanbyte", 2 },
- { 0x5ad, "bswap", -2 },
- { 0x5ae, "chkbit", 2 },
- { 0x5b0, "addc", 3 },
- { 0x5b2, "subc", 3 },
- { 0x5b4, "intdis", 0 },
- { 0x5b5, "inten", 0 },
- { 0x5cc, "mov", -2 },
- { 0x5d8, "eshro", 3 },
- { 0x5dc, "movl", -2 },
- { 0x5ec, "movt", -2 },
- { 0x5fc, "movq", -2 },
- { 0x600, "synmov", 2 },
- { 0x601, "synmovl", 2 },
- { 0x602, "synmovq", 2 },
- { 0x603, "cmpstr", 3 },
- { 0x604, "movqstr", 3 },
- { 0x605, "movstr", 3 },
- { 0x610, "atmod", 3 },
- { 0x612, "atadd", 3 },
- { 0x613, "inspacc", -2 },
- { 0x614, "ldphy", -2 },
- { 0x615, "synld", -2 },
- { 0x617, "fill", 3 },
- { 0x630, "sdma", 3 },
- { 0x631, "udma", 0 },
- { 0x640, "spanbit", -2 },
- { 0x641, "scanbit", -2 },
- { 0x642, "daddc", 3 },
- { 0x643, "dsubc", 3 },
- { 0x644, "dmovt", -2 },
- { 0x645, "modac", 3 },
- { 0x646, "condrec", -2 },
- { 0x650, "modify", 3 },
- { 0x651, "extract", 3 },
- { 0x654, "modtc", 3 },
- { 0x655, "modpc", 3 },
- { 0x656, "receive", -2 },
- { 0x658, "intctl", -2 },
- { 0x659, "sysctl", 3 },
- { 0x65b, "icctl", 3 },
- { 0x65c, "dcctl", 3 },
- { 0x65d, "halt", 0 },
- { 0x660, "calls", 1 },
- { 0x662, "send", 3 },
- { 0x663, "sendserv", 1 },
- { 0x664, "resumprcs", 1 },
- { 0x665, "schedprcs", 1 },
- { 0x666, "saveprcs", 0 },
- { 0x668, "condwait", 1 },
- { 0x669, "wait", 1 },
- { 0x66a, "signal", 1 },
- { 0x66b, "mark", 0 },
- { 0x66c, "fmark", 0 },
- { 0x66d, "flushreg", 0 },
- { 0x66f, "syncf", 0 },
- { 0x670, "emul", 3 },
- { 0x671, "ediv", 3 },
- { 0x673, "ldtime", -1 },
- { 0x674, "Fcvtir", -2 },
- { 0x675, "Fcvtilr", -2 },
- { 0x676, "Fscalerl", 3 },
- { 0x677, "Fscaler", 3 },
- { 0x680, "Fatanr", 3 },
- { 0x681, "Flogepr", 3 },
- { 0x682, "Flogr", 3 },
- { 0x683, "Fremr", 3 },
- { 0x684, "Fcmpor", 2 },
- { 0x685, "Fcmpr", 2 },
- { 0x688, "Fsqrtr", -2 },
- { 0x689, "Fexpr", -2 },
- { 0x68a, "Flogbnr", -2 },
- { 0x68b, "Froundr", -2 },
- { 0x68c, "Fsinr", -2 },
- { 0x68d, "Fcosr", -2 },
- { 0x68e, "Ftanr", -2 },
- { 0x68f, "Fclassr", 1 },
- { 0x690, "Fatanrl", 3 },
- { 0x691, "Flogeprl", 3 },
- { 0x692, "Flogrl", 3 },
- { 0x693, "Fremrl", 3 },
- { 0x694, "Fcmporl", 2 },
- { 0x695, "Fcmprl", 2 },
- { 0x698, "Fsqrtrl", -2 },
- { 0x699, "Fexprl", -2 },
- { 0x69a, "Flogbnrl", -2 },
- { 0x69b, "Froundrl", -2 },
- { 0x69c, "Fsinrl", -2 },
- { 0x69d, "Fcosrl", -2 },
- { 0x69e, "Ftanrl", -2 },
- { 0x69f, "Fclassrl", 1 },
- { 0x6c0, "Fcvtri", -2 },
- { 0x6c1, "Fcvtril", -2 },
- { 0x6c2, "Fcvtzri", -2 },
- { 0x6c3, "Fcvtzril", -2 },
- { 0x6c9, "Fmovr", -2 },
- { 0x6d9, "Fmovrl", -2 },
- { 0x6e1, "Fmovre", -2 },
- { 0x6e2, "Fcpysre", 3 },
- { 0x6e3, "Fcpyrsre", 3 },
- { 0x701, "mulo", 3 },
- { 0x708, "remo", 3 },
- { 0x70b, "divo", 3 },
- { 0x741, "muli", 3 },
- { 0x748, "remi", 3 },
- { 0x749, "modi", 3 },
- { 0x74b, "divi", 3 },
- { 0x780, "addono", 3 },
- { 0x781, "addino", 3 },
- { 0x782, "subono", 3 },
- { 0x783, "subino", 3 },
- { 0x784, "selno", 3 },
- { 0x78b, "Fdivr", 3 },
- { 0x78c, "Fmulr", 3 },
- { 0x78d, "Fsubr", 3 },
- { 0x78f, "Faddr", 3 },
- { 0x790, "addog", 3 },
- { 0x791, "addig", 3 },
- { 0x792, "subog", 3 },
- { 0x793, "subig", 3 },
- { 0x794, "selg", 3 },
- { 0x79b, "Fdivrl", 3 },
- { 0x79c, "Fmulrl", 3 },
- { 0x79d, "Fsubrl", 3 },
- { 0x79f, "Faddrl", 3 },
- { 0x7a0, "addoe", 3 },
- { 0x7a1, "addie", 3 },
- { 0x7a2, "suboe", 3 },
- { 0x7a3, "subie", 3 },
- { 0x7a4, "sele", 3 },
- { 0x7b0, "addoge", 3 },
- { 0x7b1, "addige", 3 },
- { 0x7b2, "suboge", 3 },
- { 0x7b3, "subige", 3 },
- { 0x7b4, "selge", 3 },
- { 0x7c0, "addol", 3 },
- { 0x7c1, "addil", 3 },
- { 0x7c2, "subol", 3 },
- { 0x7c3, "subil", 3 },
- { 0x7c4, "sell", 3 },
- { 0x7d0, "addone", 3 },
- { 0x7d1, "addine", 3 },
- { 0x7d2, "subone", 3 },
- { 0x7d3, "subine", 3 },
- { 0x7d4, "selne", 3 },
- { 0x7e0, "addole", 3 },
- { 0x7e1, "addile", 3 },
- { 0x7e2, "subole", 3 },
- { 0x7e3, "subile", 3 },
- { 0x7e4, "selle", 3 },
- { 0x7f0, "addoo", 3 },
- { 0x7f1, "addio", 3 },
- { 0x7f2, "suboo", 3 },
- { 0x7f3, "subio", 3 },
- { 0x7f4, "selo", 3 },
+ { 0x580, "notbit", 3 },
+ { 0x581, "and", 3 },
+ { 0x582, "andnot", 3 },
+ { 0x583, "setbit", 3 },
+ { 0x584, "notand", 3 },
+ { 0x586, "xor", 3 },
+ { 0x587, "or", 3 },
+ { 0x588, "nor", 3 },
+ { 0x589, "xnor", 3 },
+ { 0x58a, "not", -2 },
+ { 0x58b, "ornot", 3 },
+ { 0x58c, "clrbit", 3 },
+ { 0x58d, "notor", 3 },
+ { 0x58e, "nand", 3 },
+ { 0x58f, "alterbit", 3 },
+ { 0x590, "addo", 3 },
+ { 0x591, "addi", 3 },
+ { 0x592, "subo", 3 },
+ { 0x593, "subi", 3 },
+ { 0x594, "cmpob", 2 },
+ { 0x595, "cmpib", 2 },
+ { 0x596, "cmpos", 2 },
+ { 0x597, "cmpis", 2 },
+ { 0x598, "shro", 3 },
+ { 0x59a, "shrdi", 3 },
+ { 0x59b, "shri", 3 },
+ { 0x59c, "shlo", 3 },
+ { 0x59d, "rotate", 3 },
+ { 0x59e, "shli", 3 },
+ { 0x5a0, "cmpo", 2 },
+ { 0x5a1, "cmpi", 2 },
+ { 0x5a2, "concmpo", 2 },
+ { 0x5a3, "concmpi", 2 },
+ { 0x5a4, "cmpinco", 3 },
+ { 0x5a5, "cmpinci", 3 },
+ { 0x5a6, "cmpdeco", 3 },
+ { 0x5a7, "cmpdeci", 3 },
+ { 0x5ac, "scanbyte", 2 },
+ { 0x5ad, "bswap", -2 },
+ { 0x5ae, "chkbit", 2 },
+ { 0x5b0, "addc", 3 },
+ { 0x5b2, "subc", 3 },
+ { 0x5b4, "intdis", 0 },
+ { 0x5b5, "inten", 0 },
+ { 0x5cc, "mov", -2 },
+ { 0x5d8, "eshro", 3 },
+ { 0x5dc, "movl", -2 },
+ { 0x5ec, "movt", -2 },
+ { 0x5fc, "movq", -2 },
+ { 0x600, "synmov", 2 },
+ { 0x601, "synmovl", 2 },
+ { 0x602, "synmovq", 2 },
+ { 0x603, "cmpstr", 3 },
+ { 0x604, "movqstr", 3 },
+ { 0x605, "movstr", 3 },
+ { 0x610, "atmod", 3 },
+ { 0x612, "atadd", 3 },
+ { 0x613, "inspacc", -2 },
+ { 0x614, "ldphy", -2 },
+ { 0x615, "synld", -2 },
+ { 0x617, "fill", 3 },
+ { 0x630, "sdma", 3 },
+ { 0x631, "udma", 0 },
+ { 0x640, "spanbit", -2 },
+ { 0x641, "scanbit", -2 },
+ { 0x642, "daddc", 3 },
+ { 0x643, "dsubc", 3 },
+ { 0x644, "dmovt", -2 },
+ { 0x645, "modac", 3 },
+ { 0x646, "condrec", -2 },
+ { 0x650, "modify", 3 },
+ { 0x651, "extract", 3 },
+ { 0x654, "modtc", 3 },
+ { 0x655, "modpc", 3 },
+ { 0x656, "receive", -2 },
+ { 0x658, "intctl", -2 },
+ { 0x659, "sysctl", 3 },
+ { 0x65b, "icctl", 3 },
+ { 0x65c, "dcctl", 3 },
+ { 0x65d, "halt", 0 },
+ { 0x660, "calls", 1 },
+ { 0x662, "send", 3 },
+ { 0x663, "sendserv", 1 },
+ { 0x664, "resumprcs", 1 },
+ { 0x665, "schedprcs", 1 },
+ { 0x666, "saveprcs", 0 },
+ { 0x668, "condwait", 1 },
+ { 0x669, "wait", 1 },
+ { 0x66a, "signal", 1 },
+ { 0x66b, "mark", 0 },
+ { 0x66c, "fmark", 0 },
+ { 0x66d, "flushreg", 0 },
+ { 0x66f, "syncf", 0 },
+ { 0x670, "emul", 3 },
+ { 0x671, "ediv", 3 },
+ { 0x673, "ldtime", -1 },
+ { 0x674, "Fcvtir", -2 },
+ { 0x675, "Fcvtilr", -2 },
+ { 0x676, "Fscalerl", 3 },
+ { 0x677, "Fscaler", 3 },
+ { 0x680, "Fatanr", 3 },
+ { 0x681, "Flogepr", 3 },
+ { 0x682, "Flogr", 3 },
+ { 0x683, "Fremr", 3 },
+ { 0x684, "Fcmpor", 2 },
+ { 0x685, "Fcmpr", 2 },
+ { 0x688, "Fsqrtr", -2 },
+ { 0x689, "Fexpr", -2 },
+ { 0x68a, "Flogbnr", -2 },
+ { 0x68b, "Froundr", -2 },
+ { 0x68c, "Fsinr", -2 },
+ { 0x68d, "Fcosr", -2 },
+ { 0x68e, "Ftanr", -2 },
+ { 0x68f, "Fclassr", 1 },
+ { 0x690, "Fatanrl", 3 },
+ { 0x691, "Flogeprl", 3 },
+ { 0x692, "Flogrl", 3 },
+ { 0x693, "Fremrl", 3 },
+ { 0x694, "Fcmporl", 2 },
+ { 0x695, "Fcmprl", 2 },
+ { 0x698, "Fsqrtrl", -2 },
+ { 0x699, "Fexprl", -2 },
+ { 0x69a, "Flogbnrl", -2 },
+ { 0x69b, "Froundrl", -2 },
+ { 0x69c, "Fsinrl", -2 },
+ { 0x69d, "Fcosrl", -2 },
+ { 0x69e, "Ftanrl", -2 },
+ { 0x69f, "Fclassrl", 1 },
+ { 0x6c0, "Fcvtri", -2 },
+ { 0x6c1, "Fcvtril", -2 },
+ { 0x6c2, "Fcvtzri", -2 },
+ { 0x6c3, "Fcvtzril", -2 },
+ { 0x6c9, "Fmovr", -2 },
+ { 0x6d9, "Fmovrl", -2 },
+ { 0x6e1, "Fmovre", -2 },
+ { 0x6e2, "Fcpysre", 3 },
+ { 0x6e3, "Fcpyrsre", 3 },
+ { 0x701, "mulo", 3 },
+ { 0x708, "remo", 3 },
+ { 0x70b, "divo", 3 },
+ { 0x741, "muli", 3 },
+ { 0x748, "remi", 3 },
+ { 0x749, "modi", 3 },
+ { 0x74b, "divi", 3 },
+ { 0x780, "addono", 3 },
+ { 0x781, "addino", 3 },
+ { 0x782, "subono", 3 },
+ { 0x783, "subino", 3 },
+ { 0x784, "selno", 3 },
+ { 0x78b, "Fdivr", 3 },
+ { 0x78c, "Fmulr", 3 },
+ { 0x78d, "Fsubr", 3 },
+ { 0x78f, "Faddr", 3 },
+ { 0x790, "addog", 3 },
+ { 0x791, "addig", 3 },
+ { 0x792, "subog", 3 },
+ { 0x793, "subig", 3 },
+ { 0x794, "selg", 3 },
+ { 0x79b, "Fdivrl", 3 },
+ { 0x79c, "Fmulrl", 3 },
+ { 0x79d, "Fsubrl", 3 },
+ { 0x79f, "Faddrl", 3 },
+ { 0x7a0, "addoe", 3 },
+ { 0x7a1, "addie", 3 },
+ { 0x7a2, "suboe", 3 },
+ { 0x7a3, "subie", 3 },
+ { 0x7a4, "sele", 3 },
+ { 0x7b0, "addoge", 3 },
+ { 0x7b1, "addige", 3 },
+ { 0x7b2, "suboge", 3 },
+ { 0x7b3, "subige", 3 },
+ { 0x7b4, "selge", 3 },
+ { 0x7c0, "addol", 3 },
+ { 0x7c1, "addil", 3 },
+ { 0x7c2, "subol", 3 },
+ { 0x7c3, "subil", 3 },
+ { 0x7c4, "sell", 3 },
+ { 0x7d0, "addone", 3 },
+ { 0x7d1, "addine", 3 },
+ { 0x7d2, "subone", 3 },
+ { 0x7d3, "subine", 3 },
+ { 0x7d4, "selne", 3 },
+ { 0x7e0, "addole", 3 },
+ { 0x7e1, "addile", 3 },
+ { 0x7e2, "subole", 3 },
+ { 0x7e3, "subile", 3 },
+ { 0x7e4, "selle", 3 },
+ { 0x7f0, "addoo", 3 },
+ { 0x7f1, "addio", 3 },
+ { 0x7f2, "suboo", 3 },
+ { 0x7f3, "subio", 3 },
+ { 0x7f4, "selo", 3 },
#define REG_MAX 0x7f4
- { 0, NULL, 0 }
- };
- static struct tabent reg_tab_buf[REG_MAX - REG_MIN + 1];
-
- if ( reg_tab == NULL ){
- reg_tab = reg_tab_buf;
- for ( i = 0; reg_init[i].opcode != 0; i++ ){
- j = reg_init[i].opcode - REG_MIN;
- reg_tab[j].name = reg_init[i].name;
- reg_tab[j].numops = reg_init[i].numops;
- }
- }
+ { 0, NULL, 0 }
+ };
+ static struct tabent reg_tab_buf[REG_MAX - REG_MIN + 1];
- opcode = ((word1 >> 20) & 0xff0) | ((word1 >> 7) & 0xf);
- i = opcode - REG_MIN;
+ if (reg_tab == NULL)
+ {
+ reg_tab = reg_tab_buf;
- if ( (opcode<REG_MIN) || (opcode>REG_MAX) || (reg_tab[i].name==NULL) ){
- invalid( word1 );
- return;
+ for (i = 0; reg_init[i].opcode != 0; i++)
+ {
+ j = reg_init[i].opcode - REG_MIN;
+ reg_tab[j].name = reg_init[i].name;
+ reg_tab[j].numops = reg_init[i].numops;
}
+ }
- mnemp = reg_tab[i].name;
- if ( *mnemp == 'F' ){
- fp = 1;
- mnemp++;
- } else {
- fp = 0;
- }
+ opcode = ((word1 >> 20) & 0xff0) | ((word1 >> 7) & 0xf);
+ i = opcode - REG_MIN;
- (*info->fprintf_func)( stream, mnemp );
-
- s1 = (word1 >> 5) & 1;
- s2 = (word1 >> 6) & 1;
- m1 = (word1 >> 11) & 1;
- m2 = (word1 >> 12) & 1;
- m3 = (word1 >> 13) & 1;
- src = word1 & 0x1f;
- src2 = (word1 >> 14) & 0x1f;
- dst = (word1 >> 19) & 0x1f;
-
- if ( reg_tab[i].numops != 0 ){
- (*info->fprintf_func)( stream, "\t" );
-
- switch ( reg_tab[i].numops ){
- case 1:
- regop( m1, s1, src, fp );
- break;
- case -1:
- dstop( m3, dst, fp );
- break;
- case 2:
- regop( m1, s1, src, fp );
- (*info->fprintf_func)( stream, "," );
- regop( m2, s2, src2, fp );
- break;
- case -2:
- regop( m1, s1, src, fp );
- (*info->fprintf_func)( stream, "," );
- dstop( m3, dst, fp );
- break;
- case 3:
- regop( m1, s1, src, fp );
- (*info->fprintf_func)( stream, "," );
- regop( m2, s2, src2, fp );
- (*info->fprintf_func)( stream, "," );
- dstop( m3, dst, fp );
- break;
- }
- }
+ if ((opcode<REG_MIN) || (opcode>REG_MAX) || (reg_tab[i].name==NULL))
+ {
+ invalid (word1);
+ return;
+ }
+
+ mnemp = reg_tab[i].name;
+ if (*mnemp == 'F')
+ {
+ fp = 1;
+ mnemp++;
+ }
+ else
+ {
+ fp = 0;
+ }
+
+ (*info->fprintf_func) (stream, mnemp);
+
+ s1 = (word1 >> 5) & 1;
+ s2 = (word1 >> 6) & 1;
+ m1 = (word1 >> 11) & 1;
+ m2 = (word1 >> 12) & 1;
+ m3 = (word1 >> 13) & 1;
+ src = word1 & 0x1f;
+ src2 = (word1 >> 14) & 0x1f;
+ dst = (word1 >> 19) & 0x1f;
+
+ if (reg_tab[i].numops != 0)
+ {
+ (*info->fprintf_func) (stream, "\t");
+
+ switch (reg_tab[i].numops)
+ {
+ case 1:
+ regop (m1, s1, src, fp);
+ break;
+ case -1:
+ dstop (m3, dst, fp);
+ break;
+ case 2:
+ regop (m1, s1, src, fp);
+ (*info->fprintf_func) (stream, ",");
+ regop (m2, s2, src2, fp);
+ break;
+ case -2:
+ regop (m1, s1, src, fp);
+ (*info->fprintf_func) (stream, ",");
+ dstop (m3, dst, fp);
+ break;
+ case 3:
+ regop (m1, s1, src, fp);
+ (*info->fprintf_func) (stream, ",");
+ regop (m2, s2, src2, fp);
+ (*info->fprintf_func) (stream, ",");
+ dstop (m3, dst, fp);
+ break;
+ }
+ }
}
+/* Print out effective address for memb instructions. */
-/*
- * Print out effective address for memb instructions.
- */
static void
-ea( memaddr, mode, reg2, reg3, word1, word2 )
+ea (memaddr, mode, reg2, reg3, word1, word2)
bfd_vma memaddr;
int mode;
- char *reg2, *reg3;
+ const char *reg2;
+ const char *reg3;
int word1;
unsigned int word2;
{
- int scale;
- static const int scale_tab[] = { 1, 2, 4, 8, 16 };
+ int scale;
+ static const int scale_tab[] = { 1, 2, 4, 8, 16 };
- scale = (word1 >> 7) & 0x07;
- if ( (scale > 4) || (((word1 >> 5) & 0x03) != 0) ){
- invalid( word1 );
- return;
- }
- scale = scale_tab[scale];
-
- switch (mode) {
- case 4: /* (reg) */
- (*info->fprintf_func)( stream, "(%s)", reg2 );
- break;
- case 5: /* displ+8(ip) */
- print_addr( word2+8+memaddr );
- break;
- case 7: /* (reg)[index*scale] */
- if (scale == 1) {
- (*info->fprintf_func)( stream, "(%s)[%s]", reg2, reg3 );
- } else {
- (*info->fprintf_func)( stream, "(%s)[%s*%d]",reg2,reg3,scale);
- }
- break;
- case 12: /* displacement */
- print_addr( (bfd_vma)word2 );
- break;
- case 13: /* displ(reg) */
- print_addr( (bfd_vma)word2 );
- (*info->fprintf_func)( stream, "(%s)", reg2 );
- break;
- case 14: /* displ[index*scale] */
- print_addr( (bfd_vma)word2 );
- if (scale == 1) {
- (*info->fprintf_func)( stream, "[%s]", reg3 );
- } else {
- (*info->fprintf_func)( stream, "[%s*%d]", reg3, scale );
- }
- break;
- case 15: /* displ(reg)[index*scale] */
- print_addr( (bfd_vma)word2 );
- if (scale == 1) {
- (*info->fprintf_func)( stream, "(%s)[%s]", reg2, reg3 );
- } else {
- (*info->fprintf_func)( stream, "(%s)[%s*%d]",reg2,reg3,scale );
- }
- break;
- default:
- invalid( word1 );
- return;
- }
+ scale = (word1 >> 7) & 0x07;
+
+ if ((scale > 4) || (((word1 >> 5) & 0x03) != 0))
+ {
+ invalid (word1);
+ return;
+ }
+ scale = scale_tab[scale];
+
+ switch (mode)
+ {
+ case 4: /* (reg) */
+ (*info->fprintf_func)( stream, "(%s)", reg2 );
+ break;
+ case 5: /* displ+8(ip) */
+ print_addr (word2 + 8 + memaddr);
+ break;
+ case 7: /* (reg)[index*scale] */
+ if (scale == 1)
+ (*info->fprintf_func) (stream, "(%s)[%s]", reg2, reg3);
+ else
+ (*info->fprintf_func) (stream, "(%s)[%s*%d]", reg2, reg3, scale);
+ break;
+ case 12: /* displacement */
+ print_addr ((bfd_vma) word2);
+ break;
+ case 13: /* displ(reg) */
+ print_addr ((bfd_vma) word2);
+ (*info->fprintf_func) (stream, "(%s)", reg2);
+ break;
+ case 14: /* displ[index*scale] */
+ print_addr ((bfd_vma) word2);
+ if (scale == 1)
+ (*info->fprintf_func) (stream, "[%s]", reg3);
+ else
+ (*info->fprintf_func) (stream, "[%s*%d]", reg3, scale);
+ break;
+ case 15: /* displ(reg)[index*scale] */
+ print_addr ((bfd_vma) word2);
+ if (scale == 1)
+ (*info->fprintf_func) (stream, "(%s)[%s]", reg2, reg3);
+ else
+ (*info->fprintf_func) (stream, "(%s)[%s*%d]", reg2, reg3, scale);
+ break;
+ default:
+ invalid (word1);
+ return;
+ }
}
-/************************************************/
-/* Register Instruction Operand */
-/************************************************/
+/* Register Instruction Operand. */
+
static void
-regop( mode, spec, reg, fp )
- int mode, spec, reg, fp;
+regop (mode, spec, reg, fp)
+ int mode, spec, reg, fp;
{
- if ( fp ){ /* FLOATING POINT INSTRUCTION */
- if ( mode == 1 ){ /* FP operand */
- switch ( reg ){
- case 0: (*info->fprintf_func)( stream, "fp0" );
- break;
- case 1: (*info->fprintf_func)( stream, "fp1" );
- break;
- case 2: (*info->fprintf_func)( stream, "fp2" );
- break;
- case 3: (*info->fprintf_func)( stream, "fp3" );
- break;
- case 16: (*info->fprintf_func)( stream, "0f0.0" );
- break;
- case 22: (*info->fprintf_func)( stream, "0f1.0" );
- break;
- default: (*info->fprintf_func)( stream, "?" );
- break;
- }
- } else { /* Non-FP register */
- (*info->fprintf_func)( stream, reg_names[reg] );
- }
- } else { /* NOT FLOATING POINT */
- if ( mode == 1 ){ /* Literal */
- (*info->fprintf_func)( stream, "%d", reg );
- } else { /* Register */
- if ( spec == 0 ){
- (*info->fprintf_func)( stream, reg_names[reg] );
- } else {
- (*info->fprintf_func)( stream, "sf%d", reg );
- }
- }
+ if (fp)
+ {
+ /* Floating point instruction. */
+ if (mode == 1)
+ {
+ /* FP operand. */
+ switch (reg)
+ {
+ case 0: (*info->fprintf_func) (stream, "fp0");
+ break;
+ case 1: (*info->fprintf_func) (stream, "fp1");
+ break;
+ case 2: (*info->fprintf_func) (stream, "fp2");
+ break;
+ case 3: (*info->fprintf_func) (stream, "fp3");
+ break;
+ case 16: (*info->fprintf_func) (stream, "0f0.0");
+ break;
+ case 22: (*info->fprintf_func) (stream, "0f1.0");
+ break;
+ default: (*info->fprintf_func) (stream, "?");
+ break;
+ }
+ }
+ else
+ {
+ /* Non-FP register. */
+ (*info->fprintf_func) (stream, reg_names[reg]);
+ }
+ }
+ else
+ {
+ /* Not floating point. */
+ if (mode == 1)
+ {
+ /* Literal. */
+ (*info->fprintf_func) (stream, "%d", reg);
+ }
+ else
+ {
+ /* Register. */
+ if (spec == 0)
+ (*info->fprintf_func) (stream, reg_names[reg]);
+ else
+ (*info->fprintf_func) (stream, "sf%d", reg);
}
+ }
}
-/************************************************/
-/* Register Instruction Destination Operand */
-/************************************************/
+/* Register Instruction Destination Operand. */
+
static void
-dstop( mode, reg, fp )
- int mode, reg, fp;
+dstop (mode, reg, fp)
+ int mode, reg, fp;
{
- /* 'dst' operand can't be a literal. On non-FP instructions, register
- * mode is assumed and "m3" acts as if were "s3"; on FP-instructions,
- * sf registers are not allowed so m3 acts normally.
- */
- if ( fp ){
- regop( mode, 0, reg, fp );
- } else {
- regop( 0, mode, reg, fp );
- }
+ /* 'dst' operand can't be a literal. On non-FP instructions, register
+ mode is assumed and "m3" acts as if were "s3"; on FP-instructions,
+ sf registers are not allowed so m3 acts normally. */
+ if (fp)
+ regop (mode, 0, reg, fp);
+ else
+ regop (0, mode, reg, fp);
}
-
static void
-invalid( word1 )
- int word1;
+invalid (word1)
+ int word1;
{
- (*info->fprintf_func)( stream, ".word\t0x%08x", (unsigned) word1 );
+ (*info->fprintf_func) (stream, ".word\t0x%08x", (unsigned) word1);
}
static void
-print_addr(a)
-bfd_vma a;
+print_addr (a)
+ bfd_vma a;
{
(*info->print_address_func) (a, info);
}
static void
-put_abs( word1, word2 )
- unsigned long word1 ATTRIBUTE_UNUSED;
- unsigned long word2 ATTRIBUTE_UNUSED;
+put_abs (word1, word2)
+ unsigned long word1 ATTRIBUTE_UNUSED;
+ unsigned long word2 ATTRIBUTE_UNUSED;
{
#ifdef IN_GDB
- return;
+ return;
#else
- int len;
-
- switch ( (word1 >> 28) & 0xf ){
- case 0x8:
- case 0x9:
- case 0xa:
- case 0xb:
- case 0xc:
- /* MEM format instruction */
- len = mem( 0, word1, word2, 1 );
- break;
- default:
- len = 4;
- break;
- }
+ int len;
- if ( len == 8 ){
- (*info->fprintf_func)( stream, "%08x %08x\t", word1, word2 );
- } else {
- (*info->fprintf_func)( stream, "%08x \t", word1 );
- }
-;
+ switch ((word1 >> 28) & 0xf)
+ {
+ case 0x8:
+ case 0x9:
+ case 0xa:
+ case 0xb:
+ case 0xc:
+ /* MEM format instruction. */
+ len = mem (0, word1, word2, 1);
+ break;
+ default:
+ len = 4;
+ break;
+ }
+ if (len == 8)
+ (*info->fprintf_func) (stream, "%08x %08x\t", word1, word2);
+ else
+ (*info->fprintf_func) (stream, "%08x \t", word1);
#endif
}
diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c
index 4141e4f..a12cfd8 100644
--- a/opcodes/m32r-asm.c
+++ b/opcodes/m32r-asm.c
@@ -35,14 +35,19 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "m32r-opc.h"
#include "opintl.h"
#include "xregex.h"
+#include "libiberty.h"
#undef min
#define min(a,b) ((a) < (b) ? (a) : (b))
#undef max
#define max(a,b) ((a) > (b) ? (a) : (b))
-static const char * parse_insn_normal
- PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+static const char * parse_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+static const char * parse_hash PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * parse_slo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
+static const char * parse_ulo16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+ const char * m32r_cgen_parse_operand PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
/* -- assembler routines inserted here */
@@ -52,10 +57,10 @@ static const char * parse_insn_normal
static const char *
parse_hash (cd, strp, opindex, valuep)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
const char **strp;
- int opindex;
- unsigned long *valuep;
+ int opindex ATTRIBUTE_UNUSED;
+ unsigned long *valuep ATTRIBUTE_UNUSED;
{
if (**strp == '#')
++*strp;
@@ -352,7 +357,7 @@ char *
m32r_cgen_build_insn_regex (insn)
CGEN_INSN *insn;
{
- CGEN_OPCODE *opc = CGEN_INSN_OPCODE (insn);
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
int mnem_len;
char rxbuf[CGEN_MAX_RX_ELEMENTS];
diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c
index 8db9bfa..824beea 100644
--- a/opcodes/m32r-desc.c
+++ b/opcodes/m32r-desc.c
@@ -33,6 +33,13 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "opintl.h"
#include "libiberty.h"
+static void init_tables PARAMS ((void));
+static const CGEN_MACH * lookup_mach_via_bfd_name PARAMS ((const CGEN_MACH *, const char *));
+static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
+static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
/* Attributes. */
static const CGEN_ATTR_ENTRY bool_attr[] =
diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c
index 687eb51..150f6ee 100644
--- a/opcodes/m32r-dis.c
+++ b/opcodes/m32r-dis.c
@@ -47,10 +47,17 @@ static void print_keyword
static void print_insn_normal
PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
bfd_vma, int));
-static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma,
- disassemble_info *, char *, int));
-static int default_print_insn
+static int print_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int));
+static void print_hash
+ PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
+static int my_print_insn
PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+void m32r_cgen_print_operand
+ PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int));
+static int read_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
+ CGEN_EXTRACT_INFO *, unsigned long *));
/* -- disassembler routines inserted here */
@@ -68,12 +75,12 @@ do { \
static void
print_hash (cd, dis_info, value, attrs, pc, length)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
- long value;
- unsigned int attrs;
- bfd_vma pc;
- int length;
+ long value ATTRIBUTE_UNUSED;
+ unsigned int attrs ATTRIBUTE_UNUSED;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "#");
@@ -156,7 +163,7 @@ m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
int opindex;
PTR xinfo;
CGEN_FIELDS *fields;
- void const *attrs;
+ void const *attrs ATTRIBUTE_UNUSED;
bfd_vma pc;
int length;
{
@@ -264,7 +271,7 @@ m32r_cgen_init_dis (cd)
static void
print_normal (cd, dis_info, value, attrs, pc, length)
#ifdef CGEN_PRINT_NORMAL
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
#else
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
#endif
@@ -272,8 +279,8 @@ print_normal (cd, dis_info, value, attrs, pc, length)
long value;
unsigned int attrs;
#ifdef CGEN_PRINT_NORMAL
- bfd_vma pc;
- int length;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
#else
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
@@ -299,7 +306,7 @@ print_normal (cd, dis_info, value, attrs, pc, length)
static void
print_address (cd, dis_info, value, attrs, pc, length)
#ifdef CGEN_PRINT_NORMAL
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
#else
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
#endif
@@ -307,8 +314,8 @@ print_address (cd, dis_info, value, attrs, pc, length)
bfd_vma value;
unsigned int attrs;
#ifdef CGEN_PRINT_NORMAL
- bfd_vma pc;
- int length;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
#else
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
@@ -397,7 +404,7 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
Returns 0 if all is well, non-zero otherwise. */
static int
read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
bfd_vma pc;
disassemble_info *info;
char *buf;
@@ -475,8 +482,8 @@ print_insn (cd, pc, info, buf, buflen)
/* Base size may exceed this instruction's size. Extract the
relevant part from the buffer. */
- if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
- (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen
+ && (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
@@ -491,8 +498,8 @@ print_insn (cd, pc, info, buf, buflen)
/* Make sure the entire insn is loaded into insn_value, if it
can fit. */
- if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize &&
- (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ if ((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize
+ && ((unsigned) CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
{
unsigned long full_insn_value;
int rc = read_insn (cd, pc, info, buf,
@@ -530,7 +537,9 @@ print_insn (cd, pc, info, buf, buflen)
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
-#endif
+
+static int default_print_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
static int
default_print_insn (cd, pc, info)
@@ -561,6 +570,7 @@ default_print_insn (cd, pc, info)
return print_insn (cd, pc, info, buf, buflen);
}
+#endif
/* Main entry point.
Print one instruction from PC on INFO->STREAM.
diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c
index befebe9..3541f71 100644
--- a/opcodes/m32r-ibld.c
+++ b/opcodes/m32r-ibld.c
@@ -58,7 +58,18 @@ static int extract_insn_normal
CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
static void put_insn_int_value
PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
-
+const char * m32r_cgen_insert_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+int m32r_cgen_extract_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+int m32r_cgen_get_int_operand
+ PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+bfd_vma m32r_cgen_get_vma_operand
+ PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+void m32r_cgen_set_int_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
+void m32r_cgen_set_vma_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
/* Operand insertion. */
@@ -797,7 +808,7 @@ cgen_extract_fn * const m32r_cgen_extract_handlers[] =
int
m32r_cgen_get_int_operand (cd, opindex, fields)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
{
@@ -887,7 +898,7 @@ m32r_cgen_get_int_operand (cd, opindex, fields)
bfd_vma
m32r_cgen_get_vma_operand (cd, opindex, fields)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
{
@@ -982,7 +993,7 @@ m32r_cgen_get_vma_operand (cd, opindex, fields)
void
m32r_cgen_set_int_operand (cd, opindex, fields, value)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
int value;
@@ -1068,7 +1079,7 @@ m32r_cgen_set_int_operand (cd, opindex, fields, value)
void
m32r_cgen_set_vma_operand (cd, opindex, fields, value)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
bfd_vma value;
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c
index 12491d7..5793ad6 100644
--- a/opcodes/m32r-opc.c
+++ b/opcodes/m32r-opc.c
@@ -33,10 +33,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int asm_hash_insn PARAMS ((const char *));
+static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
/* Instruction formats. */
@@ -1601,7 +1602,7 @@ static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] =
static int
asm_hash_insn_p (insn)
- const CGEN_INSN *insn;
+ const CGEN_INSN *insn ATTRIBUTE_UNUSED;
{
return CGEN_ASM_HASH_P (insn);
}
@@ -1652,7 +1653,7 @@ asm_hash_insn (mnem)
static unsigned int
dis_hash_insn (buf, value)
const char * buf;
- CGEN_INSN_INT value;
+ CGEN_INSN_INT value ATTRIBUTE_UNUSED;
{
return CGEN_DIS_HASH (buf, value);
}
diff --git a/opcodes/m32r-opinst.c b/opcodes/m32r-opinst.c
index aaaa1c0..781f8e7 100644
--- a/opcodes/m32r-opinst.c
+++ b/opcodes/m32r-opinst.c
@@ -36,9 +36,9 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#else
#define OP_ENT(op) M32R_OPERAND_/**/op
#endif
-#define INPUT CGEN_OPINST_INPUT
-#define OUTPUT CGEN_OPINST_OUTPUT
-#define END CGEN_OPINST_END
+#define INPUT CGEN_OPINST_INPUT
+#define OUTPUT CGEN_OPINST_OUTPUT
+#define END CGEN_OPINST_END, "", 0, 0, 0, 0, 0
#define COND_REF CGEN_OPINST_COND_REF
static const CGEN_OPINST sfmt_empty_ops[] = {
diff --git a/opcodes/ns32k-dis.c b/opcodes/ns32k-dis.c
index 53367ab..49facb3 100644
--- a/opcodes/ns32k-dis.c
+++ b/opcodes/ns32k-dis.c
@@ -635,20 +635,20 @@ print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
break;
case 'W':
Ivalue = bit_extract (buffer, *aoffsetp, 16);
- flip_bytes (&Ivalue, 2);
+ flip_bytes ((char *) & Ivalue, 2);
*aoffsetp += 16;
Ivalue = sign_extend (Ivalue, 16);
sprintf (result, "$%d", Ivalue);
break;
case 'D':
Ivalue = bit_extract (buffer, *aoffsetp, 32);
- flip_bytes (&Ivalue, 4);
+ flip_bytes ((char *) & Ivalue, 4);
*aoffsetp += 32;
sprintf (result, "$%d", Ivalue);
break;
case 'F':
bit_copy (buffer, *aoffsetp, 32, (char *) &Fvalue);
- flip_bytes (&Fvalue, 4);
+ flip_bytes ((char *) & Fvalue, 4);
*aoffsetp += 32;
if (INVALID_FLOAT (&Fvalue, 4))
sprintf (result, "<<invalid float 0x%.8x>>", *(int *) &Fvalue);
@@ -657,7 +657,7 @@ print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset)
break;
case 'L':
bit_copy (buffer, *aoffsetp, 64, (char *) &Lvalue);
- flip_bytes (&Lvalue, 8);
+ flip_bytes ((char *) & Lvalue, 8);
*aoffsetp += 64;
if (INVALID_FLOAT (&Lvalue, 8))
sprintf (result, "<<invalid long 0x%.8x%.8x>>",
@@ -840,13 +840,13 @@ get_displacement (buffer, aoffsetp)
break;
case 0x80:
Ivalue2 = bit_extract (buffer, *aoffsetp, 16);
- flip_bytes (&Ivalue2, 2);
+ flip_bytes ((char *) & Ivalue2, 2);
Ivalue = sign_extend (Ivalue2, 14);
*aoffsetp += 16;
break;
case 0xc0:
Ivalue = bit_extract (buffer, *aoffsetp, 32);
- flip_bytes (&Ivalue, 4);
+ flip_bytes ((char *) & Ivalue, 4);
Ivalue = sign_extend (Ivalue, 30);
*aoffsetp += 32;
break;
diff --git a/opcodes/openrisc-asm.c b/opcodes/openrisc-asm.c
index 5dc75a8..93e21f0 100644
--- a/opcodes/openrisc-asm.c
+++ b/opcodes/openrisc-asm.c
@@ -35,6 +35,7 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "openrisc-opc.h"
#include "opintl.h"
#include "xregex.h"
+#include "libiberty.h"
#undef min
#define min(a,b) ((a) < (b) ? (a) : (b))
@@ -43,6 +44,14 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
static const char * parse_insn_normal
PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+long openrisc_sign_extend_16bit
+ PARAMS ((long));
+static const char * parse_hi16
+ PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * parse_lo16
+ PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+const char * openrisc_cgen_parse_operand
+ PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
/* -- assembler routines inserted here */
@@ -181,7 +190,7 @@ openrisc_cgen_parse_operand (cd, opindex, strp, fields)
{
const char * errmsg = NULL;
/* Used by scalar operands that still need to be parsed. */
- long junk;
+ long junk ATTRIBUTE_UNUSED;
switch (opindex)
{
@@ -276,7 +285,7 @@ char *
openrisc_cgen_build_insn_regex (insn)
CGEN_INSN *insn;
{
- CGEN_OPCODE *opc = CGEN_INSN_OPCODE (insn);
+ CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
int mnem_len;
char rxbuf[CGEN_MAX_RX_ELEMENTS];
diff --git a/opcodes/openrisc-desc.c b/opcodes/openrisc-desc.c
index f9605e6..b56cab6 100644
--- a/opcodes/openrisc-desc.c
+++ b/opcodes/openrisc-desc.c
@@ -34,6 +34,13 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "opintl.h"
#include "libiberty.h"
+static void init_tables PARAMS ((void));
+static const CGEN_MACH * lookup_mach_via_bfd_name PARAMS ((const CGEN_MACH *, const char *));
+static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
+static void openrisc_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
/* Attributes. */
static const CGEN_ATTR_ENTRY bool_attr[] =
diff --git a/opcodes/openrisc-dis.c b/opcodes/openrisc-dis.c
index 64cab8e..cf9a24f 100644
--- a/opcodes/openrisc-dis.c
+++ b/opcodes/openrisc-dis.c
@@ -51,6 +51,10 @@ static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma,
disassemble_info *, char *, int));
static int default_print_insn
PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+void openrisc_cgen_print_operand
+ PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int));
+static int read_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, unsigned long *));
/* -- disassembler routines inserted here */
@@ -77,7 +81,7 @@ openrisc_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
int opindex;
PTR xinfo;
CGEN_FIELDS *fields;
- void const *attrs;
+ void const *attrs ATTRIBUTE_UNUSED;
bfd_vma pc;
int length;
{
@@ -288,7 +292,7 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
Returns 0 if all is well, non-zero otherwise. */
static int
read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
bfd_vma pc;
disassemble_info *info;
char *buf;
@@ -367,7 +371,7 @@ print_insn (cd, pc, info, buf, buflen)
/* Base size may exceed this instruction's size. Extract the
relevant part from the buffer. */
if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
- (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ ((unsigned) CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
@@ -382,8 +386,8 @@ print_insn (cd, pc, info, buf, buflen)
/* Make sure the entire insn is loaded into insn_value, if it
can fit. */
- if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize &&
- (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ if ( (unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize &&
+ ((unsigned) CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
{
unsigned long full_insn_value;
int rc = read_insn (cd, pc, info, buf,
diff --git a/opcodes/openrisc-ibld.c b/opcodes/openrisc-ibld.c
index c828aba..126311a 100644
--- a/opcodes/openrisc-ibld.c
+++ b/opcodes/openrisc-ibld.c
@@ -59,7 +59,18 @@ static int extract_insn_normal
CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
static void put_insn_int_value
PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
-
+const char * openrisc_cgen_insert_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+int openrisc_cgen_extract_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+int openrisc_cgen_get_int_operand
+ PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+bfd_vma openrisc_cgen_get_vma_operand
+ PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+void openrisc_cgen_set_int_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
+void openrisc_cgen_set_vma_operand
+ PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
/* Operand insertion. */
@@ -703,6 +714,8 @@ openrisc_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_i16_2);
if (length <= 0) break;
{
+ extern long openrisc_sign_extend_16bit PARAMS ((long));
+
FLD (f_i16nc) = openrisc_sign_extend_16bit (((((FLD (f_i16_2)) << (11))) | (FLD (f_i16_1))));
}
}
@@ -741,7 +754,7 @@ cgen_extract_fn * const openrisc_cgen_extract_handlers[] =
int
openrisc_cgen_get_int_operand (cd, opindex, fields)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
{
@@ -801,7 +814,7 @@ openrisc_cgen_get_int_operand (cd, opindex, fields)
bfd_vma
openrisc_cgen_get_vma_operand (cd, opindex, fields)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
{
@@ -866,7 +879,7 @@ openrisc_cgen_get_vma_operand (cd, opindex, fields)
void
openrisc_cgen_set_int_operand (cd, opindex, fields, value)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
int value;
@@ -923,7 +936,7 @@ openrisc_cgen_set_int_operand (cd, opindex, fields, value)
void
openrisc_cgen_set_vma_operand (cd, opindex, fields, value)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
bfd_vma value;
diff --git a/opcodes/openrisc-opc.c b/opcodes/openrisc-opc.c
index c0b2869..12ca306 100644
--- a/opcodes/openrisc-opc.c
+++ b/opcodes/openrisc-opc.c
@@ -35,10 +35,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int asm_hash_insn PARAMS ((const char *));
+static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
/* Instruction formats. */
@@ -594,7 +595,7 @@ static const CGEN_OPCODE openrisc_cgen_macro_insn_opcode_table[] =
static int
asm_hash_insn_p (insn)
- const CGEN_INSN *insn;
+ const CGEN_INSN *insn ATTRIBUTE_UNUSED;
{
return CGEN_ASM_HASH_P (insn);
}
@@ -645,7 +646,7 @@ asm_hash_insn (mnem)
static unsigned int
dis_hash_insn (buf, value)
const char * buf;
- CGEN_INSN_INT value;
+ CGEN_INSN_INT value ATTRIBUTE_UNUSED;
{
return CGEN_DIS_HASH (buf, value);
}
diff --git a/opcodes/pdp11-dis.c b/opcodes/pdp11-dis.c
index e13c7aa..3c75c48 100644
--- a/opcodes/pdp11-dis.c
+++ b/opcodes/pdp11-dis.c
@@ -15,6 +15,7 @@ You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+#include "sysdep.h"
#include "dis-asm.h"
#include "opcode/pdp11.h"
diff --git a/opcodes/tic54x-dis.c b/opcodes/tic54x-dis.c
index 1db79e8..75bebf3 100644
--- a/opcodes/tic54x-dis.c
+++ b/opcodes/tic54x-dis.c
@@ -197,7 +197,8 @@ print_instruction (info, memaddr, opcode, tm_name, tm_operands, size, ext)
/* string storage for multiple operands */
char operand[4][64] = { {0},{0},{0},{0}, };
bfd_byte buf[2];
- unsigned long opcode2, lkaddr;
+ unsigned long opcode2 = 0;
+ unsigned long lkaddr = 0;
enum optype src = OP_None;
enum optype dst = OP_None;
int i, shift;
diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index b77a280..43ce2f1 100644
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -34,42 +34,28 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* two-word opcodes */
#define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16))
-static long unsigned int insert_d9
- PARAMS ((long unsigned int, long int, const char **));
-static long unsigned int extract_d9
- PARAMS ((long unsigned int, int *));
-static long unsigned int insert_d22
- PARAMS ((long unsigned int, long int, const char **));
-static long unsigned int extract_d22
- PARAMS ((long unsigned int, int *));
-static long unsigned int insert_d16_15
- PARAMS ((long unsigned int, long int, const char **));
-static long unsigned int extract_d16_15
- PARAMS ((long unsigned int, int *));
-static long unsigned int insert_d8_7
- PARAMS ((long unsigned int, long int, const char **));
-static long unsigned int extract_d8_7 PARAMS ((long unsigned int, int *));
-static long unsigned int insert_d8_6
- PARAMS ((long unsigned int, long int, const char **));
-static long unsigned int extract_d8_6 PARAMS ((long unsigned int, int *));
-static long unsigned int insert_d5_4
- PARAMS ((long unsigned int, long int, const char **));
-static long unsigned int extract_d5_4 PARAMS ((long unsigned int, int *));
-static long unsigned int insert_d16_16
- PARAMS ((long unsigned int, long int, const char **));
-static long unsigned int extract_d16_16 PARAMS ((long unsigned int, int *));
-static long unsigned int insert_i9
- PARAMS ((long unsigned int, long int, const char **));
-static long unsigned int extract_i9 PARAMS ((long unsigned int, int *));
-static long unsigned int insert_u9
- PARAMS ((long unsigned int, long unsigned int, const char **));
-static long unsigned int extract_u9 PARAMS ((long unsigned int, int *));
-static long unsigned int insert_spe
- PARAMS ((long unsigned int, long unsigned int, const char **));
-static long unsigned int extract_spe PARAMS ((long unsigned int, int *));
-static long unsigned int insert_i5div
- PARAMS ((long unsigned int, long unsigned int, const char **));
-static long unsigned int extract_i5div PARAMS ((long unsigned int, int *));
+static long unsigned insert_d9 PARAMS ((long unsigned, long, const char **));
+static long unsigned extract_d9 PARAMS ((long unsigned, int *));
+static long unsigned insert_d22 PARAMS ((long unsigned, long, const char **));
+static long unsigned extract_d22 PARAMS ((long unsigned, int *));
+static long unsigned insert_d16_15 PARAMS ((long unsigned, long, const char **));
+static long unsigned extract_d16_15 PARAMS ((long unsigned, int *));
+static long unsigned insert_d8_7 PARAMS ((long unsigned, long, const char **));
+static long unsigned extract_d8_7 PARAMS ((long unsigned, int *));
+static long unsigned insert_d8_6 PARAMS ((long unsigned, long, const char **));
+static long unsigned extract_d8_6 PARAMS ((long unsigned, int *));
+static long unsigned insert_d5_4 PARAMS ((long unsigned, long, const char **));
+static long unsigned extract_d5_4 PARAMS ((long unsigned, int *));
+static long unsigned insert_d16_16 PARAMS ((long unsigned, long, const char **));
+static long unsigned extract_d16_16 PARAMS ((long unsigned, int *));
+static long unsigned insert_i9 PARAMS ((long unsigned, long, const char **));
+static long unsigned extract_i9 PARAMS ((long unsigned, int *));
+static long unsigned insert_u9 PARAMS ((long unsigned, long, const char **));
+static long unsigned extract_u9 PARAMS ((long unsigned, int *));
+static long unsigned insert_spe PARAMS ((long unsigned, long, const char **));
+static long unsigned extract_spe PARAMS ((long unsigned, int *));
+static long unsigned insert_i5div PARAMS ((long unsigned, long, const char **));
+static long unsigned extract_i5div PARAMS ((long unsigned, int *));
/* The functions used to insert and extract complicated operands. */
@@ -322,11 +308,12 @@ extract_i9 (insn, invalid)
}
static unsigned long
-insert_u9 (insn, value, errmsg)
+insert_u9 (insn, v, errmsg)
unsigned long insn;
- unsigned long value;
+ long v;
const char ** errmsg;
{
+ unsigned long value = (unsigned long) v;
if (value > 0x1ff)
* errmsg = _(immediate_out_of_range);
@@ -348,11 +335,13 @@ extract_u9 (insn, invalid)
}
static unsigned long
-insert_spe (insn, value, errmsg)
+insert_spe (insn, v, errmsg)
unsigned long insn;
- unsigned long value;
+ long v;
const char ** errmsg;
{
+ unsigned long value = (unsigned long) v;
+
if (value != 3)
* errmsg = _("invalid register for stack adjustment");
@@ -368,11 +357,13 @@ extract_spe (insn, invalid)
}
static unsigned long
-insert_i5div (insn, value, errmsg)
+insert_i5div (insn, v, errmsg)
unsigned long insn;
- unsigned long value;
+ long v;
const char ** errmsg;
{
+ unsigned long value = (unsigned long) v;
+
if (value > 0x1ff)
{
if (value & 1)
@@ -405,7 +396,7 @@ extract_i5div (insn, invalid)
/* Warning: code in gas/config/tc-v850.c examines the contents of this array.
If you change any of the values here, be sure to look for side effects in
- that code. */
+ that code. */
const struct v850_operand v850_operands[] =
{
#define UNUSED 0
diff --git a/opcodes/vax-dis.c b/opcodes/vax-dis.c
index 9c9be01..db39bfa 100644
--- a/opcodes/vax-dis.c
+++ b/opcodes/vax-dis.c
@@ -112,7 +112,7 @@ print_insn_vax (memaddr, info)
disassemble_info *info;
{
const struct vot *votp;
- const char *argp = NULL;
+ const char *argp;
unsigned char *arg;
struct private priv;
bfd_byte *buffer = priv.the_buffer;
@@ -120,12 +120,14 @@ print_insn_vax (memaddr, info)
info->private_data = (PTR) &priv;
priv.max_fetched = priv.the_buffer;
priv.insn_start = memaddr;
+
if (setjmp (priv.bailout) != 0)
{
/* Error return. */
return -1;
}
+ argp = NULL;
/* Check if the info buffer has more than one byte left since
the last opcode might be a single byte with no argument data. */
if (info->buffer_length - (memaddr - info->buffer_vma) > 1)
diff --git a/opcodes/w65-opc.h b/opcodes/w65-opc.h
index a6e17df..25be2e9 100644
--- a/opcodes/w65-opc.h
+++ b/opcodes/w65-opc.h
@@ -402,7 +402,7 @@ struct opinfo optable[257]={
{0x42, O_wdm, "wdm", ADDR_IMPLIED},
{0xEB, O_xba, "xba", ADDR_IMPLIED},
{0xFB, O_xce, "xce", ADDR_IMPLIED},
- { 0 }
+ { 0, 0, NULL, 0 }
};
#endif
#define DISASM()\
diff --git a/opcodes/z8k-opc.h b/opcodes/z8k-opc.h
index 80c8c82..c62867c 100644
--- a/opcodes/z8k-opc.h
+++ b/opcodes/z8k-opc.h
@@ -248,7 +248,7 @@ int flags;
#endif
char *name;
unsigned char opcode;
-void (*func)();
+void (*func) PARAMS ((void));
unsigned int arg_info[4];
unsigned int byte_info[10];
int noperands;
diff --git a/opcodes/z8kgen.c b/opcodes/z8kgen.c
index b565f3c..f171724 100644
--- a/opcodes/z8kgen.c
+++ b/opcodes/z8kgen.c
@@ -1227,7 +1227,7 @@ gas ()
printf ("#endif\n");
printf ("char *name;\n");
printf ("unsigned char opcode;\n");
- printf ("void (*func)();\n");
+ printf ("void (*func) PARAMS ((void));\n");
printf ("unsigned int arg_info[4];\n");
printf ("unsigned int byte_info[%d];\n", BYTE_INFO_LEN);
printf ("int noperands;\n");
generated by cgit v1.1 at 2024-11-23 09:05:38 +0000