diff options
| -rw-r--r-- | include/opcode/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/mips.h | 12 |
2 files changed, 15 insertions, 2 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index b9b5c81..0b9420a 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,7 +1,12 @@ +Wed Feb 15 12:19:52 1995 Ian Lance Taylor <ian@cygnus.com> + + * mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define. + start-sanitize-arc Mon Feb 13 11:05:00 1995 Doug Evans <dje@canuck.cygnus.com> * arc.h (ARC_OPERAND_LIMM): New flag. + (ARC_OPERAND_ADDRESS): Likewise. Thu Feb 9 18:55:59 1995 Doug Evans <dje@canuck.cygnus.com> diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 5579099..6645828 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -218,14 +218,18 @@ struct mips_opcode #define INSN_WRITE_HI 0x01000000 /* Modifies the LO register. */ #define INSN_WRITE_LO 0x02000000 -/* Instruction stores value into memory. */ -#define INSN_STORE_MEMORY 0x04000000 /* Takes a trap (easier to keep out of delay slot). */ #define INSN_TRAP 0x04000000 +/* Instruction stores value into memory. */ +#define INSN_STORE_MEMORY 0x08000000 +/* MIPS ISA field--CPU level at which insn is supported. */ +#define INSN_ISA 0x70000000 /* MIPS ISA 2 instruction (R6000 or R4000). */ #define INSN_ISA2 0x10000000 /* MIPS ISA 3 instruction (R4000). */ #define INSN_ISA3 0x20000000 +/* MIPS R4650 instruction. */ +#define INSN_4650 0x30000000 /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ @@ -425,6 +429,8 @@ enum { M_TNE_I, M_TRUNCWD, M_TRUNCWS, + M_ULD, + M_ULD_A, M_ULH, M_ULH_A, M_ULHU, @@ -435,6 +441,8 @@ enum { M_USH_A, M_USW, M_USW_A, + M_USD, + M_USD_A, M_XOR_I }; |