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-rw-r--r--binutils/ChangeLog5
-rw-r--r--binutils/NEWS4
-rw-r--r--binutils/doc/binutils.texi12
-rw-r--r--gas/ChangeLog8
-rw-r--r--gas/config/tc-ppc.c20
-rw-r--r--gas/doc/as.texinfo3
-rw-r--r--gas/doc/c-ppc.texi5
-rw-r--r--gas/testsuite/ChangeLog9
-rw-r--r--gas/testsuite/gas/ppc/booke.d182
-rw-r--r--gas/testsuite/gas/ppc/booke.s118
-rw-r--r--gas/testsuite/gas/ppc/booke_xcoff.d4
-rw-r--r--gas/testsuite/gas/ppc/booke_xcoff.s2
-rw-r--r--gas/testsuite/gas/ppc/booke_xcoff64.d4
-rw-r--r--gas/testsuite/gas/ppc/booke_xcoff64.s2
-rw-r--r--opcodes/ChangeLog10
-rw-r--r--opcodes/ppc-dis.c4
-rw-r--r--opcodes/ppc-opc.c176
17 files changed, 97 insertions, 471 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index db2a7e0..6892138 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,8 @@
+2008-12-04 Ben Elliston <bje@au.ibm.com>
+
+ * doc/binutils.texi (objdump): Update booke documentation.
+ * NEWS: Document user-visible changes to command line options.
+
2008-12-04 Nick Clifton <nickc@redhat.com>
* objdump.c (dump_reloc_set): Append "()" to symbol names which
diff --git a/binutils/NEWS b/binutils/NEWS
index 9b0298f..f31446a 100644
--- a/binutils/NEWS
+++ b/binutils/NEWS
@@ -1,5 +1,9 @@
-*- text -*-
+* Support for PowerPC booke64 instructions has been removed. The assembler no
+ longer accepts -mbooke32 or -mbooke64 and the disassembler no longer accepts
+ -Mbooke32 or -Mbooke64. Instead, -mbooke and -Mbooke should be used.
+
Changes in 2.19:
* Added -wL switch to dump decoded contents of .debug_line.
diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi
index 100b0f5..4c1f024 100644
--- a/binutils/doc/binutils.texi
+++ b/binutils/doc/binutils.texi
@@ -1843,12 +1843,12 @@ option string. Lastly, @option{suffix}, when in AT&T mode,
instructs the disassembler to print a mnemonic suffix even when the
suffix could be inferred by the operands.
-For PPC, @option{booke}, @option{booke32} and @option{booke64} select
-disassembly of BookE instructions. @option{32} and @option{64} select
-PowerPC and PowerPC64 disassembly, respectively. @option{e300}
-selects disassembly for the e300 family. @option{440} selects
-disassembly for the PowerPC 440. @option{ppcps} selects disassembly
-for the paired single instructions of the PPC750CL.
+For PowerPC, @option{booke} controls the disassembly of BookE
+instructions. @option{32} and @option{64} select PowerPC and
+PowerPC64 disassembly, respectively. @option{e300} selects
+disassembly for the e300 family. @option{440} selects disassembly for
+the PowerPC 440. @option{ppcps} selects disassembly for the paired
+single instructions of the PPC750CL.
For MIPS, this option controls the printing of instruction mnemonic
names and register names in disassembled instructions. Multiple
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 004a620..cde9b85 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2008-12-04 Ben Elliston <bje@au.ibm.com>
+
+ * config/tc-ppc.c (parse_cpu): Remove booke64 support. Update
+ usage strings.
+ (ppc_setup_opcodes): Likewise, remove booke64 support.
+ * doc/c-ppc.texi (PowerPC-Opts): Remove -mbooke32 and -mbooke64.
+ * doc/as.texinfo (Overview): Likewise.
+
2008-12-04 Nick Clifton <nickc@redhat.com>
* doc/as.texinfo (Type): Reword description of STT_IFUNC type.
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 648ed72..cf67a01 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -919,12 +919,6 @@ parse_cpu (const char *arg)
{
ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32;
}
- /* -mbooke64 means enable 64-bit BookE support. */
- else if (strcmp (arg, "booke64") == 0)
- {
- ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE
- | PPC_OPCODE_BOOKE64 | PPC_OPCODE_64);
- }
else if (strcmp (arg, "power4") == 0)
{
ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
@@ -1149,8 +1143,7 @@ PowerPC options:\n\
fprintf (stream, _("\
-mppc64, -m620 generate code for PowerPC 620/625/630\n\
-mppc64bridge generate code for PowerPC 64, including bridge insns\n\
--mbooke64 generate code for 64-bit PowerPC BookE\n\
--mbooke, mbooke32 generate code for 32-bit PowerPC BookE\n\
+-mbooke generate code for 32-bit PowerPC BookE\n\
-mpower4 generate code for Power4 architecture\n\
-mpower5 generate code for Power5 architecture\n\
-mpower6 generate code for Power6 architecture\n\
@@ -1359,8 +1352,7 @@ ppc_setup_opcodes (void)
There are also cases where the table needs to be out
of order to disassemble the correct instruction for
- processor variants. eg. "lhae" booke64 insn must be
- found before "ld" ppc64 insn. */
+ processor variants. */
else if (0)
{
unsigned long t1 = op[0].opcode;
@@ -1420,14 +1412,6 @@ ppc_setup_opcodes (void)
|| ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64))
== (ppc_cpu & (PPC_OPCODE_32 | PPC_OPCODE_64)))
|| (ppc_cpu & PPC_OPCODE_64_BRIDGE) != 0)
- /* Certain instructions (eg: extsw) do not exist in the
- 32-bit BookE instruction set, but they do exist in the
- 64-bit BookE instruction set, and other PPC instruction
- sets. Check to see if the opcode has the BOOKE64 flag set.
- If it does make sure that the target CPU is not the BookE32. */
- && ((op->flags & PPC_OPCODE_BOOKE64) == 0
- || (ppc_cpu & PPC_OPCODE_BOOKE64) == PPC_OPCODE_BOOKE64
- || (ppc_cpu & PPC_OPCODE_BOOKE) == 0)
&& ((ppc_cpu & PPC_OPCODE_POWER4) == 0
|| (op->flags & PPC_OPCODE_NOPOWER4) == 0))
{
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index a5d936b..d1f60dd 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -409,8 +409,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
@emph{Target PowerPC options:}
[@b{-mpwrx}|@b{-mpwr2}|@b{-mpwr}|@b{-m601}|@b{-mppc}|@b{-mppc32}|@b{-m603}|@b{-m604}|
- @b{-m403}|@b{-m405}|@b{-mppc64}|@b{-m620}|@b{-mppc64bridge}|@b{-mbooke}|
- @b{-mbooke32}|@b{-mbooke64}]
+ @b{-m403}|@b{-m405}|@b{-mppc64}|@b{-m620}|@b{-mppc64bridge}|@b{-mbooke}]
[@b{-mcom}|@b{-many}|@b{-maltivec}|@b{-mvsx}] [@b{-memb}]
[@b{-mregnames}|@b{-mno-regnames}]
[@b{-mrelocatable}|@b{-mrelocatable-lib}]
diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi
index bc65685..70877cd 100644
--- a/gas/doc/c-ppc.texi
+++ b/gas/doc/c-ppc.texi
@@ -70,10 +70,7 @@ Generate code for Motorola SPE instructions.
@item -mppc64bridge
Generate code for PowerPC 64, including bridge insns.
-@item -mbooke64
-Generate code for 64-bit BookE.
-
-@item -mbooke, mbooke32
+@item -mbooke
Generate code for 32-bit BookE.
@item -me300
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 523275a..3335301 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2008-12-04 Ben Elliston <bje@au.ibm.com>
+
+ * gas/ppc/booke.s: Remove booke64 instructions.
+ * gas/ppc/booke.d: Update expected disassembly output.
+ * gas/ppc/booke_xcoff.s: Use -mbooke/-Mbooke.
+ * gas/ppc/booke_xcoff.d: Likewise.
+ * gas/ppc/booke_xcoff64.d: Likewise.
+ * gas/ppc/booke_xcoff64.s: Likewise.
+
2008-12-03 Nick Clifton <nickc@redhat.com>
* gas/elf/type.s: Add test of STT_IFUNC symbol type.
diff --git a/gas/testsuite/gas/ppc/booke.d b/gas/testsuite/gas/ppc/booke.d
index b07033f..403fa3f 100644
--- a/gas/testsuite/gas/ppc/booke.d
+++ b/gas/testsuite/gas/ppc/booke.d
@@ -1,4 +1,4 @@
-#as: -mbooke64
+#as: -mbooke
#objdump: -dr -Mbooke
#name: BookE tests
@@ -6,151 +6,35 @@
Disassembly of section \.text:
-0+0000000 <start>:
- 0: 24 25 00 30 bce 1,4\*cr1\+gt,30 <branch_target_1>
- 4: 24 46 00 3d bcel 2,4\*cr1\+eq,40 <branch_target_2>
- 8: 24 67 00 52 bcea 3,4\*cr1\+so,50 <branch_target_3>
- 8: R_PPC(64)?_ADDR14 \.text\+0x50
- c: 24 88 00 73 bcela 4,4\*cr2\+lt,70 <branch_target_4>
- c: R_PPC(64)?_ADDR14 \.text\+0x70
- 10: 4c a9 00 22 bclre 5,4\*cr2\+gt
- 14: 4c aa 00 23 bclrel 5,4\*cr2\+eq
- 18: 4d 0b 04 22 bcctre 8,4\*cr2\+so
- 1c: 4d 0c 04 23 bcctrel 8,4\*cr3\+lt
- 20: 58 00 00 74 be 94 <branch_target_5>
- 24: 58 00 00 89 bel ac <branch_target_6>
- 28: 58 00 00 f6 bea f4 <branch_target_7>
- 28: R_PPC(64)?_ADDR24 \.text\+0xf4
- 2c: 58 00 01 2b bela 128 <branch_target_8>
- 2c: R_PPC(64)?_ADDR24 \.text\+0x128
-
-0+0000030 <branch_target_1>:
- 30: e9 09 00 80 lbze r8,8\(r9\)
- 34: e9 8f 00 41 lbzue r12,4\(r15\)
- 38: 7c 86 40 fe lbzuxe r4,r6,r8
- 3c: 7c 65 38 be lbzxe r3,r5,r7
-
-0+0000040 <branch_target_2>:
- 40: f8 a6 06 40 lde r5,400\(r6\)
- 44: f8 c7 07 11 ldue r6,452\(r7\)
- 48: 7c e8 4e 3e ldxe r7,r8,r9
- 4c: 7d 4b 66 7e lduxe r10,r11,r12
-
-0+0000050 <branch_target_3>:
- 50: f9 81 02 06 lfde f12,128\(r1\)
- 54: f8 25 00 47 lfdue f1,16\(r5\)
- 58: 7c a1 1c be lfdxe f5,r1,r3
- 5c: 7c c2 24 fe lfduxe f6,r2,r4
- 60: f9 09 00 c4 lfse f8,48\(r9\)
- 64: f9 2a 01 15 lfsue f9,68\(r10\)
- 68: 7d 44 44 7e lfsuxe f10,r4,r8
- 6c: 7d 23 3c 3e lfsxe f9,r3,r7
-
-0+0000070 <branch_target_4>:
- 70: e9 45 03 24 lhae r10,50\(r5\)
- 74: e8 23 00 55 lhaue r1,5\(r3\)
- 78: 7c a1 1a fe lhauxe r5,r1,r3
- 7c: 7f be fa be lhaxe r29,r30,r31
- 80: 7c 22 1e 3c lhbrxe r1,r2,r3
- 84: e8 83 01 22 lhze r4,18\(r3\)
- 88: e8 c9 01 43 lhzue r6,20\(r9\)
- 8c: 7c a7 4a 7e lhzuxe r5,r7,r9
- 90: 7d 27 2a 3e lhzxe r9,r7,r5
-
-0+0000094 <branch_target_5>:
- 94: 7d 4f a0 fc lwarxe r10,r15,r20
- 98: 7c aa 94 3c lwbrxe r5,r10,r18
- 9c: eb 9d 00 46 lwze r28,4\(r29\)
- a0: e9 0a 02 87 lwzue r8,40\(r10\)
- a4: 7c 66 48 7e lwzuxe r3,r6,r9
- a8: 7f dd e0 3e lwzxe r30,r29,r28
-
-0+00000ac <branch_target_6>:
- ac: 7c 06 3d fc dcbae r6,r7
- b0: 7c 08 48 bc dcbfe r8,r9
- b4: 7c 0a 5b bc dcbie r10,r11
- b8: 7c 08 f0 7c dcbste r8,r30
- bc: 7c c3 0a 3c dcbte 6,r3,r1
- c0: 7c a4 11 fa dcbtste 5,r4,r2
- c4: 7c 0f 77 fc dcbze r15,r14
- c8: 7c 03 27 bc icbie r3,r4
- cc: 7c a8 48 2c icbt 5,r8,r9
- d0: 7c ca 78 3c icbte 6,r10,r15
- d4: 7c a6 02 26 mfapidi r5,r6
- d8: 7c 07 46 24 tlbivax r7,r8
- dc: 7c 09 56 26 tlbivaxe r9,r10
- e0: 7c 0b 67 24 tlbsx r11,r12
- e4: 7c 0d 77 26 tlbsxe r13,r14
- e8: 7c 00 07 a4 tlbwe
- ec: 7c 00 07 a4 tlbwe
- f0: 7c 21 0f a4 tlbwe r1,r1,1
-
-0+00000f4 <branch_target_7>:
- f4: 7c 22 1b 14 adde64 r1,r2,r3
- f8: 7c 85 37 14 adde64o r4,r5,r6
- fc: 7c e8 03 d4 addme64 r7,r8
- 100: 7d 2a 07 d4 addme64o r9,r10
- 104: 7d 6c 03 94 addze64 r11,r12
- 108: 7d ae 07 94 addze64o r13,r14
- 10c: 7e 80 04 40 mcrxr64 cr5
- 110: 7d f0 8b 10 subfe64 r15,r16,r17
- 114: 7e 53 a7 10 subfe64o r18,r19,r20
- 118: 7e b6 03 d0 subfme64 r21,r22
- 11c: 7e f8 07 d0 subfme64o r23,r24
- 120: 7f 3a 03 90 subfze64 r25,r26
- 124: 7f 7c 07 90 subfze64o r27,r28
-
-0+0000128 <branch_target_8>:
- 128: e8 22 03 28 stbe r1,50\(r2\)
- 12c: e8 64 02 89 stbue r3,40\(r4\)
- 130: 7c a6 39 fe stbuxe r5,r6,r7
- 134: 7d 09 51 be stbxe r8,r9,r10
- 138: 7d 6c 6b ff stdcxe\. r11,r12,r13
- 13c: f9 cf 00 78 stde r14,28\(r15\)
- 140: fa 11 00 59 stdue r16,20\(r17\)
- 144: 7e 53 a7 3e stdxe r18,r19,r20
- 148: 7e b6 bf 7e stduxe r21,r22,r23
- 14c: f8 38 00 3e stfde f1,12\(r24\)
- 150: f8 59 00 0f stfdue f2,0\(r25\)
- 154: 7c 7a dd be stfdxe f3,r26,r27
- 158: 7c 9c ed fe stfduxe f4,r28,r29
- 15c: 7c be ff be stfiwxe f5,r30,r31
- 160: f8 de 00 6c stfse f6,24\(r30\)
- 164: f8 fd 00 5d stfsue f7,20\(r29\)
- 168: 7d 1c dd 3e stfsxe f8,r28,r27
- 16c: 7d 3a cd 7e stfsuxe f9,r26,r25
- 170: 7f 17 b7 3c sthbrxe r24,r23,r22
- 174: ea b4 01 ea sthe r21,30\(r20\)
- 178: ea 72 02 8b sthue r19,40\(r18\)
- 17c: 7e 30 7b 7e sthuxe r17,r16,r15
- 180: 7d cd 63 3e sthxe r14,r13,r12
- 184: 7d 6a 4d 3c stwbrxe r11,r10,r9
- 188: 7d 07 31 3d stwcxe\. r8,r7,r6
- 18c: e8 a4 03 2e stwe r5,50\(r4\)
- 190: e8 62 02 8f stwue r3,40\(r2\)
- 194: 7c 22 19 7e stwuxe r1,r2,r3
- 198: 7c 85 31 3e stwxe r4,r5,r6
- 19c: 4c 00 00 66 rfci
- 1a0: 7c 60 01 06 wrtee r3
- 1a4: 7c 00 81 46 wrteei 1
- 1a8: 7c 85 02 06 mfdcrx r4,r5
- 1ac: 7c aa 3a 86 mfdcr r5,234
- 1b0: 7c e6 03 06 mtdcrx r6,r7
- 1b4: 7d 10 6b 86 mtdcr 432,r8
- 1b8: 7c 00 04 ac msync
- 1bc: 7c 09 55 ec dcba r9,r10
- 1c0: 7c 00 06 ac mbar
- 1c4: 7c 00 06 ac mbar
- 1c8: 7c 20 06 ac mbar 1
- 1cc: 7d 8d 77 24 tlbsx r12,r13,r14
- 1d0: 7d 8d 77 25 tlbsx\. r12,r13,r14
- 1d4: 7d 8d 77 26 tlbsxe r12,r13,r14
- 1d8: 7d 8d 77 27 tlbsxe\. r12,r13,r14
- 1dc: 7c 12 42 a6 mfsprg r0,2
- 1e0: 7c 12 42 a6 mfsprg r0,2
- 1e4: 7c 12 43 a6 mtsprg 2,r0
- 1e8: 7c 12 43 a6 mtsprg 2,r0
- 1ec: 7c 07 42 a6 mfsprg r0,7
- 1f0: 7c 07 42 a6 mfsprg r0,7
- 1f4: 7c 17 43 a6 mtsprg 7,r0
- 1f8: 7c 17 43 a6 mtsprg 7,r0
+0+0000000 <branch_target_1>:
+ 0: 7c a8 48 2c icbt 5,r8,r9
+ 4: 7c a6 02 26 mfapidi r5,r6
+ 8: 7c 07 46 24 tlbivax r7,r8
+ c: 7c 0b 67 24 tlbsx r11,r12
+ 10: 7c 00 07 a4 tlbwe
+ 14: 7c 00 07 a4 tlbwe
+ 18: 7c 21 0f a4 tlbwe r1,r1,1
+
+0+000001c <branch_target_2>:
+ 1c: 4c 00 00 66 rfci
+ 20: 7c 60 01 06 wrtee r3
+ 24: 7c 00 81 46 wrteei 1
+ 28: 7c 85 02 06 mfdcrx r4,r5
+ 2c: 7c aa 3a 86 mfdcr r5,234
+ 30: 7c e6 03 06 mtdcrx r6,r7
+ 34: 7d 10 6b 86 mtdcr 432,r8
+ 38: 7c 00 04 ac msync
+ 3c: 7c 09 55 ec dcba r9,r10
+ 40: 7c 00 06 ac mbar
+ 44: 7c 00 06 ac mbar
+ 48: 7c 20 06 ac mbar 1
+ 4c: 7d 8d 77 24 tlbsx r12,r13,r14
+ 50: 7d 8d 77 25 tlbsx\. r12,r13,r14
+ 54: 7c 12 42 a6 mfsprg r0,2
+ 58: 7c 12 42 a6 mfsprg r0,2
+ 5c: 7c 12 43 a6 mtsprg 2,r0
+ 60: 7c 12 43 a6 mtsprg 2,r0
+ 64: 7c 07 42 a6 mfsprg r0,7
+ 68: 7c 07 42 a6 mfsprg r0,7
+ 6c: 7c 17 43 a6 mtsprg 7,r0
+ 70: 7c 17 43 a6 mtsprg 7,r0
diff --git a/gas/testsuite/gas/ppc/booke.s b/gas/testsuite/gas/ppc/booke.s
index fa53c01..4e51305 100644
--- a/gas/testsuite/gas/ppc/booke.s
+++ b/gas/testsuite/gas/ppc/booke.s
@@ -1,127 +1,17 @@
# Motorola PowerPC BookE tests
-#as: -mbooke32
+#as: -mbooke
.section ".text"
-start:
- bce 1, 5, branch_target_1
- bcel 2, 6, branch_target_2
- bcea 3, 7, branch_target_3
- bcela 4, 8, branch_target_4
- bclre 5, 9
- bclrel 5, 10
- bcctre 8, 11
- bcctrel 8, 12
- be branch_target_5
- bel branch_target_6
- bea branch_target_7
- bela branch_target_8
-branch_target_1:
- lbze 8, 8(9)
- lbzue 12, 4(15)
- lbzuxe 4, 6, 8
- lbzxe 3, 5, 7
-
-branch_target_2:
- lde 5, 400(6)
- ldue 6, 452(7)
- ldxe 7, 8, 9
- lduxe 10, 11, 12
-
-branch_target_3:
- lfde 12, 128(1)
- lfdue 1, 16(5)
- lfdxe 5, 1, 3
- lfduxe 6, 2, 4
- lfse 8, 48(9)
- lfsue 9, 68(10)
- lfsuxe 10, 4, 8
- lfsxe 9, 3, 7
-
-branch_target_4:
- lhae 10, 50(5)
- lhaue 1, 5(3)
- lhauxe 5, 1, 3
- lhaxe 29, 30, 31
- lhbrxe 1, 2, 3
- lhze 4, 18(3)
- lhzue 6, 20(9)
- lhzuxe 5, 7, 9
- lhzxe 9, 7, 5
-
-branch_target_5:
- lwarxe 10, 15, 20
- lwbrxe 5, 10, 18
- lwze 28, 4(29)
- lwzue 8, 40(10)
- lwzuxe 3, 6, 9
- lwzxe 30, 29, 28
-
-branch_target_6:
- dcbae 6, 7
- dcbfe 8, 9
- dcbie 10, 11
- dcbste 8, 30
- dcbte 6, 3, 1
- dcbtste 5, 4, 2
- dcbze 15, 14
- icbie 3, 4
+branch_target_1:
icbt 5, 8, 9
- icbte 6, 10, 15
mfapidi 5, 6
tlbivax 7, 8
- tlbivaxe 9, 10
tlbsx 11, 12
- tlbsxe 13, 14
tlbwe
tlbwe 0,0,0
tlbwe 1,1,1
-branch_target_7:
- adde64 1, 2, 3
- adde64o 4, 5, 6
- addme64 7, 8
- addme64o 9, 10
- addze64 11, 12
- addze64o 13, 14
- mcrxr64 5
- subfe64 15, 16, 17
- subfe64o 18, 19, 20
- subfme64 21, 22
- subfme64o 23, 24
- subfze64 25, 26
- subfze64o 27, 28
-
-branch_target_8:
- stbe 1, 50(2)
- stbue 3, 40(4)
- stbuxe 5, 6, 7
- stbxe 8, 9, 10
- stdcxe. 11, 12, 13
- stde 14, 28(15)
- stdue 16, 20(17)
- stdxe 18, 19, 20
- stduxe 21, 22, 23
- stfde 1, 12(24)
- stfdue 2, 0(25)
- stfdxe 3, 26, 27
- stfduxe 4, 28, 29
- stfiwxe 5, 30, 31
- stfse 6, 24(30)
- stfsue 7, 20(29)
- stfsxe 8, 28, 27
- stfsuxe 9, 26, 25
- sthbrxe 24, 23, 22
- sthe 21, 30(20)
- sthue 19, 40(18)
- sthuxe 17, 16, 15
- sthxe 14, 13, 12
- stwbrxe 11, 10, 9
- stwcxe. 8, 7, 6
- stwe 5, 50(4)
- stwue 3, 40(2)
- stwuxe 1, 2, 3
- stwxe 4, 5, 6
-
+branch_target_2:
rfci
wrtee 3
wrteei 1
@@ -137,8 +27,6 @@ branch_target_8:
tlbsx 12, 13, 14
tlbsx. 12, 13, 14
- tlbsxe 12, 13, 14
- tlbsxe. 12, 13, 14
mfsprg 0, 2
mfsprg2 0
diff --git a/gas/testsuite/gas/ppc/booke_xcoff.d b/gas/testsuite/gas/ppc/booke_xcoff.d
index dfb308d..fee6970 100644
--- a/gas/testsuite/gas/ppc/booke_xcoff.d
+++ b/gas/testsuite/gas/ppc/booke_xcoff.d
@@ -1,5 +1,5 @@
-#as: -mppc32 -mbooke32
-#objdump: -mpowerpc -dr -Mbooke32
+#as: -mppc32 -mbooke
+#objdump: -mpowerpc -dr -Mbooke
#name: xcoff BookE tests
.*: file format aixcoff-rs6000
diff --git a/gas/testsuite/gas/ppc/booke_xcoff.s b/gas/testsuite/gas/ppc/booke_xcoff.s
index db3578d..7475a46 100644
--- a/gas/testsuite/gas/ppc/booke_xcoff.s
+++ b/gas/testsuite/gas/ppc/booke_xcoff.s
@@ -1,5 +1,5 @@
# Motorola PowerPC BookE tests
-#as: -mbooke32
+#as: -mbooke
.csect .text[PR]
.csect main[DS]
main:
diff --git a/gas/testsuite/gas/ppc/booke_xcoff64.d b/gas/testsuite/gas/ppc/booke_xcoff64.d
index bd0e6c8..4a301bd 100644
--- a/gas/testsuite/gas/ppc/booke_xcoff64.d
+++ b/gas/testsuite/gas/ppc/booke_xcoff64.d
@@ -1,5 +1,5 @@
-#as: -a64 -mppc64 -mbooke64
-#objdump: -dr -Mbooke64
+#as: -a64 -mppc64 -mbooke
+#objdump: -dr -Mbooke
#name: xcoff64 BookE tests
.*: file format aix5?coff64-rs6000
diff --git a/gas/testsuite/gas/ppc/booke_xcoff64.s b/gas/testsuite/gas/ppc/booke_xcoff64.s
index e915703..f3f58b3 100644
--- a/gas/testsuite/gas/ppc/booke_xcoff64.s
+++ b/gas/testsuite/gas/ppc/booke_xcoff64.s
@@ -1,5 +1,5 @@
# Motorola PowerPC BookE tests
-#as: -a64 -mppc64 -mbooke64
+#as: -a64 -mppc64 -mbooke
.csect .text[PR]
.csect main[DS]
main:
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index dc62aa2..b8655d0 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2008-12-04 Ben Elliston <bje@au.ibm.com>
+
+ * ppc-dis.c (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE
+ for -Mbooke.
+ (print_ppc_disassembler_options): Update usage.
+ * ppc-opc.c (DE, DES, DEO, DE_MASK): Remove.
+ (BOOKE64): Remove.
+ (PPCCHLK64): Likewise.
+ (powerpc_opcodes): Remove all BOOKE64 instructions.
+
2008-11-28 Joshua Kinard <kumba@gentoo.org>
* mips-dis.c (mips_arch_choices): Add r14000, r16000.
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index bde4c49..061aa84 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -63,7 +63,7 @@ powerpc_init_dialect (struct disassemble_info *info)
dialect |= PPC_OPCODE_PPCPS;
else if (info->disassembler_options
&& strstr (info->disassembler_options, "booke") != NULL)
- dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
+ dialect |= PPC_OPCODE_BOOKE;
else if ((info->mach == bfd_mach_ppc_e500mc)
|| (info->disassembler_options
&& strstr (info->disassembler_options, "e500mc") != NULL))
@@ -402,7 +402,7 @@ print_ppc_disassembler_options (FILE *stream)
The following PPC specific disassembler options are supported for use with\n\
the -M switch:\n");
- fprintf (stream, " booke|booke32|booke64 Disassemble the BookE instructions\n");
+ fprintf (stream, " booke Disassemble the BookE instructions\n");
fprintf (stream, " e300 Disassemble the e300 instructions\n");
fprintf (stream, " e500|e500x2 Disassemble the e500 instructions\n");
fprintf (stream, " e500mc Disassemble the e500mc instructions\n");
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 7d05f5f..0326df3 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -223,19 +223,9 @@ const struct powerpc_operand powerpc_operands[] =
#define D CT + 1
{ 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
- /* The DE field in a DE form instruction. This is like D, but is 12
- bits only. */
-#define DE D + 1
- { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
-
- /* The DES field in a DES form instruction. This is like DS, but is 14
- bits only (12 stored.) */
-#define DES DE + 1
- { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
-
/* The DQ field in a DQ form instruction. This is like D, but the
lower four bits are forced to zero. */
-#define DQ DES + 1
+#define DQ D + 1
{ 0xfff0, 0, NULL, NULL,
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
@@ -1487,10 +1477,6 @@ extract_xb6s (unsigned long insn,
#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
#define DS_MASK DSO (0x3f, 3)
-/* A DE form instruction. */
-#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
-#define DE_MASK DEO (0x3e, 0xf)
-
/* An EVSEL form instruction. */
#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
#define EVSEL_MASK EVSEL(0x3f, 0xff)
@@ -1841,7 +1827,6 @@ extract_xb6s (unsigned long insn,
#define MFDEC1 PPC_OPCODE_POWER
#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
#define BOOKE PPC_OPCODE_BOOKE
-#define BOOKE64 PPC_OPCODE_BOOKE64
#define CLASSIC PPC_OPCODE_CLASSIC
#define PPCE300 PPC_OPCODE_E300
#define PPCSPE PPC_OPCODE_SPE
@@ -1850,7 +1835,6 @@ extract_xb6s (unsigned long insn,
#define PPCBRLK PPC_OPCODE_BRLOCK
#define PPCPMR PPC_OPCODE_PMR
#define PPCCHLK PPC_OPCODE_CACHELCK
-#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
#define PPCRFMCI PPC_OPCODE_RFMCI
#define E500MC PPC_OPCODE_E500MC
@@ -2525,11 +2509,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"dozi", OP(9), OP_MASK, M601, {RT, RA, SI}},
-{"bce", B(9,0,0), B_MASK, BOOKE64, {BO, BI, BD}},
-{"bcel", B(9,0,1), B_MASK, BOOKE64, {BO, BI, BD}},
-{"bcea", B(9,1,0), B_MASK, BOOKE64, {BO, BI, BDA}},
-{"bcela", B(9,1,1), B_MASK, BOOKE64, {BO, BI, BDA}},
-
{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, {OBF, RA, UI}},
{"cmpldi", OPL(10,1), OPL_MASK, PPC64, {OBF, RA, UI}},
{"cmpli", OP(10), OP_MASK, PPC, {BF, L, RA, UI}},
@@ -3070,9 +3049,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, {BO, BI, BH}},
{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, {BO, BI}},
-{"bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, {BO, BI}},
-{"bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, {BO, BI}},
-
{"rfid", XL(19,18), 0xffffffff, PPC64, {0}},
{"crnot", XL(19,33), XL_MASK, PPCCOM, {BT, BA, BBA}},
@@ -3272,9 +3248,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, {BO, BI, BH}},
{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, {BO, BI}},
-{"bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, {BO, BI}},
-{"bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, {BO, BI}},
-
{"rlwimi", M(20,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}},
{"rlimi", M(20,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
@@ -3291,11 +3264,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlinm.", M(21,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}},
{"rlmi", M(22,0), M_MASK, M601, {RA, RS, RB, MBE, ME}},
-{"be", B(22,0,0), B_MASK, BOOKE64, {LI}},
-{"bel", B(22,0,1), B_MASK, BOOKE64, {LI}},
{"rlmi.", M(22,1), M_MASK, M601, {RA, RS, RB, MBE, ME}},
-{"bea", B(22,1,0), B_MASK, BOOKE64, {LIA}},
-{"bela", B(22,1,1), B_MASK, BOOKE64, {LIA}},
{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, {RA, RS, RB}},
{"rlwnm", M(23,0), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}},
@@ -3441,10 +3410,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"maskg.", XRC(31,29,1), X_MASK, M601, {RA, RS, RB}},
{"ldepx", X(31,29), X_MASK, E500MC, {RT, RA, RB}},
-
-{"icbte", X(31,30), X_MASK, BOOKE64, {CT, RA, RB}},
-
-{"lwzxe", X(31,31), X_MASK, BOOKE64, {RT, RA0, RB}},
{"lwepx", X(31,31), X_MASK, E500MC, {RT, RA, RB}},
{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}},
@@ -3482,12 +3447,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"andc", XRC(31,60,0), X_MASK, COM, {RA, RS, RB}},
{"andc.", XRC(31,60,1), X_MASK, COM, {RA, RS, RB}},
-{"dcbste", X(31,62), XRT_MASK, BOOKE64, {RA, RB}},
-
{"wait", X(31,62), 0xffffffff, E500MC, {0}},
-{"lwzuxe", X(31,63), X_MASK, BOOKE64, {RT, RAL, RB}},
-
{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC, {RA, RB}},
{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, {RA, RB}},
@@ -3527,9 +3488,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lbzx", X(31,87), X_MASK, COM, {RT, RA0, RB}},
-{"dcbfe", X(31,94), XRT_MASK, BOOKE64, {RA, RB}},
-
-{"lbzxe", X(31,95), X_MASK, BOOKE64, {RT, RA0, RB}},
{"lbepx", X(31,95), X_MASK, E500MC, {RT, RA, RB}},
{"lvx", X(31,103), X_MASK, PPCVEC, {VD, RA, RB}},
@@ -3554,10 +3512,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"not.", XRC(31,124,1), X_MASK, COM, {RA, RS, RBS}},
{"nor.", XRC(31,124,1), X_MASK, COM, {RA, RS, RB}},
-{"lwarxe", X(31,126), X_MASK, BOOKE64, {RT, RA0, RB}},
-
-{"lbzuxe", X(31,127), X_MASK, BOOKE64, {RT, RAL, RB}},
-
{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC, {RA, RB}},
{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, {RS}},
@@ -3577,7 +3531,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, {RT, RA, RB}},
{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
-{"dcbtstlse", X(31,142), X_MASK, PPCCHLK64, {CT, RA, RB}},
+{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, {CT, RA, RB}},
{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, {RS}},
{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, {FXM, RS}},
@@ -3602,9 +3556,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stdepx", X(31,157), X_MASK, E500MC, {RS, RA, RB}},
-{"stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, {RS, RA0, RB}},
-
-{"stwxe", X(31,159), X_MASK, BOOKE64, {RS, RA0, RB}},
{"stwepx", X(31,159), X_MASK, E500MC, {RS, RA, RB}},
{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE, {E}},
@@ -3614,7 +3565,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stvehx", X(31,167), X_MASK, PPCVEC, {VS, RA, RB}},
{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, {FCRT, RA, RB}},
-{"dcbtlse", X(31,174), X_MASK, PPCCHLK64, {CT, RA, RB}},
+{"dcbtlse", X(31,174), X_MASK, PPCCHLK, {CT, RA, RB}},
{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, {RS, A_L}},
@@ -3628,8 +3579,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"prtyd", X(31,186), XRB_MASK, POWER6, {RA, RS}},
-{"stwuxe", X(31,191), X_MASK, BOOKE64, {RS, RAS, RB}},
-
{"stvewx", X(31,199), X_MASK, PPCVEC, {VS, RA, RB}},
{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, {FCRT, RA, RB}},
@@ -3657,7 +3606,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"sleq", XRC(31,217,0), X_MASK, M601, {RA, RS, RB}},
{"sleq.", XRC(31,217,1), X_MASK, M601, {RA, RS, RB}},
-{"stbxe", X(31,223), X_MASK, BOOKE64, {RS, RA0, RB}},
{"stbepx", X(31,223), X_MASK, E500MC, {RS, RA, RB}},
{"icblc", X(31,230), X_MASK, PPCCHLK, {CT, RA, RB}},
@@ -3684,7 +3632,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, {RT, RA, RB}},
{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC, {RB}},
-{"icblce", X(31,238), X_MASK, PPCCHLK64, {CT, RA, RB}},
+{"icblce", X(31,238), X_MASK, PPCCHLK, {CT, RA, RB}},
{"mtsrin", X(31,242), XRA_MASK, PPC32, {RS, RB}},
{"mtsri", X(31,242), XRA_MASK, POWER32, {RS, RB}},
@@ -3695,10 +3643,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"slliq", XRC(31,248,0), X_MASK, M601, {RA, RS, SH}},
{"slliq.", XRC(31,248,1), X_MASK, M601, {RA, RS, SH}},
-{"dcbtste", X(31,253), X_MASK, BOOKE64, {CT, RA, RB}},
-
-{"stbuxe", X(31,255), X_MASK, BOOKE64, {RS, RAS, RB}},
-
{"dcbtstep", XRT(31,255,0), X_MASK, E500MC, {RT, RA, RB}},
{"mfdcrx", X(31,259), X_MASK, BOOKE, {RS, RA}},
@@ -3730,9 +3674,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"eqv", XRC(31,284,0), X_MASK, COM, {RA, RS, RB}},
{"eqv.", XRC(31,284,1), X_MASK, COM, {RA, RS, RB}},
-{"dcbte", X(31,286), X_MASK, BOOKE64, {CT, RA, RB}},
-
-{"lhzxe", X(31,287), X_MASK, BOOKE64, {RT, RA0, RB}},
{"lhepx", X(31,287), X_MASK, E500MC, {RT, RA, RB}},
{"mfdcrux", X(31,291), X_MASK, PPC464, {RS, RA}},
@@ -3747,8 +3688,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"xor", XRC(31,316,0), X_MASK, COM, {RA, RS, RB}},
{"xor.", XRC(31,316,1), X_MASK, COM, {RA, RS, RB}},
-{"lhzuxe", X(31,319), X_MASK, BOOKE64, {RT, RAL, RB}},
-
{"dcbtep", XRT(31,319,0), X_MASK, E500MC, {RT, RA, RB}},
{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, {RT}},
@@ -3984,8 +3923,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lhax", X(31,343), X_MASK, COM, {RT, RA0, RB}},
-{"lhaxe", X(31,351), X_MASK, BOOKE64, {RT, RA0, RB}},
-
{"lvxl", X(31,359), X_MASK, PPCVEC, {VD, RA, RB}},
{"abs", XO(31,360,0,0), XORB_MASK, M601, {RT, RA}},
@@ -4006,18 +3943,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lhaux", X(31,375), X_MASK, COM, {RT, RAL, RB}},
-{"lhauxe", X(31,383), X_MASK, BOOKE64, {RT, RAL, RB}},
-
{"mtdcrx", X(31,387), X_MASK, BOOKE, {RA, RS}},
{"dcblc", X(31,390), X_MASK, PPCCHLK, {CT, RA, RB}},
{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, {FCRT, RA, RB}},
-{"subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, {RT, RA, RB}},
-
-{"adde64", XO(31,394,0,0), XO_MASK, BOOKE64, {RT, RA, RB}},
-
-{"dcblce", X(31,398), X_MASK, PPCCHLK64, {CT, RA, RB}},
+{"dcblce", X(31,398), X_MASK, PPCCHLK, {CT, RA, RB}},
{"slbmte", X(31,402), XRA_MASK, PPC64, {RS, RB}},
@@ -4026,7 +3957,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"orc", XRC(31,412,0), X_MASK, COM, {RA, RS, RB}},
{"orc.", XRC(31,412,1), X_MASK, COM, {RA, RS, RB}},
-{"sthxe", X(31,415), X_MASK, BOOKE64, {RS, RA0, RB}},
{"sthepx", X(31,415), X_MASK, E500MC, {RS, RA, RB}},
{"mtdcrux", X(31,419), X_MASK, PPC464, {RA, RS}},
@@ -4044,8 +3974,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mr.", XRC(31,444,1), X_MASK, COM, {RA, RS, RBS}},
{"or.", XRC(31,444,1), X_MASK, COM, {RA, RS, RB}},
-{"sthuxe", X(31,447), X_MASK, BOOKE64, {RS, RAS, RB}},
-
{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, {RS}},
{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, {RS}},
{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, {RS}},
@@ -4084,13 +4012,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, {RA, RB}},
-{"subfze64", XO(31,456,0,0), XORB_MASK, BOOKE64, {RT, RA}},
-
{"divdu", XO(31,457,0,0), XO_MASK, PPC64, {RT, RA, RB}},
{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, {RT, RA, RB}},
-{"addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, {RT, RA}},
-
{"divwu", XO(31,459,0,0), XO_MASK, PPC, {RT, RA, RB}},
{"divwu.", XO(31,459,0,1), XO_MASK, PPC, {RT, RA, RB}},
@@ -4255,8 +4179,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"nand", XRC(31,476,0), X_MASK, COM, {RA, RS, RB}},
{"nand.", XRC(31,476,1), X_MASK, COM, {RA, RS, RB}},
-{"dcbie", X(31,478), XRT_MASK, BOOKE64, {RA, RB}},
-
{"dsn", X(31,483), XRT_MASK, E500MC, {RA, RB}},
{"dcread", X(31,486), X_MASK, PPC403|PPC440, {RT, RA, RB}},
@@ -4266,18 +4188,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stvxl", X(31,487), X_MASK, PPCVEC, {VS, RA, RB}},
{"nabs", XO(31,488,0,0), XORB_MASK, M601, {RT, RA}},
-{"subfme64", XO(31,488,0,0), XORB_MASK, BOOKE64, {RT, RA}},
{"nabs.", XO(31,488,0,1), XORB_MASK, M601, {RT, RA}},
{"divd", XO(31,489,0,0), XO_MASK, PPC64, {RT, RA, RB}},
{"divd.", XO(31,489,0,1), XO_MASK, PPC64, {RT, RA, RB}},
-{"addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, {RT, RA}},
-
{"divw", XO(31,491,0,0), XO_MASK, PPC, {RT, RA, RB}},
{"divw.", XO(31,491,0,1), XO_MASK, PPC, {RT, RA, RB}},
-{"icbtlse", X(31,494), X_MASK, PPCCHLK64, {CT, RA, RB}},
+{"icbtlse", X(31,494), X_MASK, PPCCHLK, {CT, RA, RB}},
{"slbia", X(31,498), 0xffffffff, PPC64, {0}},
@@ -4285,8 +4204,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"cmpb", X(31,508), X_MASK, POWER6, {RA, RS, RB}},
-{"stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, {RS, RA, RB}},
-
{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, {BF}},
{"lbdx", X(31,515), X_MASK, E500MC, {RT, RA, RB}},
@@ -4334,12 +4251,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"maskir", XRC(31,541,0), X_MASK, M601, {RA, RS, RB}},
{"maskir.", XRC(31,541,1), X_MASK, M601, {RA, RS, RB}},
-{"lwbrxe", X(31,542), X_MASK, BOOKE64, {RT, RA0, RB}},
-
-{"lfsxe", X(31,543), X_MASK, BOOKE64, {FRT, RA0, RB}},
-
-{"mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, {BF}},
-
{"lhdx", X(31,547), X_MASK, E500MC, {RT, RA, RB}},
{"bbelr", X(31,550), X_MASK, PPCBRLK, {0}},
@@ -4356,8 +4267,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lfsux", X(31,567), X_MASK, COM, {FRT, RAS, RB}},
-{"lfsuxe", X(31,575), X_MASK, BOOKE64, {FRT, RAS, RB}},
-
{"lwdx", X(31,579), X_MASK, E500MC, {RT, RA, RB}},
{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, {FCRT, RA, RB}},
@@ -4375,7 +4284,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lfdx", X(31,599), X_MASK, COM, {FRT, RA0, RB}},
-{"lfdxe", X(31,607), X_MASK, BOOKE64, {FRT, RA0, RB}},
{"lfdepx", X(31,607), X_MASK, E500MC, {RT, RA, RB}},
{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, {FRT, RB}},
@@ -4395,8 +4303,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lfdux", X(31,631), X_MASK, COM, {FRT, RAS, RB}},
-{"lfduxe", X(31,639), X_MASK, BOOKE64, {FRT, RAS, RB}},
-
{"stbdx", X(31,643), X_MASK, E500MC, {RS, RA, RB}},
{"stvlx", X(31,647), X_MASK, CELL, {VS, RA0, RB}},
@@ -4430,10 +4336,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"sre", XRC(31,665,0), X_MASK, M601, {RA, RS, RB}},
{"sre.", XRC(31,665,1), X_MASK, M601, {RA, RS, RB}},
-{"stwbrxe", X(31,670), X_MASK, BOOKE64, {RS, RA0, RB}},
-
-{"stfsxe", X(31,671), X_MASK, BOOKE64, {FRS, RA0, RB}},
-
{"sthdx", X(31,675), X_MASK, E500MC, {RS, RA, RB}},
{"stvrx", X(31,679), X_MASK, CELL, {VS, RA0, RB}},
@@ -4444,8 +4346,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"sriq", XRC(31,696,0), X_MASK, M601, {RA, RS, SH}},
{"sriq.", XRC(31,696,1), X_MASK, M601, {RA, RS, SH}},
-{"stfsuxe", X(31,703), X_MASK, BOOKE64, {FRS, RAS, RB}},
-
{"stwdx", X(31,707), X_MASK, E500MC, {RS, RA, RB}},
{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, {FCRT, RA, RB}},
@@ -4471,7 +4371,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"sreq", XRC(31,729,0), X_MASK, M601, {RA, RS, RB}},
{"sreq.", XRC(31,729,1), X_MASK, M601, {RA, RS, RB}},
-{"stfdxe", X(31,735), X_MASK, BOOKE64, {FRS, RA0, RB}},
{"stfdepx", X(31,735), X_MASK, E500MC, {RS, RA, RB}},
{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, {RT, FRB}},
@@ -4505,10 +4404,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"srliq", XRC(31,760,0), X_MASK, M601, {RA, RS, SH}},
{"srliq.", XRC(31,760,1), X_MASK, M601, {RA, RS, SH}},
-{"dcbae", X(31,766), XRT_MASK, BOOKE64, {RA, RB}},
-
-{"stfduxe", X(31,767), X_MASK, BOOKE64, {FRS, RAS, RB}},
-
{"lvlxl", X(31,775), X_MASK, CELL, {VD, RA0, RB}},
{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, {FCRT, RA, RB}},
@@ -4521,7 +4416,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
{"tlbivax", X(31,786), XRT_MASK, BOOKE, {RA, RB}},
-{"tlbivaxe", X(31,787), XRT_MASK, BOOKE64, {RA, RB}},
{"tlbilx", X(31,787), X_MASK, E500MC, {T, RA0, RB}},
{"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, {0}},
{"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, {0}},
@@ -4542,10 +4436,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"srad", XRC(31,794,0), X_MASK, PPC64, {RA, RS, RB}},
{"srad.", XRC(31,794,1), X_MASK, PPC64, {RA, RS, RB}},
-{"lhbrxe", X(31,798), X_MASK, BOOKE64, {RT, RA0, RB}},
-
-{"ldxe", X(31,799), X_MASK, BOOKE64, {RT, RA0, RB}},
-
{"lfddx", X(31,803), X_MASK, E500MC, {FRT, RA, RB}},
{"lvrxl", X(31,807), X_MASK, CELL, {VD, RA0, RB}},
@@ -4568,7 +4458,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"divo", XO(31,331,1,0), XO_MASK, M601, {RT, RA, RB}},
{"divo.", XO(31,331,1,1), XO_MASK, M601, {RT, RA, RB}},
-{"lduxe", X(31,831), X_MASK, BOOKE64, {RT, RA0, RB}},
{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, {XT6, RA, RB}},
@@ -4594,15 +4483,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stvlxl", X(31,903), X_MASK, CELL, {VS, RA0, RB}},
{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, {FCRT, RA, RB}},
-{"subfe64o", XO(31,392,1,0), XO_MASK, BOOKE64, {RT, RA, RB}},
-
-{"adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, {RT, RA, RB}},
-
{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, {RTO, RA, RB}},
{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, {RTO, RA, RB}},
-{"tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, {RTO, RA, RB}},
-{"tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, {RTO, RA, RB}},
{"slbmfee", X(31,915), XRA_MASK, PPC64, {RT, RB}},
{"stwcix", X(31,917), X_MASK, POWER6, {RS, RA0, RB}},
@@ -4623,10 +4506,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, {RA, RS}},
{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, {RA, RS}},
-{"sthbrxe", X(31,926), X_MASK, BOOKE64, {RS, RA0, RB}},
-
-{"stdxe", X(31,927), X_MASK, BOOKE64, {RS, RA0, RB}},
-
{"stfddx", X(31,931), X_MASK, E500MC, {FRS, RA, RB}},
{"stvrxl", X(31,935), X_MASK, CELL, {VS, RA0, RB}},
@@ -4645,17 +4524,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"extsb", XRC(31,954,0), XRB_MASK, PPC, {RA, RS}},
{"extsb.", XRC(31,954,1), XRB_MASK, PPC, {RA, RS}},
-{"stduxe", X(31,959), X_MASK, BOOKE64, {RS, RAS, RB}},
-
{"iccci", X(31,966), XRT_MASK, PPC403|PPC440, {RA, RB}},
-{"subfze64o", XO(31,456,1,0), XORB_MASK, BOOKE64, {RT, RA}},
-
{"divduo", XO(31,457,1,0), XO_MASK, PPC64, {RT, RA, RB}},
{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, {RT, RA, RB}},
-{"addze64o", XO(31,458,1,0), XORB_MASK, BOOKE64, {RT, RA}},
-
{"divwuo", XO(31,459,1,0), XO_MASK, PPC, {RT, RA, RB}},
{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, {RT, RA, RB}},
@@ -4672,25 +4545,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stfiwx", X(31,983), X_MASK, PPC, {FRS, RA0, RB}},
-{"extsw", XRC(31,986,0), XRB_MASK, PPC64|BOOKE64, {RA, RS}},
+{"extsw", XRC(31,986,0), XRB_MASK, PPC64, {RA, RS}},
{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, {RA, RS}},
-{"icbie", X(31,990), XRT_MASK, BOOKE64, {RA, RB}},
-{"stfiwxe", X(31,991), X_MASK, BOOKE64, {FRS, RA0, RB}},
-
{"icbiep", XRT(31,991,0), XRT_MASK, E500MC, {RA, RB}},
{"icread", X(31,998), XRT_MASK, PPC403|PPC440, {RA, RB}},
{"nabso", XO(31,488,1,0), XORB_MASK, M601, {RT, RA}},
-{"subfme64o", XO(31,488,1,0), XORB_MASK, BOOKE64, {RT, RA}},
{"nabso.", XO(31,488,1,1), XORB_MASK, M601, {RT, RA}},
{"divdo", XO(31,489,1,0), XO_MASK, PPC64, {RT, RA, RB}},
{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, {RT, RA, RB}},
-{"addme64o", XO(31,490,1,0), XORB_MASK, BOOKE64, {RT, RA}},
-
{"divwo", XO(31,491,1,0), XO_MASK, PPC, {RT, RA, RB}},
{"divwo.", XO(31,491,1,1), XO_MASK, PPC, {RT, RA, RB}},
@@ -4703,7 +4570,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"dcbz", X(31,1014), XRT_MASK, PPC, {RA, RB}},
{"dclz", X(31,1014), XRT_MASK, PPC, {RA, RB}},
-{"dcbze", X(31,1022), XRT_MASK, BOOKE64, {RA, RB}},
{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC, {RA, RB}},
{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, {RA, RB}},
@@ -4788,21 +4654,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lfdp", OP(57), OP_MASK, POWER6, {FRT, D, RA0}},
-{"lbze", DEO(58,0), DE_MASK, BOOKE64, {RT, DE, RA0}},
-{"lbzue", DEO(58,1), DE_MASK, BOOKE64, {RT, DE, RAL}},
-{"lhze", DEO(58,2), DE_MASK, BOOKE64, {RT, DE, RA0}},
-{"lhzue", DEO(58,3), DE_MASK, BOOKE64, {RT, DE, RAL}},
-{"lhae", DEO(58,4), DE_MASK, BOOKE64, {RT, DE, RA0}},
-{"lhaue", DEO(58,5), DE_MASK, BOOKE64, {RT, DE, RAL}},
-{"lwze", DEO(58,6), DE_MASK, BOOKE64, {RT, DE, RA0}},
-{"lwzue", DEO(58,7), DE_MASK, BOOKE64, {RT, DE, RAL}},
-{"stbe", DEO(58,8), DE_MASK, BOOKE64, {RS, DE, RA0}},
-{"stbue", DEO(58,9), DE_MASK, BOOKE64, {RS, DE, RAS}},
-{"sthe", DEO(58,10), DE_MASK, BOOKE64, {RS, DE, RA0}},
-{"sthue", DEO(58,11), DE_MASK, BOOKE64, {RS, DE, RAS}},
-{"stwe", DEO(58,14), DE_MASK, BOOKE64, {RS, DE, RA0}},
-{"stwue", DEO(58,15), DE_MASK, BOOKE64, {RS, DE, RAS}},
-
{"ld", DSO(58,0), DS_MASK, PPC64, {RT, DS, RA0}},
{"ldu", DSO(58,1), DS_MASK, PPC64, {RT, DS, RAL}},
{"lwa", DSO(58,2), DS_MASK, PPC64, {RT, DS, RA0}},
@@ -4920,19 +4771,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stfdp", OP(61), OP_MASK, POWER6, {FRT, D, RA0}},
-{"lde", DEO(62,0), DE_MASK, BOOKE64, {RT, DES, RA0}},
-{"ldue", DEO(62,1), DE_MASK, BOOKE64, {RT, DES, RA0}},
-{"lfse", DEO(62,4), DE_MASK, BOOKE64, {FRT, DES, RA0}},
-{"lfsue", DEO(62,5), DE_MASK, BOOKE64, {FRT, DES, RAS}},
-{"lfde", DEO(62,6), DE_MASK, BOOKE64, {FRT, DES, RA0}},
-{"lfdue", DEO(62,7), DE_MASK, BOOKE64, {FRT, DES, RAS}},
-{"stde", DEO(62,8), DE_MASK, BOOKE64, {RS, DES, RA0}},
-{"stdue", DEO(62,9), DE_MASK, BOOKE64, {RS, DES, RAS}},
-{"stfse", DEO(62,12), DE_MASK, BOOKE64, {FRS, DES, RA0}},
-{"stfsue", DEO(62,13), DE_MASK, BOOKE64, {FRS, DES, RAS}},
-{"stfde", DEO(62,14), DE_MASK, BOOKE64, {FRS, DES, RA0}},
-{"stfdue", DEO(62,15), DE_MASK, BOOKE64, {FRS, DES, RAS}},
-
{"std", DSO(62,0), DS_MASK, PPC64, {RS, DS, RA0}},
{"stdu", DSO(62,1), DS_MASK, PPC64, {RS, DS, RAS}},
{"stq", DSO(62,2), DS_MASK, POWER4, {RSQ, DS, RA0}},
generated by cgit v1.1 at 2024-11-29 10:44:34 +0000