diff options
39 files changed, 55 insertions, 2902 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index f1a707d..61ef89f 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,19 @@ +2019-12-17 Alan Modra <amodra@gmail.com> + + * coff-tic80.c: Delete file. + * cpu-tic80.c: Delete file. + * archures.c: Remove tic80 support. + * coffcode.h: Likewise. + * coffswap.h: Likewise. + * targets.c: Likewise. + * config.bfd: Likewise. + * configure.ac: Likewise. + * Makefile.am: Likewise. + * Makefile.in: Regenerate. + * bfd-in2.h: Regenerate. + * configure: Regenerate. + * po/SRC-POTFILES.in: Regenerate. + 2019-12-13 Alan Modra <amodra@gmail.com> PR 25237 diff --git a/bfd/Makefile.am b/bfd/Makefile.am index e5bd28f..92c3b36 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -160,7 +160,6 @@ ALL_MACHINES = \ cpu-tic4x.lo \ cpu-tic54x.lo \ cpu-tic6x.lo \ - cpu-tic80.lo \ cpu-tilegx.lo \ cpu-tilepro.lo \ cpu-v850.lo \ @@ -246,7 +245,6 @@ ALL_MACHINES_CFILES = \ cpu-tic4x.c \ cpu-tic54x.c \ cpu-tic6x.c \ - cpu-tic80.c \ cpu-tilegx.c \ cpu-tilepro.c \ cpu-v850.c \ @@ -278,7 +276,6 @@ BFD32_BACKENDS = \ coff-tic30.lo \ coff-tic4x.lo \ coff-tic54x.lo \ - coff-tic80.lo \ coff-z80.lo \ coff-z8k.lo \ coffgen.lo \ @@ -414,7 +411,6 @@ BFD32_BACKENDS_CFILES = \ coff-tic30.c \ coff-tic4x.c \ coff-tic54x.c \ - coff-tic80.c \ coff-z80.c \ coff-z8k.c \ coffgen.c \ diff --git a/bfd/Makefile.in b/bfd/Makefile.in index 15334f1..1e17260 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -584,7 +584,6 @@ ALL_MACHINES = \ cpu-tic4x.lo \ cpu-tic54x.lo \ cpu-tic6x.lo \ - cpu-tic80.lo \ cpu-tilegx.lo \ cpu-tilepro.lo \ cpu-v850.lo \ @@ -670,7 +669,6 @@ ALL_MACHINES_CFILES = \ cpu-tic4x.c \ cpu-tic54x.c \ cpu-tic6x.c \ - cpu-tic80.c \ cpu-tilegx.c \ cpu-tilepro.c \ cpu-v850.c \ @@ -703,7 +701,6 @@ BFD32_BACKENDS = \ coff-tic30.lo \ coff-tic4x.lo \ coff-tic54x.lo \ - coff-tic80.lo \ coff-z80.lo \ coff-z8k.lo \ coffgen.lo \ @@ -839,7 +836,6 @@ BFD32_BACKENDS_CFILES = \ coff-tic30.c \ coff-tic4x.c \ coff-tic54x.c \ - coff-tic80.c \ coff-z80.c \ coff-z8k.c \ coffgen.c \ @@ -1323,7 +1319,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-tic30.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-tic4x.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-tic54x.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-tic80.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-x86_64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-z80.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/coff-z8k.Plo@am__quote@ @@ -1402,7 +1397,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-tic4x.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-tic54x.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-tic6x.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-tic80.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-tilegx.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-tilepro.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-v850.Plo@am__quote@ diff --git a/bfd/archures.c b/bfd/archures.c index 7866c60..e8873d4 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -355,7 +355,6 @@ DESCRIPTION .#define bfd_mach_tic4x 40 . bfd_arch_tic54x, {* Texas Instruments TMS320C54X. *} . bfd_arch_tic6x, {* Texas Instruments TMS320C6X. *} -. bfd_arch_tic80, {* TI TMS320c80 (MVP). *} . bfd_arch_v850, {* NEC V850. *} . bfd_arch_v850_rh850,{* NEC V850 (using RH850 ABI). *} .#define bfd_mach_v850 1 @@ -668,7 +667,6 @@ extern const bfd_arch_info_type bfd_tic30_arch; extern const bfd_arch_info_type bfd_tic4x_arch; extern const bfd_arch_info_type bfd_tic54x_arch; extern const bfd_arch_info_type bfd_tic6x_arch; -extern const bfd_arch_info_type bfd_tic80_arch; extern const bfd_arch_info_type bfd_tilegx_arch; extern const bfd_arch_info_type bfd_tilepro_arch; extern const bfd_arch_info_type bfd_v850_arch; @@ -756,7 +754,6 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_tic4x_arch, &bfd_tic54x_arch, &bfd_tic6x_arch, - &bfd_tic80_arch, &bfd_tilegx_arch, &bfd_tilepro_arch, &bfd_v850_arch, diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index ed91ed2..c6a5801 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1738,7 +1738,6 @@ enum bfd_architecture #define bfd_mach_tic4x 40 bfd_arch_tic54x, /* Texas Instruments TMS320C54X. */ bfd_arch_tic6x, /* Texas Instruments TMS320C6X. */ - bfd_arch_tic80, /* TI TMS320c80 (MVP). */ bfd_arch_v850, /* NEC V850. */ bfd_arch_v850_rh850,/* NEC V850 (using RH850 ABI). */ #define bfd_mach_v850 1 diff --git a/bfd/coff-tic80.c b/bfd/coff-tic80.c deleted file mode 100644 index 9e49a16..0000000 --- a/bfd/coff-tic80.c +++ /dev/null @@ -1,711 +0,0 @@ -/* BFD back-end for Texas Instruments TMS320C80 Multimedia Video Processor (MVP). - Copyright (C) 1996-2019 Free Software Foundation, Inc. - - Written by Fred Fish (fnf@cygnus.com) - - There is nothing new under the sun. This file draws a lot on other - coff files. - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -#include "sysdep.h" -#include "bfd.h" -#include "bfdlink.h" -#include "libbfd.h" -#ifdef _CONST -/* Newlib-based hosts define _CONST as a STDC-safe alias for const, - but to the tic80 toolchain it means something altogether different. - Since sysdep.h will have pulled in stdio.h and hence _ansi.h which - contains this definition, we must undef it before including the - tic80-specific definition. */ -#undef _CONST -#endif /* _CONST */ -#include "coff/tic80.h" -#include "coff/internal.h" -#include "libcoff.h" - -#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (2) -#define COFF_ALIGN_IN_SECTION_HEADER 1 -#define COFF_ALIGN_IN_SFLAGS 1 -#define COFF_ENCODE_ALIGNMENT(S,X) ((S).s_flags |= (((unsigned)(X) & 0xf) << 8)) -#define COFF_DECODE_ALIGNMENT(X) (((X) >> 8) & 0xf) - -#define GET_SCNHDR_FLAGS H_GET_16 -#define PUT_SCNHDR_FLAGS H_PUT_16 - -static bfd_reloc_status_type ppbase_reloc - (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **); -static bfd_reloc_status_type glob15_reloc - (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **); -static bfd_reloc_status_type glob16_reloc - (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **); -static bfd_reloc_status_type local16_reloc - (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **); - - -static reloc_howto_type tic80_howto_table[] = -{ - - HOWTO (R_RELLONG, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - NULL, /* special_function */ - "RELLONG", /* name */ - TRUE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_MPPCR, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - NULL, /* special_function */ - "MPPCR", /* name */ - TRUE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - TRUE), /* pcrel_offset */ - - HOWTO (R_ABS, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - NULL, /* special_function */ - "ABS", /* name */ - TRUE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PPBASE, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - ppbase_reloc, /* special_function */ - "PPBASE", /* name */ - TRUE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PPLBASE, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - ppbase_reloc, /* special_function */ - "PPLBASE", /* name */ - TRUE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PP15, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 15, /* bitsize */ - FALSE, /* pc_relative */ - 6, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - glob15_reloc, /* special_function */ - "PP15", /* name */ - TRUE, /* partial_inplace */ - 0x1ffc0, /* src_mask */ - 0x1ffc0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PP15W, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 15, /* bitsize */ - FALSE, /* pc_relative */ - 6, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - glob15_reloc, /* special_function */ - "PP15W", /* name */ - TRUE, /* partial_inplace */ - 0x1ffc0, /* src_mask */ - 0x1ffc0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PP15H, /* type */ - 1, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 15, /* bitsize */ - FALSE, /* pc_relative */ - 6, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - glob15_reloc, /* special_function */ - "PP15H", /* name */ - TRUE, /* partial_inplace */ - 0x1ffc0, /* src_mask */ - 0x1ffc0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PP16B, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 6, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - glob16_reloc, /* special_function */ - "PP16B", /* name */ - TRUE, /* partial_inplace */ - 0x3ffc0, /* src_mask */ - 0x3ffc0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PPL15, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 15, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - NULL, /* special_function */ - "PPL15", /* name */ - TRUE, /* partial_inplace */ - 0x7fff, /* src_mask */ - 0x7fff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PPL15W, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 15, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - NULL, /* special_function */ - "PPL15W", /* name */ - TRUE, /* partial_inplace */ - 0x7fff, /* src_mask */ - 0x7fff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PPL15H, /* type */ - 1, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 15, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - NULL, /* special_function */ - "PPL15H", /* name */ - TRUE, /* partial_inplace */ - 0x7fff, /* src_mask */ - 0x7fff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PPL16B, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - local16_reloc, /* special_function */ - "PPL16B", /* name */ - TRUE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PPN15, /* type */ - 0, /* rightshift */ - -2, /* size (0 = byte, 1 = short, 2 = long) */ - 15, /* bitsize */ - FALSE, /* pc_relative */ - 6, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - glob15_reloc, /* special_function */ - "PPN15", /* name */ - TRUE, /* partial_inplace */ - 0x1ffc0, /* src_mask */ - 0x1ffc0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PPN15W, /* type */ - 2, /* rightshift */ - -2, /* size (0 = byte, 1 = short, 2 = long) */ - 15, /* bitsize */ - FALSE, /* pc_relative */ - 6, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - glob15_reloc, /* special_function */ - "PPN15W", /* name */ - TRUE, /* partial_inplace */ - 0x1ffc0, /* src_mask */ - 0x1ffc0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PPN15H, /* type */ - 1, /* rightshift */ - -2, /* size (0 = byte, 1 = short, 2 = long) */ - 15, /* bitsize */ - FALSE, /* pc_relative */ - 6, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - glob15_reloc, /* special_function */ - "PPN15H", /* name */ - TRUE, /* partial_inplace */ - 0x1ffc0, /* src_mask */ - 0x1ffc0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PPN16B, /* type */ - 0, /* rightshift */ - -2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 6, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - glob16_reloc, /* special_function */ - "PPN16B", /* name */ - TRUE, /* partial_inplace */ - 0x3ffc0, /* src_mask */ - 0x3ffc0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PPLN15, /* type */ - 0, /* rightshift */ - -2, /* size (0 = byte, 1 = short, 2 = long) */ - 15, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - NULL, /* special_function */ - "PPLN15", /* name */ - TRUE, /* partial_inplace */ - 0x7fff, /* src_mask */ - 0x7fff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PPLN15W, /* type */ - 2, /* rightshift */ - -2, /* size (0 = byte, 1 = short, 2 = long) */ - 15, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - NULL, /* special_function */ - "PPLN15W", /* name */ - TRUE, /* partial_inplace */ - 0x7fff, /* src_mask */ - 0x7fff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PPLN15H, /* type */ - 1, /* rightshift */ - -2, /* size (0 = byte, 1 = short, 2 = long) */ - 15, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - NULL, /* special_function */ - "PPLN15H", /* name */ - TRUE, /* partial_inplace */ - 0x7fff, /* src_mask */ - 0x7fff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - HOWTO (R_PPLN16B, /* type */ - 0, /* rightshift */ - -2, /* size (0 = byte, 1 = short, 2 = long) */ - 15, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - local16_reloc, /* special_function */ - "PPLN16B", /* name */ - TRUE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE) /* pcrel_offset */ -}; - -/* Special relocation functions, used when the output file is not - itself a COFF TIc80 file. */ - -/* This special function is used for the base address type - relocations. */ - -static bfd_reloc_status_type -ppbase_reloc (bfd *abfd ATTRIBUTE_UNUSED, - arelent *reloc_entry ATTRIBUTE_UNUSED, - asymbol *symbol_in ATTRIBUTE_UNUSED, - void * data ATTRIBUTE_UNUSED, - asection *input_section ATTRIBUTE_UNUSED, - bfd *output_bfd ATTRIBUTE_UNUSED, - char **error_message ATTRIBUTE_UNUSED) -{ - /* FIXME. */ - abort (); -} - -/* This special function is used for the global 15 bit relocations. */ - -static bfd_reloc_status_type -glob15_reloc (bfd *abfd ATTRIBUTE_UNUSED, - arelent *reloc_entry ATTRIBUTE_UNUSED, - asymbol *symbol_in ATTRIBUTE_UNUSED, - void * data ATTRIBUTE_UNUSED, - asection *input_section ATTRIBUTE_UNUSED, - bfd *output_bfd ATTRIBUTE_UNUSED, - char **error_message ATTRIBUTE_UNUSED) -{ - /* FIXME. */ - abort (); -} - -/* This special function is used for the global 16 bit relocations. */ - -static bfd_reloc_status_type -glob16_reloc (bfd *abfd ATTRIBUTE_UNUSED, - arelent *reloc_entry ATTRIBUTE_UNUSED, - asymbol *symbol_in ATTRIBUTE_UNUSED, - void * data ATTRIBUTE_UNUSED, - asection *input_section ATTRIBUTE_UNUSED, - bfd *output_bfd ATTRIBUTE_UNUSED, - char **error_message ATTRIBUTE_UNUSED) -{ - /* FIXME. */ - abort (); -} - -/* This special function is used for the local 16 bit relocations. */ - -static bfd_reloc_status_type -local16_reloc (bfd *abfd ATTRIBUTE_UNUSED, - arelent *reloc_entry ATTRIBUTE_UNUSED, - asymbol *symbol_in ATTRIBUTE_UNUSED, - void * data ATTRIBUTE_UNUSED, - asection *input_section ATTRIBUTE_UNUSED, - bfd *output_bfd ATTRIBUTE_UNUSED, - char **error_message ATTRIBUTE_UNUSED) -{ - /* FIXME. */ - abort (); -} - -/* Code to turn an external r_type into a pointer to an entry in the howto_table. - If passed an r_type we don't recognize the abort rather than silently failing - to generate an output file. */ - -static void -rtype2howto (arelent *cache_ptr, struct internal_reloc *dst) -{ - unsigned int i; - - for (i = 0; i < sizeof tic80_howto_table / sizeof tic80_howto_table[0]; i++) - { - if (tic80_howto_table[i].type == dst->r_type) - { - cache_ptr->howto = tic80_howto_table + i; - return; - } - } - - _bfd_error_handler (_("unsupported relocation type %#x"), - (unsigned int) dst->r_type); - cache_ptr->howto = tic80_howto_table + 0; -} - -#define RTYPE2HOWTO(cache_ptr, dst) rtype2howto (cache_ptr, dst) -#define coff_rtype_to_howto coff_tic80_rtype_to_howto - -static reloc_howto_type * -coff_tic80_rtype_to_howto (bfd *abfd ATTRIBUTE_UNUSED, - asection *sec, - struct internal_reloc *rel, - struct coff_link_hash_entry *h ATTRIBUTE_UNUSED, - struct internal_syment *sym ATTRIBUTE_UNUSED, - bfd_vma *addendp) -{ - arelent genrel; - - if (rel -> r_symndx == -1 && addendp != NULL) - { - /* This is a TI "internal relocation", which means that the relocation - amount is the amount by which the current section is being relocated - in the output section. */ - *addendp = (sec -> output_section -> vma + sec -> output_offset) - sec -> vma; - } - RTYPE2HOWTO (&genrel, rel); - return genrel.howto; -} - -#ifndef BADMAG -#define BADMAG(x) TIC80BADMAG(x) -#endif - -#define coff_relocate_section coff_tic80_relocate_section - -/* We need a special relocation routine to handle the PP relocs. Most - of this is a copy of _bfd_coff_generic_relocate_section. */ - -static bfd_boolean -coff_tic80_relocate_section (bfd *output_bfd, - struct bfd_link_info *info, - bfd *input_bfd, - asection *input_section, - bfd_byte *contents, - struct internal_reloc *relocs, - struct internal_syment *syms, - asection **sections) -{ - struct internal_reloc *rel; - struct internal_reloc *relend; - - rel = relocs; - relend = rel + input_section->reloc_count; - for (; rel < relend; rel++) - { - long symndx; - struct coff_link_hash_entry *h; - struct internal_syment *sym; - bfd_vma addend; - bfd_vma val; - reloc_howto_type *howto; - bfd_reloc_status_type rstat; - bfd_vma addr; - - symndx = rel->r_symndx; - - if (symndx == -1) - { - h = NULL; - sym = NULL; - } - else - { - h = obj_coff_sym_hashes (input_bfd)[symndx]; - sym = syms + symndx; - } - - /* COFF treats common symbols in one of two ways. Either the - size of the symbol is included in the section contents, or it - is not. We assume that the size is not included, and force - the rtype_to_howto function to adjust the addend as needed. */ - - if (sym != NULL && sym->n_scnum != 0) - addend = - sym->n_value; - else - addend = 0; - - howto = bfd_coff_rtype_to_howto (input_bfd, input_section, rel, h, - sym, &addend); - if (howto == NULL) - return FALSE; - - val = 0; - - if (h == NULL) - { - asection *sec; - - if (symndx == -1) - { - sec = bfd_abs_section_ptr; - val = 0; - } - else - { - sec = sections[symndx]; - val = (sec->output_section->vma - + sec->output_offset - + sym->n_value); - if (! obj_pe (output_bfd)) - val -= sec->vma; - } - } - else - { - if (h->root.type == bfd_link_hash_defined - || h->root.type == bfd_link_hash_defweak) - { - asection *sec; - - sec = h->root.u.def.section; - val = (h->root.u.def.value - + sec->output_section->vma - + sec->output_offset); - } - - else if (! bfd_link_relocatable (info)) - (*info->callbacks->undefined_symbol) - (info, h->root.root.string, input_bfd, input_section, - rel->r_vaddr - input_section->vma, TRUE); - } - - addr = rel->r_vaddr - input_section->vma; - - /* FIXME: This code assumes little endian, but the PP can - apparently be bi-endian. I don't know if the bi-endianness - applies to the instruction set or just to the data. */ - switch (howto->type) - { - default: - case R_ABS: - case R_RELLONGX: - case R_PPL15: - case R_PPL15W: - case R_PPL15H: - case R_PPLN15: - case R_PPLN15W: - case R_PPLN15H: - rstat = _bfd_final_link_relocate (howto, input_bfd, input_section, - contents, addr, val, addend); - break; - - case R_PP15: - case R_PP15W: - case R_PP15H: - case R_PPN15: - case R_PPN15W: - case R_PPN15H: - /* Offset the address so that we can use 4 byte relocations. */ - rstat = _bfd_final_link_relocate (howto, input_bfd, input_section, - contents + 2, addr, val, addend); - break; - - case R_PP16B: - case R_PPN16B: - { - /* The most significant bit is stored in bit 6. */ - bfd_byte hold; - - hold = contents[addr + 4]; - contents[addr + 4] &=~ 0x20; - contents[addr + 4] |= (contents[addr] >> 1) & 0x20; - rstat = _bfd_final_link_relocate (howto, input_bfd, input_section, - contents + 2, addr, - val, addend); - contents[addr] &=~ 0x40; - contents[addr] |= (contents[addr + 4] << 1) & 0x40; - contents[addr + 4] &=~ 0x20; - contents[addr + 4] |= hold & 0x20; - break; - } - - case R_PPL16B: - case R_PPLN16B: - { - /* The most significant bit is stored in bit 28. */ - bfd_byte hold; - - hold = contents[addr + 1]; - contents[addr + 1] &=~ 0x80; - contents[addr + 1] |= (contents[addr + 3] << 3) & 0x80; - rstat = _bfd_final_link_relocate (howto, input_bfd, input_section, - contents, addr, - val, addend); - contents[addr + 3] &= ~0x10; - contents[addr + 3] |= (contents[addr + 1] >> 3) & 0x10; - contents[addr + 1] &=~ 0x80; - contents[addr + 1] |= hold & 0x80; - break; - } - - case R_PPBASE: - /* Parameter RAM is from 0x1000000 to 0x1000800. */ - contents[addr] &=~ 0x3; - if (val >= 0x1000000 && val < 0x1000800) - contents[addr] |= 0x3; - else - contents[addr] |= 0x2; - rstat = bfd_reloc_ok; - break; - - case R_PPLBASE: - /* Parameter RAM is from 0x1000000 to 0x1000800. */ - contents[addr + 2] &= ~0xc0; - if (val >= 0x1000000 && val < 0x1000800) - contents[addr + 2] |= 0xc0; - else - contents[addr + 2] |= 0x80; - rstat = bfd_reloc_ok; - break; - } - - switch (rstat) - { - default: - abort (); - case bfd_reloc_ok: - break; - case bfd_reloc_outofrange: - _bfd_error_handler - /* xgettext: c-format */ - (_("%pB: bad reloc address %#" PRIx64 " in section `%pA'"), - input_bfd, (uint64_t) rel->r_vaddr, input_section); - return FALSE; - case bfd_reloc_overflow: - { - const char *name; - char buf[SYMNMLEN + 1]; - - if (symndx == -1) - name = "*ABS*"; - else if (h != NULL) - name = NULL; - else - { - name = _bfd_coff_internal_syment_name (input_bfd, sym, buf); - if (name == NULL) - return FALSE; - } - - (*info->callbacks->reloc_overflow) - (info, (h ? &h->root : NULL), name, howto->name, - (bfd_vma) 0, input_bfd, input_section, - rel->r_vaddr - input_section->vma); - } - } - } - return TRUE; -} - -#define TIC80COFF 1 /* Customize coffcode.h */ -#undef C_AUTOARG /* Clashes with TIc80's C_UEXT */ -#undef C_LASTENT /* Clashes with TIc80's C_STATLAB */ - -#ifndef bfd_pe_print_pdata -#define bfd_pe_print_pdata NULL -#endif - -#include "coffcode.h" - -CREATE_LITTLE_COFF_TARGET_VEC (tic80_coff_vec, "coff-tic80", D_PAGED, 0, '_', NULL, COFF_SWAP_TABLE) diff --git a/bfd/coffcode.h b/bfd/coffcode.h index 948bb70..ac5312f 100644 --- a/bfd/coffcode.h +++ b/bfd/coffcode.h @@ -2330,12 +2330,6 @@ coff_set_arch_mach_hook (bfd *abfd, void * filehdr) break; #endif -#ifdef TIC80_ARCH_MAGIC - case TIC80_ARCH_MAGIC: - arch = bfd_arch_tic80; - break; -#endif - #ifdef MCOREMAGIC case MCOREMAGIC: arch = bfd_arch_mcore; @@ -2715,12 +2709,6 @@ coff_set_flags (bfd * abfd, return TRUE; #endif -#ifdef TIC80_ARCH_MAGIC - case bfd_arch_tic80: - *magicp = TIC80_ARCH_MAGIC; - return TRUE; -#endif - #ifdef ARMMAGIC case bfd_arch_arm: #ifdef ARM_WINCE @@ -2883,7 +2871,7 @@ sort_by_secaddr (const void * arg1, const void * arg2) /* Calculate the file position for each section. */ #define ALIGN_SECTIONS_IN_FILE -#if defined(TIC80COFF) || defined(TICOFF) +#ifdef TICOFF #undef ALIGN_SECTIONS_IN_FILE #endif @@ -3811,9 +3799,6 @@ coff_write_object_contents (bfd * abfd) but it doesn't hurt to set it internally. */ internal_f.f_target_id = TI_TARGET_ID; #endif -#ifdef TIC80_TARGET_ID - internal_f.f_target_id = TIC80_TARGET_ID; -#endif /* FIXME, should do something about the other byte orders and architectures. */ @@ -3841,10 +3826,6 @@ coff_write_object_contents (bfd * abfd) internal_a.magic = TICOFF_AOUT_MAGIC; #define __A_MAGIC_SET__ #endif -#ifdef TIC80COFF - internal_a.magic = TIC80_ARCH_MAGIC; -#define __A_MAGIC_SET__ -#endif /* TIC80 */ #if defined(ARM) #define __A_MAGIC_SET__ @@ -4775,7 +4756,7 @@ coff_slurp_symbol_table (bfd * abfd) case C_ALIAS: /* Duplicate tag. */ #endif /* New storage classes for TI COFF. */ -#if defined(TIC80COFF) || defined(TICOFF) +#ifdef TICOFF case C_UEXT: /* Tentative external definition. */ #endif case C_EXTLAB: /* External load time label. */ diff --git a/bfd/coffswap.h b/bfd/coffswap.h index 60a04d4..a94f817 100644 --- a/bfd/coffswap.h +++ b/bfd/coffswap.h @@ -264,9 +264,6 @@ coff_swap_filehdr_in (bfd * abfd, void * src, void * dst) filehdr_dst->f_nsyms = H_GET_32 (abfd, filehdr_src->f_nsyms); filehdr_dst->f_opthdr = H_GET_16 (abfd, filehdr_src->f_opthdr); filehdr_dst->f_flags = H_GET_16 (abfd, filehdr_src->f_flags); -#ifdef TIC80_TARGET_ID - filehdr_dst->f_target_id = H_GET_16 (abfd, filehdr_src->f_target_id); -#endif #ifdef COFF_ADJUST_FILEHDR_IN_POST COFF_ADJUST_FILEHDR_IN_POST (abfd, src, dst); @@ -289,9 +286,6 @@ coff_swap_filehdr_out (bfd *abfd, void * in, void * out) H_PUT_32 (abfd, filehdr_in->f_nsyms, filehdr_out->f_nsyms); H_PUT_16 (abfd, filehdr_in->f_opthdr, filehdr_out->f_opthdr); H_PUT_16 (abfd, filehdr_in->f_flags, filehdr_out->f_flags); -#ifdef TIC80_TARGET_ID - H_PUT_16 (abfd, filehdr_in->f_target_id, filehdr_out->f_target_id); -#endif #ifdef COFF_ADJUST_FILEHDR_OUT_POST COFF_ADJUST_FILEHDR_OUT_POST (abfd, in, out); diff --git a/bfd/config.bfd b/bfd/config.bfd index 0a96927..a0ab37e 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -1333,11 +1333,6 @@ case "${targ}" in targ_selvecs="tic6x_elf32_linux_be_vec tic6x_elf32_le_vec tic6x_elf32_be_vec" ;; - tic80*-*-*) - targ_defvec=tic80_coff_vec - targ_underscore=yes - ;; - #ifdef BFD64 tilegx-*-*) targ_defvec=tilegx_elf64_le_vec diff --git a/bfd/configure b/bfd/configure index abd7b2a..bf95857 100755 --- a/bfd/configure +++ b/bfd/configure @@ -14923,7 +14923,6 @@ do tic6x_elf32_c6000_le_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;; tic6x_elf32_linux_be_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;; tic6x_elf32_linux_le_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;; - tic80_coff_vec) tb="$tb coff-tic80.lo $coff" ;; tilegx_elf32_be_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;; tilegx_elf32_le_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;; tilegx_elf64_be_vec) tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;; diff --git a/bfd/configure.ac b/bfd/configure.ac index 7eee83a..c673a29 100644 --- a/bfd/configure.ac +++ b/bfd/configure.ac @@ -659,7 +659,6 @@ do tic6x_elf32_c6000_le_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;; tic6x_elf32_linux_be_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;; tic6x_elf32_linux_le_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;; - tic80_coff_vec) tb="$tb coff-tic80.lo $coff" ;; tilegx_elf32_be_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;; tilegx_elf32_le_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;; tilegx_elf64_be_vec) tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;; diff --git a/bfd/cpu-tic80.c b/bfd/cpu-tic80.c deleted file mode 100644 index 2fcbd9d..0000000 --- a/bfd/cpu-tic80.c +++ /dev/null @@ -1,42 +0,0 @@ -/* bfd back-end for TI TMS320C80 (MVP) support - Copyright (C) 1996-2019 Free Software Foundation, Inc. - Written by Fred Fish at Cygnus support (fnf@cygnus.com) - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "sysdep.h" -#include "bfd.h" -#include "libbfd.h" - -const bfd_arch_info_type bfd_tic80_arch = -{ - 32, /* Bits in a word. */ - 32, /* Bits in an address. */ - 8, /* Bits in a byte. */ - bfd_arch_tic80, /* Architecture number. */ - 0, /* Only 1 machine. */ - "tic80", /* Architecture name. */ - "tic80", /* Printable name. */ - 2, /* Section alignment power. */ - TRUE, /* Default machine. */ - bfd_default_compatible, - bfd_default_scan, - bfd_arch_default_fill, - NULL, /* Pointer to next in chain. */ - 0 /* Maximum offset of a reloc from the start of an insn. */ -}; diff --git a/bfd/po/SRC-POTFILES.in b/bfd/po/SRC-POTFILES.in index 04c4c07..a84908b 100644 --- a/bfd/po/SRC-POTFILES.in +++ b/bfd/po/SRC-POTFILES.in @@ -32,7 +32,6 @@ coff-stgo32.c coff-tic30.c coff-tic4x.c coff-tic54x.c -coff-tic80.c coff-x86_64.c coff-z80.c coff-z8k.c @@ -117,7 +116,6 @@ cpu-tic30.c cpu-tic4x.c cpu-tic54x.c cpu-tic6x.c -cpu-tic80.c cpu-tilegx.c cpu-tilepro.c cpu-v850.c diff --git a/bfd/targets.c b/bfd/targets.c index fb0c669..0c84a72 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -899,7 +899,6 @@ extern const bfd_target tic6x_elf32_c6000_be_vec; extern const bfd_target tic6x_elf32_c6000_le_vec; extern const bfd_target tic6x_elf32_linux_be_vec; extern const bfd_target tic6x_elf32_linux_le_vec; -extern const bfd_target tic80_coff_vec; extern const bfd_target tilegx_elf32_be_vec; extern const bfd_target tilegx_elf32_le_vec; extern const bfd_target tilegx_elf64_be_vec; @@ -1306,7 +1305,6 @@ static const bfd_target * const _bfd_target_vector[] = &tic54x_coff2_vec, &tic6x_elf32_be_vec, &tic6x_elf32_le_vec, - &tic80_coff_vec, &tilegx_elf32_be_vec, &tilegx_elf32_le_vec, diff --git a/binutils/ChangeLog b/binutils/ChangeLog index 80c7fc3..b8ae470 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,8 @@ +2019-12-17 Alan Modra <amodra@gmail.com> + + * testsuite/binutils-all/objcopy.exp: Remove tic80 support. + * testsuite/binutils-all/objdump.exp: Likewise. + 2019-12-11 Alan Modra <amodra@gmail.com> * od-xcoff.c (dump_dumpx_core): Adjust for bfd_h_get_8 change. diff --git a/binutils/testsuite/binutils-all/objcopy.exp b/binutils/testsuite/binutils-all/objcopy.exp index 6739ab7..88f63fe 100644 --- a/binutils/testsuite/binutils-all/objcopy.exp +++ b/binutils/testsuite/binutils-all/objcopy.exp @@ -81,7 +81,6 @@ proc objcopy_test {testname srcfile} { setup_xfail "m8*-*" setup_xfail "sh-*-coff*" setup_xfail "tic54x-*-*" - setup_xfail "tic80-*-*" clear_xfail "hppa*64*-*-hpux*" "hppa*-*-linux*" "hppa*-*-lites*" clear_xfail "hppa*-*-*n*bsd*" "hppa*-*-rtems*" "*-*-*elf*" diff --git a/binutils/testsuite/binutils-all/objdump.exp b/binutils/testsuite/binutils-all/objdump.exp index 58b66d4..5089ea8 100644 --- a/binutils/testsuite/binutils-all/objdump.exp +++ b/binutils/testsuite/binutils-all/objdump.exp @@ -39,7 +39,7 @@ lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 iamcu ip2022 lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k MCore mep c5 h1 MicroBlaze lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k lappend cpus_expected or1k or1knd pj powerpc pyramid riscv romp rs6000 s390 sh sparc -lappend cpus_expected tic54x tic80 tilegx tms320c30 tms320c4x tms320c54x +lappend cpus_expected tic54x tilegx tms320c30 tms320c4x tms320c54x lappend cpus_expected v850 vax x86-64 xscale xtensa z8k z8001 z8002 # Make sure the target CPU shows up in the list. diff --git a/gas/ChangeLog b/gas/ChangeLog index 48c5430..875bcf8 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2019-12-17 Alan Modra <amodra@gmail.com> + + * doc/as.texi: Remove mention of tic80. + 2019-12-12 H.J. Lu <hongjiu.lu@intel.com> PR gas/25274 diff --git a/gas/doc/as.texi b/gas/doc/as.texi index 532ed7a..c132f86 100644 --- a/gas/doc/as.texi +++ b/gas/doc/as.texi @@ -4588,7 +4588,7 @@ with no-op instructions when appropriate. The way the required alignment is specified varies from system to system. For the arc, hppa, i386 using ELF, iq2000, m68k, or1k, -s390, sparc, tic4x, tic80 and xtensa, the first expression is the +s390, sparc, tic4x and xtensa, the first expression is the alignment request in bytes. For example @samp{.align 8} advances the location counter until it is a multiple of 8. If the location counter is already a multiple of 8, no change is needed. For the tic54x, the diff --git a/include/ChangeLog b/include/ChangeLog index a9be17a..ce3e049 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2019-12-17 Alan Modra <amodra@gmail.com> + + * coff/tic80.h: Delete file. + * opcode/tic80.h: Delete file. + 2019-12-16 Alan Modra <amodra@gmail.com> * opcode/crx.h (inst <match>): Make unsigned int. diff --git a/include/coff/tic80.h b/include/coff/tic80.h deleted file mode 100644 index 921ee50..0000000 --- a/include/coff/tic80.h +++ /dev/null @@ -1,123 +0,0 @@ -/* coff information for TI TMS320C80 (MVP) - - Copyright (C) 2001-2019 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#define DO_NOT_DEFINE_FILHDR -#define DO_NOT_DEFINE_SCNHDR -#define L_LNNO_SIZE 2 -#include "coff/external.h" - -/********************** FILE HEADER **********************/ - -struct external_filehdr - { - char f_magic[2]; /* magic number */ - char f_nscns[2]; /* number of sections */ - char f_timdat[4]; /* time & date stamp */ - char f_symptr[4]; /* file pointer to symtab */ - char f_nsyms[4]; /* number of symtab entries */ - char f_opthdr[2]; /* sizeof(optional hdr) */ - char f_flags[2]; /* flags */ - char f_target_id[2];/* target id (TIc80 specific) */ -}; - -#define TIC80_ARCH_MAGIC 0x0C1 /* Goes in the file header magic number field */ -#define TIC80_TARGET_ID 0x95 /* Goes in the target id field */ - -#define TIC80BADMAG(x) ((x).f_magic != TIC80_ARCH_MAGIC) - -#define FILHDR struct external_filehdr -#define FILHSZ 22 - -#define TIC80_AOUTHDR_MAGIC 0x108 /* Goes in the optional file header magic number field */ - -/********************** SECTION HEADER **********************/ - -struct external_scnhdr -{ - char s_name[8]; /* section name */ - char s_paddr[4]; /* physical address, aliased s_nlib */ - char s_vaddr[4]; /* virtual address */ - char s_size[4]; /* section size */ - char s_scnptr[4]; /* file ptr to raw data for section */ - char s_relptr[4]; /* file ptr to relocation */ - char s_lnnoptr[4]; /* file ptr to line numbers */ - char s_nreloc[2]; /* number of relocation entries */ - char s_nlnno[2]; /* number of line number entries*/ - char s_flags[2]; /* flags */ - char s_reserved[1]; /* reserved (TIc80 specific) */ - char s_mempage[1]; /* memory page number (TIc80) */ -}; - -/* Names of "special" sections. */ -#define _TEXT ".text" -#define _DATA ".data" -#define _BSS ".bss" -#define _CINIT ".cinit" -#define _CONST ".const" -#define _SWITCH ".switch" -#define _STACK ".stack" -#define _SYSMEM ".sysmem" - -#define SCNHDR struct external_scnhdr -#define SCNHSZ 40 - -/* FIXME - need to correlate external_auxent with - TIc80 Code Generation Tools User's Guide, CG:A-25 */ - -/********************** RELOCATION DIRECTIVES **********************/ - -/* The external reloc has an offset field, because some of the reloc - types on the h8 don't have room in the instruction for the entire - offset - eg the strange jump and high page addressing modes. */ - -struct external_reloc -{ - char r_vaddr[4]; - char r_symndx[4]; - char r_reserved[2]; - char r_type[2]; -}; - -#define RELOC struct external_reloc -#define RELSZ 12 - -/* TIc80 relocation types. */ - -#define R_ABS 0x00 /* Absolute address - no relocation */ -#define R_RELLONGX 0x11 /* PP: 32 bits, direct */ -#define R_PPBASE 0x34 /* PP: Global base address type */ -#define R_PPLBASE 0x35 /* PP: Local base address type */ -#define R_PP15 0x38 /* PP: Global 15 bit offset */ -#define R_PP15W 0x39 /* PP: Global 15 bit offset divided by 4 */ -#define R_PP15H 0x3A /* PP: Global 15 bit offset divided by 2 */ -#define R_PP16B 0x3B /* PP: Global 16 bit offset for bytes */ -#define R_PPL15 0x3C /* PP: Local 15 bit offset */ -#define R_PPL15W 0x3D /* PP: Local 15 bit offset divided by 4 */ -#define R_PPL15H 0x3E /* PP: Local 15 bit offset divided by 2 */ -#define R_PPL16B 0x3F /* PP: Local 16 bit offset for bytes */ -#define R_PPN15 0x40 /* PP: Global 15 bit negative offset */ -#define R_PPN15W 0x41 /* PP: Global 15 bit negative offset divided by 4 */ -#define R_PPN15H 0x42 /* PP: Global 15 bit negative offset divided by 2 */ -#define R_PPN16B 0x43 /* PP: Global 16 bit negative byte offset */ -#define R_PPLN15 0x44 /* PP: Local 15 bit negative offset */ -#define R_PPLN15W 0x45 /* PP: Local 15 bit negative offset divided by 4 */ -#define R_PPLN15H 0x46 /* PP: Local 15 bit negative offset divided by 2 */ -#define R_PPLN16B 0x47 /* PP: Local 16 bit negative byte offset */ -#define R_MPPCR15W 0x4E /* MP: 15 bit PC-relative divided by 4 */ -#define R_MPPCR 0x4F /* MP: 32 bit PC-relative divided by 4 */ diff --git a/include/opcode/tic80.h b/include/opcode/tic80.h deleted file mode 100644 index ac1249f..0000000 --- a/include/opcode/tic80.h +++ /dev/null @@ -1,283 +0,0 @@ -/* tic80.h -- Header file for TI TMS320C80 (MV) opcode table - Copyright (C) 1996-2019 Free Software Foundation, Inc. - Written by Fred Fish (fnf@cygnus.com), Cygnus Support - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING3. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef TIC80_H -#define TIC80_H - -/* The opcode table is an array of struct tic80_opcode. */ - -struct tic80_opcode -{ - /* The opcode name. */ - - const char *name; - - /* The opcode itself. Those bits which will be filled in with operands - are zeroes. */ - - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a mask - containing ones indicating those bits which must match the opcode - field, and zeroes indicating those bits which need not match (and are - presumably filled in by operands). */ - - unsigned long mask; - - /* Special purpose flags for this opcode. */ - - unsigned char flags; - - /* An array of operand codes. Each code is an index into the operand - table. They appear in the order which the operands must appear in - assembly code, and are terminated by a zero. FIXME: Adjust size to - match actual requirements when TIc80 support is complete */ - - unsigned char operands[8]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise in - the order in which the disassembler should consider instructions. - FIXME: This isn't currently true. */ - -extern const struct tic80_opcode tic80_opcodes[]; -extern const int tic80_num_opcodes; - - -/* The operands table is an array of struct tic80_operand. */ - -struct tic80_operand -{ - /* The number of bits in the operand. */ - - int bits; - - /* How far the operand is left shifted in the instruction. */ - - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - - unsigned long (*insert) - (unsigned long instruction, long op, const char **errmsg); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & TIC80_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - - long (*extract) (unsigned long instruction, int *invalid); - - /* One bit syntax flags. */ - - unsigned long flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the tic80_opcodes table. */ - -extern const struct tic80_operand tic80_operands[]; - - -/* Values defined for the flags field of a struct tic80_operand. - - Note that flags for all predefined symbols, such as the general purpose - registers (ex: r10), control registers (ex: FPST), condition codes (ex: - eq0.b), bit numbers (ex: gt.b), etc are large enough that they can be - or'd into an int where the lower bits contain the actual numeric value - that correponds to this predefined symbol. This way a single int can - contain both the value of the symbol and it's type. - */ - -/* This operand must be an even register number. Floating point numbers - for example are stored in even/odd register pairs. */ - -#define TIC80_OPERAND_EVEN (1u << 0) - -/* This operand must be an odd register number and must be one greater than - the register number of the previous operand. I.E. the second register in - an even/odd register pair. */ - -#define TIC80_OPERAND_ODD (1u << 1) - -/* This operand takes signed values. */ - -#define TIC80_OPERAND_SIGNED (1u << 2) - -/* This operand may be either a predefined constant name or a numeric value. - An example would be a condition code like "eq0.b" which has the numeric - value 0x2. */ - -#define TIC80_OPERAND_NUM (1u << 3) - -/* This operand should be wrapped in parentheses rather than separated - from the previous one by a comma. This is used for various - instructions, like the load and store instructions, which want - their operands to look like "displacement(reg)" */ - -#define TIC80_OPERAND_PARENS (1u << 4) - -/* This operand is a PC relative branch offset. The disassembler prints - these symbolically if possible. Note that the offsets are taken as word - offsets. */ - -#define TIC80_OPERAND_PCREL (1u << 5) - -/* This flag is a hint to the disassembler for using hex as the prefered - printing format, even for small positive or negative immediate values. - Normally values in the range -999 to 999 are printed as signed decimal - values and other values are printed in hex. */ - -#define TIC80_OPERAND_BITFIELD (1u << 6) - -/* This operand may have a ":m" modifier specified by bit 17 in a short - immediate form instruction. */ - -#define TIC80_OPERAND_M_SI (1u << 7) - -/* This operand may have a ":m" modifier specified by bit 15 in a long - immediate or register form instruction. */ - -#define TIC80_OPERAND_M_LI (1u << 8) - -/* This operand may have a ":s" modifier specified in bit 11 in a long - immediate or register form instruction. */ - -#define TIC80_OPERAND_SCALED (1u << 9) - -/* This operand is a floating point value */ - -#define TIC80_OPERAND_FLOAT (1u << 10) - -/* This operand is an byte offset from a base relocation. The lower - two bits of the final relocated address are ignored when the value is - written to the program counter. */ - -#define TIC80_OPERAND_BASEREL (1u << 11) - -/* This operand is an "endmask" field for a shift instruction. - It is treated special in that it can have values of 0-32, - where 0 and 32 result in the same instruction. The assembler - must be able to accept both endmask values. This disassembler - has no way of knowing from the instruction which value was - given at assembly time, so it just uses '0'. */ - -#define TIC80_OPERAND_ENDMASK (1u << 12) - -/* This operand is one of the 32 general purpose registers. - The disassembler prints these with a leading 'r'. */ - -#define TIC80_OPERAND_GPR (1u << 27) - -/* This operand is a floating point accumulator register. - The disassembler prints these with a leading 'a'. */ - -#define TIC80_OPERAND_FPA (1u << 28) - -/* This operand is a control register number, either numeric or - symbolic (like "EIF", "EPC", etc). - The disassembler prints these symbolically. */ - -#define TIC80_OPERAND_CR (1u << 29) - -/* This operand is a condition code, either numeric or - symbolic (like "eq0.b", "ne0.w", etc). - The disassembler prints these symbolically. */ - -#define TIC80_OPERAND_CC (1u << 30) - -/* This operand is a bit number, either numeric or - symbolic (like "eq.b", "or.f", etc). - The disassembler prints these symbolically. - Note that they appear in the instruction in 1's complement relative - to the values given in the manual. */ - -#define TIC80_OPERAND_BITNUM (1u << 31) - -/* This mask is used to strip operand bits from an int that contains - both operand bits and a numeric value in the lsbs. */ - -#define TIC80_OPERAND_MASK (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR | TIC80_OPERAND_CC | TIC80_OPERAND_BITNUM) - - -/* Flag bits for the struct tic80_opcode flags field. */ - -#define TIC80_VECTOR 01 /* Is a vector instruction */ -#define TIC80_NO_R0_DEST 02 /* Register r0 cannot be a destination register */ - - -/* The opcodes library contains a table that allows translation from predefined - symbol names to numeric values, and vice versa. */ - -/* Structure to hold information about predefined symbols. */ - -struct predefined_symbol -{ - char *name; /* name to recognize */ - int value; -}; - -#define PDS_NAME(pdsp) ((pdsp) -> name) -#define PDS_VALUE(pdsp) ((pdsp) -> value) - -/* Translation array. */ -extern const struct predefined_symbol tic80_predefined_symbols[]; -/* How many members in the array. */ -extern const int tic80_num_predefined_symbols; - -/* Translate value to symbolic name. */ -const char *tic80_value_to_symbol (int val, int class); - -/* Translate symbolic name to value. */ -int tic80_symbol_to_value (char *name, int class); - -const struct predefined_symbol *tic80_next_predefined_symbol - (const struct predefined_symbol *); - -#endif /* TIC80_H */ diff --git a/ld/ChangeLog b/ld/ChangeLog index 4b7e746..f23d70b 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,12 @@ +2019-12-17 Alan Modra <amodra@gmail.com> + + * emulparams/tic80coff.sh: Delete file. + * scripttempl/tic80coff.sc: Delete file. + * configure.tgt: Remove tic80 support. + * Makefile.am: Likewise. + * Makefile.in: Regenerate. + * po/BLD-POTFILES.in: Regenerate. + 2019-12-12 H.J. Lu <hongjiu.lu@intel.com> * testsuite/ld-i386/align-branch-1.d: New file. diff --git a/ld/Makefile.am b/ld/Makefile.am index ddc7a78..cd2ff30 100644 --- a/ld/Makefile.am +++ b/ld/Makefile.am @@ -379,7 +379,6 @@ ALL_EMULATION_SOURCES = \ etic3xcoff_onchip.c \ etic4xcoff.c \ etic54xcoff.c \ - etic80coff.c \ ev850.c \ ev850_rh850.c \ evanilla.c \ @@ -869,7 +868,6 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS) @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/etic3xcoff_onchip.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/etic4xcoff.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/etic54xcoff.Pc@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/etic80coff.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ev850.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ev850_rh850.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/evanilla.Pc@am__quote@ diff --git a/ld/Makefile.in b/ld/Makefile.in index fdf0612..d27bafb 100644 --- a/ld/Makefile.in +++ b/ld/Makefile.in @@ -869,7 +869,6 @@ ALL_EMULATION_SOURCES = \ etic3xcoff_onchip.c \ etic4xcoff.c \ etic54xcoff.c \ - etic80coff.c \ ev850.c \ ev850_rh850.c \ evanilla.c \ @@ -1490,7 +1489,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/etic3xcoff_onchip.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/etic4xcoff.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/etic54xcoff.Po@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/etic80coff.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ev850.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ev850_rh850.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/evanilla.Po@am__quote@ @@ -2475,7 +2473,6 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS) @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/etic3xcoff_onchip.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/etic4xcoff.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/etic54xcoff.Pc@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/etic80coff.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ev850.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ev850_rh850.Pc@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/evanilla.Pc@am__quote@ diff --git a/ld/configure.tgt b/ld/configure.tgt index c0c8a69..1e90d88 100644 --- a/ld/configure.tgt +++ b/ld/configure.tgt @@ -901,9 +901,6 @@ tic6x-*-uclinux) targ_emul=elf32_tic6x_linux_le targ_extra_emuls="elf32_tic6x_linux_be elf32_tic6x_le elf32_tic6x_be" targ_extra_libpath=$targ_extra_emuls ;; -tic80-*-*) targ_emul=tic80coff - targ_extra_ofiles= - ;; tilegx-*-*) targ_emul=elf64tilegx targ_extra_emuls="elf64tilegx_be elf32tilegx elf32tilegx_be" targ_extra_libpath=$targ_extra_emuls diff --git a/ld/emulparams/tic80coff.sh b/ld/emulparams/tic80coff.sh deleted file mode 100644 index 5fce934..0000000 --- a/ld/emulparams/tic80coff.sh +++ /dev/null @@ -1,50 +0,0 @@ -# This file is sourced by the genscripts.sh script. -# These are shell variables that are used later by either genscripts -# or on of the scripts that it sources. - -# The name of the scripttempl script to use. In this case, genscripts -# uses scripttempl/tic80coff.sc -# -SCRIPT_NAME=tic80coff - -# The name of the emultempl script to use. If set to "template" then -# genscripts.sh will use the script emultempl/template.em. If not set, -# then the default value is "generic". -# -# TEMPLATE_NAME= - -# If this is set to an nonempty string, genscripts.sh will invoke the -# scripttempl script an extra time to create a shared library script. -# -# GENERATE_SHLIB_SCRIPT= - -# The BFD output format to use. The scripttempl script will use it in -# an OUTPUT_FORMAT expression in the linker script. -# -OUTPUT_FORMAT="coff-tic80" - -# This is normally set to indicate the architecture to use, such as -# "sparc". The scripttempl script will normally use it in an OUTPUT_ARCH -# expression in the linker script. -# -ARCH=tic80 - -# Some scripttempl scripts use this to set the entry address in an ENTRY -# expression in the linker script. -# -# ENTRY= - -# The scripttempl script uses this to set the start address of the -# ".text" section. -# -TEXT_START_ADDR=0x2000000 - -# The genscripts.sh script uses this to set the default value of -# DATA_ALIGNMENT when running the scripttempl script. -# -# SEGMENT_SIZE= - -# If SEGMENT_SIZE is not defined, the genscripts.sh script uses this -# to define it. -# -TARGET_PAGE_SIZE=0x1000 diff --git a/ld/po/BLD-POTFILES.in b/ld/po/BLD-POTFILES.in index 846f2ab..d171bb9 100644 --- a/ld/po/BLD-POTFILES.in +++ b/ld/po/BLD-POTFILES.in @@ -292,7 +292,6 @@ etic3xcoff.c etic3xcoff_onchip.c etic4xcoff.c etic54xcoff.c -etic80coff.c ev850.c ev850_rh850.c evanilla.c diff --git a/ld/scripttempl/tic80coff.sc b/ld/scripttempl/tic80coff.sc deleted file mode 100644 index 692227a..0000000 --- a/ld/scripttempl/tic80coff.sc +++ /dev/null @@ -1,86 +0,0 @@ -# Linker script for TI TMS320C80 (tic80) COFF. -# -# Copyright (C) 2014-2019 Free Software Foundation, Inc. -# -# Copying and distribution of this file, with or without modification, -# are permitted in any medium without royalty provided the copyright -# notice and this notice are preserved. -# -# Besides the shell variables set by the emulparams script, and the LD_FLAG -# variable, the genscripts.sh script will set the following variables for each -# time this script is run to generate one of the linker scripts for ldscripts: -# -# RELOCATING: Set to a non-empty string when the linker is going to be doing -# a final relocation. -# -# CONSTRUCTING: Set to a non-empty string when the linker is going to be -# building global constructor and destructor tables. -# -# DATA_ALIGNMENT: Set to an ALIGN expression when the output should be page -# aligned, or to "." when generating the -N script. -# -# CREATE_SHLIB: Set to a non-empty string when generating a script for -# the -shared linker arg. - -test -z "$TEXT_START_ADDR" && TEXT_START_ADDR="0x80000 + SIZEOF_HEADERS" -test -z "$ENTRY" && ENTRY=__start - -cat <<EOF -/* Copyright (C) 2014-2019 Free Software Foundation, Inc. - - Copying and distribution of this script, with or without modification, - are permitted in any medium without royalty provided the copyright - notice and this notice are preserved. */ - -OUTPUT_FORMAT("${OUTPUT_FORMAT}") -${LIB_SEARCH_DIRS} - -${RELOCATING+ENTRY (${ENTRY})} - -SECTIONS -{ - .text ${RELOCATING+ $TEXT_START_ADDR} : { - ${RELOCATING+KEEP (*(SORT_NONE(.init))) - KEEP (*(SORT_NONE(.fini)))} - *(.text) - } - .const ALIGN(4) : { - *(.const) - } - .ctors ALIGN(4) : { - ${CONSTRUCTING+ . = ALIGN(4);} - ${CONSTRUCTING+ ___CTOR_LIST__ = .;} - ${CONSTRUCTING+ LONG(-1)} - *(.ctors) - ${CONSTRUCTING+ ___CTOR_END__ = .;} - ${CONSTRUCTING+ LONG(0)} - } - .dtors ALIGN(4) : { - ${CONSTRUCTING+ ___DTOR_LIST__ = .;} - ${CONSTRUCTING+ LONG(-1)} - ${CONSTRUCTING+ *(.dtors)} - ${CONSTRUCTING+ ___DTOR_END__ = .;} - ${CONSTRUCTING+ LONG(0)} - } - ${RELOCATING+ etext = .;} - .data : { - *(.data) - ${RELOCATING+ __edata = .}; - } - .bss : { - ${RELOCATING+ __bss_start = .}; - *(.bss) - *(COMMON) - ${RELOCATING+ _end = ALIGN(0x8)}; - ${RELOCATING+ __end = ALIGN(0x8)}; - } - .stab 0 ${RELOCATING+(NOLOAD)} : - { - [ .stab ] - } - .stabstr 0 ${RELOCATING+(NOLOAD)} : - { - [ .stabstr ] - } -} -EOF diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 26f25a4..744d8f8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,17 @@ 2019-12-17 Alan Modra <amodra@gmail.com> + * tic80-dis.c: Delete file. + * tic80-opc.c: Delete file. + * disassemble.c: Remove tic80 support. + * disassemble.h: Likewise. + * Makefile.am: Likewise. + * configure.ac: Likewise. + * Makefile.in: Regenerate. + * configure: Regenerate. + * po/POTFILES.in: Regenerate. + +2019-12-17 Alan Modra <amodra@gmail.com> + * bpf-ibld.c: Regenerate. 2019-12-16 Alan Modra <amodra@gmail.com> diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index 20a8a8d..3ef0c48 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -245,8 +245,6 @@ TARGET_LIBOPCODES_CFILES = \ tic54x-dis.c \ tic54x-opc.c \ tic6x-dis.c \ - tic80-dis.c \ - tic80-opc.c \ tilegx-dis.c \ tilegx-opc.c \ tilepro-dis.c \ diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 74faef8..6515df0 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -635,8 +635,6 @@ TARGET_LIBOPCODES_CFILES = \ tic54x-dis.c \ tic54x-opc.c \ tic6x-dis.c \ - tic80-dis.c \ - tic80-opc.c \ tilegx-dis.c \ tilegx-opc.c \ tilepro-dis.c \ @@ -1051,8 +1049,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tic54x-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tic54x-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tic6x-dis.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tic80-dis.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tic80-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tilegx-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tilegx-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tilepro-dis.Plo@am__quote@ diff --git a/opcodes/configure b/opcodes/configure index 6a0b919..5903fe4 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -12933,7 +12933,6 @@ if test x${all_targets} = xfalse ; then bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;; bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;; bfd_tic6x_arch) ta="$ta tic6x-dis.lo" ;; - bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; bfd_tilegx_arch) ta="$ta tilegx-dis.lo tilegx-opc.lo" ;; bfd_tilepro_arch) ta="$ta tilepro-dis.lo tilepro-opc.lo" ;; bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; diff --git a/opcodes/configure.ac b/opcodes/configure.ac index 500c701..96fb596 100644 --- a/opcodes/configure.ac +++ b/opcodes/configure.ac @@ -324,7 +324,6 @@ if test x${all_targets} = xfalse ; then bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;; bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;; bfd_tic6x_arch) ta="$ta tic6x-dis.lo" ;; - bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; bfd_tilegx_arch) ta="$ta tilegx-dis.lo tilegx-opc.lo" ;; bfd_tilepro_arch) ta="$ta tilepro-dis.lo tilepro-opc.lo" ;; bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 7c91997..cc1de69 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -88,7 +88,6 @@ #define ARCH_tic4x #define ARCH_tic54x #define ARCH_tic6x -#define ARCH_tic80 #define ARCH_tilegx #define ARCH_tilepro #define ARCH_v850 @@ -464,11 +463,6 @@ disassembler (enum bfd_architecture a, disassemble = print_insn_tic6x; break; #endif -#ifdef ARCH_tic80 - case bfd_arch_tic80: - disassemble = print_insn_tic80; - break; -#endif #ifdef ARCH_ft32 case bfd_arch_ft32: disassemble = print_insn_ft32; diff --git a/opcodes/disassemble.h b/opcodes/disassemble.h index ceb2814..9455085 100644 --- a/opcodes/disassemble.h +++ b/opcodes/disassemble.h @@ -87,7 +87,6 @@ extern int print_insn_tic30 (bfd_vma, disassemble_info *); extern int print_insn_tic4x (bfd_vma, disassemble_info *); extern int print_insn_tic54x (bfd_vma, disassemble_info *); extern int print_insn_tic6x (bfd_vma, disassemble_info *); -extern int print_insn_tic80 (bfd_vma, disassemble_info *); extern int print_insn_tilegx (bfd_vma, disassemble_info *); extern int print_insn_tilepro (bfd_vma, disassemble_info *); extern int print_insn_v850 (bfd_vma, disassemble_info *); diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in index eab55fc..7572204 100644 --- a/opcodes/po/POTFILES.in +++ b/opcodes/po/POTFILES.in @@ -205,8 +205,6 @@ tic4x-dis.c tic54x-dis.c tic54x-opc.c tic6x-dis.c -tic80-dis.c -tic80-opc.c tilegx-dis.c tilegx-opc.c tilepro-dis.c diff --git a/opcodes/tic80-dis.c b/opcodes/tic80-dis.c deleted file mode 100644 index 3bb05c0..0000000 --- a/opcodes/tic80-dis.c +++ /dev/null @@ -1,315 +0,0 @@ -/* Print TI TMS320C80 (MVP) instructions - Copyright (C) 1996-2019 Free Software Foundation, Inc. - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include "opcode/tic80.h" -#include "disassemble.h" - -static int length; - -/* Print an integer operand. Try to be somewhat smart about the - format by assuming that small positive or negative integers are - probably loop increment values, structure offsets, or similar - values that are more meaningful printed as signed decimal values. - Larger numbers are probably better printed as hex values. */ - -static void -print_operand_integer (struct disassemble_info *info, long value) -{ - if ((value > 9999 || value < -9999)) - (*info->fprintf_func) (info->stream, "%#lx", value); - else - (*info->fprintf_func) (info->stream, "%ld", value); -} - -/* FIXME: depends upon sizeof (long) == sizeof (float) and - also upon host floating point format matching target - floating point format. */ - -static void -print_operand_float (struct disassemble_info *info, long value) -{ - union { float f; long l; } fval; - - fval.l = value; - (*info->fprintf_func) (info->stream, "%g", fval.f); -} - -static void -print_operand_control_register (struct disassemble_info *info, long value) -{ - const char *tmp; - - tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CR); - if (tmp != NULL) - (*info->fprintf_func) (info->stream, "%s", tmp); - else - (*info->fprintf_func) (info->stream, "%#lx", value); -} - -static void -print_operand_condition_code (struct disassemble_info *info, long value) -{ - const char *tmp; - - tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CC); - if (tmp != NULL) - (*info->fprintf_func) (info->stream, "%s", tmp); - else - (*info->fprintf_func) (info->stream, "%ld", value); -} - -static void -print_operand_bitnum (struct disassemble_info *info, long value) -{ - int bitnum; - const char *tmp; - - bitnum = ~value & 0x1F; - tmp = tic80_value_to_symbol (bitnum, TIC80_OPERAND_BITNUM); - if (tmp != NULL) - (*info->fprintf_func) (info->stream, "%s", tmp); - else - (*info->fprintf_func) (info->stream, "%d", bitnum); -} - -/* Print the operand as directed by the flags. */ - -#define M_SI(insn,op) ((((op)->flags & TIC80_OPERAND_M_SI) != 0) && ((insn) & (1 << 17))) -#define M_LI(insn,op) ((((op)->flags & TIC80_OPERAND_M_LI) != 0) && ((insn) & (1 << 15))) -#define R_SCALED(insn,op) ((((op)->flags & TIC80_OPERAND_SCALED) != 0) && ((insn) & (1 << 11))) - -static void -print_operand (struct disassemble_info *info, - long value, - unsigned long insn, - const struct tic80_operand *operand, - bfd_vma memaddr) -{ - if ((operand->flags & TIC80_OPERAND_GPR) != 0) - { - (*info->fprintf_func) (info->stream, "r%ld", value); - if (M_SI (insn, operand) || M_LI (insn, operand)) - { - (*info->fprintf_func) (info->stream, ":m"); - } - } - else if ((operand->flags & TIC80_OPERAND_FPA) != 0) - (*info->fprintf_func) (info->stream, "a%ld", value); - - else if ((operand->flags & TIC80_OPERAND_PCREL) != 0) - (*info->print_address_func) (memaddr + 4 * value, info); - - else if ((operand->flags & TIC80_OPERAND_BASEREL) != 0) - (*info->print_address_func) (value, info); - - else if ((operand->flags & TIC80_OPERAND_BITNUM) != 0) - print_operand_bitnum (info, value); - - else if ((operand->flags & TIC80_OPERAND_CC) != 0) - print_operand_condition_code (info, value); - - else if ((operand->flags & TIC80_OPERAND_CR) != 0) - print_operand_control_register (info, value); - - else if ((operand->flags & TIC80_OPERAND_FLOAT) != 0) - print_operand_float (info, value); - - else if ((operand->flags & TIC80_OPERAND_BITFIELD)) - (*info->fprintf_func) (info->stream, "%#lx", value); - - else - print_operand_integer (info, value); - - /* If this is a scaled operand, then print the modifier. */ - if (R_SCALED (insn, operand)) - (*info->fprintf_func) (info->stream, ":s"); -} - -/* Get the next 32 bit word from the instruction stream and convert it - into internal format in the unsigned long INSN, for which we are - passed the address. Return 0 on success, -1 on error. */ - -static int -fill_instruction (struct disassemble_info *info, - bfd_vma memaddr, - unsigned long *insnp) -{ - bfd_byte buffer[4]; - int status; - - /* Get the bits for the next 32 bit word and put in buffer. */ - status = (*info->read_memory_func) (memaddr + length, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - /* Read was successful, so increment count of bytes read and convert - the bits into internal format. */ - - length += 4; - if (info->endian == BFD_ENDIAN_LITTLE) - *insnp = bfd_getl32 (buffer); - - else if (info->endian == BFD_ENDIAN_BIG) - *insnp = bfd_getb32 (buffer); - - else - /* FIXME: Should probably just default to one or the other. */ - abort (); - - return 0; -} - -/* We have chosen an opcode table entry. */ - -static int -print_one_instruction (struct disassemble_info *info, - bfd_vma memaddr, - unsigned long insn, - const struct tic80_opcode *opcode) -{ - const struct tic80_operand *operand; - long value; - int status; - const unsigned char *opindex; - int close_paren; - - (*info->fprintf_func) (info->stream, "%-10s", opcode->name); - - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - operand = tic80_operands + *opindex; - - /* Extract the value from the instruction. */ - if (operand->extract) - value = (*operand->extract) (insn, NULL); - - else if (operand->bits == 32) - { - status = fill_instruction (info, memaddr, (unsigned long *) &value); - if (status == -1) - return status; - } - else - { - value = (insn >> operand->shift) & ((1 << operand->bits) - 1); - - if ((operand->flags & TIC80_OPERAND_SIGNED) != 0 - && (value & (1 << (operand->bits - 1))) != 0) - value -= 1 << operand->bits; - } - - /* If this operand is enclosed in parenthesis, then print - the open paren, otherwise just print the regular comma - separator, except for the first operand. */ - if ((operand->flags & TIC80_OPERAND_PARENS) == 0) - { - close_paren = 0; - if (opindex != opcode->operands) - (*info->fprintf_func) (info->stream, ","); - } - else - { - close_paren = 1; - (*info->fprintf_func) (info->stream, "("); - } - - print_operand (info, value, insn, operand, memaddr); - - /* If we printed an open paren before printing this operand, close - it now. The flag gets reset on each loop. */ - if (close_paren) - (*info->fprintf_func) (info->stream, ")"); - } - - return length; -} - -/* There are no specific bits that tell us for certain whether a vector - instruction opcode contains one or two instructions. However since - a destination register of r0 is illegal, we can check for nonzero - values in both destination register fields. Only opcodes that have - two valid instructions will have non-zero in both. */ - -#define TWO_INSN(insn) ((((insn) & (0x1F << 27)) != 0) && (((insn) & (0x1F << 22)) != 0)) - -static int -print_instruction (struct disassemble_info *info, - bfd_vma memaddr, - unsigned long insn, - const struct tic80_opcode *vec_opcode) -{ - const struct tic80_opcode *opcode; - const struct tic80_opcode *opcode_end; - - /* Find the first opcode match in the opcodes table. For vector - opcodes (vec_opcode != NULL) find the first match that is not the - previously found match. FIXME: there should be faster ways to - search (hash table or binary search), but don't worry too much - about it until other TIc80 support is finished. */ - - opcode_end = tic80_opcodes + tic80_num_opcodes; - for (opcode = tic80_opcodes; opcode < opcode_end; opcode++) - { - if ((insn & opcode->mask) == opcode->opcode && - opcode != vec_opcode) - break; - } - - if (opcode == opcode_end) - { - /* No match found, just print the bits as a .word directive. */ - (*info->fprintf_func) (info->stream, ".word %#08lx", insn); - } - else - { - /* Match found, decode the instruction. */ - length = print_one_instruction (info, memaddr, insn, opcode); - if (opcode->flags & TIC80_VECTOR && vec_opcode == NULL && TWO_INSN (insn)) - { - /* There is another instruction to print from the same opcode. - Print the separator and then find and print the other - instruction. */ - (*info->fprintf_func) (info->stream, " || "); - length = print_instruction (info, memaddr, insn, opcode); - } - } - - return length; -} - -int -print_insn_tic80 (bfd_vma memaddr, struct disassemble_info *info) -{ - unsigned long insn; - int status; - - length = 0; - info->bytes_per_line = 8; - status = fill_instruction (info, memaddr, &insn); - if (status != -1) - status = print_instruction (info, memaddr, insn, NULL); - - return status; -} diff --git a/opcodes/tic80-opc.c b/opcodes/tic80-opc.c deleted file mode 100644 index 517bf62..0000000 --- a/opcodes/tic80-opc.c +++ /dev/null @@ -1,1211 +0,0 @@ -/* Opcode table for TI TMS320C80 (MVP). - Copyright (C) 1996-2019 Free Software Foundation, Inc. - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include "opcode/tic80.h" - -/* This file holds various tables for the TMS320C80 (MVP). - - The opcode table is strictly constant data, so the compiler should - be able to put it in the .text section. - - This file also holds the operand table. All knowledge about - inserting operands into instructions and vice-versa is kept in this - file. - - The predefined register table maps from register names to register - values. */ - - -/* Table of predefined symbol names, such as general purpose registers, - floating point registers, condition codes, control registers, and bit - numbers. - - The table is sorted case independently by name so that it is suitable for - searching via a binary search using a case independent comparison - function. - - Note that the type of the symbol is stored in the upper bits of the value - field, which allows the value and type to be passed around as a unit in a - single int. The types have to be masked off before using the numeric - value as a number. -*/ - -const struct predefined_symbol tic80_predefined_symbols[] = -{ - { "a0", TIC80_OPERAND_FPA | 0 }, - { "a1", TIC80_OPERAND_FPA | 1 }, - { "alw.b", TIC80_OPERAND_CC | 7 }, - { "alw.h", TIC80_OPERAND_CC | 15 }, - { "alw.w", TIC80_OPERAND_CC | 23 }, - { "ANASTAT", TIC80_OPERAND_CR | 0x34 }, - { "BRK1", TIC80_OPERAND_CR | 0x39 }, - { "BRK2", TIC80_OPERAND_CR | 0x3A }, - { "CONFIG", TIC80_OPERAND_CR | 2 }, - { "DLRU", TIC80_OPERAND_CR | 0x500 }, - { "DTAG0", TIC80_OPERAND_CR | 0x400 }, - { "DTAG1", TIC80_OPERAND_CR | 0x401 }, - { "DTAG10", TIC80_OPERAND_CR | 0x40A }, - { "DTAG11", TIC80_OPERAND_CR | 0x40B }, - { "DTAG12", TIC80_OPERAND_CR | 0x40C }, - { "DTAG13", TIC80_OPERAND_CR | 0x40D }, - { "DTAG14", TIC80_OPERAND_CR | 0x40E }, - { "DTAG15", TIC80_OPERAND_CR | 0x40F }, - { "DTAG2", TIC80_OPERAND_CR | 0x402 }, - { "DTAG3", TIC80_OPERAND_CR | 0x403 }, - { "DTAG4", TIC80_OPERAND_CR | 0x404 }, - { "DTAG5", TIC80_OPERAND_CR | 0x405 }, - { "DTAG6", TIC80_OPERAND_CR | 0x406 }, - { "DTAG7", TIC80_OPERAND_CR | 0x407 }, - { "DTAG8", TIC80_OPERAND_CR | 0x408 }, - { "DTAG9", TIC80_OPERAND_CR | 0x409 }, - { "ECOMCNTL", TIC80_OPERAND_CR | 0x33 }, - { "EIP", TIC80_OPERAND_CR | 1 }, - { "EPC", TIC80_OPERAND_CR | 0 }, - { "eq.b", TIC80_OPERAND_BITNUM | 0 }, - { "eq.f", TIC80_OPERAND_BITNUM | 20 }, - { "eq.h", TIC80_OPERAND_BITNUM | 10 }, - { "eq.w", TIC80_OPERAND_BITNUM | 20 }, - { "eq0.b", TIC80_OPERAND_CC | 2 }, - { "eq0.h", TIC80_OPERAND_CC | 10 }, - { "eq0.w", TIC80_OPERAND_CC | 18 }, - { "FLTADR", TIC80_OPERAND_CR | 0x11 }, - { "FLTDTH", TIC80_OPERAND_CR | 0x14 }, - { "FLTDTL", TIC80_OPERAND_CR | 0x13 }, - { "FLTOP", TIC80_OPERAND_CR | 0x10 }, - { "FLTTAG", TIC80_OPERAND_CR | 0x12 }, - { "FPST", TIC80_OPERAND_CR | 8 }, - { "ge.b", TIC80_OPERAND_BITNUM | 5 }, - { "ge.f", TIC80_OPERAND_BITNUM | 25 }, - { "ge.h", TIC80_OPERAND_BITNUM | 15 }, - { "ge.w", TIC80_OPERAND_BITNUM | 25 }, - { "ge0.b", TIC80_OPERAND_CC | 3 }, - { "ge0.h", TIC80_OPERAND_CC | 11 }, - { "ge0.w", TIC80_OPERAND_CC | 19 }, - { "gt.b", TIC80_OPERAND_BITNUM | 2 }, - { "gt.f", TIC80_OPERAND_BITNUM | 22 }, - { "gt.h", TIC80_OPERAND_BITNUM | 12 }, - { "gt.w", TIC80_OPERAND_BITNUM | 22 }, - { "gt0.b", TIC80_OPERAND_CC | 1 }, - { "gt0.h", TIC80_OPERAND_CC | 9 }, - { "gt0.w", TIC80_OPERAND_CC | 17 }, - { "hi.b", TIC80_OPERAND_BITNUM | 6 }, - { "hi.h", TIC80_OPERAND_BITNUM | 16 }, - { "hi.w", TIC80_OPERAND_BITNUM | 26 }, - { "hs.b", TIC80_OPERAND_BITNUM | 9 }, - { "hs.h", TIC80_OPERAND_BITNUM | 19 }, - { "hs.w", TIC80_OPERAND_BITNUM | 29 }, - { "ib.f", TIC80_OPERAND_BITNUM | 28 }, - { "IE", TIC80_OPERAND_CR | 6 }, - { "ILRU", TIC80_OPERAND_CR | 0x300 }, - { "in.f", TIC80_OPERAND_BITNUM | 27 }, - { "IN0P", TIC80_OPERAND_CR | 0x4000 }, - { "IN1P", TIC80_OPERAND_CR | 0x4001 }, - { "INTPEN", TIC80_OPERAND_CR | 4 }, - { "ITAG0", TIC80_OPERAND_CR | 0x200 }, - { "ITAG1", TIC80_OPERAND_CR | 0x201 }, - { "ITAG10", TIC80_OPERAND_CR | 0x20A }, - { "ITAG11", TIC80_OPERAND_CR | 0x20B }, - { "ITAG12", TIC80_OPERAND_CR | 0x20C }, - { "ITAG13", TIC80_OPERAND_CR | 0x20D }, - { "ITAG14", TIC80_OPERAND_CR | 0x20E }, - { "ITAG15", TIC80_OPERAND_CR | 0x20F }, - { "ITAG2", TIC80_OPERAND_CR | 0x202 }, - { "ITAG3", TIC80_OPERAND_CR | 0x203 }, - { "ITAG4", TIC80_OPERAND_CR | 0x204 }, - { "ITAG5", TIC80_OPERAND_CR | 0x205 }, - { "ITAG6", TIC80_OPERAND_CR | 0x206 }, - { "ITAG7", TIC80_OPERAND_CR | 0x207 }, - { "ITAG8", TIC80_OPERAND_CR | 0x208 }, - { "ITAG9", TIC80_OPERAND_CR | 0x209 }, - { "le.b", TIC80_OPERAND_BITNUM | 3 }, - { "le.f", TIC80_OPERAND_BITNUM | 23 }, - { "le.h", TIC80_OPERAND_BITNUM | 13 }, - { "le.w", TIC80_OPERAND_BITNUM | 23 }, - { "le0.b", TIC80_OPERAND_CC | 6 }, - { "le0.h", TIC80_OPERAND_CC | 14 }, - { "le0.w", TIC80_OPERAND_CC | 22 }, - { "lo.b", TIC80_OPERAND_BITNUM | 8 }, - { "lo.h", TIC80_OPERAND_BITNUM | 18 }, - { "lo.w", TIC80_OPERAND_BITNUM | 28 }, - { "ls.b", TIC80_OPERAND_BITNUM | 7 }, - { "ls.h", TIC80_OPERAND_BITNUM | 17 }, - { "ls.w", TIC80_OPERAND_BITNUM | 27 }, - { "lt.b", TIC80_OPERAND_BITNUM | 4 }, - { "lt.f", TIC80_OPERAND_BITNUM | 24 }, - { "lt.h", TIC80_OPERAND_BITNUM | 14 }, - { "lt.w", TIC80_OPERAND_BITNUM | 24 }, - { "lt0.b", TIC80_OPERAND_CC | 4 }, - { "lt0.h", TIC80_OPERAND_CC | 12 }, - { "lt0.w", TIC80_OPERAND_CC | 20 }, - { "MIP", TIC80_OPERAND_CR | 0x31 }, - { "MPC", TIC80_OPERAND_CR | 0x30 }, - { "ne.b", TIC80_OPERAND_BITNUM | 1 }, - { "ne.f", TIC80_OPERAND_BITNUM | 21 }, - { "ne.h", TIC80_OPERAND_BITNUM | 11 }, - { "ne.w", TIC80_OPERAND_BITNUM | 21 }, - { "ne0.b", TIC80_OPERAND_CC | 5 }, - { "ne0.h", TIC80_OPERAND_CC | 13 }, - { "ne0.w", TIC80_OPERAND_CC | 21 }, - { "nev.b", TIC80_OPERAND_CC | 0 }, - { "nev.h", TIC80_OPERAND_CC | 8 }, - { "nev.w", TIC80_OPERAND_CC | 16 }, - { "ob.f", TIC80_OPERAND_BITNUM | 29 }, - { "or.f", TIC80_OPERAND_BITNUM | 31 }, - { "ou.f", TIC80_OPERAND_BITNUM | 26 }, - { "OUTP", TIC80_OPERAND_CR | 0x4002 }, - { "PKTREQ", TIC80_OPERAND_CR | 0xD }, - { "PPERROR", TIC80_OPERAND_CR | 0xA }, - { "r0", TIC80_OPERAND_GPR | 0 }, - { "r1", TIC80_OPERAND_GPR | 1 }, - { "r10", TIC80_OPERAND_GPR | 10 }, - { "r11", TIC80_OPERAND_GPR | 11 }, - { "r12", TIC80_OPERAND_GPR | 12 }, - { "r13", TIC80_OPERAND_GPR | 13 }, - { "r14", TIC80_OPERAND_GPR | 14 }, - { "r15", TIC80_OPERAND_GPR | 15 }, - { "r16", TIC80_OPERAND_GPR | 16 }, - { "r17", TIC80_OPERAND_GPR | 17 }, - { "r18", TIC80_OPERAND_GPR | 18 }, - { "r19", TIC80_OPERAND_GPR | 19 }, - { "r2", TIC80_OPERAND_GPR | 2 }, - { "r20", TIC80_OPERAND_GPR | 20 }, - { "r21", TIC80_OPERAND_GPR | 21 }, - { "r22", TIC80_OPERAND_GPR | 22 }, - { "r23", TIC80_OPERAND_GPR | 23 }, - { "r24", TIC80_OPERAND_GPR | 24 }, - { "r25", TIC80_OPERAND_GPR | 25 }, - { "r26", TIC80_OPERAND_GPR | 26 }, - { "r27", TIC80_OPERAND_GPR | 27 }, - { "r28", TIC80_OPERAND_GPR | 28 }, - { "r29", TIC80_OPERAND_GPR | 29 }, - { "r3", TIC80_OPERAND_GPR | 3 }, - { "r30", TIC80_OPERAND_GPR | 30 }, - { "r31", TIC80_OPERAND_GPR | 31 }, - { "r4", TIC80_OPERAND_GPR | 4 }, - { "r5", TIC80_OPERAND_GPR | 5 }, - { "r6", TIC80_OPERAND_GPR | 6 }, - { "r7", TIC80_OPERAND_GPR | 7 }, - { "r8", TIC80_OPERAND_GPR | 8 }, - { "r9", TIC80_OPERAND_GPR | 9 }, - { "SYSSTK", TIC80_OPERAND_CR | 0x20 }, - { "SYSTMP", TIC80_OPERAND_CR | 0x21 }, - { "TCOUNT", TIC80_OPERAND_CR | 0xE }, - { "TSCALE", TIC80_OPERAND_CR | 0xF }, - { "uo.f", TIC80_OPERAND_BITNUM | 30 }, -}; - -const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / sizeof (struct predefined_symbol); - -/* This function takes a predefined symbol name in NAME, symbol class - in CLASS, and translates it to a numeric value, which it returns. - - If CLASS is zero, any symbol that matches NAME is translated. If - CLASS is non-zero, then only a symbol that has symbol_class CLASS is - matched. - - If no translation is possible, it returns -1, a value not used by - any predefined symbol. Note that the predefined symbol array is - presorted case independently by name. - - This function is implemented with the assumption that there are no - duplicate names in the predefined symbol array, which happens to be - true at the moment. - - */ - -int -tic80_symbol_to_value (char *name, int symbol_class) -{ - const struct predefined_symbol *pdsp; - int low = 0; - int middle; - int high = tic80_num_predefined_symbols - 1; - int cmp; - int rtnval = -1; - - while (low <= high) - { - middle = (low + high) / 2; - cmp = strcasecmp (name, tic80_predefined_symbols[middle].name); - if (cmp < 0) - { - high = middle - 1; - } - else if (cmp > 0) - { - low = middle + 1; - } - else - { - pdsp = &tic80_predefined_symbols[middle]; - if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp))) - { - rtnval = PDS_VALUE (pdsp); - } - /* For now we assume that there are no duplicate names */ - break; - } - } - return (rtnval); -} - -/* This function takes a value VAL and finds a matching predefined - symbol that is in the operand symbol_class specified by CLASS. If CLASS - is zero, the first matching symbol is returned. */ - -const char * -tic80_value_to_symbol (int val, int symbol_class) -{ - const struct predefined_symbol *pdsp; - int ival; - char *name; - - name = NULL; - for (pdsp = tic80_predefined_symbols; - pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols; - pdsp++) - { - ival = PDS_VALUE (pdsp) & ~TIC80_OPERAND_MASK; - if (ival == val) - { - if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp))) - { - /* Found the desired match */ - name = PDS_NAME (pdsp); - break; - } - } - } - return (name); -} - -/* This function returns a pointer to the next symbol in the predefined - symbol table after PDSP, or NULL if PDSP points to the last symbol. If - PDSP is NULL, it returns the first symbol in the table. Thus it can be - used to walk through the table by first calling it with NULL and then - calling it with each value it returned on the previous call, until it - returns NULL. */ - -const struct predefined_symbol * -tic80_next_predefined_symbol (const struct predefined_symbol *pdsp) -{ - if (pdsp == NULL) - { - pdsp = tic80_predefined_symbols; - } - else if (pdsp >= tic80_predefined_symbols && - pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols - 1) - { - pdsp++; - } - else - { - pdsp = NULL; - } - return (pdsp); -} - - - -/* The operands table. The fields are: - - bits, shift, insertion function, extraction function, flags - */ - -const struct tic80_operand tic80_operands[] = -{ - - /* The zero index is used to indicate the end of the list of operands. */ - -#define UNUSED (0) - { 0, 0, 0, 0, 0 }, - - /* Short signed immediate value in bits 14-0. */ - -#define SSI (UNUSED + 1) - { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED }, - - /* Short unsigned immediate value in bits 14-0 */ - -#define SUI (SSI + 1) - { 15, 0, NULL, NULL, 0 }, - - /* Short unsigned bitfield in bits 14-0. We distinguish this - from a regular unsigned immediate value only for the convenience - of the disassembler and the user. */ - -#define SUBF (SUI + 1) - { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD }, - - /* Long signed immediate in following 32 bit word */ - -#define LSI (SUBF + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED }, - - /* Long unsigned immediate in following 32 bit word */ - -#define LUI (LSI + 1) - { 32, 0, NULL, NULL, 0 }, - - /* Long unsigned bitfield in following 32 bit word. We distinguish - this from a regular unsigned immediate value only for the - convenience of the disassembler and the user. */ - -#define LUBF (LUI + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD }, - - /* Single precision floating point immediate in following 32 bit - word. */ - -#define SPFI (LUBF + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT }, - - /* Register in bits 4-0 */ - -#define REG_0 (SPFI + 1) - { 5, 0, NULL, NULL, TIC80_OPERAND_GPR }, - - /* Even register in bits 4-0 */ - -#define REG_0_E (REG_0 + 1) - { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN }, - - /* Register in bits 26-22 */ - -#define REG_22 (REG_0_E + 1) - { 5, 22, NULL, NULL, TIC80_OPERAND_GPR }, - - /* Even register in bits 26-22 */ - -#define REG_22_E (REG_22 + 1) - { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN }, - - /* Register in bits 31-27 */ - -#define REG_DEST (REG_22_E + 1) - { 5, 27, NULL, NULL, TIC80_OPERAND_GPR }, - - /* Even register in bits 31-27 */ - -#define REG_DEST_E (REG_DEST + 1) - { 5, 27, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN }, - - /* Floating point accumulator register (a0-a3) specified by bit 16 (MSB) - and bit 11 (LSB) */ - /* FIXME! Needs to use functions to insert and extract the register - number in bits 16 and 11. */ - -#define REG_FPA (REG_DEST_E + 1) - { 0, 0, NULL, NULL, TIC80_OPERAND_FPA }, - - /* Short signed PC word offset in bits 14-0 */ - -#define OFF_SS_PC (REG_FPA + 1) - { 15, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED }, - - /* Long signed PC word offset in following 32 bit word */ - -#define OFF_SL_PC (OFF_SS_PC + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED }, - - /* Short signed base relative byte offset in bits 14-0 */ - -#define OFF_SS_BR (OFF_SL_PC + 1) - { 15, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED }, - - /* Long signed base relative byte offset in following 32 bit word */ - -#define OFF_SL_BR (OFF_SS_BR + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED }, - - /* Long signed base relative byte offset in following 32 bit word - with optional ":s" modifier flag in bit 11 */ - -#define OFF_SL_BR_SCALED (OFF_SL_BR + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED }, - - /* BITNUM in bits 31-27 */ - -#define BITNUM (OFF_SL_BR_SCALED + 1) - { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM }, - - /* Condition code in bits 31-27 */ - -#define CC (BITNUM + 1) - { 5, 27, NULL, NULL, TIC80_OPERAND_CC }, - - /* Control register number in bits 14-0 */ - -#define CR_SI (CC + 1) - { 15, 0, NULL, NULL, TIC80_OPERAND_CR }, - - /* Control register number in next 32 bit word */ - -#define CR_LI (CR_SI + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_CR }, - - /* A base register in bits 26-22, enclosed in parens */ - -#define REG_BASE (CR_LI + 1) - { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS }, - - /* A base register in bits 26-22, enclosed in parens, with optional ":m" - flag in bit 17 (short immediate instructions only) */ - -#define REG_BASE_M_SI (REG_BASE + 1) - { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI }, - - /* A base register in bits 26-22, enclosed in parens, with optional ":m" - flag in bit 15 (long immediate and register instructions only) */ - -#define REG_BASE_M_LI (REG_BASE_M_SI + 1) - { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI }, - - /* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */ - -#define REG_SCALED (REG_BASE_M_LI + 1) - { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED }, - - /* Unsigned immediate in bits 4-0, used only for shift instructions */ - -#define ROTATE (REG_SCALED + 1) - { 5, 0, NULL, NULL, 0 }, - - /* Unsigned immediate in bits 9-5, used only for shift instructions */ -#define ENDMASK (ROTATE + 1) - { 5, 5, NULL, NULL, TIC80_OPERAND_ENDMASK }, - -}; - -const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands); - - -/* Macros used to generate entries for the opcodes table. */ - -#define FIXME 0 - -/* Short-Immediate Format Instructions - basic opcode */ -#define OP_SI(x) (((x) & 0x7F) << 15) -#define MASK_SI OP_SI(0x7F) - -/* Long-Immediate Format Instructions - basic opcode */ -#define OP_LI(x) (((x) & 0x3FF) << 12) -#define MASK_LI OP_LI(0x3FF) - -/* Register Format Instructions - basic opcode */ -#define OP_REG(x) OP_LI(x) /* For readability */ -#define MASK_REG MASK_LI /* For readability */ - -/* The 'n' bit at bit 10 */ -#define n(x) ((x) << 10) - -/* The 'i' bit at bit 11 */ -#define i(x) ((x) << 11) - -/* The 'F' bit at bit 27 */ -#define F(x) ((x) << 27) - -/* The 'E' bit at bit 27 */ -#define E(x) ((x) << 27) - -/* The 'M' bit at bit 15 in register and long immediate opcodes */ -#define M_REG(x) ((x) << 15) -#define M_LI(x) ((x) << 15) - -/* The 'M' bit at bit 17 in short immediate opcodes */ -#define M_SI(x) ((x) << 17) - -/* The 'SZ' field at bits 14-13 in register and long immediate opcodes */ -#define SZ_REG(x) ((x) << 13) -#define SZ_LI(x) ((x) << 13) - -/* The 'SZ' field at bits 16-15 in short immediate opcodes */ -#define SZ_SI(x) ((x) << 15) - -/* The 'D' (direct external memory access) bit at bit 10 in long immediate - and register opcodes. */ -#define D(x) ((x) << 10) - -/* The 'S' (scale offset by data size) bit at bit 11 in long immediate - and register opcodes. */ -#define S(x) ((x) << 11) - -/* The 'PD' field at bits 10-9 in floating point instructions */ -#define PD(x) ((x) << 9) - -/* The 'P2' field at bits 8-7 in floating point instructions */ -#define P2(x) ((x) << 7) - -/* The 'P1' field at bits 6-5 in floating point instructions */ -#define P1(x) ((x) << 5) - -/* The 'a' field at bit 16 in vector instructions */ -#define V_a1(x) ((x) << 16) - -/* The 'a' field at bit 11 in vector instructions */ -#define V_a0(x) ((x) << 11) - -/* The 'm' field at bit 10 in vector instructions */ -#define V_m(x) ((x) << 10) - -/* The 'S' field at bit 9 in vector instructions */ -#define V_S(x) ((x) << 9) - -/* The 'Z' field at bit 8 in vector instructions */ -#define V_Z(x) ((x) << 8) - -/* The 'p' field at bit 6 in vector instructions */ -#define V_p(x) ((x) << 6) - -/* The opcode field at bits 21-17 for vector instructions */ -#define OP_V(x) ((x) << 17) -#define MASK_V OP_V(0x1F) - - -/* The opcode table. Formatted for better readability on a wide screen. Also, all - entries with the same mnemonic are sorted so that they are adjacent in the table, - allowing the use of a hash table to locate the first of a sequence of opcodes that have - a particular name. The short immediate forms also come before the long immediate forms - so that the assembler will pick the "best fit" for the size of the operand, except for - the case of the PC relative forms, where the long forms come first and are the default - forms. */ - -const struct tic80_opcode tic80_opcodes[] = { - - /* The "nop" instruction is really "rdcr 0,r0". We put it first so that this - specific bit pattern will get disassembled as a nop rather than an rdcr. The - mask of all ones ensures that this will happen. */ - - {"nop", OP_SI(0x4), ~0, 0, {0} }, - - /* The "br" instruction is really "bbz target,r0,31". We put it first so that - this specific bit pattern will get disassembled as a br rather than bbz. */ - - {"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} }, - {"br", OP_LI(0x391), 0xFFFFF000, 0, {OFF_SL_PC} }, - {"br", OP_REG(0x390), 0xFFFFF000, 0, {REG_0} }, - {"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} }, - {"br.a", OP_LI(0x393), 0xFFFFF000, 0, {OFF_SL_PC} }, - {"br.a", OP_REG(0x392), 0xFFFFF000, 0, {REG_0} }, - - /* Signed integer ADD */ - - {"add", OP_SI(0x58), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, - {"add", OP_LI(0x3B1), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, - {"add", OP_REG(0x3B0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Unsigned integer ADD */ - - {"addu", OP_SI(0x59), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, - {"addu", OP_LI(0x3B3), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, - {"addu", OP_REG(0x3B2), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Bitwise AND */ - - {"and", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, - {"and", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, - {"and", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"and.tt", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, - {"and.tt", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, - {"and.tt", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Bitwise AND with ones complement of both sources */ - - {"and.ff", OP_SI(0x18), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, - {"and.ff", OP_LI(0x331), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, - {"and.ff", OP_REG(0x330), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Bitwise AND with ones complement of source 1 */ - - {"and.ft", OP_SI(0x14), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, - {"and.ft", OP_LI(0x329), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, - {"and.ft", OP_REG(0x328), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Bitwise AND with ones complement of source 2 */ - - {"and.tf", OP_SI(0x12), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, - {"and.tf", OP_LI(0x325), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, - {"and.tf", OP_REG(0x324), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Branch Bit One - nonannulled */ - - {"bbo", OP_SI(0x4A), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, - {"bbo", OP_LI(0x395), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, - {"bbo", OP_REG(0x394), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, - - /* Branch Bit One - annulled */ - - {"bbo.a", OP_SI(0x4B), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, - {"bbo.a", OP_LI(0x397), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, - {"bbo.a", OP_REG(0x396), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, - - /* Branch Bit Zero - nonannulled */ - - {"bbz", OP_SI(0x48), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, - {"bbz", OP_LI(0x391), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, - {"bbz", OP_REG(0x390), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, - - /* Branch Bit Zero - annulled */ - - {"bbz.a", OP_SI(0x49), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, - {"bbz.a", OP_LI(0x393), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, - {"bbz.a", OP_REG(0x392), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, - - /* Branch Conditional - nonannulled */ - - {"bcnd", OP_SI(0x4C), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, - {"bcnd", OP_LI(0x399), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, - {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, - - /* Branch Conditional - annulled */ - - {"bcnd.a", OP_SI(0x4D), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, - {"bcnd.a", OP_LI(0x39B), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, - {"bcnd.a", OP_REG(0x39A), MASK_REG, 0, {REG_0, REG_22, CC} }, - - /* Branch Control Register */ - - {"brcr", OP_SI(0x6), MASK_SI, 0, {CR_SI} }, - {"brcr", OP_LI(0x30D), MASK_LI, 0, {CR_LI} }, - {"brcr", OP_REG(0x30C), MASK_REG, 0, {REG_0} }, - - /* Branch and save return - nonannulled */ - - {"bsr", OP_SI(0x40), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, - {"bsr", OP_LI(0x381), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, - {"bsr", OP_REG(0x380), MASK_REG, 0, {REG_0, REG_DEST} }, - - /* Branch and save return - annulled */ - - {"bsr.a", OP_SI(0x41), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, - {"bsr.a", OP_LI(0x383), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, - {"bsr.a", OP_REG(0x382), MASK_REG, 0, {REG_0, REG_DEST} }, - - /* Send command */ - - {"cmnd", OP_SI(0x2), MASK_SI, 0, {SUI} }, - {"cmnd", OP_LI(0x305), MASK_LI, 0, {LUI} }, - {"cmnd", OP_REG(0x304), MASK_REG, 0, {REG_0} }, - - /* Integer compare */ - - {"cmp", OP_SI(0x50), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, - {"cmp", OP_LI(0x3A1), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, - {"cmp", OP_REG(0x3A0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Flush data cache subblock - don't clear subblock preset flag */ - - {"dcachec", OP_SI(0x38), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} }, - {"dcachec", OP_LI(0x371), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} }, - {"dcachec", OP_REG(0x370), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} }, - - /* Flush data cache subblock - clear subblock preset flag */ - - {"dcachef", OP_SI(0x38) | F(1), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} }, - {"dcachef", OP_LI(0x371) | F(1), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} }, - {"dcachef", OP_REG(0x370) | F(1), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} }, - - /* Direct load signed data into register */ - - {"dld", OP_LI(0x345) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld", OP_REG(0x344) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.b", OP_LI(0x341) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.b", OP_REG(0x340) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.d", OP_LI(0x347) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"dld.d", OP_REG(0x346) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"dld.h", OP_LI(0x343) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.h", OP_REG(0x342) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - - /* Direct load unsigned data into register */ - - {"dld.ub", OP_LI(0x351) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.ub", OP_REG(0x350) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.uh", OP_LI(0x353) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.uh", OP_REG(0x352) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - - /* Direct store data into memory */ - - {"dst", OP_LI(0x365) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst", OP_REG(0x364) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst.b", OP_LI(0x361) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst.b", OP_REG(0x360) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst.d", OP_LI(0x367) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"dst.d", OP_REG(0x366) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"dst.h", OP_LI(0x363) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst.h", OP_REG(0x362) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - - /* Emulation stop */ - - {"estop", OP_LI(0x3FC), MASK_LI, 0, {0} }, - - /* Emulation trap */ - - {"etrap", OP_SI(0x1) | E(1), MASK_SI | E(1), 0, {SUI} }, - {"etrap", OP_LI(0x303) | E(1), MASK_LI | E(1), 0, {LUI} }, - {"etrap", OP_REG(0x302) | E(1), MASK_REG | E(1), 0, {REG_0} }, - - /* Floating-point addition */ - - {"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, - {"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, - {"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, - {"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, - {"fadd.ssd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, - {"fadd.ssd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, - {"fadd.sss", OP_LI(0x3E1) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, - {"fadd.sss", OP_REG(0x3E0) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, - - /* Floating point compare */ - - {"fcmp.dd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST} }, - {"fcmp.ds", OP_REG(0x3EA) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST} }, - {"fcmp.sd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST} }, - {"fcmp.sd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST} }, - {"fcmp.ss", OP_LI(0x3EB) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, - {"fcmp.ss", OP_REG(0x3EA) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, - - /* Floating point divide */ - - {"fdiv.ddd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, - {"fdiv.dsd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, - {"fdiv.sdd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, - {"fdiv.sdd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, - {"fdiv.ssd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, - {"fdiv.ssd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, - {"fdiv.sss", OP_LI(0x3E7) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, - {"fdiv.sss", OP_REG(0x3E6) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, - - /* Floating point multiply */ - - {"fmpy.ddd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, - {"fmpy.dsd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, - {"fmpy.iii", OP_LI(0x3E5) | PD(2) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_22, REG_DEST} }, - {"fmpy.iii", OP_REG(0x3E4) | PD(2) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, - {"fmpy.sdd", OP_LI(0x3E5) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, - {"fmpy.sdd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, - {"fmpy.ssd", OP_LI(0x3E5) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, - {"fmpy.ssd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, - {"fmpy.sss", OP_LI(0x3E5) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, - {"fmpy.sss", OP_REG(0x3E4) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, - {"fmpy.uuu", OP_LI(0x3E5) | PD(3) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LUI, REG_22, REG_DEST} }, - {"fmpy.uuu", OP_REG(0x3E4) | PD(3) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, - - /* Convert/Round to Minus Infinity */ - - {"frndm.dd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, - {"frndm.di", OP_REG(0x3E8) | PD(2) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndm.ds", OP_REG(0x3E8) | PD(0) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndm.du", OP_REG(0x3E8) | PD(3) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndm.id", OP_LI(0x3E9) | PD(1) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndm.id", OP_REG(0x3E8) | PD(1) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndm.is", OP_LI(0x3E9) | PD(0) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndm.is", OP_REG(0x3E8) | PD(0) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndm.sd", OP_LI(0x3E9) | PD(1) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, - {"frndm.sd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndm.si", OP_LI(0x3E9) | PD(2) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndm.si", OP_REG(0x3E8) | PD(2) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndm.ss", OP_LI(0x3E9) | PD(0) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndm.ss", OP_REG(0x3E8) | PD(0) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndm.su", OP_LI(0x3E9) | PD(3) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndm.su", OP_REG(0x3E8) | PD(3) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndm.ud", OP_LI(0x3E9) | PD(1) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndm.ud", OP_REG(0x3E8) | PD(1) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndm.us", OP_LI(0x3E9) | PD(0) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndm.us", OP_REG(0x3E8) | PD(0) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - - /* Convert/Round to Nearest */ - - {"frndn.dd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, - {"frndn.di", OP_REG(0x3E8) | PD(2) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndn.ds", OP_REG(0x3E8) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndn.du", OP_REG(0x3E8) | PD(3) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndn.id", OP_LI(0x3E9) | PD(1) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndn.id", OP_REG(0x3E8) | PD(1) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndn.is", OP_LI(0x3E9) | PD(0) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndn.is", OP_REG(0x3E8) | PD(0) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndn.sd", OP_LI(0x3E9) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, - {"frndn.sd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndn.si", OP_LI(0x3E9) | PD(2) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndn.si", OP_REG(0x3E8) | PD(2) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndn.ss", OP_LI(0x3E9) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndn.ss", OP_REG(0x3E8) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndn.su", OP_LI(0x3E9) | PD(3) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndn.su", OP_REG(0x3E8) | PD(3) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndn.ud", OP_LI(0x3E9) | PD(1) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndn.ud", OP_REG(0x3E8) | PD(1) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndn.us", OP_LI(0x3E9) | PD(0) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndn.us", OP_REG(0x3E8) | PD(0) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - - /* Convert/Round to Positive Infinity */ - - {"frndp.dd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, - {"frndp.di", OP_REG(0x3E8) | PD(2) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndp.ds", OP_REG(0x3E8) | PD(0) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndp.du", OP_REG(0x3E8) | PD(3) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndp.id", OP_LI(0x3E9) | PD(1) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndp.id", OP_REG(0x3E8) | PD(1) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndp.is", OP_LI(0x3E9) | PD(0) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndp.is", OP_REG(0x3E8) | PD(0) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndp.sd", OP_LI(0x3E9) | PD(1) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, - {"frndp.sd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndp.si", OP_LI(0x3E9) | PD(2) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndp.si", OP_REG(0x3E8) | PD(2) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndp.ss", OP_LI(0x3E9) | PD(0) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndp.ss", OP_REG(0x3E8) | PD(0) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndp.su", OP_LI(0x3E9) | PD(3) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndp.su", OP_REG(0x3E8) | PD(3) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndp.ud", OP_LI(0x3E9) | PD(1) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndp.ud", OP_REG(0x3E8) | PD(1) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndp.us", OP_LI(0x3E9) | PD(0) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndp.us", OP_REG(0x3E8) | PD(0) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - - /* Convert/Round to Zero */ - - {"frndz.dd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, - {"frndz.di", OP_REG(0x3E8) | PD(2) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndz.ds", OP_REG(0x3E8) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndz.du", OP_REG(0x3E8) | PD(3) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} }, - {"frndz.id", OP_LI(0x3E9) | PD(1) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndz.id", OP_REG(0x3E8) | PD(1) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndz.is", OP_LI(0x3E9) | PD(0) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndz.is", OP_REG(0x3E8) | PD(0) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndz.sd", OP_LI(0x3E9) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, - {"frndz.sd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndz.si", OP_LI(0x3E9) | PD(2) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndz.si", OP_REG(0x3E8) | PD(2) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndz.ss", OP_LI(0x3E9) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndz.ss", OP_REG(0x3E8) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndz.su", OP_LI(0x3E9) | PD(3) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"frndz.su", OP_REG(0x3E8) | PD(3) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - {"frndz.ud", OP_LI(0x3E9) | PD(1) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} }, - {"frndz.ud", OP_REG(0x3E8) | PD(1) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"frndz.us", OP_LI(0x3E9) | PD(0) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, - {"frndz.us", OP_REG(0x3E8) | PD(0) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - - /* Floating point square root */ - - {"fsqrt.dd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} }, - {"fsqrt.sd", OP_LI(0x3EF) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} }, - {"fsqrt.sd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} }, - {"fsqrt.ss", OP_LI(0x3EF) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, - {"fsqrt.ss", OP_REG(0x3EE) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, - - /* Floating point subtraction */ - - { "fsub.ddd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} }, - { "fsub.dsd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} }, - { "fsub.sdd", OP_LI(0x3E3) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} }, - { "fsub.sdd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} }, - { "fsub.ssd", OP_LI(0x3E3) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} }, - { "fsub.ssd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} }, - { "fsub.sss", OP_LI(0x3E3) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, - { "fsub.sss", OP_REG(0x3E2) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, - - /* Illegal instructions */ - - {"illop0", OP_SI(0x0), MASK_SI, 0, {0} }, - {"illopF", 0x1FF << 13, 0x1FF << 13, 0, {0} }, - - /* Jump and save return */ - - {"jsr", OP_SI(0x44), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, - {"jsr", OP_LI(0x389), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, - {"jsr", OP_REG(0x388), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, - {"jsr.a", OP_SI(0x45), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, - {"jsr.a", OP_LI(0x38B), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, - {"jsr.a", OP_REG(0x38A), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, - - /* Load Signed Data Into Register */ - - {"ld", OP_SI(0x22), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"ld", OP_LI(0x345) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld", OP_REG(0x344) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.b", OP_SI(0x20), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"ld.b", OP_LI(0x341) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.b", OP_REG(0x340) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.d", OP_SI(0x23), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} }, - {"ld.d", OP_LI(0x347) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"ld.d", OP_REG(0x346) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"ld.h", OP_SI(0x21), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"ld.h", OP_LI(0x343) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.h", OP_REG(0x342) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - - /* Load Unsigned Data Into Register */ - - {"ld.ub", OP_SI(0x28), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"ld.ub", OP_LI(0x351) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.ub", OP_REG(0x350) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.uh", OP_SI(0x29), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"ld.uh", OP_LI(0x353) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.uh", OP_REG(0x352) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - - /* Leftmost one */ - - {"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} }, - - /* Bitwise logical OR. Note that "or.tt" and "or" are the same instructions. */ - - {"or.ff", OP_SI(0x1E), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, - {"or.ff", OP_LI(0x33D), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, - {"or.ff", OP_REG(0x33C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"or.ft", OP_SI(0x1D), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, - {"or.ft", OP_LI(0x33B), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, - {"or.ft", OP_REG(0x33A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"or.tf", OP_SI(0x1B), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, - {"or.tf", OP_LI(0x337), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, - {"or.tf", OP_REG(0x336), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"or.tt", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, - {"or.tt", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, - {"or.tt", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"or", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, - {"or", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, - {"or", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Read Control Register */ - - {"rdcr", OP_SI(0x4), MASK_SI | (0x1F << 22), 0, {CR_SI, REG_DEST} }, - {"rdcr", OP_LI(0x309), MASK_LI | (0x1F << 22), 0, {CR_LI, REG_DEST} }, - {"rdcr", OP_REG(0x308), MASK_REG | (0x1F << 22), 0, {REG_0, REG_DEST} }, - - /* Rightmost one */ - - {"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} }, - - /* Shift Register Left - note that rotl, shl, and ins are all alternate names for one of the shift instructions. - They appear prior to their sl equivalent so that they will be diassembled as the alternate name. */ - - - {"ins", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"ins", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"rotl", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"rotl", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"shl", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"shl", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.dm", OP_REG(0x312) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.dm", OP_SI(0x9) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.ds", OP_REG(0x314) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.ds", OP_SI(0xA) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.dz", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.dz", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.em", OP_REG(0x318) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.em", OP_SI(0xC) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.es", OP_REG(0x31A) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.es", OP_SI(0xD) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.ez", OP_REG(0x316) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.ez", OP_SI(0xB) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.im", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.im", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sl.iz", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sl.iz", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - - /* Shift Register Left With Inverted Endmask */ - - {"sli.dm", OP_REG(0x312) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.dm", OP_SI(0x9) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sli.ds", OP_REG(0x314) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.ds", OP_SI(0xA) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sli.dz", OP_REG(0x310) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.dz", OP_SI(0x8) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sli.em", OP_REG(0x318) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.em", OP_SI(0xC) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sli.es", OP_REG(0x31A) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.es", OP_SI(0xD) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sli.ez", OP_REG(0x316) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.ez", OP_SI(0xB) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sli.im", OP_REG(0x31E) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.im", OP_SI(0xF) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sli.iz", OP_REG(0x31C) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sli.iz", OP_SI(0xE) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - - /* Shift Register Right - note that exts, extu, rotr, sra, and srl are all alternate names for one of the shift instructions. - They appear prior to their sr equivalent so that they will be diassembled as the alternate name. */ - - {"exts", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"exts", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"extu", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"extu", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"rotr", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"rotr", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sra", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sra", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"srl", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"srl", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.dm", OP_REG(0x312) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.dm", OP_SI(0x9) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.ds", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.ds", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.dz", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.dz", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.em", OP_REG(0x318) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.em", OP_SI(0xC) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.es", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.es", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.ez", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.ez", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.im", OP_REG(0x31E) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.im", OP_SI(0xF) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sr.iz", OP_REG(0x31C) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sr.iz", OP_SI(0xE) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - - /* Shift Register Right With Inverted Endmask */ - - {"sri.dm", OP_REG(0x312) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.dm", OP_SI(0x9) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sri.ds", OP_REG(0x314) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.ds", OP_SI(0xA) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sri.dz", OP_REG(0x310) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.dz", OP_SI(0x8) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sri.em", OP_REG(0x318) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.em", OP_SI(0xC) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sri.es", OP_REG(0x31A) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.es", OP_SI(0xD) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sri.ez", OP_REG(0x316) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.ez", OP_SI(0xB) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sri.im", OP_REG(0x31E) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.im", OP_SI(0xF) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - {"sri.iz", OP_REG(0x31C) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, - {"sri.iz", OP_SI(0xE) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, - - /* Store Data into Memory */ - - {"st", OP_SI(0x32), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"st", OP_LI(0x365) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st", OP_REG(0x364) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st.b", OP_SI(0x30), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"st.b", OP_LI(0x361) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st.b", OP_REG(0x360) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st.d", OP_SI(0x33), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} }, - {"st.d", OP_LI(0x367) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"st.d", OP_REG(0x366) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"st.h", OP_SI(0x31), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, - {"st.h", OP_LI(0x363) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st.h", OP_REG(0x362) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - - /* Signed Integer Subtract */ - - {"sub", OP_SI(0x5A), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, - {"sub", OP_LI(0x3B5), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, - {"sub", OP_REG(0x3B4), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Unsigned Integer Subtract */ - - {"subu", OP_SI(0x5B), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, - {"subu", OP_LI(0x3B7), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, - {"subu", OP_REG(0x3B6), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Write Control Register - Is a special form of the "swcr" instruction so comes before it in the table. */ - - {"wrcr", OP_SI(0x5), MASK_SI | (0x1F << 27), 0, {CR_SI, REG_22} }, - {"wrcr", OP_LI(0x30B), MASK_LI | (0x1F << 27), 0, {CR_LI, REG_22} }, - {"wrcr", OP_REG(0x30A), MASK_REG | (0x1F << 27), 0, {REG_0, REG_22} }, - - /* Swap Control Register */ - - {"swcr", OP_SI(0x5), MASK_SI, 0, {CR_SI, REG_22, REG_DEST} }, - {"swcr", OP_LI(0x30B), MASK_LI, 0, {CR_LI, REG_22, REG_DEST} }, - {"swcr", OP_REG(0x30A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - /* Trap */ - - {"trap", OP_SI(0x1) | E(0), MASK_SI | E(1), 0, {SUI} }, - {"trap", OP_LI(0x303) | E(0), MASK_LI | E(1), 0, {LUI} }, - {"trap", OP_REG(0x302) | E(0), MASK_REG | E(1), 0, {REG_0} }, - - /* Vector Floating-Point Add */ - - {"vadd.dd", OP_REG(0x3C0) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E} }, - {"vadd.sd", OP_LI(0x3C1) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E} }, - {"vadd.sd", OP_REG(0x3C0) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} }, - {"vadd.ss", OP_LI(0x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, - {"vadd.ss", OP_REG(0x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, - - /* Vector Floating-Point Multiply and Add to Accumulator FIXME! This is not yet fully implemented. - From the documentation there appears to be no way to tell the difference between the opcodes for - instructions that have register destinations and instructions that have accumulator destinations. - Further investigation is necessary. Since this isn't critical to getting a TIC80 toolchain up - and running, it is defered until later. */ - - /* Vector Floating-Point Multiply - Note: If r0 is in the destination reg, then this is a "vector nop" instruction. */ - - {"vmpy.dd", OP_REG(0x3C4) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0_E, REG_22_E, REG_22_E} }, - {"vmpy.sd", OP_LI(0x3C5) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22_E, REG_22_E} }, - {"vmpy.sd", OP_REG(0x3C4) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22_E, REG_22_E} }, - {"vmpy.ss", OP_LI(0x3C5) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} }, - {"vmpy.ss", OP_REG(0x3C4) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, - - /* Vector Floating-Point Multiply and Subtract from Accumulator - FIXME: See note above for vmac instruction */ - - /* Vector Floating-Point Subtract Accumulator From Source - FIXME: See note above for vmac instruction */ - - /* Vector Round With Floating-Point Input - FIXME: See note above for vmac instruction */ - - /* Vector Round with Integer Input */ - - {"vrnd.id", OP_LI (0x3CB) | P2(1) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22_E}}, - {"vrnd.id", OP_REG (0x3CA) | P2(1) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E}}, - {"vrnd.is", OP_LI (0x3CB) | P2(0) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22}}, - {"vrnd.is", OP_REG (0x3CA) | P2(0) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}}, - {"vrnd.ud", OP_LI (0x3CB) | P2(1) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22_E}}, - {"vrnd.ud", OP_REG (0x3CA) | P2(1) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E}}, - {"vrnd.us", OP_LI (0x3CB) | P2(0) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22}}, - {"vrnd.us", OP_REG (0x3CA) | P2(0) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}}, - - /* Vector Floating-Point Subtract */ - - {"vsub.dd", OP_REG(0x3C2) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E} }, - {"vsub.sd", OP_LI(0x3C3) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E} }, - {"vsub.sd", OP_REG(0x3C2) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} }, - {"vsub.ss", OP_LI(0x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, - {"vsub.ss", OP_REG(0x3C2) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, - - /* Vector Load Data Into Register - Note that the vector load/store instructions come after the other - vector instructions so that the disassembler will always print the load/store instruction second for - vector instructions that have two instructions in the same opcode. */ - - {"vld0.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} }, - {"vld0.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, - {"vld1.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} }, - {"vld1.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, - - /* Vector Store Data Into Memory - Note that the vector load/store instructions come after the other - vector instructions so that the disassembler will always print the load/store instruction second for - vector instructions that have two instructions in the same opcode. */ - - {"vst.d", OP_V(0x1E) | V_m(0) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} }, - {"vst.s", OP_V(0x1E) | V_m(0) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, - - {"xnor", OP_SI(0x19), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, - {"xnor", OP_LI(0x333), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, - {"xnor", OP_REG(0x332), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - - {"xor", OP_SI(0x16), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, - {"xor", OP_LI(0x32D), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, - {"xor", OP_REG(0x32C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - -}; - -const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]); |