diff options
| -rw-r--r-- | include/opcode/riscv.h | 2 | ||||
| -rw-r--r-- | opcodes/riscv-dis.c | 48 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 236 |
3 files changed, 285 insertions, 1 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index dd8ff16..0480cea 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -332,6 +332,7 @@ static const char * const riscv_pred_succ[16] = /* ABI names for selected c-registers. */ #define C_CRA 1 +#define C_CSP 2 #define NGPR 32 #define NFPR 32 @@ -536,6 +537,7 @@ extern const char * const riscv_vta[2]; extern const char * const riscv_vma[2]; extern const struct riscv_opcode riscv_opcodes[]; +extern const struct riscv_opcode riscv_capmode_opcodes[]; extern const struct riscv_opcode riscv_insn_types[]; #endif /* _RISCV_H_ */ diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 9477dba..a888652 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -66,6 +66,9 @@ static const char * const *riscv_gpcr_names; /* If set, disassemble as most general instruction. */ static int no_aliases; +/* If true, use capability mode. */ +static bool capmode = false; + static void set_default_riscv_dis_options (void) { @@ -366,6 +369,28 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info case 'X': /* CHERI */ switch (*++oparg) { + case 'C': /* RVC */ + switch (*++oparg) + { + case 's': /* CS1 c8-c15. */ + case 'w': /* CS1 c8-c15. */ + print (info->stream, "%s", + riscv_gpcr_names[EXTRACT_OPERAND (CRS1S, l) + 8]); + break; + case 't': /* CS2 c8-c15. */ + case 'x': /* CS2 c8-c15. */ + print (info->stream, "%s", + riscv_gpcr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); + break; + case 'c': /* CS1, constrained to equal csp. */ + print (info->stream, "%s", riscv_gpcr_names[C_CSP]); + break; + case 'V': /* CS2 */ + print (info->stream, "%s", + riscv_gpcr_names[EXTRACT_OPERAND (CRS2, l)]); + break; + } + break; case 's': print (info->stream, "%s", riscv_gpcr_names[rs1]); break; @@ -602,8 +627,10 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) const struct riscv_opcode *op; static bool init = 0; static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; + static const struct riscv_opcode *riscv_capmode_hash[OP_MASK_OP + 1]; struct riscv_private_data *pd; int insnlen; + bool use_capmode = capmode; #define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP)) @@ -614,6 +641,10 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) if (!riscv_hash[OP_HASH_IDX (op->match)]) riscv_hash[OP_HASH_IDX (op->match)] = op; + for (op = riscv_capmode_opcodes; op->name; op++) + if (!riscv_capmode_hash[OP_HASH_IDX (op->match)]) + riscv_capmode_hash[OP_HASH_IDX (op->match)] = op; + init = 1; } @@ -650,7 +681,11 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) info->target = 0; info->target2 = 0; - op = riscv_hash[OP_HASH_IDX (word)]; + again: + if (use_capmode) + op = riscv_capmode_hash[OP_HASH_IDX (word)]; + else + op = riscv_hash[OP_HASH_IDX (word)]; if (op != NULL) { /* If XLEN is not known, get its value from the ELF class. */ @@ -726,6 +761,12 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) } } + if (use_capmode) + { + use_capmode = false; + goto again; + } + /* We did not find a match, so just print the instruction bits. */ info->insn_type = dis_noninsn; switch (insnlen) @@ -1010,6 +1051,7 @@ riscv_get_disassembler (bfd *abfd) { const char *default_arch = "rv64gc"; + capmode = false; if (abfd) { const struct elf_backend_data *ebd = get_elf_backend_data (abfd); @@ -1029,6 +1071,10 @@ riscv_get_disassembler (bfd *abfd) default_arch = attr[Tag_RISCV_arch].s; } } + + if (bfd_get_flavour (abfd) == bfd_target_elf_flavour + && elf_elfheader (abfd)->e_flags & EF_RISCV_CAPMODE) + capmode = true; } riscv_release_subset_list (&riscv_subsets); diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 85b388b..8a3aba5 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1969,6 +1969,242 @@ const struct riscv_opcode riscv_opcodes[] = /* Terminate the list. */ {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} + +/* l{b|h|w|d}[u] rd, offset(rs1) -> cl{b|h|w|d}[u] rd, offset(cs1) */ + +}; + +/* Instructions with different semantics in capability mode. */ + +const struct riscv_opcode riscv_capmode_opcodes[] = +{ +/* name, xlen, isa, operands, match, mask, match_func, pinfo. */ +{"cret", 0, INSN_CLASS_C, "", MATCH_C_JR|(C_CRA << OP_SH_RD), MASK_C_JR|MASK_CD, match_opcode, INSN_ALIAS|INSN_BRANCH }, +{"cret", 0, INSN_CLASS_I, "", MATCH_JALR|(C_CRA << OP_SH_RS1), MASK_JALR|MASK_CD|MASK_CS1|MASK_IMM, match_opcode, INSN_ALIAS|INSN_BRANCH }, +{"cjr", 0, INSN_CLASS_C, "Xd", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS|INSN_BRANCH }, +{"cjr", 0, INSN_CLASS_I, "Xs", MATCH_JALR, MASK_JALR|MASK_CD|MASK_IMM, match_opcode, INSN_ALIAS|INSN_BRANCH }, +{"cjr", 0, INSN_CLASS_I, "o(Xs)", MATCH_JALR, MASK_JALR|MASK_CD, match_opcode, INSN_ALIAS|INSN_BRANCH }, +{"cjr", 0, INSN_CLASS_I, "Xs,j", MATCH_JALR, MASK_JALR|MASK_CD, match_opcode, INSN_ALIAS|INSN_BRANCH }, +{"cjalr", 0, INSN_CLASS_C, "Xd", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS|INSN_JSR }, +{"cjalr", 0, INSN_CLASS_I, "Xs", MATCH_JALR|(C_CRA << OP_SH_RD), MASK_JALR|MASK_CD|MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR }, +{"cjalr", 0, INSN_CLASS_I, "o(Xs)", MATCH_JALR|(C_CRA << OP_SH_RD), MASK_JALR|MASK_CD, match_opcode, INSN_ALIAS|INSN_JSR }, +{"cjalr", 0, INSN_CLASS_I, "Xs,j", MATCH_JALR|(C_CRA << OP_SH_RD), MASK_JALR|MASK_CD, match_opcode, INSN_ALIAS|INSN_JSR }, +{"cjalr", 0, INSN_CLASS_I, "Xd,Xs", MATCH_JALR, MASK_JALR|MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR }, +{"cjalr", 0, INSN_CLASS_I, "Xd,o(Xs)", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR }, +{"cjalr", 0, INSN_CLASS_I, "Xd,Xs,j", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR }, +{"j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH }, +{"j", 0, INSN_CLASS_I, "a", MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH }, +{"cjal", 0, INSN_CLASS_I, "Xd,a", MATCH_JAL, MASK_JAL, match_opcode, INSN_JSR }, +{"cjal", 0, INSN_CLASS_I, "a", MATCH_JAL|(C_CRA << OP_SH_RD), MASK_JAL|MASK_CD, match_opcode, INSN_ALIAS|INSN_JSR }, +{"clb", 0, INSN_CLASS_I, "d,o(Xs)", MATCH_LB, MASK_LB, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"clbu", 0, INSN_CLASS_I, "d,o(Xs)", MATCH_LBU, MASK_LBU, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"clh", 0, INSN_CLASS_I, "d,o(Xs)", MATCH_LH, MASK_LH, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"clhu", 0, INSN_CLASS_I, "d,o(Xs)", MATCH_LHU, MASK_LHU, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"clw", 0, INSN_CLASS_C, "d,Cm(XCc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"clw", 0, INSN_CLASS_C, "Ct,Ck(XCs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"clw", 0, INSN_CLASS_I, "d,o(Xs)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"auipcc", 0, INSN_CLASS_I, "Xd,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 }, +{"csb", 0, INSN_CLASS_I, "t,q(Xs)", MATCH_SB, MASK_SB, match_opcode, INSN_DREF|INSN_1_BYTE }, +{"csh", 0, INSN_CLASS_I, "t,q(Xs)", MATCH_SH, MASK_SH, match_opcode, INSN_DREF|INSN_2_BYTE }, +{"csw", 0, INSN_CLASS_C, "CV,CM(XCc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"csw", 0, INSN_CLASS_C, "Ct,Ck(XCs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"csw", 0, INSN_CLASS_I, "t,q(Xs)", MATCH_SW, MASK_SW, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"clwu", 64, INSN_CLASS_I, "d,o(Xs)", MATCH_LWU, MASK_LWU, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"cld", 64, INSN_CLASS_C, "d,Cn(XCc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"cld", 64, INSN_CLASS_C, "Ct,Cl(XCs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"cld", 64, INSN_CLASS_I, "d,o(Xs)", MATCH_LD, MASK_LD, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"csd", 64, INSN_CLASS_C, "CV,CN(XCc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"csd", 64, INSN_CLASS_C, "Ct,Cl(XCs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"csd", 64, INSN_CLASS_I, "t,q(Xs)", MATCH_SD, MASK_SD, match_opcode, INSN_DREF|INSN_8_BYTE }, + +/* Atomic memory operation instruction subset. */ +{"clr.w", 0, INSN_CLASS_A, "d,0(Xs)", MATCH_LR_W, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"csc.w", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_SC_W, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoadd.w", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOADD_W, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoswap.w", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoand.w", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOAND_W, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoor.w", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOOR_W, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoxor.w", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOXOR_W, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camomax.w", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAX_W, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camomaxu.w", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camomin.w", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMIN_W, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camominu.w", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMINU_W, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"clr.w.aq", 0, INSN_CLASS_A, "d,0(Xs)", MATCH_LR_W|MASK_AQ, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"csc.w.aq", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_SC_W|MASK_AQ, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoadd.w.aq", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOADD_W|MASK_AQ, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoswap.w.aq", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOSWAP_W|MASK_AQ, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoand.w.aq", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOAND_W|MASK_AQ, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoor.w.aq", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOOR_W|MASK_AQ, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoxor.w.aq", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOXOR_W|MASK_AQ, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camomax.w.aq", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAX_W|MASK_AQ, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camomaxu.w.aq", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAXU_W|MASK_AQ, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camomin.w.aq", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMIN_W|MASK_AQ, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camominu.w.aq", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMINU_W|MASK_AQ, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"clr.w.rl", 0, INSN_CLASS_A, "d,0(Xs)", MATCH_LR_W|MASK_RL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"csc.w.rl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_SC_W|MASK_RL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoadd.w.rl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOADD_W|MASK_RL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoswap.w.rl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOSWAP_W|MASK_RL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoand.w.rl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOAND_W|MASK_RL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoor.w.rl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOOR_W|MASK_RL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoxor.w.rl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOXOR_W|MASK_RL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camomax.w.rl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAX_W|MASK_RL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camomaxu.w.rl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAXU_W|MASK_RL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camomin.w.rl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMIN_W|MASK_RL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camominu.w.rl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMINU_W|MASK_RL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"clr.w.aqrl", 0, INSN_CLASS_A, "d,0(Xs)", MATCH_LR_W|MASK_AQRL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"csc.w.aqrl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_SC_W|MASK_AQRL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoadd.w.aqrl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOADD_W|MASK_AQRL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoswap.w.aqrl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOSWAP_W|MASK_AQRL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoand.w.aqrl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOAND_W|MASK_AQRL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOOR_W|MASK_AQRL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camoxor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOXOR_W|MASK_AQRL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camomax.w.aqrl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAX_W|MASK_AQRL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camomaxu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAXU_W|MASK_AQRL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camomin.w.aqrl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMIN_W|MASK_AQRL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"camominu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMINU_W|MASK_AQRL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"clr.d", 64, INSN_CLASS_A, "d,0(Xs)", MATCH_LR_D, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"csc.d", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_SC_D, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoadd.d", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOADD_D, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoswap.d", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoand.d", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOAND_D, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoor.d", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOOR_D, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoxor.d", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOXOR_D, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camomax.d", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAX_D, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camomaxu.d", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camomin.d", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMIN_D, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camominu.d", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMINU_D, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"clr.d.aq", 64, INSN_CLASS_A, "d,0(Xs)", MATCH_LR_D|MASK_AQ, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"csc.d.aq", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_SC_D|MASK_AQ, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoadd.d.aq", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOADD_D|MASK_AQ, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoswap.d.aq", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOSWAP_D|MASK_AQ, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoand.d.aq", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOAND_D|MASK_AQ, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoor.d.aq", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOOR_D|MASK_AQ, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoxor.d.aq", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOXOR_D|MASK_AQ, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camomax.d.aq", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAX_D|MASK_AQ, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camomaxu.d.aq", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAXU_D|MASK_AQ, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camomin.d.aq", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMIN_D|MASK_AQ, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camominu.d.aq", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMINU_D|MASK_AQ, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"clr.d.rl", 64, INSN_CLASS_A, "d,0(Xs)", MATCH_LR_D|MASK_RL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"csc.d.rl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_SC_D|MASK_RL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoadd.d.rl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOADD_D|MASK_RL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoswap.d.rl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOSWAP_D|MASK_RL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoand.d.rl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOAND_D|MASK_RL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoor.d.rl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOOR_D|MASK_RL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoxor.d.rl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOXOR_D|MASK_RL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camomax.d.rl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAX_D|MASK_RL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camomaxu.d.rl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAXU_D|MASK_RL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camomin.d.rl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMIN_D|MASK_RL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camominu.d.rl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMINU_D|MASK_RL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"clr.d.aqrl", 64, INSN_CLASS_A, "d,0(Xs)", MATCH_LR_D|MASK_AQRL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"csc.d.aqrl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_SC_D|MASK_AQRL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoadd.d.aqrl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOADD_D|MASK_AQRL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoswap.d.aqrl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOSWAP_D|MASK_AQRL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoand.d.aqrl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOAND_D|MASK_AQRL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoor.d.aqrl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOOR_D|MASK_AQRL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoxor.d.aqrl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOXOR_D|MASK_AQRL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camomax.d.aqrl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAX_D|MASK_AQRL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camomaxu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMAXU_D|MASK_AQRL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camomin.d.aqrl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(Xs)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, + +/* Single-precision floating-point instruction subset. */ +{"cflw", 32, INSN_CLASS_F_AND_C, "D,Cm(XCc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"cflw", 32, INSN_CLASS_F_AND_C, "CD,Ck(XCs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"cflw", 0, INSN_CLASS_F, "D,o(Xs)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"cfsw", 32, INSN_CLASS_F_AND_C, "CT,CM(XCc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"cfsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(XCs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, +{"cfsw", 0, INSN_CLASS_F, "T,q(Xs)", MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, + +/* Double-precision floating-point instruction subset. */ +{"cfld", 0, INSN_CLASS_D_AND_C, "D,Cn(XCc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"cfld", 0, INSN_CLASS_D_AND_C, "CD,Cl(XCs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"cfld", 0, INSN_CLASS_D, "D,o(Xs)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"cfsd", 0, INSN_CLASS_D_AND_C, "CT,CN(XCc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"cfsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(XCs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, +{"cfsd", 0, INSN_CLASS_D, "T,q(Xs)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, + +/* Quad-precision floating-point instruction subset. */ +{"cflq", 0, INSN_CLASS_Q, "D,o(Xs)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, +{"cfsq", 0, INSN_CLASS_Q, "T,q(Xs)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, + +/* Compressed instructions. */ +{"c.cjr", 0, INSN_CLASS_C, "Xd", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_BRANCH }, +{"c.cjalr", 0, INSN_CLASS_C, "Xd", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_JSR }, +{"c.clwsp", 0, INSN_CLASS_C, "d,Cm(XCc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 }, +{"c.clw", 0, INSN_CLASS_C, "Ct,Ck(XCs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.cswsp", 0, INSN_CLASS_C, "CV,CM(XCc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.csw", 0, INSN_CLASS_C, "Ct,Ck(XCs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"c.cincoffsetimm4cspn", 0, INSN_CLASS_C, "Ct,XCc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, 0 }, +{"c.cincoffsetimm16csp", 0, INSN_CLASS_C, "XCc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, 0 }, +{"c.cldsp", 64, INSN_CLASS_C, "d,Cn(XCc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_DREF|INSN_8_BYTE }, +{"c.cld", 64, INSN_CLASS_C, "Ct,Cl(XCs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.csdsp", 64, INSN_CLASS_C, "CV,CN(XCc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.csd", 64, INSN_CLASS_C, "Ct,Cl(XCs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.clcsp", 64, INSN_CLASS_C, "Xd,Cn(XCc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_DREF|INSN_16_BYTE }, +{"c.clc", 64, INSN_CLASS_C, "XCt,Cl(XCs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_DREF|INSN_16_BYTE }, +{"c.cscsp", 64, INSN_CLASS_C, "XCV,CN(XCc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_DREF|INSN_16_BYTE }, +{"c.csc", 64, INSN_CLASS_C, "XCt,Cl(XCs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_DREF|INSN_16_BYTE }, +{"c.cfldsp", 32, INSN_CLASS_D_AND_C, "D,Cn(XCc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.cfld", 32, INSN_CLASS_D_AND_C, "CD,Cl(XCs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.cfsdsp", 32, INSN_CLASS_D_AND_C, "CT,CN(XCc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.cfsd", 32, INSN_CLASS_D_AND_C, "CD,Cl(XCs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.clcsp", 32, INSN_CLASS_C, "Xd,Cm(XCc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.clc", 32, INSN_CLASS_C, "XCt,Ck(XCs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.cscsp", 32, INSN_CLASS_C, "XCV,CM(XCc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"c.csc", 32, INSN_CLASS_C, "XCt,Ck(XCs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_8_BYTE }, + +/* CHERI */ + +/* Memory-Access Instructions */ +{"clc", 32, INSN_CLASS_XCHERI, "Xd,o(Xs)", MATCH_LD, MASK_LD, match_opcode, INSN_DREF|INSN_8_BYTE}, +{"clc", 64, INSN_CLASS_XCHERI, "Xd,o(Xs)", MATCH_LQ, MASK_LQ, match_opcode, INSN_DREF|INSN_16_BYTE}, +{"csc", 32, INSN_CLASS_XCHERI, "Xt,q(Xs)", MATCH_SD, MASK_SD, match_opcode, INSN_DREF|INSN_8_BYTE}, +{"csc", 64, INSN_CLASS_XCHERI, "Xt,q(Xs)", MATCH_SQ, MASK_SQ, match_opcode, INSN_DREF|INSN_16_BYTE}, + +/* Atomic Memory-Access Instructions */ +{"clr.b", 0, INSN_CLASS_XCHERI_AND_A, "d,0(Xs)", MATCH_LR_B, MASK_LR_B | MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE}, +{"csc.b", 0, INSN_CLASS_XCHERI_AND_A, "d,t,0(Xs)", MATCH_SC_B, MASK_SC_B | MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE}, +{"clr.b.aq", 0, INSN_CLASS_XCHERI_AND_A, "d,0(Xs)", MATCH_LR_B | MASK_AQ, MASK_LR_B | MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE}, +{"csc.b.aq", 0, INSN_CLASS_XCHERI_AND_A, "d,t,0(Xs)", MATCH_SC_B | MASK_AQ, MASK_SC_B | MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE}, +{"clr.b.rl", 0, INSN_CLASS_XCHERI_AND_A, "d,0(Xs)", MATCH_LR_B | MASK_RL, MASK_LR_B | MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE}, +{"csc.b.rl", 0, INSN_CLASS_XCHERI_AND_A, "d,t,0(Xs)", MATCH_SC_B | MASK_RL, MASK_SC_B | MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE}, +{"clr.b.aqrl", 0, INSN_CLASS_XCHERI_AND_A, "d,0(Xs)", MATCH_LR_B | MASK_AQRL, MASK_LR_B | MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE}, +{"csc.b.aqrl", 0, INSN_CLASS_XCHERI_AND_A, "d,t,0(Xs)", MATCH_SC_B | MASK_AQRL, MASK_SC_B | MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE}, +{"clr.h", 0, INSN_CLASS_XCHERI_AND_A, "d,0(Xs)", MATCH_LR_B, MASK_LR_B | MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE}, +{"csc.h", 0, INSN_CLASS_XCHERI_AND_A, "d,t,0(Xs)", MATCH_SC_B, MASK_SC_B | MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE}, +{"clr.h.aq", 0, INSN_CLASS_XCHERI_AND_A, "d,0(Xs)", MATCH_LR_H | MASK_AQ, MASK_LR_H | MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE}, +{"csc.h.aq", 0, INSN_CLASS_XCHERI_AND_A, "d,t,0(Xs)", MATCH_SC_H | MASK_AQ, MASK_SC_H | MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE}, +{"clr.h.rl", 0, INSN_CLASS_XCHERI_AND_A, "d,0(Xs)", MATCH_LR_H | MASK_RL, MASK_LR_H | MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE}, +{"csc.h.rl", 0, INSN_CLASS_XCHERI_AND_A, "d,t,0(Xs)", MATCH_SC_H | MASK_RL, MASK_SC_H | MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE}, +{"clr.h.aqrl", 0, INSN_CLASS_XCHERI_AND_A, "d,0(Xs)", MATCH_LR_H | MASK_AQRL, MASK_LR_H | MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE}, +{"csc.h.aqrl", 0, INSN_CLASS_XCHERI_AND_A, "d,t,0(Xs)", MATCH_SC_H | MASK_AQRL, MASK_SC_H | MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE}, +{"clr.c", 32, INSN_CLASS_XCHERI_AND_A, "Xd,0(Xs)", MATCH_LR_D, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE}, +{"clr.c", 64, INSN_CLASS_XCHERI_AND_A, "Xd,0(Xs)", MATCH_LR_Q, MASK_LR_Q | MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE}, +{"csc.c", 32, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_SC_D, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE}, +{"csc.c", 64, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_SC_Q, MASK_SC_Q | MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE}, +{"clr.c.aq", 32, INSN_CLASS_XCHERI_AND_A, "Xd,0(Xs)", MATCH_LR_D | MASK_AQ, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE}, +{"clr.c.aq", 64, INSN_CLASS_XCHERI_AND_A, "Xd,0(Xs)", MATCH_LR_Q | MASK_AQ, MASK_LR_Q | MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE}, +{"csc.c.aq", 32, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_SC_D | MASK_AQ, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE}, +{"csc.c.aq", 64, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_SC_Q | MASK_AQ, MASK_SC_Q | MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE}, +{"clr.c.rl", 32, INSN_CLASS_XCHERI_AND_A, "Xd,0(Xs)", MATCH_LR_D | MASK_RL, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE}, +{"clr.c.rl", 64, INSN_CLASS_XCHERI_AND_A, "Xd,0(Xs)", MATCH_LR_Q | MASK_RL, MASK_LR_Q | MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE}, +{"csc.c.rl", 32, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_SC_D | MASK_RL, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE}, +{"csc.c.rl", 64, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_SC_Q | MASK_RL, MASK_SC_Q | MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE}, +{"clr.c.aqrl", 32, INSN_CLASS_XCHERI_AND_A, "Xd,0(Xs)", MATCH_LR_D | MASK_AQRL, MASK_LR_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE}, +{"clr.c.aqrl", 64, INSN_CLASS_XCHERI_AND_A, "Xd,0(Xs)", MATCH_LR_Q | MASK_AQRL, MASK_LR_Q | MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE}, +{"csc.c.aqrl", 32, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_SC_D | MASK_AQRL, MASK_SC_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE}, +{"csc.c.aqrl", 64, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_SC_Q | MASK_AQRL, MASK_SC_Q | MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE}, +{"camoswap.c", 32, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoswap.c", 64, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_AMOSWAP_Q, MASK_AMOSWAP_Q | MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE }, +{"camoswap.c.aq", 32, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_AMOSWAP_D | MASK_AQ, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoswap.c.aq", 64, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_AMOSWAP_Q | MASK_AQ, MASK_AMOSWAP_Q | MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE }, +{"camoswap.c.rl", 32, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_AMOSWAP_D | MASK_RL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoswap.c.rl", 64, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_AMOSWAP_Q | MASK_RL, MASK_AMOSWAP_Q | MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE }, +{"camoswap.c.aqrl", 32, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_AMOSWAP_D | MASK_AQRL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"camoswap.c.aqrl", 64, INSN_CLASS_XCHERI_AND_A, "Xd,t,0(Xs)", MATCH_AMOSWAP_Q | MASK_AQRL, MASK_AMOSWAP_Q | MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE }, + +/* Terminate the list. */ +{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} }; /* Instruction format for .insn directive. */ |