diff options
| -rw-r--r-- | gas/ChangeLog | 10 | ||||
| -rw-r--r-- | gas/config/tc-arm.c | 33 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.d | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.l | 57 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.s | 57 |
5 files changed, 162 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 5712c4c..5333e17 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,15 @@ 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> + * config/tc-arm.c (M_MNEM_vmaxv, M_MNEM_vmaxav, M_MNEM_vminv, + M_MNEM_vminav): New instruction encodings. + (do_mve_vmaxv): New encoding function. + (insns): Add entries for new MVE mnemonics. + * testsuite/gas/arm/mve-vmaxv-vminv-bad.d: New test. + * testsuite/gas/arm/mve-vmaxv-vminv-bad.l: New test. + * testsuite/gas/arm/mve-vmaxv-vminv-bad.s: New test. + +2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> + * config/tc-arm.c (do_mve_vmaxnmv): New encoding function. (insns): Add entries for new mnemonics. * testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.d: New test. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 82ed9d2..6dd1316 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -14163,6 +14163,10 @@ do_t_loloop (void) #define M_MNEM_vdwdup 0xee011f60 #define M_MNEM_vidup 0xee010f6e #define M_MNEM_viwdup 0xee010f60 +#define M_MNEM_vmaxv 0xeee20f00 +#define M_MNEM_vmaxav 0xeee00f00 +#define M_MNEM_vminv 0xeee20f80 +#define M_MNEM_vminav 0xeee00f80 /* Neon instruction encoder helpers. */ @@ -17269,6 +17273,31 @@ do_mve_vmaxnmv (void) } static void +do_mve_vmaxv (void) +{ + enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL); + struct neon_type_el et; + + if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv) + et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY); + else + et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + if (inst.operands[0].reg == REG_SP) + as_tsktsk (MVE_BAD_SP); + else if (inst.operands[0].reg == REG_PC) + as_tsktsk (MVE_BAD_PC); + + mve_encode_rq (et.type == NT_unsigned, et.size); +} + + +static void do_neon_qrdmlah (void) { /* Check we're on the correct architecture. */ @@ -24434,6 +24463,10 @@ static const struct asm_opcode insns[] = mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup), mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina), mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina), + mCEF(vmaxv, _vmaxv, 2, (RR, RMQ), mve_vmaxv), + mCEF(vmaxav, _vmaxav, 2, (RR, RMQ), mve_vmaxv), + mCEF(vminv, _vminv, 2, (RR, RMQ), mve_vmaxv), + mCEF(vminav, _vminav, 2, (RR, RMQ), mve_vmaxv), #undef THUMB_VARIANT #define THUMB_VARIANT & mve_fp_ext diff --git a/gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.d b/gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.d new file mode 100644 index 0000000..9dd5c3e --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VMAXV, VMAXAV, VMIMV and VMINAV instructions +#as: -march=armv8.1-m.main+mve +#error_output: mve-vmaxv-vminv-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.l b/gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.l new file mode 100644 index 0000000..16d109d --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.l @@ -0,0 +1,57 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vmaxv.u64 r0,q1' +[^:]*:11: Error: bad type in SIMD instruction -- `vmaxv.f16 r0,q1' +[^:]*:12: Error: bad type in SIMD instruction -- `vminv.s64 r0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vminv.f32 r0,q1' +[^:]*:14: Error: bad type in SIMD instruction -- `vmaxav.u16 r0,q1' +[^:]*:15: Error: bad type in SIMD instruction -- `vmaxav.f32 r0,q1' +[^:]*:16: Error: bad type in SIMD instruction -- `vminav.u32 r0,q1' +[^:]*:17: Error: bad type in SIMD instruction -- `vminav.f16 r0,q1' +[^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:20: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:21: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:27: Error: syntax error -- `vmaxveq.s32 r0,q1' +[^:]*:28: Error: syntax error -- `vmaxveq.s32 r0,q1' +[^:]*:30: Error: syntax error -- `vmaxveq.s32 r0,q1' +[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxvt.s32 r0,q1' +[^:]*:33: Error: instruction missing MVE vector predication code -- `vmaxv.s32 r0,q1' +[^:]*:35: Error: syntax error -- `vmaxaveq.s32 r0,q1' +[^:]*:36: Error: syntax error -- `vmaxaveq.s32 r0,q1' +[^:]*:38: Error: syntax error -- `vmaxaveq.s32 r0,q1' +[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxavt.s32 r0,q1' +[^:]*:41: Error: instruction missing MVE vector predication code -- `vmaxav.s32 r0,q1' +[^:]*:43: Error: syntax error -- `vminveq.s32 r0,q1' +[^:]*:44: Error: syntax error -- `vminveq.s32 r0,q1' +[^:]*:46: Error: syntax error -- `vminveq.s32 r0,q1' +[^:]*:47: Error: vector predicated instruction should be in VPT/VPST block -- `vminvt.s32 r0,q1' +[^:]*:49: Error: instruction missing MVE vector predication code -- `vminv.s32 r0,q1' +[^:]*:51: Error: syntax error -- `vminaveq.s32 r0,q1' +[^:]*:52: Error: syntax error -- `vminaveq.s32 r0,q1' +[^:]*:54: Error: syntax error -- `vminaveq.s32 r0,q1' +[^:]*:55: Error: vector predicated instruction should be in VPT/VPST block -- `vminavt.s32 r0,q1' +[^:]*:57: Error: instruction missing MVE vector predication code -- `vminav.s32 r0,q1' diff --git a/gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.s b/gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.s new file mode 100644 index 0000000..e274a7a --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmaxv-vminv-bad.s @@ -0,0 +1,57 @@ +.macro cond, op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().s16 r0, q1 +.endr +.endm + +.syntax unified +.thumb +vmaxv.u64 r0, q1 +vmaxv.f16 r0, q1 +vminv.s64 r0, q1 +vminv.f32 r0, q1 +vmaxav.u16 r0, q1 +vmaxav.f32 r0, q1 +vminav.u32 r0, q1 +vminav.f16 r0, q1 +vmaxv.s32 sp, q1 +vmaxav.s32 pc, q1 +vminv.s32 pc, q1 +vminav.s32 sp, q1 +cond vmaxv +cond vmaxav +cond vminv +cond vminav +it eq +vmaxveq.s32 r0, q1 +vmaxveq.s32 r0, q1 +vpst +vmaxveq.s32 r0, q1 +vmaxvt.s32 r0, q1 +vpst +vmaxv.s32 r0, q1 +it eq +vmaxaveq.s32 r0, q1 +vmaxaveq.s32 r0, q1 +vpst +vmaxaveq.s32 r0, q1 +vmaxavt.s32 r0, q1 +vpst +vmaxav.s32 r0, q1 +it eq +vminveq.s32 r0, q1 +vminveq.s32 r0, q1 +vpst +vminveq.s32 r0, q1 +vminvt.s32 r0, q1 +vpst +vminv.s32 r0, q1 +it eq +vminaveq.s32 r0, q1 +vminaveq.s32 r0, q1 +vpst +vminaveq.s32 r0, q1 +vminavt.s32 r0, q1 +vpst +vminav.s32 r0, q1 |