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-rw-r--r--opcodes/ChangeLog15
-rw-r--r--opcodes/fr30-asm.c2
-rw-r--r--opcodes/fr30-desc.c33
-rw-r--r--opcodes/fr30-dis.c37
-rw-r--r--opcodes/m32r-asm.c2
-rw-r--r--opcodes/m32r-desc.c33
-rw-r--r--opcodes/m32r-dis.c37
-rw-r--r--opcodes/openrisc-asm.c2
-rw-r--r--opcodes/openrisc-desc.c33
-rw-r--r--opcodes/openrisc-dis.c37
-rw-r--r--opcodes/xstormy16-asm.c2
-rw-r--r--opcodes/xstormy16-desc.c33
-rw-r--r--opcodes/xstormy16-dis.c37
13 files changed, 283 insertions, 20 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1d5247d..d16b5b6 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,18 @@
+2002-05-15 Nick Clifton <nickc@cambridge.redhat.com>
+
+ * fr30-asm.c: Regenerate.
+ * fr30-desc.c: Regenerate.
+ * fr30-dis.c: Regenerate.
+ * m32r-asm.c: Regenerate.
+ * m32r-desc.c: Regenerate.
+ * m32r-dis.c: Regenerate.
+ * openrisc-asm.c: Regenerate.
+ * openrisc-desc.c: Regenerate.
+ * openrisc-dis.c: Regenerate.
+ * xstormy16-asm.c: Regenerate.
+ * xstormy16-desc.c: Regenerate.
+ * xstormy16-dis.c: Regenerate.
+
2002-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
* mips-dis.c (is_newabi): EABI is not a NewABI.
diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c
index 40f015a..be9c36c 100644
--- a/opcodes/fr30-asm.c
+++ b/opcodes/fr30-asm.c
@@ -571,7 +571,7 @@ parse_insn_normal (cd, insn, strp, fields)
}
/* We have an operand of some sort. */
- errmsg = fr30_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
+ errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
&str, fields);
if (errmsg)
return errmsg;
diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c
index fd6afee..18963b9 100644
--- a/opcodes/fr30-desc.c
+++ b/opcodes/fr30-desc.c
@@ -1747,10 +1747,43 @@ void
fr30_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
+ unsigned int i;
+ CGEN_INSN *insns;
+
+ if (cd->macro_insn_table.init_entries)
+ {
+ insns = cd->macro_insn_table.init_entries;
+ for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+ {
+ if (CGEN_INSN_RX ((insns)))
+ regfree(CGEN_INSN_RX (insns));
+ }
+ }
+
+ if (cd->insn_table.init_entries)
+ {
+ insns = cd->insn_table.init_entries;
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ {
+ if (CGEN_INSN_RX (insns))
+ regfree(CGEN_INSN_RX (insns));
+ }
+ }
+
+
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
if (cd->insn_table.init_entries)
free ((CGEN_INSN *) cd->insn_table.init_entries);
+
if (cd->hw_table.entries)
free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+ if (cd->operand_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
free (cd);
}
diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c
index 961ce22..7affa86 100644
--- a/opcodes/fr30-dis.c
+++ b/opcodes/fr30-dis.c
@@ -632,11 +632,21 @@ default_print_insn (cd, pc, info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
+typedef struct cpu_desc_list {
+ struct cpu_desc_list *next;
+ int isa;
+ int mach;
+ int endian;
+ CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
int
print_insn_fr30 (pc, info)
bfd_vma pc;
disassemble_info *info;
{
+ static cpu_desc_list *cd_list = 0;
+ cpu_desc_list *cl = 0;
static CGEN_CPU_DESC cd = 0;
static int prev_isa;
static int prev_mach;
@@ -667,18 +677,27 @@ print_insn_fr30 (pc, info)
#ifdef CGEN_COMPUTE_ISA
isa = CGEN_COMPUTE_ISA (info);
#else
- isa = 0;
+ isa = info->insn_sets;
#endif
- /* If we've switched cpu's, close the current table and open a new one. */
+ /* If we've switched cpu's, try to find a handle we've used before */
if (cd
&& (isa != prev_isa
|| mach != prev_mach
|| endian != prev_endian))
{
- fr30_cgen_cpu_close (cd);
cd = 0;
- }
+ for (cl = cd_list; cl; cl = cl->next)
+ {
+ if (cl->isa == isa &&
+ cl->mach == mach &&
+ cl->endian == endian)
+ {
+ cd = cl->cd;
+ break;
+ }
+ }
+ }
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
@@ -699,6 +718,16 @@ print_insn_fr30 (pc, info)
CGEN_CPU_OPEN_END);
if (!cd)
abort ();
+
+ /* save this away for future reference */
+ cl = xmalloc (sizeof (struct cpu_desc_list));
+ cl->cd = cd;
+ cl->isa = isa;
+ cl->mach = mach;
+ cl->endian = endian;
+ cl->next = cd_list;
+ cd_list = cl;
+
fr30_cgen_init_dis (cd);
}
diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c
index 718dd99..4abe187 100644
--- a/opcodes/m32r-asm.c
+++ b/opcodes/m32r-asm.c
@@ -573,7 +573,7 @@ parse_insn_normal (cd, insn, strp, fields)
}
/* We have an operand of some sort. */
- errmsg = m32r_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
+ errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
&str, fields);
if (errmsg)
return errmsg;
diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c
index 4acf720..de7bde4 100644
--- a/opcodes/m32r-desc.c
+++ b/opcodes/m32r-desc.c
@@ -1441,10 +1441,43 @@ void
m32r_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
+ unsigned int i;
+ CGEN_INSN *insns;
+
+ if (cd->macro_insn_table.init_entries)
+ {
+ insns = cd->macro_insn_table.init_entries;
+ for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+ {
+ if (CGEN_INSN_RX ((insns)))
+ regfree(CGEN_INSN_RX (insns));
+ }
+ }
+
+ if (cd->insn_table.init_entries)
+ {
+ insns = cd->insn_table.init_entries;
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ {
+ if (CGEN_INSN_RX (insns))
+ regfree(CGEN_INSN_RX (insns));
+ }
+ }
+
+
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
if (cd->insn_table.init_entries)
free ((CGEN_INSN *) cd->insn_table.init_entries);
+
if (cd->hw_table.entries)
free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+ if (cd->operand_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
free (cd);
}
diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c
index 40d7679..07560e1 100644
--- a/opcodes/m32r-dis.c
+++ b/opcodes/m32r-dis.c
@@ -563,11 +563,21 @@ default_print_insn (cd, pc, info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
+typedef struct cpu_desc_list {
+ struct cpu_desc_list *next;
+ int isa;
+ int mach;
+ int endian;
+ CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
int
print_insn_m32r (pc, info)
bfd_vma pc;
disassemble_info *info;
{
+ static cpu_desc_list *cd_list = 0;
+ cpu_desc_list *cl = 0;
static CGEN_CPU_DESC cd = 0;
static int prev_isa;
static int prev_mach;
@@ -598,18 +608,27 @@ print_insn_m32r (pc, info)
#ifdef CGEN_COMPUTE_ISA
isa = CGEN_COMPUTE_ISA (info);
#else
- isa = 0;
+ isa = info->insn_sets;
#endif
- /* If we've switched cpu's, close the current table and open a new one. */
+ /* If we've switched cpu's, try to find a handle we've used before */
if (cd
&& (isa != prev_isa
|| mach != prev_mach
|| endian != prev_endian))
{
- m32r_cgen_cpu_close (cd);
cd = 0;
- }
+ for (cl = cd_list; cl; cl = cl->next)
+ {
+ if (cl->isa == isa &&
+ cl->mach == mach &&
+ cl->endian == endian)
+ {
+ cd = cl->cd;
+ break;
+ }
+ }
+ }
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
@@ -630,6 +649,16 @@ print_insn_m32r (pc, info)
CGEN_CPU_OPEN_END);
if (!cd)
abort ();
+
+ /* save this away for future reference */
+ cl = xmalloc (sizeof (struct cpu_desc_list));
+ cl->cd = cd;
+ cl->isa = isa;
+ cl->mach = mach;
+ cl->endian = endian;
+ cl->next = cd_list;
+ cd_list = cl;
+
m32r_cgen_init_dis (cd);
}
diff --git a/opcodes/openrisc-asm.c b/opcodes/openrisc-asm.c
index 96a6c4d..d47659b 100644
--- a/opcodes/openrisc-asm.c
+++ b/opcodes/openrisc-asm.c
@@ -492,7 +492,7 @@ parse_insn_normal (cd, insn, strp, fields)
}
/* We have an operand of some sort. */
- errmsg = openrisc_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
+ errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
&str, fields);
if (errmsg)
return errmsg;
diff --git a/opcodes/openrisc-desc.c b/opcodes/openrisc-desc.c
index e5eded9..f66514c 100644
--- a/opcodes/openrisc-desc.c
+++ b/opcodes/openrisc-desc.c
@@ -1017,10 +1017,43 @@ void
openrisc_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
+ unsigned int i;
+ CGEN_INSN *insns;
+
+ if (cd->macro_insn_table.init_entries)
+ {
+ insns = cd->macro_insn_table.init_entries;
+ for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+ {
+ if (CGEN_INSN_RX ((insns)))
+ regfree(CGEN_INSN_RX (insns));
+ }
+ }
+
+ if (cd->insn_table.init_entries)
+ {
+ insns = cd->insn_table.init_entries;
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ {
+ if (CGEN_INSN_RX (insns))
+ regfree(CGEN_INSN_RX (insns));
+ }
+ }
+
+
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
if (cd->insn_table.init_entries)
free ((CGEN_INSN *) cd->insn_table.init_entries);
+
if (cd->hw_table.entries)
free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+ if (cd->operand_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
free (cd);
}
diff --git a/opcodes/openrisc-dis.c b/opcodes/openrisc-dis.c
index 628a86c..e6a7d6a 100644
--- a/opcodes/openrisc-dis.c
+++ b/opcodes/openrisc-dis.c
@@ -450,11 +450,21 @@ default_print_insn (cd, pc, info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
+typedef struct cpu_desc_list {
+ struct cpu_desc_list *next;
+ int isa;
+ int mach;
+ int endian;
+ CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
int
print_insn_openrisc (pc, info)
bfd_vma pc;
disassemble_info *info;
{
+ static cpu_desc_list *cd_list = 0;
+ cpu_desc_list *cl = 0;
static CGEN_CPU_DESC cd = 0;
static int prev_isa;
static int prev_mach;
@@ -485,18 +495,27 @@ print_insn_openrisc (pc, info)
#ifdef CGEN_COMPUTE_ISA
isa = CGEN_COMPUTE_ISA (info);
#else
- isa = 0;
+ isa = info->insn_sets;
#endif
- /* If we've switched cpu's, close the current table and open a new one. */
+ /* If we've switched cpu's, try to find a handle we've used before */
if (cd
&& (isa != prev_isa
|| mach != prev_mach
|| endian != prev_endian))
{
- openrisc_cgen_cpu_close (cd);
cd = 0;
- }
+ for (cl = cd_list; cl; cl = cl->next)
+ {
+ if (cl->isa == isa &&
+ cl->mach == mach &&
+ cl->endian == endian)
+ {
+ cd = cl->cd;
+ break;
+ }
+ }
+ }
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
@@ -517,6 +536,16 @@ print_insn_openrisc (pc, info)
CGEN_CPU_OPEN_END);
if (!cd)
abort ();
+
+ /* save this away for future reference */
+ cl = xmalloc (sizeof (struct cpu_desc_list));
+ cl->cd = cd;
+ cl->isa = isa;
+ cl->mach = mach;
+ cl->endian = endian;
+ cl->next = cd_list;
+ cd_list = cl;
+
openrisc_cgen_init_dis (cd);
}
diff --git a/opcodes/xstormy16-asm.c b/opcodes/xstormy16-asm.c
index 3f26b18..047339d 100644
--- a/opcodes/xstormy16-asm.c
+++ b/opcodes/xstormy16-asm.c
@@ -479,7 +479,7 @@ parse_insn_normal (cd, insn, strp, fields)
}
/* We have an operand of some sort. */
- errmsg = xstormy16_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
+ errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
&str, fields);
if (errmsg)
return errmsg;
diff --git a/opcodes/xstormy16-desc.c b/opcodes/xstormy16-desc.c
index 41da91b..0c50625 100644
--- a/opcodes/xstormy16-desc.c
+++ b/opcodes/xstormy16-desc.c
@@ -1458,10 +1458,43 @@ void
xstormy16_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
+ unsigned int i;
+ CGEN_INSN *insns;
+
+ if (cd->macro_insn_table.init_entries)
+ {
+ insns = cd->macro_insn_table.init_entries;
+ for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+ {
+ if (CGEN_INSN_RX ((insns)))
+ regfree(CGEN_INSN_RX (insns));
+ }
+ }
+
+ if (cd->insn_table.init_entries)
+ {
+ insns = cd->insn_table.init_entries;
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ {
+ if (CGEN_INSN_RX (insns))
+ regfree(CGEN_INSN_RX (insns));
+ }
+ }
+
+
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
if (cd->insn_table.init_entries)
free ((CGEN_INSN *) cd->insn_table.init_entries);
+
if (cd->hw_table.entries)
free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+ if (cd->operand_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
free (cd);
}
diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c
index bd6c593..f3cc8e6 100644
--- a/opcodes/xstormy16-dis.c
+++ b/opcodes/xstormy16-dis.c
@@ -483,11 +483,21 @@ default_print_insn (cd, pc, info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
+typedef struct cpu_desc_list {
+ struct cpu_desc_list *next;
+ int isa;
+ int mach;
+ int endian;
+ CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
int
print_insn_xstormy16 (pc, info)
bfd_vma pc;
disassemble_info *info;
{
+ static cpu_desc_list *cd_list = 0;
+ cpu_desc_list *cl = 0;
static CGEN_CPU_DESC cd = 0;
static int prev_isa;
static int prev_mach;
@@ -518,18 +528,27 @@ print_insn_xstormy16 (pc, info)
#ifdef CGEN_COMPUTE_ISA
isa = CGEN_COMPUTE_ISA (info);
#else
- isa = 0;
+ isa = info->insn_sets;
#endif
- /* If we've switched cpu's, close the current table and open a new one. */
+ /* If we've switched cpu's, try to find a handle we've used before */
if (cd
&& (isa != prev_isa
|| mach != prev_mach
|| endian != prev_endian))
{
- xstormy16_cgen_cpu_close (cd);
cd = 0;
- }
+ for (cl = cd_list; cl; cl = cl->next)
+ {
+ if (cl->isa == isa &&
+ cl->mach == mach &&
+ cl->endian == endian)
+ {
+ cd = cl->cd;
+ break;
+ }
+ }
+ }
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
@@ -550,6 +569,16 @@ print_insn_xstormy16 (pc, info)
CGEN_CPU_OPEN_END);
if (!cd)
abort ();
+
+ /* save this away for future reference */
+ cl = xmalloc (sizeof (struct cpu_desc_list));
+ cl->cd = cd;
+ cl->isa = isa;
+ cl->mach = mach;
+ cl->endian = endian;
+ cl->next = cd_list;
+ cd_list = cl;
+
xstormy16_cgen_init_dis (cd);
}
generated by cgit v1.1 at 2024-11-23 06:57:56 +0000