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-rw-r--r--gdb/ChangeLog22
-rw-r--r--gdb/NEWS2
-rw-r--r--gdb/doc/ChangeLog6
-rw-r--r--gdb/doc/gdb.texinfo43
-rw-r--r--gdb/features/sparc/sparc32-cp0.xml19
-rw-r--r--gdb/features/sparc/sparc32-cpu.xml42
-rw-r--r--gdb/features/sparc/sparc32-fpu.xml43
-rw-r--r--gdb/features/sparc/sparc32-solaris.c98
-rw-r--r--gdb/features/sparc/sparc32-solaris.xml15
-rw-r--r--gdb/features/sparc/sparc64-cp0.xml17
-rw-r--r--gdb/features/sparc/sparc64-cpu.xml42
-rw-r--r--gdb/features/sparc/sparc64-fpu.xml60
-rw-r--r--gdb/features/sparc/sparc64-solaris.c112
-rw-r--r--gdb/features/sparc/sparc64-solaris.xml15
-rw-r--r--gdb/sparc-tdep.c75
-rw-r--r--gdb/sparc-tdep.h6
-rw-r--r--gdb/sparc64-tdep.c16
-rw-r--r--gdb/testsuite/ChangeLog5
-rw-r--r--gdb/testsuite/gdb.xml/tdesc-regs.exp9
19 files changed, 647 insertions, 0 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index f13305c..3e8f9c8 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,25 @@
+2017-02-06 Ivo Raisr <ivo.raisr@oracle.com>
+
+ PR tdep/20936
+ Provide and use sparc32 and sparc64 target description XML files.
+ * features/sparc/sparc32-cp0.xml, features/sparc/sparc32-cpu.xml,
+ features/sparc/sparc32-fpu.xml: New files for sparc 32-bit.
+ * features/sparc/sparc64-cp0.xml, features/sparc/sparc64-cpu.xml,
+ features/sparc/sparc64-fpu.xml: New files for sparc 64-bit.
+ * features/sparc/sparc32-solaris.xml: New file.
+ * features/sparc/sparc64-solaris.xml: New file.
+ * features/sparc/sparc32-solaris.c: Generated.
+ * features/sparc/sparc64-solaris.c: Generated.
+ * sparc-tdep.h: Account for differences in target descriptions.
+ * sparc-tdep.c (sparc32_register_name): Use target provided registers.
+ (sparc32_register_type): Use target provided registers.
+ (validate_tdesc_registers): New function.
+ (sparc32_gdbarch_init): Use tdesc_has_registers.
+ Set pseudoregister functions.
+ * sparc64-tdep.c (sparc64_register_name): Use target provided registers.
+ (sparc64_register_type): Use target provided registers.
+ (sparc64_init_abi): Set pseudoregister functions.
+
2017-02-03 Tom Tromey <tom@tromey.com>
PR rust/21097:
diff --git a/gdb/NEWS b/gdb/NEWS
index 21e8cd3..b71b1ea 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -47,6 +47,8 @@
end
end
+* Target descriptions can now describe registers for sparc32 and sparc64.
+
* New native configurations
FreeBSD/mips mips*-*-freebsd
diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog
index 670e9b7..9b5e140 100644
--- a/gdb/doc/ChangeLog
+++ b/gdb/doc/ChangeLog
@@ -1,3 +1,9 @@
+2017-02-06 Ivo Raisr <ivo.raisr@oracle.com>
+
+ PR tdep/20936
+ * gdb.texinfo: (Standard Target Features): Document SPARC features.
+ (Sparc Features): New node.
+
2017-01-27 Walfred Tedeschi <walfred.tedeschi@intel.com>
* gdb.texinfo (i386 Features): Add system segment registers
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index b9b4c82..a969d1b 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -41030,6 +41030,7 @@ registers using the capitalization used in the description.
* Nios II Features::
* PowerPC Features::
* S/390 and System z Features::
+* Sparc Features::
* TIC6x Features::
@end menu
@@ -41381,6 +41382,48 @@ through @samp{f15} to present the 128-bit wide vector registers
contain the 128-bit wide vector registers @samp{v16} through
@samp{v31}.
+@node Sparc Features
+@subsection Sparc Features
+@cindex target descriptions, sparc32 features
+@cindex target descriptions, sparc64 features
+The @samp{org.gnu.gdb.sparc.cpu} feature is required for sparc32/sparc64
+targets. It should describe the following registers:
+
+@itemize @minus
+@item
+@samp{g0} through @samp{g7}
+@item
+@samp{o0} through @samp{o7}
+@item
+@samp{l0} through @samp{l7}
+@item
+@samp{i0} through @samp{i7}
+@end itemize
+
+They may be 32-bit or 64-bit depending on the target.
+
+Also the @samp{org.gnu.gdb.sparc.fpu} feature is required for sparc32/sparc64
+targets. It should describe the following registers:
+
+@itemize @minus
+@item
+@samp{f0} through @samp{f31}
+@item
+@samp{f32} through @samp{f62} for sparc64
+@end itemize
+
+The @samp{org.gnu.gdb.sparc.cp0} feature is required for sparc32/sparc64
+targets. It should describe the following registers:
+
+@itemize @minus
+@item
+@samp{y}, @samp{psr}, @samp{wim}, @samp{tbr}, @samp{pc}, @samp{npc},
+@samp{fsr}, and @samp{csr} for sparc32
+@item
+@samp{pc}, @samp{npc}, @samp{state}, @samp{fsr}, @samp{fprs}, and @samp{y}
+for sparc64
+@end itemize
+
@node TIC6x Features
@subsection TMS320C6x Features
@cindex target descriptions, TIC6x features
diff --git a/gdb/features/sparc/sparc32-cp0.xml b/gdb/features/sparc/sparc32-cp0.xml
new file mode 100644
index 0000000..b39d026
--- /dev/null
+++ b/gdb/features/sparc/sparc32-cp0.xml
@@ -0,0 +1,19 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2013-2017 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.sparc.cp0">
+ <reg name="y" bitsize="32" type="uint32" regnum="64"/>
+ <reg name="psr" bitsize="32" type="uint32" regnum="65"/>
+ <reg name="wim" bitsize="32" type="uint32" regnum="66"/>
+ <reg name="tbr" bitsize="32" type="uint32" regnum="67"/>
+ <reg name="pc" bitsize="32" type="code_ptr" regnum="68"/>
+ <reg name="npc" bitsize="32" type="code_ptr" regnum="69"/>
+ <reg name="fsr" bitsize="32" type="uint32" regnum="70"/>
+ <reg name="csr" bitsize="32" type="uint32" regnum="71"/>
+</feature>
+
diff --git a/gdb/features/sparc/sparc32-cpu.xml b/gdb/features/sparc/sparc32-cpu.xml
new file mode 100644
index 0000000..2c3ea58
--- /dev/null
+++ b/gdb/features/sparc/sparc32-cpu.xml
@@ -0,0 +1,42 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2013-2017 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.sparc.cpu">
+ <reg name="g0" bitsize="32" type="uint32" regnum="0"/>
+ <reg name="g1" bitsize="32" type="uint32" regnum="1"/>
+ <reg name="g2" bitsize="32" type="uint32" regnum="2"/>
+ <reg name="g3" bitsize="32" type="uint32" regnum="3"/>
+ <reg name="g4" bitsize="32" type="uint32" regnum="4"/>
+ <reg name="g5" bitsize="32" type="uint32" regnum="5"/>
+ <reg name="g6" bitsize="32" type="uint32" regnum="6"/>
+ <reg name="g7" bitsize="32" type="uint32" regnum="7"/>
+ <reg name="o0" bitsize="32" type="uint32" regnum="8"/>
+ <reg name="o1" bitsize="32" type="uint32" regnum="9"/>
+ <reg name="o2" bitsize="32" type="uint32" regnum="10"/>
+ <reg name="o3" bitsize="32" type="uint32" regnum="11"/>
+ <reg name="o4" bitsize="32" type="uint32" regnum="12"/>
+ <reg name="o5" bitsize="32" type="uint32" regnum="13"/>
+ <reg name="sp" bitsize="32" type="uint32" regnum="14"/>
+ <reg name="o7" bitsize="32" type="uint32" regnum="15"/>
+ <reg name="l0" bitsize="32" type="uint32" regnum="16"/>
+ <reg name="l1" bitsize="32" type="uint32" regnum="17"/>
+ <reg name="l2" bitsize="32" type="uint32" regnum="18"/>
+ <reg name="l3" bitsize="32" type="uint32" regnum="19"/>
+ <reg name="l4" bitsize="32" type="uint32" regnum="20"/>
+ <reg name="l5" bitsize="32" type="uint32" regnum="21"/>
+ <reg name="l6" bitsize="32" type="uint32" regnum="22"/>
+ <reg name="l7" bitsize="32" type="uint32" regnum="23"/>
+ <reg name="i0" bitsize="32" type="uint32" regnum="24"/>
+ <reg name="i1" bitsize="32" type="uint32" regnum="25"/>
+ <reg name="i2" bitsize="32" type="uint32" regnum="26"/>
+ <reg name="i3" bitsize="32" type="uint32" regnum="27"/>
+ <reg name="i4" bitsize="32" type="uint32" regnum="28"/>
+ <reg name="i5" bitsize="32" type="uint32" regnum="29"/>
+ <reg name="fp" bitsize="32" type="uint32" regnum="30"/>
+ <reg name="i7" bitsize="32" type="uint32" regnum="31"/>
+</feature>
diff --git a/gdb/features/sparc/sparc32-fpu.xml b/gdb/features/sparc/sparc32-fpu.xml
new file mode 100644
index 0000000..b59bbe3
--- /dev/null
+++ b/gdb/features/sparc/sparc32-fpu.xml
@@ -0,0 +1,43 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2013-2017 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.sparc.fpu">
+ <reg name="f0" bitsize="32" type="ieee_single" regnum="32"/>
+ <reg name="f1" bitsize="32" type="ieee_single" regnum="33"/>
+ <reg name="f2" bitsize="32" type="ieee_single" regnum="34"/>
+ <reg name="f3" bitsize="32" type="ieee_single" regnum="35"/>
+ <reg name="f4" bitsize="32" type="ieee_single" regnum="36"/>
+ <reg name="f5" bitsize="32" type="ieee_single" regnum="37"/>
+ <reg name="f6" bitsize="32" type="ieee_single" regnum="38"/>
+ <reg name="f7" bitsize="32" type="ieee_single" regnum="39"/>
+ <reg name="f8" bitsize="32" type="ieee_single" regnum="40"/>
+ <reg name="f9" bitsize="32" type="ieee_single" regnum="41"/>
+ <reg name="f10" bitsize="32" type="ieee_single" regnum="42"/>
+ <reg name="f11" bitsize="32" type="ieee_single" regnum="43"/>
+ <reg name="f12" bitsize="32" type="ieee_single" regnum="44"/>
+ <reg name="f13" bitsize="32" type="ieee_single" regnum="45"/>
+ <reg name="f14" bitsize="32" type="ieee_single" regnum="46"/>
+ <reg name="f15" bitsize="32" type="ieee_single" regnum="47"/>
+ <reg name="f16" bitsize="32" type="ieee_single" regnum="48"/>
+ <reg name="f17" bitsize="32" type="ieee_single" regnum="49"/>
+ <reg name="f18" bitsize="32" type="ieee_single" regnum="50"/>
+ <reg name="f19" bitsize="32" type="ieee_single" regnum="51"/>
+ <reg name="f20" bitsize="32" type="ieee_single" regnum="52"/>
+ <reg name="f21" bitsize="32" type="ieee_single" regnum="53"/>
+ <reg name="f22" bitsize="32" type="ieee_single" regnum="54"/>
+ <reg name="f23" bitsize="32" type="ieee_single" regnum="55"/>
+ <reg name="f24" bitsize="32" type="ieee_single" regnum="56"/>
+ <reg name="f25" bitsize="32" type="ieee_single" regnum="57"/>
+ <reg name="f26" bitsize="32" type="ieee_single" regnum="58"/>
+ <reg name="f27" bitsize="32" type="ieee_single" regnum="59"/>
+ <reg name="f28" bitsize="32" type="ieee_single" regnum="60"/>
+ <reg name="f29" bitsize="32" type="ieee_single" regnum="61"/>
+ <reg name="f30" bitsize="32" type="ieee_single" regnum="62"/>
+ <reg name="f31" bitsize="32" type="ieee_single" regnum="63"/>
+</feature>
+
diff --git a/gdb/features/sparc/sparc32-solaris.c b/gdb/features/sparc/sparc32-solaris.c
new file mode 100644
index 0000000..2f13292
--- /dev/null
+++ b/gdb/features/sparc/sparc32-solaris.c
@@ -0,0 +1,98 @@
+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
+ Original: sparc32-solaris.xml */
+
+#include "defs.h"
+#include "osabi.h"
+#include "target-descriptions.h"
+
+struct target_desc *tdesc_sparc32_solaris;
+static void
+initialize_tdesc_sparc32_solaris (void)
+{
+ struct target_desc *result = allocate_target_description ();
+ struct tdesc_feature *feature;
+
+ set_tdesc_architecture (result, bfd_scan_arch ("sparc"));
+
+ set_tdesc_osabi (result, osabi_from_tdesc_string ("Solaris"));
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.sparc.cpu");
+ tdesc_create_reg (feature, "g0", 0, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "g1", 1, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "g2", 2, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "g3", 3, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "g4", 4, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "g5", 5, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "g6", 6, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "g7", 7, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "o0", 8, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "o1", 9, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "o2", 10, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "o3", 11, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "o4", 12, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "o5", 13, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "sp", 14, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "o7", 15, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "l0", 16, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "l1", 17, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "l2", 18, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "l3", 19, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "l4", 20, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "l5", 21, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "l6", 22, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "l7", 23, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "i0", 24, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "i1", 25, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "i2", 26, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "i3", 27, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "i4", 28, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "i5", 29, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "fp", 30, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "i7", 31, 1, NULL, 32, "uint32");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.sparc.cp0");
+ tdesc_create_reg (feature, "y", 64, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "psr", 65, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "wim", 66, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "tbr", 67, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "pc", 68, 1, NULL, 32, "code_ptr");
+ tdesc_create_reg (feature, "npc", 69, 1, NULL, 32, "code_ptr");
+ tdesc_create_reg (feature, "fsr", 70, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "csr", 71, 1, NULL, 32, "uint32");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.sparc.fpu");
+ tdesc_create_reg (feature, "f0", 32, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f1", 33, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f2", 34, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f3", 35, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f4", 36, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f5", 37, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f6", 38, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f7", 39, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f8", 40, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f9", 41, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f10", 42, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f11", 43, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f12", 44, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f13", 45, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f14", 46, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f15", 47, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f16", 48, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f17", 49, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f18", 50, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f19", 51, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f20", 52, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f21", 53, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f22", 54, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f23", 55, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f24", 56, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f25", 57, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f26", 58, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f27", 59, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f28", 60, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f29", 61, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f30", 62, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f31", 63, 1, NULL, 32, "ieee_single");
+
+ tdesc_sparc_solaris = result;
+}
diff --git a/gdb/features/sparc/sparc32-solaris.xml b/gdb/features/sparc/sparc32-solaris.xml
new file mode 100644
index 0000000..2887afb
--- /dev/null
+++ b/gdb/features/sparc/sparc32-solaris.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2013-2017 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>sparc</architecture>
+ <osabi>Solaris</osabi>
+ <xi:include href="sparc32-cpu.xml"/>
+ <xi:include href="sparc32-cp0.xml"/>
+ <xi:include href="sparc32-fpu.xml"/>
+</target>
diff --git a/gdb/features/sparc/sparc64-cp0.xml b/gdb/features/sparc/sparc64-cp0.xml
new file mode 100644
index 0000000..bc257b3
--- /dev/null
+++ b/gdb/features/sparc/sparc64-cp0.xml
@@ -0,0 +1,17 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2013-2017 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.sparc.cp0">
+ <reg name="pc" bitsize="64" type="code_ptr" regnum="80"/>
+ <reg name="npc" bitsize="64" type="code_ptr" regnum="81"/>
+ <reg name="state" bitsize="64" type="uint64" regnum="82"/>
+ <reg name="fsr" bitsize="64" type="uint64" regnum="83"/>
+ <reg name="fprs" bitsize="64" type="uint64" regnum="84"/>
+ <reg name="y" bitsize="64" type="uint64" regnum="85"/>
+</feature>
+
diff --git a/gdb/features/sparc/sparc64-cpu.xml b/gdb/features/sparc/sparc64-cpu.xml
new file mode 100644
index 0000000..3ea0828
--- /dev/null
+++ b/gdb/features/sparc/sparc64-cpu.xml
@@ -0,0 +1,42 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2013-2017 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.sparc.cpu">
+ <reg name="g0" bitsize="64" type="uint64" regnum="0"/>
+ <reg name="g1" bitsize="64" type="uint64" regnum="1"/>
+ <reg name="g2" bitsize="64" type="uint64" regnum="2"/>
+ <reg name="g3" bitsize="64" type="uint64" regnum="3"/>
+ <reg name="g4" bitsize="64" type="uint64" regnum="4"/>
+ <reg name="g5" bitsize="64" type="uint64" regnum="5"/>
+ <reg name="g6" bitsize="64" type="uint64" regnum="6"/>
+ <reg name="g7" bitsize="64" type="uint64" regnum="7"/>
+ <reg name="o0" bitsize="64" type="uint64" regnum="8"/>
+ <reg name="o1" bitsize="64" type="uint64" regnum="9"/>
+ <reg name="o2" bitsize="64" type="uint64" regnum="10"/>
+ <reg name="o3" bitsize="64" type="uint64" regnum="11"/>
+ <reg name="o4" bitsize="64" type="uint64" regnum="12"/>
+ <reg name="o5" bitsize="64" type="uint64" regnum="13"/>
+ <reg name="sp" bitsize="64" type="uint64" regnum="14"/>
+ <reg name="o7" bitsize="64" type="uint64" regnum="15"/>
+ <reg name="l0" bitsize="64" type="uint64" regnum="16"/>
+ <reg name="l1" bitsize="64" type="uint64" regnum="17"/>
+ <reg name="l2" bitsize="64" type="uint64" regnum="18"/>
+ <reg name="l3" bitsize="64" type="uint64" regnum="19"/>
+ <reg name="l4" bitsize="64" type="uint64" regnum="20"/>
+ <reg name="l5" bitsize="64" type="uint64" regnum="21"/>
+ <reg name="l6" bitsize="64" type="uint64" regnum="22"/>
+ <reg name="l7" bitsize="64" type="uint64" regnum="23"/>
+ <reg name="i0" bitsize="64" type="uint64" regnum="24"/>
+ <reg name="i1" bitsize="64" type="uint64" regnum="25"/>
+ <reg name="i2" bitsize="64" type="uint64" regnum="26"/>
+ <reg name="i3" bitsize="64" type="uint64" regnum="27"/>
+ <reg name="i4" bitsize="64" type="uint64" regnum="28"/>
+ <reg name="i5" bitsize="64" type="uint64" regnum="29"/>
+ <reg name="fp" bitsize="64" type="uint64" regnum="30"/>
+ <reg name="i7" bitsize="64" type="uint64" regnum="31"/>
+</feature>
diff --git a/gdb/features/sparc/sparc64-fpu.xml b/gdb/features/sparc/sparc64-fpu.xml
new file mode 100644
index 0000000..8a23380
--- /dev/null
+++ b/gdb/features/sparc/sparc64-fpu.xml
@@ -0,0 +1,60 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2013-2017 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.sparc.fpu">
+ <reg name="f0" bitsize="32" type="ieee_single" regnum="32"/>
+ <reg name="f1" bitsize="32" type="ieee_single" regnum="33"/>
+ <reg name="f2" bitsize="32" type="ieee_single" regnum="34"/>
+ <reg name="f3" bitsize="32" type="ieee_single" regnum="35"/>
+ <reg name="f4" bitsize="32" type="ieee_single" regnum="36"/>
+ <reg name="f5" bitsize="32" type="ieee_single" regnum="37"/>
+ <reg name="f6" bitsize="32" type="ieee_single" regnum="38"/>
+ <reg name="f7" bitsize="32" type="ieee_single" regnum="39"/>
+ <reg name="f8" bitsize="32" type="ieee_single" regnum="40"/>
+ <reg name="f9" bitsize="32" type="ieee_single" regnum="41"/>
+ <reg name="f10" bitsize="32" type="ieee_single" regnum="42"/>
+ <reg name="f11" bitsize="32" type="ieee_single" regnum="43"/>
+ <reg name="f12" bitsize="32" type="ieee_single" regnum="44"/>
+ <reg name="f13" bitsize="32" type="ieee_single" regnum="45"/>
+ <reg name="f14" bitsize="32" type="ieee_single" regnum="46"/>
+ <reg name="f15" bitsize="32" type="ieee_single" regnum="47"/>
+ <reg name="f16" bitsize="32" type="ieee_single" regnum="48"/>
+ <reg name="f17" bitsize="32" type="ieee_single" regnum="49"/>
+ <reg name="f18" bitsize="32" type="ieee_single" regnum="50"/>
+ <reg name="f19" bitsize="32" type="ieee_single" regnum="51"/>
+ <reg name="f20" bitsize="32" type="ieee_single" regnum="52"/>
+ <reg name="f21" bitsize="32" type="ieee_single" regnum="53"/>
+ <reg name="f22" bitsize="32" type="ieee_single" regnum="54"/>
+ <reg name="f23" bitsize="32" type="ieee_single" regnum="55"/>
+ <reg name="f24" bitsize="32" type="ieee_single" regnum="56"/>
+ <reg name="f25" bitsize="32" type="ieee_single" regnum="57"/>
+ <reg name="f26" bitsize="32" type="ieee_single" regnum="58"/>
+ <reg name="f27" bitsize="32" type="ieee_single" regnum="59"/>
+ <reg name="f28" bitsize="32" type="ieee_single" regnum="60"/>
+ <reg name="f29" bitsize="32" type="ieee_single" regnum="61"/>
+ <reg name="f30" bitsize="32" type="ieee_single" regnum="62"/>
+ <reg name="f31" bitsize="32" type="ieee_single" regnum="63"/>
+
+ <reg name="f32" bitsize="64" type="ieee_double" regnum="64"/>
+ <reg name="f34" bitsize="64" type="ieee_double" regnum="65"/>
+ <reg name="f36" bitsize="64" type="ieee_double" regnum="66"/>
+ <reg name="f38" bitsize="64" type="ieee_double" regnum="67"/>
+ <reg name="f40" bitsize="64" type="ieee_double" regnum="68"/>
+ <reg name="f42" bitsize="64" type="ieee_double" regnum="69"/>
+ <reg name="f44" bitsize="64" type="ieee_double" regnum="70"/>
+ <reg name="f46" bitsize="64" type="ieee_double" regnum="71"/>
+ <reg name="f48" bitsize="64" type="ieee_double" regnum="72"/>
+ <reg name="f50" bitsize="64" type="ieee_double" regnum="73"/>
+ <reg name="f52" bitsize="64" type="ieee_double" regnum="74"/>
+ <reg name="f54" bitsize="64" type="ieee_double" regnum="75"/>
+ <reg name="f56" bitsize="64" type="ieee_double" regnum="76"/>
+ <reg name="f58" bitsize="64" type="ieee_double" regnum="77"/>
+ <reg name="f60" bitsize="64" type="ieee_double" regnum="78"/>
+ <reg name="f62" bitsize="64" type="ieee_double" regnum="79"/>
+</feature>
+
diff --git a/gdb/features/sparc/sparc64-solaris.c b/gdb/features/sparc/sparc64-solaris.c
new file mode 100644
index 0000000..ecc7b0f
--- /dev/null
+++ b/gdb/features/sparc/sparc64-solaris.c
@@ -0,0 +1,112 @@
+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
+ Original: sparc64-solaris.xml */
+
+#include "defs.h"
+#include "osabi.h"
+#include "target-descriptions.h"
+
+struct target_desc *tdesc_sparc64_solaris;
+static void
+initialize_tdesc_sparc64_solaris (void)
+{
+ struct target_desc *result = allocate_target_description ();
+ struct tdesc_feature *feature;
+
+ set_tdesc_architecture (result, bfd_scan_arch ("sparc"));
+
+ set_tdesc_osabi (result, osabi_from_tdesc_string ("Solaris"));
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.sparc.cpu");
+ tdesc_create_reg (feature, "g0", 0, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "g1", 1, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "g2", 2, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "g3", 3, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "g4", 4, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "g5", 5, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "g6", 6, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "g7", 7, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "o0", 8, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "o1", 9, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "o2", 10, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "o3", 11, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "o4", 12, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "o5", 13, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "sp", 14, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "o7", 15, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "l0", 16, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "l1", 17, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "l2", 18, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "l3", 19, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "l4", 20, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "l5", 21, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "l6", 22, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "l7", 23, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "i0", 24, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "i1", 25, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "i2", 26, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "i3", 27, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "i4", 28, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "i5", 29, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "fp", 30, 1, NULL, 32, "uint64");
+ tdesc_create_reg (feature, "i7", 31, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.sparc.cp0");
+ tdesc_create_reg (feature, "pc", 80, 1, NULL, 64, "code_ptr");
+ tdesc_create_reg (feature, "npc", 81, 1, NULL, 64, "code_ptr");
+ tdesc_create_reg (feature, "state", 82, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "fsr", 83, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "fprs", 84, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "y", 85, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.sparc.fpu");
+ tdesc_create_reg (feature, "f0", 32, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f1", 33, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f2", 34, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f3", 35, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f4", 36, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f5", 37, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f6", 38, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f7", 39, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f8", 40, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f9", 41, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f10", 42, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f11", 43, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f12", 44, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f13", 45, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f14", 46, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f15", 47, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f16", 48, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f17", 49, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f18", 50, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f19", 51, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f20", 52, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f21", 53, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f22", 54, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f23", 55, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f24", 56, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f25", 57, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f26", 58, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f27", 59, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f28", 60, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f29", 61, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f30", 62, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f31", 63, 1, NULL, 32, "ieee_single");
+ tdesc_create_reg (feature, "f32", 64, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f34", 65, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f36", 66, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f38", 67, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f40", 68, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f42", 69, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f44", 70, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f46", 71, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f48", 72, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f50", 73, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f52", 74, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f54", 75, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f56", 76, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f58", 77, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f60", 78, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f62", 79, 1, NULL, 64, "ieee_double");
+
+ tdesc_sparc64_solaris = result;
+}
diff --git a/gdb/features/sparc/sparc64-solaris.xml b/gdb/features/sparc/sparc64-solaris.xml
new file mode 100644
index 0000000..767fd9a
--- /dev/null
+++ b/gdb/features/sparc/sparc64-solaris.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2013-2017 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>sparc:v9</architecture>
+ <osabi>Solaris</osabi>
+ <xi:include href="sparc64-cpu.xml"/>
+ <xi:include href="sparc64-cp0.xml"/>
+ <xi:include href="sparc64-fpu.xml"/>
+</target>
diff --git a/gdb/sparc-tdep.c b/gdb/sparc-tdep.c
index 81cbce2..afbcf2e 100644
--- a/gdb/sparc-tdep.c
+++ b/gdb/sparc-tdep.c
@@ -33,6 +33,7 @@
#include "osabi.h"
#include "regcache.h"
#include "target.h"
+#include "target-descriptions.h"
#include "value.h"
#include "sparc-tdep.h"
@@ -304,6 +305,10 @@ sparc_structure_or_union_p (const struct type *type)
#define SPARC32_CP0_REGISTERS \
"y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
+static const char *sparc_core_register_names[] = { SPARC_CORE_REGISTERS };
+static const char *sparc32_fpu_register_names[] = { SPARC32_FPU_REGISTERS };
+static const char *sparc32_cp0_register_names[] = { SPARC32_CP0_REGISTERS };
+
static const char *sparc32_register_names[] =
{
SPARC_CORE_REGISTERS,
@@ -346,6 +351,9 @@ sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
static const char *
sparc32_register_name (struct gdbarch *gdbarch, int regnum)
{
+ if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
+ return tdesc_register_name (gdbarch, regnum);
+
if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
return sparc32_register_names[regnum];
@@ -431,6 +439,9 @@ sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
static struct type *
sparc32_register_type (struct gdbarch *gdbarch, int regnum)
{
+ if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
+ return tdesc_register_type (gdbarch, regnum);
+
if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
return builtin_type (gdbarch)->builtin_float;
@@ -1686,11 +1697,36 @@ sparc_iterate_over_regset_sections (struct gdbarch *gdbarch,
}
+static int
+validate_tdesc_registers (const struct target_desc *tdesc,
+ struct tdesc_arch_data *tdesc_data,
+ const char *feature_name,
+ const char *register_names[],
+ unsigned int registers_num,
+ unsigned int reg_start)
+{
+ int valid_p = 1;
+ const struct tdesc_feature *feature;
+
+ feature = tdesc_find_feature (tdesc, feature_name);
+ if (feature == NULL)
+ return 0;
+
+ for (unsigned int i = 0; i < registers_num; i++)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ reg_start + i,
+ register_names[i]);
+
+ return valid_p;
+}
+
static struct gdbarch *
sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
{
struct gdbarch_tdep *tdep;
+ const struct target_desc *tdesc = info.target_desc;
struct gdbarch *gdbarch;
+ int valid_p = 1;
/* If there is already a candidate, use it. */
arches = gdbarch_list_lookup_by_info (arches, &info);
@@ -1704,6 +1740,10 @@ sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
tdep->pc_regnum = SPARC32_PC_REGNUM;
tdep->npc_regnum = SPARC32_NPC_REGNUM;
tdep->step_trap = sparc_step_trap;
+ tdep->fpu_register_names = sparc32_fpu_register_names;
+ tdep->fpu_registers_num = ARRAY_SIZE (sparc32_fpu_register_names);
+ tdep->cp0_register_names = sparc32_cp0_register_names;
+ tdep->cp0_registers_num = ARRAY_SIZE (sparc32_cp0_register_names);
set_gdbarch_long_double_bit (gdbarch, 128);
set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad);
@@ -1712,6 +1752,8 @@ sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
set_gdbarch_register_name (gdbarch, sparc32_register_name);
set_gdbarch_register_type (gdbarch, sparc32_register_type);
set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
+ set_tdesc_pseudo_register_name (gdbarch, sparc32_pseudo_register_name);
+ set_tdesc_pseudo_register_type (gdbarch, sparc32_pseudo_register_type);
set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
@@ -1763,6 +1805,39 @@ sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind);
+ if (tdesc_has_registers (tdesc))
+ {
+ struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
+
+ /* Validate that the descriptor provides the mandatory registers
+ and allocate their numbers. */
+ valid_p &= validate_tdesc_registers (tdesc, tdesc_data,
+ "org.gnu.gdb.sparc.cpu",
+ sparc_core_register_names,
+ ARRAY_SIZE (sparc_core_register_names),
+ SPARC_G0_REGNUM);
+ valid_p &= validate_tdesc_registers (tdesc, tdesc_data,
+ "org.gnu.gdb.sparc.fpu",
+ tdep->fpu_register_names,
+ tdep->fpu_registers_num,
+ SPARC_F0_REGNUM);
+ valid_p &= validate_tdesc_registers (tdesc, tdesc_data,
+ "org.gnu.gdb.sparc.cp0",
+ tdep->cp0_register_names,
+ tdep->cp0_registers_num,
+ SPARC_F0_REGNUM +
+ tdep->fpu_registers_num);
+ if (!valid_p)
+ {
+ tdesc_data_cleanup (tdesc_data);
+ return NULL;
+ }
+
+ /* Target description may have changed. */
+ info.tdep_info = tdesc_data;
+ tdesc_use_registers (gdbarch, tdesc, tdesc_data);
+ }
+
/* If we have register sets, enable the generic core file support. */
if (tdep->gregset)
set_gdbarch_iterate_over_regset_sections
diff --git a/gdb/sparc-tdep.h b/gdb/sparc-tdep.h
index 4990873..268272efe 100644
--- a/gdb/sparc-tdep.h
+++ b/gdb/sparc-tdep.h
@@ -63,6 +63,12 @@ struct gdbarch_tdep
int pc_regnum;
int npc_regnum;
+ /* Register names specific for architecture (sparc32 vs. sparc64) */
+ const char **fpu_register_names;
+ size_t fpu_registers_num;
+ const char **cp0_register_names;
+ size_t cp0_registers_num;
+
/* Register sets. */
const struct regset *gregset;
size_t sizeof_gregset;
diff --git a/gdb/sparc64-tdep.c b/gdb/sparc64-tdep.c
index 3525098..43beffb 100644
--- a/gdb/sparc64-tdep.c
+++ b/gdb/sparc64-tdep.c
@@ -31,6 +31,7 @@
#include "objfiles.h"
#include "osabi.h"
#include "regcache.h"
+#include "target-descriptions.h"
#include "target.h"
#include "value.h"
@@ -241,6 +242,9 @@ sparc64_fprs_type (struct gdbarch *gdbarch)
"fprs", \
"y"
+static const char *sparc64_fpu_register_names[] = { SPARC64_FPU_REGISTERS };
+static const char *sparc64_cp0_register_names[] = { SPARC64_CP0_REGISTERS };
+
static const char *sparc64_register_names[] =
{
SPARC_CORE_REGISTERS,
@@ -290,6 +294,9 @@ sparc64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
static const char *
sparc64_register_name (struct gdbarch *gdbarch, int regnum)
{
+ if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
+ return tdesc_register_name (gdbarch, regnum);
+
if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
return sparc64_register_names[regnum];
@@ -328,6 +335,9 @@ sparc64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
static struct type *
sparc64_register_type (struct gdbarch *gdbarch, int regnum)
{
+ if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
+ return tdesc_register_type (gdbarch, regnum);
+
/* Raw registers. */
if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
return builtin_type (gdbarch)->builtin_data_ptr;
@@ -1222,6 +1232,10 @@ sparc64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
tdep->pc_regnum = SPARC64_PC_REGNUM;
tdep->npc_regnum = SPARC64_NPC_REGNUM;
+ tdep->fpu_register_names = sparc64_fpu_register_names;
+ tdep->fpu_registers_num = ARRAY_SIZE (sparc64_fpu_register_names);
+ tdep->cp0_register_names = sparc64_cp0_register_names;
+ tdep->cp0_registers_num = ARRAY_SIZE (sparc64_cp0_register_names);
/* This is what all the fuss is about. */
set_gdbarch_long_bit (gdbarch, 64);
@@ -1232,6 +1246,8 @@ sparc64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
set_gdbarch_register_name (gdbarch, sparc64_register_name);
set_gdbarch_register_type (gdbarch, sparc64_register_type);
set_gdbarch_num_pseudo_regs (gdbarch, SPARC64_NUM_PSEUDO_REGS);
+ set_tdesc_pseudo_register_name (gdbarch, sparc64_pseudo_register_name);
+ set_tdesc_pseudo_register_type (gdbarch, sparc64_pseudo_register_type);
set_gdbarch_pseudo_register_read (gdbarch, sparc64_pseudo_register_read);
set_gdbarch_pseudo_register_write (gdbarch, sparc64_pseudo_register_write);
diff --git a/gdb/testsuite/ChangeLog b/gdb/testsuite/ChangeLog
index c098bd0..9aeec87 100644
--- a/gdb/testsuite/ChangeLog
+++ b/gdb/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2017-02-06 Ivo Raisr <ivo.raisr@oracle.com>
+
+ PR tdep/20936
+ * gdb.xml/tdesc-regs.exp: Provide sparc core registers for the tests.
+
2017-02-03 Tom Tromey <tom@tromey.com>
PR rust/21097:
diff --git a/gdb/testsuite/gdb.xml/tdesc-regs.exp b/gdb/testsuite/gdb.xml/tdesc-regs.exp
index 9909aad..70fc0e0 100644
--- a/gdb/testsuite/gdb.xml/tdesc-regs.exp
+++ b/gdb/testsuite/gdb.xml/tdesc-regs.exp
@@ -57,6 +57,15 @@ switch -glob -- [istarget] {
"s390*-*-*" {
set core-regs {s390-core32.xml s390-acr.xml s390-fpr.xml}
}
+ "sparc-*-*" {
+ set regdir "sparc/"
+ set core-regs {sparc32-cpu.xml sparc32-fpu.xml sparc32-cp0.xml}
+ }
+ "sparc64-*-*" {
+ set architecture "sparc:v9"
+ set regdir "sparc/"
+ set core-regs {sparc64-cpu.xml sparc64-fpu.xml sparc64-cp0.xml}
+ }
"spu*-*-*" {
# This may be either the spu-linux-nat target, or the Cell/B.E.
# multi-architecture debugger in SPU standalone executable mode.
generated by cgit v1.1 at 2024-11-23 12:55:14 +0000