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-rw-r--r--bfd/aix5ppc-core.c56
-rw-r--r--bfd/archures.c4
-rw-r--r--bfd/bfd-in2.h34
-rw-r--r--bfd/config.bfd7
-rwxr-xr-xbfd/configure2
-rw-r--r--bfd/configure.in2
-rw-r--r--bfd/libbfd.h22
-rw-r--r--bfd/reloc.c60
-rw-r--r--bfd/targets.c4
-rw-r--r--cpu/m32c.cpu91
-rw-r--r--cpu/m32c.opc513
-rw-r--r--gas/config/tc-m32c.c6
-rw-r--r--gas/configure.tgt25
-rw-r--r--ld/configure.tgt697
-rw-r--r--opcodes/configure.in4
-rw-r--r--opcodes/disassemble.c12
-rw-r--r--opcodes/m32c-asm.c510
-rw-r--r--opcodes/m32c-desc.c263
-rw-r--r--opcodes/m32c-desc.h437
-rw-r--r--opcodes/m32c-dis.c191
-rw-r--r--opcodes/m32c-ibld.c169
-rw-r--r--opcodes/m32c-opc.c186
-rw-r--r--opcodes/m32c-opc.h32
23 files changed, 1492 insertions, 1835 deletions
diff --git a/bfd/aix5ppc-core.c b/bfd/aix5ppc-core.c
index 0dc977a..89b6d8a 100644
--- a/bfd/aix5ppc-core.c
+++ b/bfd/aix5ppc-core.c
@@ -2,7 +2,7 @@
Copyright 2001, 2002, 2003, 2004
Free Software Foundation, Inc.
Written by Tom Rix
- Contributed by Redhat.
+ Contributed by Red Hat Inc.
This file is part of BFD, the Binary File Descriptor library.
@@ -28,14 +28,10 @@
#include "sysdep.h"
#include "libbfd.h"
-const bfd_target *xcoff64_core_p
- PARAMS ((bfd *));
-bfd_boolean xcoff64_core_file_matches_executable_p
- PARAMS ((bfd *, bfd *));
-char *xcoff64_core_file_failing_command
- PARAMS ((bfd *));
-int xcoff64_core_file_failing_signal
- PARAMS ((bfd *));
+const bfd_target *xcoff64_core_p (bfd *);
+bfd_boolean xcoff64_core_file_matches_executable_p (bfd *, bfd *);
+char *xcoff64_core_file_failing_command (bfd *);
+int xcoff64_core_file_failing_signal (bfd *);
/* Aix 5.1 system include file. */
@@ -50,8 +46,7 @@ int xcoff64_core_file_failing_signal
((bfd_signed_vma)(v) < 0 || (bfd_signed_vma)(v) > (bfd_signed_vma)(s).st_size)
const bfd_target *
-xcoff64_core_p (abfd)
- bfd *abfd;
+xcoff64_core_p (bfd *abfd)
{
struct core_dumpxx core, *new_core_hdr;
struct stat statbuf;
@@ -111,8 +106,7 @@ xcoff64_core_p (abfd)
return return_value;
}
- new_core_hdr = (struct core_dumpxx *)
- bfd_zalloc (abfd, sizeof (struct core_dumpxx));
+ new_core_hdr = bfd_zalloc (abfd, sizeof (struct core_dumpxx));
if (NULL == new_core_hdr)
return return_value;
@@ -232,9 +226,7 @@ xcoff64_core_p (abfd)
/* Return `TRUE' if given core is from the given executable. */
bfd_boolean
-xcoff64_core_file_matches_executable_p (core_bfd, exec_bfd)
- bfd *core_bfd;
- bfd *exec_bfd;
+xcoff64_core_file_matches_executable_p (bfd *core_bfd, bfd *exec_bfd)
{
struct core_dumpxx core;
char *path, *s;
@@ -298,8 +290,7 @@ xcoff64_core_file_matches_executable_p (core_bfd, exec_bfd)
}
char *
-xcoff64_core_file_failing_command (abfd)
- bfd *abfd;
+xcoff64_core_file_failing_command (bfd *abfd)
{
struct core_dumpxx *c = core_hdr (abfd);
char *return_value = 0;
@@ -311,8 +302,7 @@ xcoff64_core_file_failing_command (abfd)
}
int
-xcoff64_core_file_failing_signal (abfd)
- bfd *abfd;
+xcoff64_core_file_failing_signal (bfd *abfd)
{
struct core_dumpxx *c = core_hdr (abfd);
int return_value = 0;
@@ -325,41 +315,33 @@ xcoff64_core_file_failing_signal (abfd)
#else /* AIX_5_CORE */
-const bfd_target *xcoff64_core_p
- PARAMS ((bfd *));
-bfd_boolean xcoff64_core_file_matches_executable_p
- PARAMS ((bfd *, bfd *));
-char *xcoff64_core_file_failing_command
- PARAMS ((bfd *));
-int xcoff64_core_file_failing_signal
- PARAMS ((bfd *));
+const bfd_target *xcoff64_core_p (bfd *);
+bfd_boolean xcoff64_core_file_matches_executable_p (bfd *, bfd *);
+char *xcoff64_core_file_failing_command (bfd *);
+int xcoff64_core_file_failing_signal (bfd *);
const bfd_target *
-xcoff64_core_p (abfd)
- bfd *abfd ATTRIBUTE_UNUSED;
+xcoff64_core_p (bfd *abfd ATTRIBUTE_UNUSED)
{
bfd_set_error (bfd_error_wrong_format);
return 0;
}
bfd_boolean
-xcoff64_core_file_matches_executable_p (core_bfd, exec_bfd)
- bfd *core_bfd ATTRIBUTE_UNUSED;
- bfd *exec_bfd ATTRIBUTE_UNUSED;
+xcoff64_core_file_matches_executable_p (bfd *core_bfd ATTRIBUTE_UNUSED,
+ bfd *exec_bfd ATTRIBUTE_UNUSED)
{
return FALSE;
}
char *
-xcoff64_core_file_failing_command (abfd)
- bfd *abfd ATTRIBUTE_UNUSED;
+xcoff64_core_file_failing_command (bfd *abfd ATTRIBUTE_UNUSED)
{
return 0;
}
int
-xcoff64_core_file_failing_signal (abfd)
- bfd *abfd ATTRIBUTE_UNUSED;
+xcoff64_core_file_failing_signal (bfd *abfd ATTRIBUTE_UNUSED)
{
return 0;
}
diff --git a/bfd/archures.c b/bfd/archures.c
index 0588610..eb042a6 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -438,6 +438,7 @@ extern const bfd_arch_info_type bfd_mmix_arch;
extern const bfd_arch_info_type bfd_mn10200_arch;
extern const bfd_arch_info_type bfd_mn10300_arch;
extern const bfd_arch_info_type bfd_msp430_arch;
+extern const bfd_arch_info_type bfd_ms1_arch;
extern const bfd_arch_info_type bfd_ns32k_arch;
extern const bfd_arch_info_type bfd_openrisc_arch;
extern const bfd_arch_info_type bfd_or32_arch;
@@ -460,7 +461,6 @@ extern const bfd_arch_info_type bfd_w65_arch;
extern const bfd_arch_info_type bfd_xstormy16_arch;
extern const bfd_arch_info_type bfd_xtensa_arch;
extern const bfd_arch_info_type bfd_z8k_arch;
-extern const bfd_arch_info_type bfd_ms1_arch;
static const bfd_arch_info_type * const bfd_archures_list[] =
{
@@ -490,6 +490,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_ia64_arch,
&bfd_ip2k_arch,
&bfd_iq2000_arch,
+ &bfd_m32c_arch,
&bfd_m32r_arch,
&bfd_m68hc11_arch,
&bfd_m68hc12_arch,
@@ -523,7 +524,6 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_xstormy16_arch,
&bfd_xtensa_arch,
&bfd_z8k_arch,
- &bfd_m32c_arch,
#endif
0
};
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 062a819..c9c75c2 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -3035,6 +3035,25 @@ of the container. */
/* DLX relocs */
BFD_RELOC_DLX_JMP26,
+/* Renesas M16C/M32C Relocations. */
+ BFD_RELOC_M16C_8_PCREL8,
+ BFD_RELOC_M16C_16_PCREL8,
+ BFD_RELOC_M16C_8_PCREL16,
+ BFD_RELOC_M16C_8_ELABEL24,
+ BFD_RELOC_M16C_8_ABS16,
+ BFD_RELOC_M16C_16_ABS16,
+ BFD_RELOC_M16C_16_ABS24,
+ BFD_RELOC_M16C_16_ABS32,
+ BFD_RELOC_M16C_24_ABS16,
+ BFD_RELOC_M16C_24_ABS24,
+ BFD_RELOC_M16C_24_ABS32,
+ BFD_RELOC_M16C_32_ABS16,
+ BFD_RELOC_M16C_32_ABS24,
+ BFD_RELOC_M16C_32_ABS32,
+ BFD_RELOC_M16C_40_ABS16,
+ BFD_RELOC_M16C_40_ABS24,
+ BFD_RELOC_M16C_40_ABS32,
+
/* Renesas M32R (formerly Mitsubishi M32R) relocs.
This is a 24 bit absolute address. */
BFD_RELOC_M32R_24,
@@ -3802,6 +3821,21 @@ This is the 5 bits of a value. */
BFD_RELOC_VAX_JMP_SLOT,
BFD_RELOC_VAX_RELATIVE,
+/* Morpho MS1 - 16 bit immediate relocation. */
+ BFD_RELOC_MS1_PC16,
+
+/* Morpho MS1 - Hi 16 bits of an address. */
+ BFD_RELOC_MS1_HI16,
+
+/* Morpho MS1 - Low 16 bits of an address. */
+ BFD_RELOC_MS1_LO16,
+
+/* Morpho MS1 - Used to tell the linker which vtable entries are used. */
+ BFD_RELOC_MS1_GNU_VTINHERIT,
+
+/* Morpho MS1 - Used to tell the linker which vtable entries are used. */
+ BFD_RELOC_MS1_GNU_VTENTRY,
+
/* msp430 specific relocation codes */
BFD_RELOC_MSP430_10_PCREL,
BFD_RELOC_MSP430_16_PCREL,
diff --git a/bfd/config.bfd b/bfd/config.bfd
index 6cd28f3..ba7676e 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -177,9 +177,6 @@ case "${targ}" in
;;
#endif /* BFD64 */
- m32c-*-elf)
- targ_defvec=bfd_elf32_m32c_vec
- ;;
am33_2.0-*-linux*)
targ_defvec=bfd_elf32_am33lin_vec
;;
@@ -665,6 +662,10 @@ case "${targ}" in
targ_defvec=bfd_elf32_iq2000_vec
;;
+ m32c-*-elf)
+ targ_defvec=bfd_elf32_m32c_vec
+ ;;
+
m32r*le-*-linux*)
targ_defvec=bfd_elf32_m32rlelin_vec
targ_selvecs="bfd_elf32_m32rlin_vec bfd_elf32_m32rlelin_vec"
diff --git a/bfd/configure b/bfd/configure
index b30121c..dc3ab6e 100755
--- a/bfd/configure
+++ b/bfd/configure
@@ -12939,7 +12939,6 @@ do
# This list is alphabetized to make it easy to compare
# with the two vector lists in targets.c. For the same reason,
# use one entry per line, even though this leads to long lines.
- bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;;
a29kcoff_big_vec) tb="$tb coff-a29k.lo cofflink.lo" ;;
a_out_adobe_vec) tb="$tb aout-adobe.lo aout32.lo" ;;
aix5coff64_vec) tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
@@ -13004,6 +13003,7 @@ do
tb="$tb elf32-arm.lo elf32.lo $elf" ;;
bfd_elf32_littlearm_vec) tb="$tb elf32-arm.lo elf32.lo $elf" ;;
bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;;
+ bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;;
bfd_elf32_m32r_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
bfd_elf32_m32rle_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
bfd_elf32_m32rlin_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
diff --git a/bfd/configure.in b/bfd/configure.in
index 3949e3a..8853151 100644
--- a/bfd/configure.in
+++ b/bfd/configure.in
@@ -560,7 +560,6 @@ do
# This list is alphabetized to make it easy to compare
# with the two vector lists in targets.c. For the same reason,
# use one entry per line, even though this leads to long lines.
- bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;;
a29kcoff_big_vec) tb="$tb coff-a29k.lo cofflink.lo" ;;
a_out_adobe_vec) tb="$tb aout-adobe.lo aout32.lo" ;;
aix5coff64_vec) tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;;
@@ -625,6 +624,7 @@ do
tb="$tb elf32-arm.lo elf32.lo $elf" ;;
bfd_elf32_littlearm_vec) tb="$tb elf32-arm.lo elf32.lo $elf" ;;
bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;;
+ bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;;
bfd_elf32_m32r_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
bfd_elf32_m32rle_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
bfd_elf32_m32rlin_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 723d9be..2a83aae 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1338,6 +1338,23 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_DLX_HI16_S",
"BFD_RELOC_DLX_LO16",
"BFD_RELOC_DLX_JMP26",
+ "BFD_RELOC_M16C_8_PCREL8",
+ "BFD_RELOC_M16C_16_PCREL8",
+ "BFD_RELOC_M16C_8_PCREL16",
+ "BFD_RELOC_M16C_8_ELABEL24",
+ "BFD_RELOC_M16C_8_ABS16",
+ "BFD_RELOC_M16C_16_ABS16",
+ "BFD_RELOC_M16C_16_ABS24",
+ "BFD_RELOC_M16C_16_ABS32",
+ "BFD_RELOC_M16C_24_ABS16",
+ "BFD_RELOC_M16C_24_ABS24",
+ "BFD_RELOC_M16C_24_ABS32",
+ "BFD_RELOC_M16C_32_ABS16",
+ "BFD_RELOC_M16C_32_ABS24",
+ "BFD_RELOC_M16C_32_ABS32",
+ "BFD_RELOC_M16C_40_ABS16",
+ "BFD_RELOC_M16C_40_ABS24",
+ "BFD_RELOC_M16C_40_ABS32",
"BFD_RELOC_M32R_24",
"BFD_RELOC_M32R_10_PCREL",
"BFD_RELOC_M32R_18_PCREL",
@@ -1729,6 +1746,11 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_VAX_GLOB_DAT",
"BFD_RELOC_VAX_JMP_SLOT",
"BFD_RELOC_VAX_RELATIVE",
+ "BFD_RELOC_MS1_PC16",
+ "BFD_RELOC_MS1_HI16",
+ "BFD_RELOC_MS1_LO16",
+ "BFD_RELOC_MS1_GNU_VTINHERIT",
+ "BFD_RELOC_MS1_GNU_VTENTRY",
"BFD_RELOC_MSP430_10_PCREL",
"BFD_RELOC_MSP430_16_PCREL",
"BFD_RELOC_MSP430_16",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index 9d10d25..fb8a9db 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -3069,6 +3069,43 @@ ENUMDOC
DLX relocs
ENUM
+ BFD_RELOC_M16C_8_PCREL8
+ENUMX
+ BFD_RELOC_M16C_16_PCREL8
+ENUMX
+ BFD_RELOC_M16C_8_PCREL16
+ENUMX
+ BFD_RELOC_M16C_8_ELABEL24
+ENUMX
+ BFD_RELOC_M16C_8_ABS16
+ENUMX
+ BFD_RELOC_M16C_16_ABS16
+ENUMX
+ BFD_RELOC_M16C_16_ABS24
+ENUMX
+ BFD_RELOC_M16C_16_ABS32
+ENUMX
+ BFD_RELOC_M16C_24_ABS16
+ENUMX
+ BFD_RELOC_M16C_24_ABS24
+ENUMX
+ BFD_RELOC_M16C_24_ABS32
+ENUMX
+ BFD_RELOC_M16C_32_ABS16
+ENUMX
+ BFD_RELOC_M16C_32_ABS24
+ENUMX
+ BFD_RELOC_M16C_32_ABS32
+ENUMX
+ BFD_RELOC_M16C_40_ABS16
+ENUMX
+ BFD_RELOC_M16C_40_ABS24
+ENUMX
+ BFD_RELOC_M16C_40_ABS32
+ENUMDOC
+ Renesas M16C/M32C Relocations.
+
+ENUM
BFD_RELOC_M32R_24
ENUMDOC
Renesas M32R (formerly Mitsubishi M32R) relocs.
@@ -4044,7 +4081,7 @@ ENUMX
ENUMDOC
NS CR16C Relocations.
-ENUM
+ENUM
BFD_RELOC_CRX_REL4
ENUMX
BFD_RELOC_CRX_REL8
@@ -4257,6 +4294,27 @@ ENUMDOC
Relocations used by VAX ELF.
ENUM
+ BFD_RELOC_MS1_PC16
+ENUMDOC
+ Morpho MS1 - 16 bit immediate relocation.
+ENUM
+ BFD_RELOC_MS1_HI16
+ENUMDOC
+ Morpho MS1 - Hi 16 bits of an address.
+ENUM
+ BFD_RELOC_MS1_LO16
+ENUMDOC
+ Morpho MS1 - Low 16 bits of an address.
+ENUM
+ BFD_RELOC_MS1_GNU_VTINHERIT
+ENUMDOC
+ Morpho MS1 - Used to tell the linker which vtable entries are used.
+ENUM
+ BFD_RELOC_MS1_GNU_VTENTRY
+ENUMDOC
+ Morpho MS1 - Used to tell the linker which vtable entries are used.
+
+ENUM
BFD_RELOC_MSP430_10_PCREL
ENUMX
BFD_RELOC_MSP430_16_PCREL
diff --git a/bfd/targets.c b/bfd/targets.c
index 6d05dc8..355ac6a 100644
--- a/bfd/targets.c
+++ b/bfd/targets.c
@@ -596,6 +596,7 @@ extern const bfd_target bfd_elf32_mcore_big_vec;
extern const bfd_target bfd_elf32_mcore_little_vec;
extern const bfd_target bfd_elf32_mn10200_vec;
extern const bfd_target bfd_elf32_mn10300_vec;
+extern const bfd_target bfd_elf32_ms1_vec;
extern const bfd_target bfd_elf32_msp430_vec;
extern const bfd_target bfd_elf32_nbigmips_vec;
extern const bfd_target bfd_elf32_nlittlemips_vec;
@@ -792,7 +793,6 @@ extern const bfd_target sco5_core_vec;
extern const bfd_target trad_core_vec;
extern const bfd_target bfd_elf32_am33lin_vec;
-extern const bfd_target bfd_elf32_ms1_vec;
static const bfd_target * const _bfd_target_vector[] = {
#ifdef SELECT_VECS
@@ -903,6 +903,7 @@ static const bfd_target * const _bfd_target_vector[] = {
&bfd_elf32_mcore_little_vec,
&bfd_elf32_mn10200_vec,
&bfd_elf32_mn10300_vec,
+ &bfd_elf32_ms1_vec,
&bfd_elf32_msp430_vec,
#ifdef BFD64
&bfd_elf32_nbigmips_vec,
@@ -1125,7 +1126,6 @@ static const bfd_target * const _bfd_target_vector[] = {
&we32kcoff_vec,
&z8kcoff_vec,
&bfd_elf32_am33lin_vec,
- &bfd_elf32_ms1_vec,
#endif /* not SELECT_VECS */
/* Always support S-records, for convenience. */
diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu
index 7c7dca1..095e7cd 100644
--- a/cpu/m32c.cpu
+++ b/cpu/m32c.cpu
@@ -195,6 +195,7 @@
(dnf f-16-1 "opcode" (all-isas) 16 1)
(dnf f-16-2 "opcode" (all-isas) 16 2)
(dnf f-16-4 "opcode" (all-isas) 16 4)
+(dnf f-16-8 "opcode" (all-isas) 16 8)
(dnf f-18-1 "opcode" (all-isas) 18 1)
(dnf f-18-2 "opcode" (all-isas) 18 2)
(dnf f-18-3 "opcode" (all-isas) 18 3)
@@ -204,6 +205,8 @@
(dnf f-20-4 "opcode" (all-isas) 20 4)
(dnf f-21-3 "opcode" (all-isas) 21 3)
(dnf f-24-2 "opcode" (all-isas) 24 2)
+(dnf f-24-8 "opcode" (all-isas) 24 8)
+(dnf f-32-16 "opcode" (all-isas) 32 16)
;-------------------------------------------------------------
; Registers
@@ -554,6 +557,14 @@
(and UHI (srl UHI value 8) #x00ff)
(and UHI (sll UHI value 8) #xff00))) ; extract
)
+(df f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT
+ ((value pc) (or SI
+ (or (srl value 16) (and value #xff00))
+ (sll (and value #xff) 16)))
+ ((value pc) (or SI
+ (or (srl value 16) (and value #xff00))
+ (sll (and value #xff) 16)))
+ )
(dnmf f-dsp-16-u24 "24 bit unsigned" (all-isas) UINT
(f-dsp-16-u16 f-dsp-32-u8)
@@ -876,15 +887,16 @@
; Labels
;-------------------------------------------------------------
-(df f-lab-5-3 "3 bit pc relative signed offset" (PCREL-ADDR all-isas) 5 3 INT
+(df f-lab-5-3 "3 bit pc relative unsigned offset" (PCREL-ADDR all-isas) 5 3 UINT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
(dnmf f-lab32-jmp-s "unsigned 3 bit pc relative offset" (PCREL-ADDR all-isas) UINT
(f-2-2 f-7-1)
- (sequence () ; insert
- (set (ifield f-7-1) (and (sub (ifield f-lab32-jmp-s) pc) #x1))
- (set (ifield f-2-2) (srl (sub (ifield f-lab32-jmp-s) pc) 1))
+ (sequence ((SI val)) ; insert
+ (set val (sub (sub (ifield f-lab32-jmp-s) pc) 2))
+ (set (ifield f-7-1) (and val #x1))
+ (set (ifield f-2-2) (srl val 1))
)
(sequence () ; extract
(set (ifield f-lab32-jmp-s) (add pc (add (or (sll (ifield f-2-2) 1)
@@ -1744,6 +1756,10 @@
h-sint DFLT f-dsp-8-s8
((parse "signed8")) () ()
)
+(define-full-operand Dsp-8-u24 "unsigned 24 bit displacement at offset 8 bits" (all-isas)
+ h-uint DFLT f-dsp-8-u24
+ ((parse "unsigned24")) () ()
+)
(define-full-operand Dsp-10-u6 "unsigned 6 bit displacement at offset 10 bits" (all-isas)
h-uint DFLT f-dsp-10-u6
((parse "unsigned6")) () ()
@@ -1825,7 +1841,7 @@
((parse "unsigned8")) () ()
)
(define-full-operand Dsp-40-s8 "signed 8 bit displacement at offset 40 bits" (all-isas)
- h-uint DFLT f-dsp-40-s8
+ h-sint DFLT f-dsp-40-s8
((parse "signed8")) () ()
)
(define-full-operand Dsp-40-u16 "unsigned 16 bit displacement at offset 40 bits" (all-isas)
@@ -1833,7 +1849,7 @@
((parse "unsigned16")) () ()
)
(define-full-operand Dsp-40-s16 "signed 16 bit displacement at offset 40 bits" (all-isas)
- h-uint DFLT f-dsp-40-s16
+ h-sint DFLT f-dsp-40-s16
((parse "signed16")) () ()
)
(define-full-operand Dsp-40-u24 "unsigned 24 bit displacement at offset 40 bits" (all-isas)
@@ -1845,7 +1861,7 @@
((parse "unsigned8")) () ()
)
(define-full-operand Dsp-48-s8 "signed 8 bit displacement at offset 48 bits" (all-isas)
- h-uint DFLT f-dsp-48-s8
+ h-sint DFLT f-dsp-48-s8
((parse "signed8")) () ()
)
(define-full-operand Dsp-48-u16 "unsigned 16 bit displacement at offset 48 bits" (all-isas)
@@ -1853,7 +1869,7 @@
((parse "unsigned16")) () ()
)
(define-full-operand Dsp-48-s16 "signed 16 bit displacement at offset 48 bits" (all-isas)
- h-uint DFLT f-dsp-48-s16
+ h-sint DFLT f-dsp-48-s16
((parse "signed16")) () ()
)
(define-full-operand Dsp-48-u24 "unsigned 24 bit displacement at offset 48 bits" (all-isas)
@@ -1886,7 +1902,7 @@
() () ()
)
(define-full-operand Imm-13-u3 "signed 3 bit immediate at offset 13 bits" (all-isas)
- h-uint DFLT f-imm-13-u3
+ h-sint DFLT f-imm-13-u3
((parse "signed4")) () ()
)
(define-full-operand Imm-20-s4 "signed 4 bit immediate at offset 20 bits" (all-isas)
@@ -1994,7 +2010,7 @@
((parse "unsigned_bitbase8") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase16-16-s8 "signed bit,base:8 at offset 16for m16c" (m16c-isa)
- h-uint DFLT f-dsp-16-s8
+ h-sint DFLT f-dsp-16-s8
((parse "signed_bitbase8") (print "signed_bitbase")) () ()
)
(define-full-operand BitBase16-16-u16 "unsigned bit,base:16 at offset 16 for m16c" (m16c-isa)
@@ -2002,7 +2018,7 @@
((parse "unsigned_bitbase16") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase16-8-u11-S "signed bit,base:11 at offset 16 for m16c" (m16c-isa)
- h-sint DFLT f-bitbase16-u11-S
+ h-uint DFLT f-bitbase16-u11-S
((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
)
@@ -2050,12 +2066,18 @@
; Labels
;-------------------------------------------------------------
-(dnop Lab-5-3 "3 bit label" (all-isas) h-iaddr f-lab-5-3)
-(dnop Lab32-jmp-s "3 bit label" (all-isas) h-iaddr f-lab32-jmp-s)
-(dnop Lab-8-8 "8 bit label" (all-isas) h-iaddr f-lab-8-8)
-(dnop Lab-8-16 "16 bit label" (all-isas) h-iaddr f-lab-8-16)
+(define-full-operand Lab-5-3 "3 bit label" (all-isas RELAX)
+ h-iaddr DFLT f-lab-5-3
+ ((parse "lab_5_3")) () () )
+
+(define-full-operand Lab32-jmp-s "3 bit label" (all-isas RELAX)
+ h-iaddr DFLT f-lab32-jmp-s
+ ((parse "lab_5_3")) () () )
+
+(dnop Lab-8-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-8-8)
+(dnop Lab-8-16 "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16)
(dnop Lab-8-24 "24 bit label" (all-isas) h-iaddr f-lab-8-24)
-(dnop Lab-16-8 "8 bit label" (all-isas) h-iaddr f-lab-16-8)
+(dnop Lab-16-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-16-8)
(dnop Lab-24-8 "8 bit label" (all-isas) h-iaddr f-lab-24-8)
(dnop Lab-32-8 "8 bit label" (all-isas) h-iaddr f-lab-32-8)
(dnop Lab-40-8 "8 bit label" (all-isas) h-iaddr f-lab-40-8)
@@ -7957,7 +7979,7 @@
(dni jcnd16-5
"jCnd label"
- ((machine 16))
+ (RELAXABLE (machine 16))
"j$cond16j5 ${Lab-8-8}"
(+ (f-0-4 #x6) (f-4-1 1) cond16j5 Lab-8-8)
(jcnd16-sem cond16j5 Lab-8-8)
@@ -7966,7 +7988,7 @@
(dni jcnd16
"jCnd label"
- ((machine 16))
+ (RELAXABLE (machine 16))
"j$cond16j ${Lab-16-8}"
(+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xC) cond16j Lab-16-8)
(jcnd16-sem cond16j Lab-16-8)
@@ -7975,7 +7997,7 @@
(dni jcnd32
"jCnd label"
- ((machine 32))
+ (RELAXABLE (machine 32))
"j$cond32j ${Lab-8-8}"
(+ (f-0-1 1) (f-4-3 5) cond32j Lab-8-8)
(jcnd32-sem cond32j Lab-8-8)
@@ -7987,19 +8009,19 @@
;-------------------------------------------------------------
; jmp.s label3 (m16 #1)
-(dni jmp16.s "jmp.s Lab-5-3" ((machine 16))
+(dni jmp16.s "jmp.s Lab-5-3" (RELAXABLE (machine 16))
("jmp.s ${Lab-5-3}")
(+ (f-0-4 6) (f-4-1 0) Lab-5-3)
(sequence () (set pc Lab-5-3))
())
; jmp.b label8 (m16 #2)
-(dni jmp16.b "jmp.b Lab-8-8" ((machine 16))
+(dni jmp16.b "jmp.b Lab-8-8" (RELAXABLE (machine 16))
("jmp.b ${Lab-8-8}")
(+ (f-0-4 #xF) (f-4-4 #xE) Lab-8-8)
(sequence () (set pc Lab-8-8))
())
; jmp.w label16 (m16 #3)
-(dni jmp16.w "jmp.w Lab-8-16" ((machine 16))
+(dni jmp16.w "jmp.w Lab-8-16" (RELAXABLE (machine 16))
("jmp.w ${Lab-8-16}")
(+ (f-0-4 #xF) (f-4-4 4) Lab-8-16)
(sequence () (set pc Lab-8-16))
@@ -8032,20 +8054,20 @@
; jmp.s label3 (m32 #1)
(dni jmp32.s
"jmp.s label"
- ((machine 32))
+ (RELAXABLE (machine 32))
"jmp.s ${Lab32-jmp-s}"
(+ (f-0-2 1) (f-4-3 5) Lab32-jmp-s)
(set pc Lab32-jmp-s)
()
)
; jmp.b label8 (m32 #2)
-(dni jmp32.b "jmp.b Lab-8-8" ((machine 32))
+(dni jmp32.b "jmp.b Lab-8-8" (RELAXABLE (machine 32))
("jmp.b ${Lab-8-8}")
(+ (f-0-4 #xB) (f-4-4 #xB) Lab-8-8)
(set pc Lab-8-8)
())
; jmp.w label16 (m32 #3)
-(dni jmp32.w "jmp.w Lab-8-16" ((machine 32))
+(dni jmp32.w "jmp.w Lab-8-16" (RELAXABLE (machine 32))
("jmp.w ${Lab-8-16}")
(+ (f-0-4 #xC) (f-4-4 #xE) Lab-8-16)
(set pc Lab-8-16)
@@ -8089,7 +8111,7 @@
)
; jsr.w label16 (m16 #1)
-(dni jsr16.w "jsr.w Lab-8-16" ((machine 16))
+(dni jsr16.w "jsr.w Lab-8-16" (RELAXABLE (machine 16))
("jsr.w ${Lab-8-16}")
(+ (f-0-4 #xF) (f-4-4 5) Lab-8-16)
(jsr16-sem 3 Lab-8-16)
@@ -8145,7 +8167,7 @@
(jsr32-sem 6 dst32-16-24-Unprefixed-SI)
())
; jsr.w label16 (m32 #1)
-(dni jsr32.w "jsr.w label" ((machine 32))
+(dni jsr32.w "jsr.w label" (RELAXABLE (machine 32))
("jsr.w ${Lab-8-16}")
(+ (f-0-4 #xC) (f-4-4 #xF) Lab-8-16)
(jsr32-sem 3 Lab-8-16)
@@ -8531,11 +8553,6 @@
(binary-arith-imm-dst mov G (f-0-4 7) (f-4-3 2) (f-8-4 #xC) #x9 #x2 #xF mov-sem)
; mov.L:G #imm32,dst (m32 #2)
(binary-arith32-imm-dst-defn SI SI .l 0 mov G #xB #x3 #x1 mov-sem)
-; mov.size:Q #imm4,dst (m16 #2 m32 #3)
-(binary-arith16-imm4-dst-defn QI .b 0 0 mov (f-0-4 #xD) (f-4-3 4) mov-sem)
-(binary-arith16-imm4-dst-defn QI .w 0 1 mov (f-0-4 #xD) (f-4-3 4) mov-sem)
-(binary-arith32-imm4-dst-defn QI .b 1 0 mov #x7 #x2 mov-sem)
-(binary-arith32-imm4-dst-defn HI .w 1 1 mov #x7 #x2 mov-sem)
; mov.BW:S #imm,dst2 (m32 #4)
(binary-arith32-s-imm-dst QI .b 0 mov #x0 #x2 mov-sem)
(binary-arith32-s-imm-dst HI .w 1 mov #x0 #x2 mov-sem)
@@ -8558,8 +8575,14 @@
)
(mov32-wl-s-defn HI w #x9 Imm-8-HI a0 #xC)
(mov32-wl-s-defn HI w #x9 Imm-8-HI a1 #xD)
-(mov32-wl-s-defn SI l #xB Dsp-16-u24 a0 #xC)
-(mov32-wl-s-defn SI l #xB Dsp-16-u24 a1 #xD)
+(mov32-wl-s-defn SI l #xB Dsp-8-u24 a0 #xC)
+(mov32-wl-s-defn SI l #xB Dsp-8-u24 a1 #xD)
+
+; mov.size:Q #imm4,dst (m16 #2 m32 #3)
+(binary-arith16-imm4-dst-defn QI .b 0 0 mov (f-0-4 #xD) (f-4-3 4) mov-sem)
+(binary-arith16-imm4-dst-defn QI .w 0 1 mov (f-0-4 #xD) (f-4-3 4) mov-sem)
+(binary-arith32-imm4-dst-defn QI .b 1 0 mov #x7 #x2 mov-sem)
+(binary-arith32-imm4-dst-defn HI .w 1 1 mov #x7 #x2 mov-sem)
; mov.BW:Z #0,dst (m16 #5 m32 #6)
(dni mov16.b-Z-imm8-dst3
diff --git a/cpu/m32c.opc b/cpu/m32c.opc
index 3824118..7caf21d 100644
--- a/cpu/m32c.opc
+++ b/cpu/m32c.opc
@@ -33,8 +33,7 @@
<arch>-opc.c additions use: "-- opc.c"
<arch>-asm.c additions use: "-- asm.c"
<arch>-dis.c additions use: "-- dis.c"
- <arch>-ibd.h additions use: "-- ibd.h"
-*/
+ <arch>-ibd.h additions use: "-- ibd.h". */
/* -- opc.h */
@@ -76,7 +75,7 @@ m32c_asm_hash (const char *mnem)
}
/* -- asm.c */
-#include <ctype.h>
+#include "safe-ctype.h"
#define MACH_M32C 5 /* Must match md_begin. */
@@ -104,25 +103,40 @@ m32c_cgen_isa_register (const char **strp)
return 0;
}
+#define PARSE_UNSIGNED \
+ do \
+ { \
+ /* Don't successfully parse literals beginning with '['. */ \
+ if (**strp == '[') \
+ return "Invalid literal"; /* Anything -- will not be seen. */ \
+ \
+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);\
+ if (errmsg) \
+ return errmsg; \
+ } \
+ while (0)
+
+#define PARSE_SIGNED \
+ do \
+ { \
+ /* Don't successfully parse literals beginning with '['. */ \
+ if (**strp == '[') \
+ return "Invalid literal"; /* Anything -- will not be seen. */ \
+ \
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); \
+ if (errmsg) \
+ return errmsg; \
+ } \
+ while (0)
+
static const char *
parse_unsigned6 (CGEN_CPU_DESC cd, const char **strp,
int opindex, unsigned long *valuep)
{
const char *errmsg = 0;
unsigned long value;
- long have_zero = 0;
-
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
- if (strncmp (*strp, "0x0", 3) == 0
- || (**strp == '0' && *(*strp + 1) != 'x'))
- have_zero = 1;
-
- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
- if (errmsg)
- return errmsg;
+ PARSE_UNSIGNED;
if (value > 0x3f)
return _("imm:6 immediate is out of range");
@@ -139,17 +153,11 @@ parse_unsigned8 (CGEN_CPU_DESC cd, const char **strp,
unsigned long value;
long have_zero = 0;
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-
if (strncmp (*strp, "0x0", 3) == 0
|| (**strp == '0' && *(*strp + 1) != 'x'))
have_zero = 1;
- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
- if (errmsg)
- return errmsg;
+ PARSE_UNSIGNED;
if (value > 0xff)
return _("dsp:8 immediate is out of range");
@@ -169,18 +177,12 @@ parse_signed4 (CGEN_CPU_DESC cd, const char **strp,
const char *errmsg = 0;
signed long value;
long have_zero = 0;
-
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
if (strncmp (*strp, "0x0", 3) == 0
|| (**strp == '0' && *(*strp + 1) != 'x'))
have_zero = 1;
- errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
- if (errmsg)
- return errmsg;
+ PARSE_SIGNED;
if (value < -8 || value > 7)
return _("Immediate is out of range -8 to 7");
@@ -200,13 +202,7 @@ parse_signed8 (CGEN_CPU_DESC cd, const char **strp,
const char *errmsg = 0;
signed long value;
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-
- errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
- if (errmsg)
- return errmsg;
+ PARSE_SIGNED;
if (value <= 255 && value > 127)
value -= 0x100;
@@ -226,13 +222,13 @@ parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp,
unsigned long value;
long have_zero = 0;
- /* Don't successfully parse literals beginning with '[' */
+ /* Don't successfully parse literals beginning with '['. */
if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
+ return "Invalid literal"; /* Anything -- will not be seen. */
- /* Don't successfully parse register names */
+ /* Don't successfully parse register names. */
if (m32c_cgen_isa_register (strp))
- return "Invalid literal"; /* anything -- will not be seen */
+ return "Invalid literal"; /* Anything -- will not be seen. */
if (strncmp (*strp, "0x0", 3) == 0
|| (**strp == '0' && *(*strp + 1) != 'x'))
@@ -262,14 +258,8 @@ parse_signed16 (CGEN_CPU_DESC cd, const char **strp,
{
const char *errmsg = 0;
signed long value;
-
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
- errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
- if (errmsg)
- return errmsg;
+ PARSE_SIGNED;
if (value <= 65535 && value > 32767)
value -= 0x10000;
@@ -288,13 +278,13 @@ parse_unsigned20 (CGEN_CPU_DESC cd, const char **strp,
const char *errmsg = 0;
unsigned long value;
- /* Don't successfully parse literals beginning with '[' */
+ /* Don't successfully parse literals beginning with '['. */
if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
+ return "Invalid literal"; /* Anything -- will not be seen. */
- /* Don't successfully parse register names */
+ /* Don't successfully parse register names. */
if (m32c_cgen_isa_register (strp))
- return "Invalid literal"; /* anything -- will not be seen */
+ return "Invalid literal"; /* Anything -- will not be seen. */
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
if (errmsg)
@@ -314,13 +304,13 @@ parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp,
const char *errmsg = 0;
unsigned long value;
- /* Don't successfully parse literals beginning with '[' */
+ /* Don't successfully parse literals beginning with '['. */
if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
+ return "Invalid literal"; /* Anything -- will not be seen. */
- /* Don't successfully parse register names */
+ /* Don't successfully parse register names. */
if (m32c_cgen_isa_register (strp))
- return "Invalid literal"; /* anything -- will not be seen */
+ return "Invalid literal"; /* Anything -- will not be seen. */
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
if (errmsg)
@@ -335,21 +325,11 @@ parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp,
static const char *
parse_signed32 (CGEN_CPU_DESC cd, const char **strp,
- int opindex, signed long *valuep)
+ int opindex, signed long *valuep)
{
const char *errmsg = 0;
signed long value;
-#if 0
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-
- /* Don't successfully parse register names */
- if (m32c_cgen_isa_register (strp))
- return "Invalid literal"; /* anything -- will not be seen */
-#endif
-
errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
if (errmsg)
return errmsg;
@@ -364,18 +344,8 @@ parse_imm1_S (CGEN_CPU_DESC cd, const char **strp,
{
const char *errmsg = 0;
signed long value;
-
-#if 0
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
- /* Don't successfully parse register names */
- if (m32c_cgen_isa_register (strp))
- return "Invalid literal"; /* anything -- will not be seen */
-#endif
-
- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
if (errmsg)
return errmsg;
@@ -393,17 +363,7 @@ parse_imm3_S (CGEN_CPU_DESC cd, const char **strp,
const char *errmsg = 0;
signed long value;
-#if 0
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-
- /* Don't successfully parse register names */
- if (m32c_cgen_isa_register (strp))
- return "Invalid literal"; /* anything -- will not be seen */
-#endif
-
- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
if (errmsg)
return errmsg;
@@ -415,18 +375,48 @@ parse_imm3_S (CGEN_CPU_DESC cd, const char **strp,
}
static const char *
+parse_lab_5_3 (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex ATTRIBUTE_UNUSED,
+ int opinfo,
+ enum cgen_parse_operand_result *type_addr,
+ unsigned long *valuep)
+{
+ const char *errmsg = 0;
+ unsigned long value;
+ enum cgen_parse_operand_result op_res;
+
+ errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_5_3,
+ opinfo, & op_res, & value);
+
+ if (type_addr)
+ *type_addr = op_res;
+
+ if (op_res == CGEN_PARSE_OPERAND_ADDRESS)
+ {
+ /* This is a hack; the field cannot handle near-zero signed
+ offsets that CGEN wants to put in to indicate an "empty"
+ operand at first. */
+ *valuep = 2;
+ return 0;
+ }
+ if (errmsg)
+ return errmsg;
+
+ if (value < 2 || value > 9)
+ return _("immediate is out of range 2-9");
+
+ *valuep = value;
+ return 0;
+}
+
+static const char *
parse_Bitno16R (CGEN_CPU_DESC cd, const char **strp,
int opindex, unsigned long *valuep)
{
const char *errmsg = 0;
unsigned long value;
-#if 0
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-#endif
-
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
if (errmsg)
return errmsg;
@@ -449,12 +439,6 @@ parse_unsigned_bitbase (CGEN_CPU_DESC cd, const char **strp,
const char *newp = *strp;
unsigned long long bitbase;
-#if 0
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-#endif
-
errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit);
if (errmsg)
return errmsg;
@@ -467,7 +451,7 @@ parse_unsigned_bitbase (CGEN_CPU_DESC cd, const char **strp,
if (errmsg)
return errmsg;
- bitbase = (unsigned long long)bit + ((unsigned long long)base * 8);
+ bitbase = (unsigned long long) bit + ((unsigned long long) base * 8);
if (bitbase >= (1ull << bits))
return _("bit,base is out of range");
@@ -489,12 +473,6 @@ parse_signed_bitbase (CGEN_CPU_DESC cd, const char **strp,
long long bitbase;
long long limit;
-#if 0
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-#endif
-
errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit);
if (errmsg)
return errmsg;
@@ -575,21 +553,22 @@ parse_signed_bitbase19 (CGEN_CPU_DESC cd, const char **strp,
}
/* Parse the suffix as :<char> or as nothing followed by a whitespace. */
+
static const char *
parse_suffix (const char **strp, char suffix)
{
const char *newp = *strp;
- if (**strp == ':' && tolower (*(*strp + 1)) == suffix)
+ if (**strp == ':' && TOLOWER (*(*strp + 1)) == suffix)
newp = *strp + 2;
- if (isspace (*newp))
+ if (ISSPACE (*newp))
{
*strp = newp;
return 0;
}
- return "Invalid suffix"; /* anything -- will not be seen */
+ return "Invalid suffix"; /* Anything -- will not be seen. */
}
static const char *
@@ -621,6 +600,7 @@ parse_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp,
}
/* Parse an empty suffix. Fail if the next char is ':'. */
+
static const char *
parse_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp,
int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED)
@@ -639,16 +619,16 @@ parse_r0l_r0h (CGEN_CPU_DESC cd, const char **strp,
signed long junk;
const char *newp = *strp;
- /* Parse r0[hl] */
+ /* Parse r0[hl]. */
errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0l_r0h, & value);
if (errmsg)
return errmsg;
if (*newp != ',')
- return "not a valid r0l/r0h pair";
+ return _("not a valid r0l/r0h pair");
++newp;
- /* Parse the second register in the pair */
+ /* Parse the second register in the pair. */
if (value == 0) /* r0l */
errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0h, & junk);
else
@@ -661,7 +641,8 @@ parse_r0l_r0h (CGEN_CPU_DESC cd, const char **strp,
return 0;
}
-/* Accept .b or .w in any case */
+/* Accept .b or .w in any case. */
+
static const char *
parse_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp,
int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED)
@@ -671,196 +652,14 @@ parse_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp,
|| *(*strp + 1) == 'w' || *(*strp + 1) == 'W'))
{
*strp += 2;
- return 0;
+ return NULL;
}
- return "Invalid size specifier";
+
+ return _("Invalid size specifier");
}
-/* static const char * parse_abs (CGEN_CPU_DESC, const char **, int, */
-/* unsigned long *, unsigned long); */
-/* static const char * parse_abs16 (CGEN_CPU_DESC, const char **, int, */
-/* int ATTRIBUTE_UNUSED, */
-/* enum cgen_parse_operand_result * ATTRIBUTE_UNUSED, */
-/* unsigned long * ); */
-/* static const char * parse_abs24 (CGEN_CPU_DESC, const char **, int, */
-/* int ATTRIBUTE_UNUSED, */
-/* enum cgen_parse_operand_result * ATTRIBUTE_UNUSED, */
-/* unsigned long *); */
-
-/* /\* Parse absolute *\/ */
-
-/* static const char * */
-/* parse_abs16 (CGEN_CPU_DESC cd, const char **strp, int opindex, */
-/* int reloc ATTRIBUTE_UNUSED, */
-/* enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED, */
-/* unsigned long *valuep) */
-/* { */
-/* return parse_abs (cd, strp, opindex, valuep, 16); */
-/* } */
-
-/* static const char * */
-/* parse_abs24 (CGEN_CPU_DESC cd, const char **strp, int opindex, */
-/* int reloc ATTRIBUTE_UNUSED, */
-/* enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED, */
-/* unsigned long *valuep) */
-/* { */
-/* return parse_abs (cd, strp, opindex, valuep, 24); */
-/* } */
-
-/* static const char * */
-/* parse_abs (CGEN_CPU_DESC cd, const char **strp, int opindex, */
-/* unsigned long *valuep, */
-/* unsigned long length) */
-/* { */
-/* const char *errmsg = 0; */
-/* const char *op; */
-/* int has_register = 0; */
-
-/* for (op = *strp; *op != '\0'; op++) */
-/* { */
-/* if (*op == '[') */
-/* { */
-/* has_register = 1; */
-/* break; */
-/* } */
-/* else if (*op == ',') */
-/* break; */
-/* } */
-
-/* if (has_register || m32c_cgen_isa_register (strp)) */
-/* errmsg = _("immediate value cannot be register"); */
-/* else */
-/* { */
-/* enum cgen_parse_operand_result result_type; */
-/* bfd_vma value; */
-/* const char *errmsg; */
-
-/* errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, */
-/* &result_type, &value); */
-/* *valuep = value; */
-/* } */
-/* return errmsg; */
-/* } */
-/* /\* Handle signed/unsigned literal. *\/ */
-
-/* static const char * */
-/* parse_imm8 (cd, strp, opindex, valuep) */
-/* CGEN_CPU_DESC cd; */
-/* const char **strp; */
-/* int opindex; */
-/* unsigned long *valuep; */
-/* { */
-/* const char *errmsg = 0; */
-/* long value; */
-/* long have_zero = 0; */
-
-/* if (strncmp (*strp, "0x0", 3) == 0 */
-/* || (**strp == '0' && *(*strp + 1) != 'x')) */
-/* have_zero = 1; */
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */
-/* *valuep = value; */
-/* /\* If this field may require a relocation then use larger dsp16. *\/ */
-/* if (! have_zero && value == 0) */
-/* errmsg = _("immediate value may not fit in dsp8 field"); */
-
-/* return errmsg; */
-/* } */
-
-/* static const char * */
-/* parse_imm16 (cd, strp, opindex, valuep) */
-/* CGEN_CPU_DESC cd; */
-/* const char **strp; */
-/* int opindex; */
-/* unsigned long *valuep; */
-/* { */
-/* const char *errmsg; */
-/* long value; */
-
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */
-/* *valuep = value; */
-/* return errmsg; */
-/* } */
-
-/* static const char * */
-/* parse_imm24 (cd, strp, opindex, valuep) */
-/* CGEN_CPU_DESC cd; */
-/* const char **strp; */
-/* int opindex; */
-/* unsigned long *valuep; */
-/* { */
-/* const char *errmsg; */
-/* long value; */
-
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */
-/* *valuep = value; */
-/* return errmsg; */
-/* } */
-
-/* static const char * */
-/* parse_imm32 (cd, strp, opindex, valuep) */
-/* CGEN_CPU_DESC cd; */
-/* const char **strp; */
-/* int opindex; */
-/* unsigned long *valuep; */
-/* { */
-/* const char *errmsg; */
-/* long value; */
-
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */
-/* *valuep = value; */
-/* return errmsg; */
-/* } */
-
-/* /\* Handle bitfields. *\/ */
-
-/* static const char * */
-/* parse_boff8 (cd, strp, opindex, valuep) */
-/* CGEN_CPU_DESC cd; */
-/* const char **strp; */
-/* int opindex; */
-/* unsigned long *valuep; */
-/* { */
-/* const char *errmsg; */
-/* long bit_value, value; */
-
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & bit_value); */
-/* if (errmsg == 0) */
-/* { */
-/* *strp = *strp + 1; */
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */
-/* } */
-/* value = value * 8 + bit_value; */
-/* *valuep = value; */
-/* if (value > 0x100) */
-/* errmsg = _("Operand out of range. Must be between 0 and 255."); */
-/* return errmsg; */
-/* } */
-
-/* static const char * */
-/* parse_boff16 (cd, strp, opindex, valuep) */
-/* CGEN_CPU_DESC cd; */
-/* const char **strp; */
-/* int opindex; */
-/* unsigned long *valuep; */
-/* { */
-/* const char *errmsg; */
-/* long bit_value, value; */
-
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & bit_value); */
-/* if (errmsg == 0) */
-/* { */
-/* *strp = *strp + 1; */
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */
-/* } */
-/* value = value * 8 + bit_value; */
-/* *valuep = value; */
-/* if (value > 0x1000) */
-/* errmsg = _("Operand out of range. Must be between 0 and 65535."); */
-/* return errmsg; */
-/* } */
-
-
-/* Special check to ensure that instruction exists for given machine */
+/* Special check to ensure that instruction exists for given machine. */
+
int
m32c_cgen_insn_supported (CGEN_CPU_DESC cd,
const CGEN_INSN *insn)
@@ -868,7 +667,7 @@ m32c_cgen_insn_supported (CGEN_CPU_DESC cd,
int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
int isas = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ISA);
- /* If attributes are absent, assume no restriction. */
+ /* If attributes are absent, assume no restriction. */
if (machs == 0)
machs = ~0;
@@ -883,8 +682,7 @@ parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
const char **strp,
int opindex ATTRIBUTE_UNUSED,
unsigned long *valuep,
- int push
- )
+ int push)
{
const char *errmsg = 0;
int regno = 0;
@@ -940,23 +738,23 @@ parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
return errmsg;
}
-#define POP 0
+#define POP 0
#define PUSH 1
static const char *
parse_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- unsigned long *valuep)
+ const char **strp,
+ int opindex ATTRIBUTE_UNUSED,
+ unsigned long *valuep)
{
return parse_regset (cd, strp, opindex, valuep, POP);
}
static const char *
parse_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- unsigned long *valuep)
+ const char **strp,
+ int opindex ATTRIBUTE_UNUSED,
+ unsigned long *valuep)
{
return parse_regset (cd, strp, opindex, valuep, PUSH);
}
@@ -966,17 +764,19 @@ parse_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
#include "elf/m32c.h"
#include "elf-bfd.h"
-/* Always print the short insn format suffix as ':<char>' */
+/* Always print the short insn format suffix as ':<char>'. */
+
static void
-print_suffix (PTR dis_info, char suffix)
+print_suffix (void * dis_info, char suffix)
{
disassemble_info *info = dis_info;
+
(*info->fprintf_func) (info->stream, ":%c", suffix);
}
static void
print_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
@@ -988,7 +788,7 @@ print_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
static void
print_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
@@ -999,7 +799,7 @@ print_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
static void
print_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
@@ -1010,7 +810,7 @@ print_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
static void
print_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
@@ -1019,10 +819,11 @@ print_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
print_suffix (dis_info, 'z');
}
-/* Print the empty suffix */
+/* Print the empty suffix. */
+
static void
print_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info ATTRIBUTE_UNUSED,
+ void * dis_info ATTRIBUTE_UNUSED,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
@@ -1033,13 +834,14 @@ print_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
static void
print_r0l_r0h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = dis_info;
+
if (value == 0)
(*info->fprintf_func) (info->stream, "r0h,r0l");
else
@@ -1048,62 +850,65 @@ print_r0l_r0h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
static void
print_unsigned_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
unsigned long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = dis_info;
+
(*info->fprintf_func) (info->stream, "%ld,0x%lx", value & 0x7, value >> 3);
}
static void
print_signed_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
signed long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = dis_info;
+
(*info->fprintf_func) (info->stream, "%ld,%ld", value & 0x7, value >> 3);
}
static void
print_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
- /* Always print the size as '.w' */
+ /* Always print the size as '.w'. */
disassemble_info *info = dis_info;
+
(*info->fprintf_func) (info->stream, ".w");
}
-#define POP 0
+#define POP 0
#define PUSH 1
-static void print_pop_regset (CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int);
-static void print_push_regset (CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int);
+static void print_pop_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
+static void print_push_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
/* Print a set of registers, R0,R1,A0,A1,SB,FB. */
static void
print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
- long value,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED,
- int push)
+ void * dis_info,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED,
+ int push)
{
static char * m16c_register_names [] =
- {
- "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb"
- };
+ {
+ "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb"
+ };
disassemble_info *info = dis_info;
int mask;
int index = 0;
@@ -1138,38 +943,22 @@ print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
static void
print_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
- long value,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
+ void * dis_info,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
{
print_regset (cd, dis_info, value, attrs, pc, length, POP);
}
static void
print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
- long value,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
+ void * dis_info,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
{
print_regset (cd, dis_info, value, attrs, pc, length, PUSH);
}
-#if 0 /* not used? */
-static void
-print_boff (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
- long value,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = dis_info;
- if (value)
- info->fprintf_func (info->stream, "%d,%d", value % 16,
- (value / 16) * 2);
-}
-
-#endif /* not used? */
diff --git a/gas/config/tc-m32c.c b/gas/config/tc-m32c.c
index 8ee44f8..1a9ca40 100644
--- a/gas/config/tc-m32c.c
+++ b/gas/config/tc-m32c.c
@@ -156,7 +156,7 @@ md_begin (void)
gas_cgen_cpu_desc = m32c_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach,
CGEN_CPU_OPEN_ENDIAN,
CGEN_ENDIAN_BIG,
- CGEN_CPU_OPEN_ISAS, & m32c_isa,
+ CGEN_CPU_OPEN_ISAS, m32c_isa,
CGEN_CPU_OPEN_END);
m32c_cgen_init_asm (gas_cgen_cpu_desc);
@@ -757,6 +757,7 @@ md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED,
{ M32C_OPERAND_DSP_24_U24, BFD_RELOC_24, 3 },
{ M32C_OPERAND_DSP_32_U24, BFD_RELOC_24, 4 },
{ M32C_OPERAND_DSP_40_U24, BFD_RELOC_24, 5 },
+ { M32C_OPERAND_DSP_8_U24, BFD_RELOC_24, 1 },
/* Absolute relocs for 32-bit fields. */
{ M32C_OPERAND_IMM_16_SI, BFD_RELOC_32, 2 },
@@ -782,7 +783,7 @@ md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED,
fprintf
(stderr,
- "Error: tc-m32c.c:md_cgen_lookup_reloc Unimplemented relocation %d\n",
+ "Error: tc-m32c.c:md_cgen_lookup_reloc Unimplemented relocation for operand %d\n",
operand->type);
return BFD_RELOC_NONE;
@@ -1014,4 +1015,3 @@ m32c_is_colon_insn (char *start ATTRIBUTE_UNUSED)
return 0;
}
-
diff --git a/gas/configure.tgt b/gas/configure.tgt
index 095e3f1..0311d06 100644
--- a/gas/configure.tgt
+++ b/gas/configure.tgt
@@ -30,9 +30,8 @@ eval `echo $targ | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/cpu=\1 vendor=\2 os=\3/'`
# endian and arch.
# Note: This table is alpha-sorted, please try to keep it that way.
case ${cpu} in
- m32c) cpu_type=m32c endian=big ;;
- am33_2.0) cpu_type=mn10300 endian=little ;;
alpha*) cpu_type=alpha ;;
+ am33_2.0) cpu_type=mn10300 endian=little ;;
arm*be|arm*b) cpu_type=arm endian=big ;;
arm*) cpu_type=arm endian=little ;;
c4x*) cpu_type=tic4x ;;
@@ -43,18 +42,19 @@ case ${cpu} in
ia64) cpu_type=ia64 ;;
ip2k) cpu_type=ip2k endian=big ;;
iq2000) cpu_type=iq2000 endian=big ;;
+ m32c) cpu_type=m32c endian=big ;;
m32r) cpu_type=m32r endian=big ;;
m32rle) cpu_type=m32r endian=little ;;
- m6811|m6812|m68hc12) cpu_type=m68hc11 ;;
- m680[012346]0) cpu_type=m68k ;;
+ m5200) cpu_type=m68k ;;
m68008) cpu_type=m68k ;;
+ m680[012346]0) cpu_type=m68k ;;
+ m6811|m6812|m68hc12) cpu_type=m68hc11 ;;
m683??) cpu_type=m68k ;;
- m5200) cpu_type=m68k ;;
m8*) cpu_type=m88k ;;
- ms1) cpu_type=ms1 endian=big ;;
maxq) cpu_type=maxq ;;
mips*el) cpu_type=mips endian=little ;;
mips*) cpu_type=mips endian=big ;;
+ ms1) cpu_type=ms1 endian=big ;;
or32*) cpu_type=or32 endian=big ;;
pjl*) cpu_type=pj endian=little ;;
pj*) cpu_type=pj endian=big ;;
@@ -63,16 +63,16 @@ case ${cpu} in
rs6000*) cpu_type=ppc ;;
s390x*) cpu_type=s390 arch=s390x ;;
s390*) cpu_type=s390 arch=s390 ;;
- sh5*) cpu_type=sh64 endian=big ;;
sh5le*) cpu_type=sh64 endian=little ;;
- sh64*) cpu_type=sh64 endian=big ;;
+ sh5*) cpu_type=sh64 endian=big ;;
sh64le*) cpu_type=sh64 endian=little ;;
+ sh64*) cpu_type=sh64 endian=big ;;
sh*le) cpu_type=sh endian=little ;;
sh*) cpu_type=sh endian=big ;;
- sparclite*) cpu_type=sparc arch=sparclite ;;
- sparclet*) cpu_type=sparc arch=sparclet ;;
sparc64*) cpu_type=sparc arch=v9-64 ;;
sparc86x*) cpu_type=sparc arch=sparc86x ;;
+ sparclet*) cpu_type=sparc arch=sparclet ;;
+ sparclite*) cpu_type=sparc arch=sparclite ;;
sparc*) cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c.
strongarm*be) cpu_type=arm endian=big ;;
strongarm*b) cpu_type=arm endian=big ;;
@@ -90,7 +90,6 @@ esac
generic_target=${cpu_type}-$vendor-$os
# Note: This table is alpha-sorted, please try to keep it that way.
case ${generic_target} in
- m32c-*-elf) fmt=elf ;;
a29k-*-coff) fmt=coff ;;
a29k-amd-udi) fmt=coff ;;
a29k-amd-ebmon) fmt=coff ;;
@@ -246,6 +245,8 @@ case ${generic_target} in
iq2000-*-elf) fmt=elf ;;
+ m32c-*-elf) fmt=elf ;;
+
m32r-*-elf*) fmt=elf ;;
m32r-*-linux*) fmt=elf em=linux;;
@@ -308,6 +309,8 @@ case ${generic_target} in
mn10300-*-linux*) fmt=elf em=linux ;;
mn10300-*-*) fmt=elf ;;
+ ms1-*-elf) fmt=elf bfd_gas=yes ;;
+
msp430-*-*) fmt=elf ;;
ns32k-pc532-mach*) fmt=aout em=pc532mach ;;
diff --git a/ld/configure.tgt b/ld/configure.tgt
index c153204..1c15ab6 100644
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
@@ -15,19 +15,80 @@
targ_extra_emuls=
targ_extra_ofiles=
+# Please try to keep this table in alphabetic order - it makes it
+# much easier to lookup a specific archictecture. Naturally any
+# architecture variants should be kept together even if their names
+# break the alpha sorting.
case "${targ}" in
-am33_2.0-*-linux*) targ_emul=elf32am33lin ;;
-m32c-*-elf) targ_emul=elf32m32c ;;
-arm-epoc-pe) targ_emul=arm_epoc_pe ;
- targ_extra_ofiles="deffilep.o pe-dll.o" ;;
-arm-*-wince) targ_emul=armpe ;
+a29k-*-udi) targ_emul=sa29200 ;;
+a29k-*-ebmon) targ_emul=ebmon29k ;;
+a29k-*-*) targ_emul=a29k
+ ;;
+alpha*-*-freebsd* | alpha*-*-kfreebsd*-gnu)
+ targ_emul=elf64alpha_fbsd
+ targ_extra_emuls="elf64alpha alpha"
+ tdir_alpha=`echo ${targ_alias} | sed -e 's/freebsd/freebsdecoff/'` ;;
+alpha*-*-linuxecoff*) targ_emul=alpha targ_extra_emuls=elf64alpha
+ tdir_elf64alpha=`echo ${targ_alias} | sed -e 's/ecoff//'` ;;
+alpha*-*-linux-*) targ_emul=elf64alpha targ_extra_emuls=alpha
+ tdir_alpha=`echo ${targ_alias} | sed -e 's/linux/linuxecoff/'` ;;
+alpha*-*-osf*) targ_emul=alpha ;;
+alpha*-*-gnu*) targ_emul=elf64alpha ;;
+alpha*-*-netware*) targ_emul=alpha ;;
+alpha*-*-netbsd*) targ_emul=elf64alpha_nbsd ;;
+alpha*-*-openbsd*) targ_emul=elf64alpha
+ ;;
+arc-*-elf*) targ_emul=arcelf
+ ;;
+arm-epoc-pe) targ_emul=arm_epoc_pe ; targ_extra_ofiles="deffilep.o pe-dll.o" ;;
+arm-*-wince) targ_emul=armpe ; targ_extra_ofiles="deffilep.o pe-dll.o" ;;
+arm-*-pe) targ_emul=armpe ; targ_extra_ofiles="deffilep.o pe-dll.o" ;;
+arm-*-aout | armel-*-aout) targ_emul=armaoutl ;;
+armeb-*-aout) targ_emul=armaoutb ;;
+arm-*-coff) targ_emul=armcoff ;;
+arm-*-freebsd* | arm-*-kfreebsd*-gnu)
+ targ_emul=armelf_fbsd
+ targ_extra_emuls="armelf" ;;
+armeb-*-netbsdelf*) targ_emul=armelfb_nbsd;
+ targ_extra_emuls="armelf_nbsd armelf armnbsd" ;;
+arm-*-netbsdelf*) targ_emul=armelf_nbsd;
+ targ_extra_emuls="armelfb_nbsd armelf armnbsd" ;;
+arm-*-netbsd*) targ_emul=armnbsd;
+ targ_extra_emuls="armelf armelf_nbsd armelfb_nbsd" ;;
+arm-*-nto*) targ_emul=armnto ;;
+arm-*-openbsd*) targ_emul=armnbsd ;;
+arm-*-rtems*) targ_emul=armelf ;;
+armeb-*-elf) targ_emul=armelfb ;;
+arm-*-elf | arm*-*-eabi*)
+ targ_emul=armelf ;;
+arm*-*-symbianelf*) targ_emul=armsymbian;;
+arm-*-kaos*) targ_emul=armelf ;;
+arm9e-*-elf) targ_emul=armelf ;;
+arm*b-*-linux-gnueabi) targ_emul=armelfb_linux_eabi ;;
+arm*b-*-linux-*) targ_emul=armelfb_linux; targ_extra_emuls=armelfb ;;
+arm*-*-linux-gnueabi) targ_emul=armelf_linux_eabi ;;
+arm*-*-linux-*) targ_emul=armelf_linux; targ_extra_emuls=armelf ;;
+arm*-*-uclinux*) targ_emul=armelf_linux; targ_extra_emuls=armelf ;;
+arm-*-vxworks) targ_emul=armelf_vxworks ;;
+arm*-*-conix*) targ_emul=armelf ;;
+thumb-*-linux-* | thumb-*-uclinux*) targ_emul=armelf_linux; targ_extra_emuls=armelf ;;
+strongarm-*-coff) targ_emul=armcoff ;;
+strongarm-*-elf) targ_emul=armelf ;;
+strongarm-*-kaos*) targ_emul=armelf ;;
+thumb-*-coff) targ_emul=armcoff ;;
+thumb-*-elf) targ_emul=armelf ;;
+thumb-epoc-pe) targ_emul=arm_epoc_pe ;
targ_extra_ofiles="deffilep.o pe-dll.o" ;;
-arm-*-pe) targ_emul=armpe ;
+thumb-*-pe) targ_emul=armpe ;
targ_extra_ofiles="deffilep.o pe-dll.o" ;;
-arc-*-elf*) targ_emul=arcelf ;;
+xscale-*-coff) targ_emul=armcoff ;;
+xscale-*-elf) targ_emul=armelf
+ ;;
avr-*-*) targ_emul=avr2
- targ_extra_emuls="avr1 avr3 avr4 avr5" ;;
-cr16c-*-elf*) targ_emul=elf32cr16c ;;
+ targ_extra_emuls="avr1 avr3 avr4 avr5"
+ ;;
+cr16c-*-elf*) targ_emul=elf32cr16c
+ ;;
cris-*-*aout*) targ_emul=crisaout
targ_extra_emuls="criself crislinux"
targ_extra_libpath=$targ_extra_emuls ;;
@@ -35,104 +96,41 @@ cris-*-linux-* | crisv32-*-linux-*)
targ_emul=crislinux ;;
cris-*-* | crisv32-*-*) targ_emul=criself
targ_extra_emuls="crisaout crislinux"
- targ_extra_libpath=$targ_extra_emuls ;;
-crx-*-elf*) targ_emul=elf32crx ;;
+ targ_extra_libpath=$targ_extra_emuls
+ ;;
+crx-*-elf*) targ_emul=elf32crx
+ ;;
d10v-*-*) targ_emul=d10velf ;;
d30v-*-*ext*) targ_emul=d30v_e; targ_extra_emuls="d30velf d30v_o" ;;
d30v-*-*onchip*) targ_emul=d30v_o; targ_extra_emuls="d30velf d30v_e" ;;
-d30v-*-*) targ_emul=d30velf; targ_extra_emuls="d30v_e d30v_o" ;;
-dlx-*-elf*) targ_emul=elf32_dlx ;;
-ms1-*elf) targ_emul=elf32ms1 ;;
-sparc64-*-aout*) targ_emul=sparcaout ;;
-sparc64-*-elf*) targ_emul=elf64_sparc ;;
-sparc-sun-sunos4*) targ_emul=sun4 ;;
-sparclite*-*-elf) targ_emul=elf32_sparc ;;
-sparclite*-*-coff) targ_emul=coff_sparc ;;
-sparclite*-fujitsu-*) targ_emul=sparcaout ;;
-sparc*-*-aout) targ_emul=sparcaout ;;
-sparc*-*-coff) targ_emul=coff_sparc ;;
-sparc*-*-elf) targ_emul=elf32_sparc ;;
-sparc*-*-sysv4*) targ_emul=elf32_sparc ;;
-sparc64-*-freebsd* | sparcv9-*-freebsd* | sparc64-*-kfreebsd*-gnu | sparcv9-*-kfreebsd*-gnu)
- targ_emul=elf64_sparc_fbsd
- targ_extra_emuls="elf64_sparc elf32_sparc"
- targ_extra_libpath=$targ_extra_emuls
- tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/64//'`
+d30v-*-*) targ_emul=d30velf; targ_extra_emuls="d30v_e d30v_o"
;;
-sparc*-*-linux*aout*) targ_emul=sparclinux
- targ_extra_emuls="elf32_sparc sun4"
- tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/aout//'`
- tdir_sun4=sparc-sun-sunos4
+dlx-*-elf*) targ_emul=elf32_dlx
;;
-sparc64-*-linux-*) targ_emul=elf64_sparc
- targ_extra_emuls="elf32_sparc sparclinux sun4"
- targ_extra_libpath=elf32_sparc
- tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/64//'`
- tdir_sparclinux=${tdir_elf32_sparc}aout
- tdir_sun4=sparc-sun-sunos4
+fr30-*-*) targ_emul=elf32fr30
;;
-sparc*-*-linux-*) targ_emul=elf32_sparc
- targ_extra_emuls="sparclinux elf64_sparc sun4"
- targ_extra_libpath=elf64_sparc
- tdir_sparclinux=${targ_alias}aout
- tdir_elf64_sparc=`echo ${targ_alias} | sed -e 's/32//'`
- tdir_sun4=sparc-sun-sunos4
+frv-*-*linux*) targ_emul=elf32frvfd ;;
+frv-*-*) targ_emul=elf32frv ; targ_extra_emuls="elf32frvfd"
;;
-sparc64-*-netbsd* | sparc64-*-openbsd*)
- targ_emul=elf64_sparc
- targ_extra_emuls="elf32_sparc"
+h8300-*-hms* | h8300-*-coff* | h8300-*-rtemscoff*)
+ targ_emul=h8300; targ_extra_emuls="h8300h h8300s h8300hn h8300sn h8300sx h8300sxn" ;;
+h8300-*-elf* | h8300-*-rtems*)
+ targ_emul=h8300elf;
+ targ_extra_emuls="h8300helf h8300self h8300hnelf h8300snelf h8300sxelf h8300sxnelf" ;;
+h8500-*-hms* | h8500-*-coff* | h8500-*-rtems*)
+ targ_emul=h8500
+ targ_extra_emuls="h8500s h8500b h8500m h8500c"
;;
-sparc*-*-netbsd*elf*) targ_emul=elf32_sparc ;;
-sparc*-*-netbsd*) targ_emul=sparcnbsd ;;
-sparc-*-solaris2.[0-6] | sparc-*-solaris2.[0-6].*)
- targ_emul=elf32_sparc ;;
-sparc-*-solaris2*) targ_emul=elf32_sparc
- targ_extra_emuls="elf64_sparc"
- targ_extra_libpath=$targ_extra_emuls
- tdir_elf64_sparc=`echo ${targ_alias} | sed -e 's/32//'`
+hppa*64*-*-linux-*) targ_emul=hppa64linux ;;
+hppa*64*-*) targ_emul=elf64hppa ;;
+hppa*-*-linux-*) targ_emul=hppalinux ;;
+hppa*-*-*elf*) targ_emul=hppaelf ;;
+hppa*-*-lites*) targ_emul=hppaelf ;;
+hppa*-*-netbsd*) targ_emul=hppanbsd ;;
+hppa*-*-openbsd*) targ_emul=hppaobsd
;;
-sparcv9-*-solaris2* | sparc64-*-solaris2*)
- targ_emul=elf64_sparc
- targ_extra_emuls="elf32_sparc"
- targ_extra_libpath=$targ_extra_emuls
- tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/64//'`
+i370-*-elf* | i370-*-linux-*) targ_emul=elf32i370
;;
-sparc*-*-solaris2*) targ_emul=elf32_sparc ;;
-sparc*-wrs-vxworks*) targ_emul=sparcaout ;;
-sparc*-*-rtemself*) targ_emul=elf32_sparc ;;
-sparc*-*-rtems*) targ_emul=elf32_sparc ;;
-i860-*-coff) targ_emul=coff_i860 ;;
-i860-stardent-sysv4* | i860-stardent-elf*)
- targ_emul=elf32_i860 ;;
-i960-wrs-vxworks5.0*) targ_emul=gld960 ;;
-i960-wrs-vxworks5*) targ_emul=gld960coff ;;
-i960-wrs-vxworks*) targ_emul=gld960 ;;
-i960-*-coff) targ_emul=gld960coff ;;
-i960-intel-nindy) targ_emul=gld960 ;;
-i960-*-rtems*) targ_emul=gld960coff ;;
-i960-*-elf*) targ_emul=elf32_i960 ;;
-ia64-*-elf*) targ_emul=elf64_ia64 ;;
-ia64-*-freebsd* | ia64-*-kfreebsd*-gnu)
- targ_emul=elf64_ia64_fbsd
- targ_extra_emuls="elf64_ia64" ;;
-ia64-*-netbsd*) targ_emul=elf64_ia64 ;;
-ia64-*-linux*) targ_emul=elf64_ia64 ;;
-ia64-*-aix*) targ_emul=elf64_aix ;;
-m32r*le-*-elf*) targ_emul=m32rlelf ;;
-m32r*-*-elf*) targ_emul=m32relf ;;
-m32r*le-*-linux-*) targ_emul=m32rlelf_linux ;;
-m32r*-*-linux-*) targ_emul=m32relf_linux ;;
-m68hc11-*-*|m6811-*-*) targ_emul=m68hc11elf
- targ_extra_emuls="m68hc11elfb m68hc12elf m68hc12elfb" ;;
-m68hc12-*-*|m6812-*-*) targ_emul=m68hc12elf
- targ_extra_emuls="m68hc12elfb m68hc11elf m68hc11elfb" ;;
-m68*-sun-sunos[34]*) targ_emul=sun3 ;;
-m68*-wrs-vxworks*) targ_emul=sun3 ;;
-m68*-ericsson-ose) targ_emul=sun3 ;;
-m68*-apple-aux*) targ_emul=m68kaux ;;
-maxq-*-coff) targ_emul=maxqcoff;;
-*-tandem-none) targ_emul=st2000 ;;
-i370-*-elf* | i370-*-linux-*) targ_emul=elf32i370 ;;
i[3-7]86-*-nto-qnx*) targ_emul=i386nto ;;
i[3-7]86-*-vsta) targ_emul=vsta ;;
i[3-7]86-*-go32) targ_emul=i386go32 ;;
@@ -151,22 +149,19 @@ i[3-7]86-*-bsdi*) targ_emul=i386bsd ;;
i[3-7]86-*-aout) targ_emul=i386aout ;;
i[3-7]86-*-linux*aout*) targ_emul=i386linux
targ_extra_emuls=elf_i386
- tdir_elf_i386=`echo ${targ_alias} | sed -e 's/aout//'`
- ;;
+ tdir_elf_i386=`echo ${targ_alias} | sed -e 's/aout//'` ;;
i[3-7]86-*-linux*oldld) targ_emul=i386linux; targ_extra_emuls=elf_i386 ;;
i[3-7]86-*-linux-*) targ_emul=elf_i386
targ_extra_emuls=i386linux
if test x${want64} = xtrue; then
targ_extra_emuls="$targ_extra_emuls elf_x86_64"
fi
- tdir_i386linux=${targ_alias}aout
- ;;
+ tdir_i386linux=${targ_alias}aout ;;
x86_64-*-linux-*) targ_emul=elf_x86_64
targ_extra_emuls="elf_i386 i386linux"
targ_extra_libpath=elf_i386
tdir_i386linux=`echo ${targ_alias}aout | sed -e 's/x86_64/i386/'`
- tdir_elf_i386=`echo ${targ_alias} | sed -e 's/x86_64/i386/'`
- ;;
+ tdir_elf_i386=`echo ${targ_alias} | sed -e 's/x86_64/i386/'` ;;
i[3-7]86-*-sysv[45]*) targ_emul=elf_i386 ;;
i[3-7]86-*-solaris2*) targ_emul=elf_i386_ldso
targ_extra_emuls="elf_i386 elf_x86_64"
@@ -179,30 +174,23 @@ i[3-7]86-*-netbsdelf* | \
i[3-7]86-*-netbsd*-gnu* | \
i[3-7]86-*-knetbsd*-gnu)
targ_emul=elf_i386
- targ_extra_emuls=i386nbsd
- ;;
+ targ_extra_emuls=i386nbsd ;;
i[3-7]86-*-netbsdpe*) targ_emul=i386pe
- targ_extra_ofiles="deffilep.o pe-dll.o"
- ;;
+ targ_extra_ofiles="deffilep.o pe-dll.o" ;;
i[3-7]86-*-netbsd*) targ_emul=i386nbsd
- targ_extra_emuls=elf_i386
- ;;
+ targ_extra_emuls=elf_i386 ;;
x86_64-*-netbsd*) targ_emul=elf_x86_64
targ_extra_emuls="elf_i386 i386nbsd"
tdir_elf_i386=`echo ${targ_alias} | \
sed -e 's/x86_64/i386/'`
case "${tdir_elf_i386}" in
- *-netbsdelf*) ;;
- *)
- tdir_elf_i386=`echo ${tdir_elf_i386} | \
- sed -e 's/netbsd/netbsdelf/'`
- ;;
- esac
- ;;
+ *-netbsdelf*) ;;
+ *) tdir_elf_i386=`echo ${tdir_elf_i386} | \
+ sed -e 's/netbsd/netbsdelf/'`;;
+ esac ;;
i[3-7]86-*-netware) targ_emul=i386nw ;;
i[3-7]86-*-elf*) targ_emul=elf_i386 ;;
-x86_64-*-elf*)
- targ_emul=elf_x86_64
+x86_64-*-elf*) targ_emul=elf_x86_64
targ_extra_emuls=elf_i386
;;
i[3-7]86-*-kaos*) targ_emul=elf_i386 ;;
@@ -215,8 +203,7 @@ x86_64-*-freebsd* | x86_64-*-kfreebsd*-gnu)
targ_emul=elf_x86_64_fbsd
targ_extra_emuls="elf_i386_fbsd elf_x86_64 elf_i386"
tdir_elf_i386=`echo ${targ_alias} \
- | sed -e 's/x86_64/i386/'`
- ;;
+ | sed -e 's/x86_64/i386/'` ;;
i[3-7]86-*-sysv*) targ_emul=i386coff ;;
i[3-7]86-*-ptx*) targ_emul=i386coff ;;
i[3-7]86-*-mach*) targ_emul=i386mach ;;
@@ -237,133 +224,47 @@ i[3-7]86-*-interix*) targ_emul=i386pe_posix;
i[3-7]86-*-beospe*) targ_emul=i386beos ;;
i[3-7]86-*-beos*) targ_emul=elf_i386_be ;;
i[3-7]86-*-vxworks*) targ_emul=elf_i386_vxworks ;;
-i[3-7]86-*-chaos) targ_emul=elf_i386_chaos ;;
-m8*-*-*) targ_emul=m88kbcs ;;
-a29k-*-udi) targ_emul=sa29200 ;;
-a29k-*-ebmon) targ_emul=ebmon29k ;;
-a29k-*-*) targ_emul=a29k ;;
-# arm-*-riscix*) targ_emul=riscix ;;
-arm-*-aout | armel-*-aout) targ_emul=armaoutl ;;
-armeb-*-aout) targ_emul=armaoutb ;;
-arm-*-coff) targ_emul=armcoff ;;
-arm-*-freebsd* | arm-*-kfreebsd*-gnu)
- targ_emul=armelf_fbsd
- targ_extra_emuls="armelf" ;;
-armeb-*-netbsdelf*) targ_emul=armelfb_nbsd;
- targ_extra_emuls="armelf_nbsd armelf armnbsd" ;;
-arm-*-netbsdelf*) targ_emul=armelf_nbsd;
- targ_extra_emuls="armelfb_nbsd armelf armnbsd" ;;
-arm-*-netbsd*) targ_emul=armnbsd;
- targ_extra_emuls="armelf armelf_nbsd armelfb_nbsd" ;;
-arm-*-nto*) targ_emul=armnto ;;
-arm-*-openbsd*) targ_emul=armnbsd ;;
-arm-*-rtems*) targ_emul=armelf ;;
-armeb-*-elf) targ_emul=armelfb ;;
-arm-*-elf | arm*-*-eabi*)
- targ_emul=armelf ;;
-arm*-*-symbianelf*) targ_emul=armsymbian;;
-arm-*-kaos*) targ_emul=armelf ;;
-arm9e-*-elf) targ_emul=armelf ;;
-arm*b-*-linux-gnueabi) targ_emul=armelfb_linux_eabi ;;
-arm*b-*-linux-*) targ_emul=armelfb_linux; targ_extra_emuls=armelfb ;;
-arm*-*-linux-gnueabi) targ_emul=armelf_linux_eabi ;;
-arm*-*-linux-*) targ_emul=armelf_linux; targ_extra_emuls=armelf ;;
-arm*-*-uclinux*) targ_emul=armelf_linux; targ_extra_emuls=armelf ;;
-arm-*-vxworks) targ_emul=armelf_vxworks ;;
-arm*-*-conix*) targ_emul=armelf ;;
-thumb-*-linux-* | thumb-*-uclinux*) targ_emul=armelf_linux; targ_extra_emuls=armelf ;;
-strongarm-*-coff) targ_emul=armcoff ;;
-strongarm-*-elf) targ_emul=armelf ;;
-strongarm-*-kaos*) targ_emul=armelf ;;
-thumb-*-coff) targ_emul=armcoff ;;
-thumb-*-elf) targ_emul=armelf ;;
-thumb-epoc-pe) targ_emul=arm_epoc_pe ;
- targ_extra_ofiles="deffilep.o pe-dll.o" ;;
-thumb-*-pe) targ_emul=armpe ;
- targ_extra_ofiles="deffilep.o pe-dll.o" ;;
-xscale-*-coff) targ_emul=armcoff ;;
-xscale-*-elf) targ_emul=armelf ;;
-h8300-*-hms* | h8300-*-coff* | h8300-*-rtemscoff*)
- targ_emul=h8300; targ_extra_emuls="h8300h h8300s h8300hn h8300sn h8300sx h8300sxn"
- ;;
-h8300-*-elf* | h8300-*-rtems*)
- targ_emul=h8300elf;
- targ_extra_emuls="h8300helf h8300self h8300hnelf h8300snelf h8300sxelf h8300sxnelf"
+i[3-7]86-*-chaos) targ_emul=elf_i386_chaos
;;
-h8500-*-hms* | h8500-*-coff* | h8500-*-rtems*)
- targ_emul=h8500
- targ_extra_emuls="h8500s h8500b h8500m h8500c"
- ;;
-sh-*-linux*)
- targ_emul=shlelf_linux
- targ_extra_emuls=shelf_linux
- targ_extra_libpath=shelf_linux
- ;;
-sh64eb-*-linux*) targ_emul=shelf32_linux
- targ_extra_emuls="shlelf32_linux"
- ;;
-sh64-*-linux*) targ_emul=shlelf32_linux
- targ_extra_emuls="shelf32_linux"
- targ_extra_libpath=shelf32_linux
- ;;
-sh*eb-*-linux*)
- targ_emul=shelf_linux
- ;;
-sh*-*-linux*)
- targ_emul=shlelf_linux
- ;;
-sh5le-*-netbsd*)
- targ_emul=shlelf32_nbsd
- targ_extra_emuls="shelf32_nbsd shelf64_nbsd shlelf64_nbsd shelf_nbsd shlelf_nbsd"
- ;;
-sh5-*-netbsd*)
- targ_emul=shelf32_nbsd
- targ_extra_emuls="shlelf32_nbsd shelf64_nbsd shlelf64_nbsd shelf_nbsd shlelf_nbsd"
- ;;
-sh64le-*-netbsd*)
- targ_emul=shlelf64_nbsd
- targ_extra_emuls="shelf64_nbsd shelf32_nbsd shlelf32_nbsd shelf_nbsd shlelf_nbsd"
- ;;
-sh64-*-netbsd*)
- targ_emul=shelf64_nbsd
- targ_extra_emuls="shlelf64_nbsd shelf32_nbsd shlelf32_nbsd shelf_nbsd shlelf_nbsd"
- ;;
-sh*l*-*-netbsdelf*)
- targ_emul=shlelf_nbsd
- targ_extra_emuls=shelf_nbsd
- ;;
-sh*-*-netbsdelf*)
- targ_emul=shelf_nbsd
- targ_extra_emuls=shlelf_nbsd
+i860-*-coff) targ_emul=coff_i860 ;;
+i860-stardent-sysv4* | i860-stardent-elf*)
+ targ_emul=elf32_i860
;;
-sh*-*-symbianelf*)
- targ_emul=shlsymbian
+i960-wrs-vxworks5.0*) targ_emul=gld960 ;;
+i960-wrs-vxworks5*) targ_emul=gld960coff ;;
+i960-wrs-vxworks*) targ_emul=gld960 ;;
+i960-*-coff) targ_emul=gld960coff ;;
+i960-intel-nindy) targ_emul=gld960 ;;
+i960-*-rtems*) targ_emul=gld960coff ;;
+i960-*-elf*) targ_emul=elf32_i960
;;
-shle*-*-elf* | sh[1234]*le*-*-elf | shle*-*-kaos*)
- targ_emul=shlelf
- targ_extra_emuls="shelf shl sh"
+ia64-*-elf*) targ_emul=elf64_ia64 ;;
+ia64-*-freebsd* | ia64-*-kfreebsd*-gnu)
+ targ_emul=elf64_ia64_fbsd
+ targ_extra_emuls="elf64_ia64" ;;
+ia64-*-netbsd*) targ_emul=elf64_ia64 ;;
+ia64-*-linux*) targ_emul=elf64_ia64 ;;
+ia64-*-aix*) targ_emul=elf64_aix
;;
-sh-*-rtemscoff*) targ_emul=sh; targ_extra_emuls=shl ;;
-sh-*-elf* | sh[1234]*-*-elf | sh-*-rtems* | sh-*-kaos* | sh-*-vxworks)
- targ_emul=shelf
- targ_extra_emuls="shlelf sh shl"
+ip2k-*-elf) targ_emul=elf32ip2k
;;
-sh-*-nto*) targ_emul=shelf_nto
- targ_extra_emuls=shlelf_nto
+iq2000-*-elf) targ_emul=elf32iq2000 ; targ_extra_emuls="elf32iq10"
;;
-sh-*-pe) targ_emul=shpe ;
- targ_extra_ofiles="deffilep.o pe-dll.o" ;;
-sh-*-*) targ_emul=sh; targ_extra_emuls=shl ;;
-sh64le-*-elf*)
- targ_emul=shlelf
- targ_extra_emuls="shelf shlelf32 shelf32 shlelf64 shelf64"
- targ_extra_libpath=$targ_extra_emuls
+m32c-*-elf) targ_emul=elf32m32c
;;
-sh64-*-elf*)
- targ_emul=shelf
- targ_extra_emuls="shlelf shelf32 shlelf32 shelf64 shlelf64"
- targ_extra_libpath=$targ_extra_emuls
+m32r*le-*-elf*) targ_emul=m32rlelf ;;
+m32r*-*-elf*) targ_emul=m32relf ;;
+m32r*le-*-linux-*) targ_emul=m32rlelf_linux ;;
+m32r*-*-linux-*) targ_emul=m32relf_linux
;;
+m68hc11-*-*|m6811-*-*) targ_emul=m68hc11elf
+ targ_extra_emuls="m68hc11elfb m68hc12elf m68hc12elfb" ;;
+m68hc12-*-*|m6812-*-*) targ_emul=m68hc12elf
+ targ_extra_emuls="m68hc12elfb m68hc11elf m68hc11elfb" ;;
+m68*-sun-sunos[34]*) targ_emul=sun3 ;;
+m68*-wrs-vxworks*) targ_emul=sun3 ;;
+m68*-ericsson-ose) targ_emul=sun3 ;;
+m68*-apple-aux*) targ_emul=m68kaux ;;
m68k-sony-*) targ_emul=news ;;
m68k-hp-bsd*) targ_emul=hp300bsd ;;
m68*-motorola-sysv*) targ_emul=delta68 ;;
@@ -373,12 +274,10 @@ m68*-*-elf) targ_emul=m68kelf ;;
m68*-*-hpux*) targ_emul=hp3hpux ;;
m68k-*-linux*aout*) targ_emul=m68klinux
targ_extra_emuls=m68kelf
- tdir_m68kelf=`echo ${targ_alias} | sed -e 's/aout//'`
- ;;
+ tdir_m68kelf=`echo ${targ_alias} | sed -e 's/aout//'` ;;
m68k-*-linux-*) targ_emul=m68kelf
targ_extra_emuls=m68klinux
- tdir_m68klinux=`echo ${targ_alias} | sed -e 's/linux/linuxaout/'`
- ;;
+ tdir_m68klinux=`echo ${targ_alias} | sed -e 's/linux/linuxaout/'` ;;
m68k-*-uclinux*) targ_emul=m68kelf ;;
m68*-*-gnu*) targ_emul=m68kelf ;;
m68*-*-netbsd*4k*) targ_emul=m68k4knbsd
@@ -390,21 +289,16 @@ m68*-*-netbsdaout* | m68*-*-netbsd*)
targ_extra_emuls="m68kelfnbsd m68k4knbsd" ;;
m68*-*-psos*) targ_emul=m68kpsos ;;
m68*-*-rtemscoff*) targ_emul=m68kcoff ;;
-m68*-*-rtems*) targ_emul=m68kelf ;;
-hppa*64*-*-linux-*) targ_emul=hppa64linux ;;
-hppa*64*-*) targ_emul=elf64hppa ;;
-hppa*-*-linux-*) targ_emul=hppalinux ;;
-hppa*-*-*elf*) targ_emul=hppaelf ;;
-hppa*-*-lites*) targ_emul=hppaelf ;;
-hppa*-*-netbsd*) targ_emul=hppanbsd ;;
-hppa*-*-openbsd*) targ_emul=hppaobsd ;;
-vax-dec-ultrix* | vax-dec-bsd*) targ_emul=vax ;;
-vax-*-netbsdelf*) targ_emul=elf32vax
- targ_extra_emuls=vaxnbsd ;;
-vax-*-netbsdaout* | vax-*-netbsd*)
- targ_emul=vaxnbsd
- targ_extra_emuls=elf32vax ;;
-vax-*-linux-*) targ_emul=elf32vax ;;
+m68*-*-rtems*) targ_emul=m68kelf
+ ;;
+m8*-*-*) targ_emul=m88kbcs
+ ;;
+maxq-*-coff) targ_emul=maxqcoff
+ ;;
+mcore-*-pe) targ_emul=mcorepe ;
+ targ_extra_ofiles="deffilep.o pe-dll.o" ;;
+mcore-*-elf) targ_emul=elf32mcore
+ ;;
mips*-*-pe) targ_emul=mipspe ;
targ_extra_ofiles="deffilep.o pe-dll.o" ;;
mips*-dec-ultrix*) targ_emul=mipslit ;;
@@ -412,17 +306,14 @@ mips*-dec-osf*) targ_emul=mipslit ;;
mips*-sgi-irix5*) targ_emul=elf32bsmip ;;
mips*-sgi-irix6*) targ_emul=elf32bmipn32
targ_extra_emuls="elf32bsmip elf64bmip"
- targ_extra_libpath=$targ_extra_emuls
- ;;
+ targ_extra_libpath=$targ_extra_emuls ;;
mips*-sgi-irix*) targ_emul=mipsbig ;;
mips*el-*-ecoff*) targ_emul=mipsidtl ;;
mips*-*-ecoff*) targ_emul=mipsidt ;;
mips*el-*-netbsd*) targ_emul=elf32lmip
- targ_extra_emuls="elf32bmip"
- ;;
+ targ_extra_emuls="elf32bmip" ;;
mips*-*-netbsd*) targ_emul=elf32bmip
- targ_extra_emuls="elf32lmip"
- ;;
+ targ_extra_emuls="elf32lmip" ;;
mips*-*-bsd*) targ_emul=mipsbig ;;
mips*vr4300el-*-elf*) targ_emul=elf32l4300 ;;
mips*vr4300-*-elf*) targ_emul=elf32b4300 ;;
@@ -439,101 +330,89 @@ mips*-*-vxworks*) targ_emul=elf32ebmip
mips*-*-windiss) targ_emul=elf32mipswindiss ;;
mips64*el-*-linux-*) targ_emul=elf32ltsmipn32
targ_extra_emuls="elf32btsmipn32 elf32ltsmip elf32btsmip elf64ltsmip elf64btsmip"
- targ_extra_libpath="elf32ltsmip elf64ltsmip"
- ;;
+ targ_extra_libpath="elf32ltsmip elf64ltsmip" ;;
mips64*-*-linux-*) targ_emul=elf32btsmipn32
targ_extra_emuls="elf32ltsmipn32 elf32btsmip elf32ltsmip elf64btsmip elf64ltsmip"
- targ_extra_libpath="elf32btsmip elf64btsmip"
- ;;
+ targ_extra_libpath="elf32btsmip elf64btsmip" ;;
mips*el-*-linux-*) targ_emul=elf32ltsmip
- targ_extra_emuls="elf32btsmip elf32ltsmipn32 elf64ltsmip elf32btsmipn32 elf64btsmip"
- ;;
+ targ_extra_emuls="elf32btsmip elf32ltsmipn32 elf64ltsmip elf32btsmipn32 elf64btsmip" ;;
mips*-*-linux-*) targ_emul=elf32btsmip
- targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip"
- ;;
+ targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;;
mips*-*-lnews*) targ_emul=mipslnews ;;
-mips*-*-sysv4*) targ_emul=elf32btsmip ;;
+mips*-*-sysv4*) targ_emul=elf32btsmip
+ ;;
mmix-*-*) targ_emul=mmo
targ_extra_emuls=elf64mmix
;;
+am33_2.0-*-linux*) targ_emul=elf32am33lin ;;
mn10200-*-*) targ_emul=mn10200 ;;
-mn10300-*-*) targ_emul=mn10300 ;;
-msp430-*-*) targ_emul=msp430x110
- targ_extra_emuls="msp430x112 msp430x1101 msp430x1111 msp430x1121 msp430x1122 msp430x1132 msp430x122 msp430x123 msp430x1222 msp430x1232 msp430x133 msp430x135 msp430x1331 msp430x1351 msp430x147 msp430x148 msp430x149 msp430x155 msp430x156 msp430x157 msp430x167 msp430x168 msp430x169 msp430x1610 msp430x1611 msp430x1612 msp430x311 msp430x312 msp430x313 msp430x314 msp430x315 msp430x323 msp430x325 msp430x336 msp430x337 msp430x412 msp430x413 msp430x415 msp430x417 msp430xE423 msp430xE425 msp430xE427 msp430xW423 msp430xW425 msp430xW427 msp430xG437 msp430xG438 msp430xG439 msp430x435 msp430x436 msp430x437 msp430x447 msp430x448 msp430x449" ;;
-alpha*-*-freebsd* | alpha*-*-kfreebsd*-gnu)
- targ_emul=elf64alpha_fbsd
- targ_extra_emuls="elf64alpha alpha"
- tdir_alpha=`echo ${targ_alias} | sed -e 's/freebsd/freebsdecoff/'`
+mn10300-*-*) targ_emul=mn10300
;;
-alpha*-*-linuxecoff*) targ_emul=alpha targ_extra_emuls=elf64alpha
- tdir_elf64alpha=`echo ${targ_alias} | sed -e 's/ecoff//'`
+ms1-*elf) targ_emul=elf32ms1
;;
-alpha*-*-linux-*) targ_emul=elf64alpha targ_extra_emuls=alpha
- tdir_alpha=`echo ${targ_alias} | sed -e 's/linux/linuxecoff/'`
+msp430-*-*) targ_emul=msp430x110
+ targ_extra_emuls="msp430x112 msp430x1101 msp430x1111 msp430x1121 msp430x1122 msp430x1132 msp430x122 msp430x123 msp430x1222 msp430x1232 msp430x133 msp430x135 msp430x1331 msp430x1351 msp430x147 msp430x148 msp430x149 msp430x155 msp430x156 msp430x157 msp430x167 msp430x168 msp430x169 msp430x1610 msp430x1611 msp430x1612 msp430x311 msp430x312 msp430x313 msp430x314 msp430x315 msp430x323 msp430x325 msp430x336 msp430x337 msp430x412 msp430x413 msp430x415 msp430x417 msp430xE423 msp430xE425 msp430xE427 msp430xW423 msp430xW425 msp430xW427 msp430xG437 msp430xG438 msp430xG439 msp430x435 msp430x436 msp430x437 msp430x447 msp430x448 msp430x449"
+ ;;
+ns32k-pc532-mach* | ns32k-pc532-ux*) targ_emul=pc532macha ;;
+ns32k-*-netbsd* | ns32k-pc532-lites*) targ_emul=ns32knbsd
;;
-alpha*-*-osf*) targ_emul=alpha ;;
-alpha*-*-gnu*) targ_emul=elf64alpha ;;
-alpha*-*-netware*) targ_emul=alpha ;;
-alpha*-*-netbsd*) targ_emul=elf64alpha_nbsd ;;
-alpha*-*-openbsd*) targ_emul=elf64alpha ;;
-z8k-*-coff) targ_emul=z8002; targ_extra_emuls=z8001 ;;
-ns32k-pc532-mach* | ns32k-pc532-ux*) targ_emul=pc532macha ;;
-ns32k-*-netbsd* | ns32k-pc532-lites*) targ_emul=ns32knbsd ;;
openrisc-*-*) targ_emul=elf32openrisc ;;
or32-*-coff) targ_emul=or32 ;;
or32-*-elf) targ_emul=or32elf ;;
-or32-*-rtems*) targ_emul=or32elf ;;
-pdp11-*-*) targ_emul=pdp11 ;;
+or32-*-rtems*) targ_emul=or32elf
+ ;;
+pdp11-*-*) targ_emul=pdp11
+ ;;
pjl*-*-*) targ_emul=pjlelf ; targ_extra_emuls="elf_i386" ;;
-pj*-*-*) targ_emul=pjelf ;;
+pj*-*-*) targ_emul=pjelf
+ ;;
powerpc-*-freebsd* | powerpc-*-kfreebsd*-gnu)
targ_emul=elf32ppc_fbsd;
targ_extra_emuls="elf32ppc elf32ppcsim";
targ_extra_libpath=elf32ppc;
- tdir_elf32ppcsim=`echo ${targ_alias} | sed -e 's/ppc/ppcsim/'`
- ;;
-powerpc*-*-linux*)
- case "${targ}" in
- *64*) targ_emul=elf64ppc
- targ_extra_emuls="elf32ppclinux elf32ppc elf32ppcsim"
- targ_extra_libpath="elf32ppclinux elf32ppc"
- tdir_elf32ppc=`echo "${targ_alias}" | sed -e 's/64//'`
- tdir_elf32ppclinux=$tdir_elf32ppc
- tdir_elf32ppcsim=$tdir_elf32ppc ;;
- *) targ_emul=elf32ppclinux
- targ_extra_emuls="elf32ppc elf32ppcsim"
- targ_extra_libpath=elf32ppc
- if test "${want64}" = "true"; then
- targ_extra_emuls="$targ_extra_emuls elf64ppc"
- targ_extra_libpath="$targ_extra_libpath elf64ppc"
- fi
- ;;
- esac ;;
+ tdir_elf32ppcsim=`echo ${targ_alias} | sed -e 's/ppc/ppcsim/'` ;;
+powerpc*-*-linux*) case "${targ}" in
+ *64*) targ_emul=elf64ppc
+ targ_extra_emuls="elf32ppclinux elf32ppc elf32ppcsim"
+ targ_extra_libpath="elf32ppclinux elf32ppc"
+ tdir_elf32ppc=`echo "${targ_alias}" | sed -e 's/64//'`
+ tdir_elf32ppclinux=$tdir_elf32ppc
+ tdir_elf32ppcsim=$tdir_elf32ppc
+ ;;
+ *) targ_emul=elf32ppclinux
+ targ_extra_emuls="elf32ppc elf32ppcsim"
+ targ_extra_libpath=elf32ppc
+ if test "${want64}" = "true"; then
+ targ_extra_emuls="$targ_extra_emuls elf64ppc"
+ targ_extra_libpath="$targ_extra_libpath elf64ppc"
+ fi ;;
+ esac ;;
powerpc*le-*-elf* | powerpc*le-*-eabi* | powerpc*le-*-solaris* \
| powerpc*le-*-sysv* | powerpc*le-*-vxworks*)
- case "${targ}" in
- *64*) targ_emul=elf64lppc
- targ_extra_emuls="elf32lppc elf32lppcsim"
- tdir_elf32lppc=`echo "${targ_alias}" | sed -e 's/64//'`
- tdir_elf32lppcsim=$tdir_elf32lppc ;;
- *) targ_emul=elf32lppc
- targ_extra_emuls="elf32ppcsim" ;;
- esac ;;
+ case "${targ}" in
+ *64*) targ_emul=elf64lppc
+ targ_extra_emuls="elf32lppc elf32lppcsim"
+ tdir_elf32lppc=`echo "${targ_alias}" | sed -e 's/64//'`
+ tdir_elf32lppcsim=$tdir_elf32lppc
+ ;;
+ *) targ_emul=elf32lppc
+ targ_extra_emuls="elf32ppcsim" ;;
+ esac ;;
powerpc*-*-elf* | powerpc*-*-eabi* | powerpc*-*-sysv* \
| powerpc*-*-netbsd* | powerpc-*-openbsd* | powerpc*-*-kaos*)
- case "${targ}" in
- *64*) targ_emul=elf64ppc
- targ_extra_emuls="elf32ppc elf32ppclinux elf32ppcsim"
- tdir_elf32ppc=`echo "${targ_alias}" | sed -e 's/64//'`
- tdir_elf32ppclinux=$tdir_elf32ppc
- tdir_elf32ppcsim=$tdir_elf32ppc ;;
- *) targ_emul=elf32ppc
- targ_extra_emuls="elf32ppclinux elf32ppcsim" ;;
- esac ;;
+ case "${targ}" in
+ *64*) targ_emul=elf64ppc
+ targ_extra_emuls="elf32ppc elf32ppclinux elf32ppcsim"
+ tdir_elf32ppc=`echo "${targ_alias}" | sed -e 's/64//'`
+ tdir_elf32ppclinux=$tdir_elf32ppc
+ tdir_elf32ppcsim=$tdir_elf32ppc
+ ;;
+ *) targ_emul=elf32ppc
+ targ_extra_emuls="elf32ppclinux elf32ppcsim" ;;
+ esac ;;
powerpc-*-vxworks*)
- targ_emul=elf32ppcvxworks
- targ_extra_emuls="elf32ppc elf32ppclinux elf32ppcsim"
- ;;
+ targ_emul=elf32ppcvxworks
+ targ_extra_emuls="elf32ppc elf32ppclinux elf32ppcsim" ;;
powerpc-*-nto*) targ_emul=elf32ppcnto ;;
powerpcle-*-nto*) targ_emul=elf32lppcnto ;;
powerpc-*-rtems*) targ_emul=elf32ppc ;;
@@ -548,25 +427,8 @@ powerpc-*-beos*) targ_emul=aixppc ;;
powerpc-*-windiss*) targ_emul=elf32ppcwindiss ;;
powerpc-*-lynxos*) targ_emul=ppclynx ;;
rs6000-*-aix5*) targ_emul=aix5rs6 ;;
-rs6000-*-aix*) targ_emul=aixrs6 ;;
-tic30-*-*aout*) targ_emul=tic30aout ;;
-tic30-*-*coff*) targ_emul=tic30coff ;;
-tic4x-*-* | c4x-*-*) targ_emul=tic4xcoff ; targ_extra_emuls="tic3xcoff tic3xcoff_onchip" ;;
-tic54x-*-* | c54x*-*-*) targ_emul=tic54xcoff ;;
-tic80-*-*) targ_emul=tic80coff ;;
-v850-*-*) targ_emul=v850 ;;
-v850e-*-*) targ_emul=v850 ;;
-v850ea-*-*) targ_emul=v850 ;;
-iq2000-*-elf) targ_emul=elf32iq2000 ; targ_extra_emuls="elf32iq10" ;;
-frv-*-*linux*) targ_emul=elf32frvfd ;;
-frv-*-*) targ_emul=elf32frv ; targ_extra_emuls="elf32frvfd" ;;
-w65-*-*) targ_emul=w65 ;;
-xstormy16-*-*) targ_emul=elf32xstormy16 ;;
-xtensa-*-*) targ_emul=elf32xtensa;;
-fr30-*-*) targ_emul=elf32fr30 ;;
-mcore-*-pe) targ_emul=mcorepe ;
- targ_extra_ofiles="deffilep.o pe-dll.o" ;;
-mcore-*-elf) targ_emul=elf32mcore ;;
+rs6000-*-aix*) targ_emul=aixrs6
+ ;;
s390x-*-linux*) targ_emul=elf64_s390
targ_extra_emuls=elf_s390
targ_extra_libpath=$targ_extra_emuls
@@ -578,10 +440,131 @@ s390-*-linux*) targ_emul=elf_s390
targ_extra_emuls=elf64_s390
targ_extra_libpath=$targ_extra_emuls
tdir_elf64_s390=`echo ${targ_alias} | sed -e 's/s390/s390x/'`
- fi ;;
-*-*-ieee*) targ_emul=vanilla ;;
-ip2k-*-elf) targ_emul=elf32ip2k ;;
-
+ fi
+ ;;
+sh-*-linux*) targ_emul=shlelf_linux
+ targ_extra_emuls=shelf_linux
+ targ_extra_libpath=shelf_linux ;;
+sh64eb-*-linux*) targ_emul=shelf32_linux
+ targ_extra_emuls="shlelf32_linux" ;;
+sh64-*-linux*) targ_emul=shlelf32_linux
+ targ_extra_emuls="shelf32_linux"
+ targ_extra_libpath=shelf32_linux ;;
+sh*eb-*-linux*) targ_emul=shelf_linux ;;
+sh*-*-linux*) targ_emul=shlelf_linux ;;
+sh5le-*-netbsd*) targ_emul=shlelf32_nbsd
+ targ_extra_emuls="shelf32_nbsd shelf64_nbsd shlelf64_nbsd shelf_nbsd shlelf_nbsd" ;;
+sh5-*-netbsd*) targ_emul=shelf32_nbsd
+ targ_extra_emuls="shlelf32_nbsd shelf64_nbsd shlelf64_nbsd shelf_nbsd shlelf_nbsd" ;;
+sh64le-*-netbsd*) targ_emul=shlelf64_nbsd
+ targ_extra_emuls="shelf64_nbsd shelf32_nbsd shlelf32_nbsd shelf_nbsd shlelf_nbsd" ;;
+sh64-*-netbsd*) targ_emul=shelf64_nbsd
+ targ_extra_emuls="shlelf64_nbsd shelf32_nbsd shlelf32_nbsd shelf_nbsd shlelf_nbsd" ;;
+sh*l*-*-netbsdelf*) targ_emul=shlelf_nbsd
+ targ_extra_emuls=shelf_nbsd ;;
+sh*-*-netbsdelf*) targ_emul=shelf_nbsd
+ targ_extra_emuls=shlelf_nbsd ;;
+sh*-*-symbianelf*) targ_emul=shlsymbian ;;
+shle*-*-elf* | sh[1234]*le*-*-elf | shle*-*-kaos*)
+ targ_emul=shlelf
+ targ_extra_emuls="shelf shl sh" ;;
+sh-*-rtemscoff*) targ_emul=sh; targ_extra_emuls=shl ;;
+sh-*-elf* | sh[1234]*-*-elf | sh-*-rtems* | sh-*-kaos* | sh-*-vxworks)
+ targ_emul=shelf
+ targ_extra_emuls="shlelf sh shl" ;;
+sh-*-nto*) targ_emul=shelf_nto
+ targ_extra_emuls=shlelf_nto ;;
+sh-*-pe) targ_emul=shpe ;
+ targ_extra_ofiles="deffilep.o pe-dll.o" ;;
+sh-*-*) targ_emul=sh; targ_extra_emuls=shl ;;
+sh64le-*-elf*) targ_emul=shlelf
+ targ_extra_emuls="shelf shlelf32 shelf32 shlelf64 shelf64"
+ targ_extra_libpath=$targ_extra_emuls ;;
+sh64-*-elf*) targ_emul=shelf
+ targ_extra_emuls="shlelf shelf32 shlelf32 shelf64 shlelf64"
+ targ_extra_libpath=$targ_extra_emuls ;;
+sparc64-*-aout*) targ_emul=sparcaout ;;
+sparc64-*-elf*) targ_emul=elf64_sparc ;;
+sparc-sun-sunos4*) targ_emul=sun4 ;;
+sparclite*-*-elf) targ_emul=elf32_sparc ;;
+sparclite*-*-coff) targ_emul=coff_sparc ;;
+sparclite*-fujitsu-*) targ_emul=sparcaout ;;
+sparc*-*-aout) targ_emul=sparcaout ;;
+sparc*-*-coff) targ_emul=coff_sparc ;;
+sparc*-*-elf) targ_emul=elf32_sparc ;;
+sparc*-*-sysv4*) targ_emul=elf32_sparc ;;
+sparc64-*-freebsd* | sparcv9-*-freebsd* | sparc64-*-kfreebsd*-gnu | sparcv9-*-kfreebsd*-gnu)
+ targ_emul=elf64_sparc_fbsd
+ targ_extra_emuls="elf64_sparc elf32_sparc"
+ targ_extra_libpath=$targ_extra_emuls
+ tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/64//'` ;;
+sparc*-*-linux*aout*) targ_emul=sparclinux
+ targ_extra_emuls="elf32_sparc sun4"
+ tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/aout//'`
+ tdir_sun4=sparc-sun-sunos4 ;;
+sparc64-*-linux-*) targ_emul=elf64_sparc
+ targ_extra_emuls="elf32_sparc sparclinux sun4"
+ targ_extra_libpath=elf32_sparc
+ tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/64//'`
+ tdir_sparclinux=${tdir_elf32_sparc}aout
+ tdir_sun4=sparc-sun-sunos4 ;;
+sparc*-*-linux-*) targ_emul=elf32_sparc
+ targ_extra_emuls="sparclinux elf64_sparc sun4"
+ targ_extra_libpath=elf64_sparc
+ tdir_sparclinux=${targ_alias}aout
+ tdir_elf64_sparc=`echo ${targ_alias} | sed -e 's/32//'`
+ tdir_sun4=sparc-sun-sunos4 ;;
+sparc64-*-netbsd* | sparc64-*-openbsd*)
+ targ_emul=elf64_sparc
+ targ_extra_emuls="elf32_sparc" ;;
+sparc*-*-netbsd*elf*) targ_emul=elf32_sparc ;;
+sparc*-*-netbsd*) targ_emul=sparcnbsd ;;
+sparc-*-solaris2.[0-6] | sparc-*-solaris2.[0-6].*)
+ targ_emul=elf32_sparc ;;
+sparc-*-solaris2*) targ_emul=elf32_sparc
+ targ_extra_emuls="elf64_sparc"
+ targ_extra_libpath=$targ_extra_emuls
+ tdir_elf64_sparc=`echo ${targ_alias} | sed -e 's/32//'` ;;
+sparcv9-*-solaris2* | sparc64-*-solaris2*)
+ targ_emul=elf64_sparc
+ targ_extra_emuls="elf32_sparc"
+ targ_extra_libpath=$targ_extra_emuls
+ tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/64//'` ;;
+sparc*-*-solaris2*) targ_emul=elf32_sparc ;;
+sparc*-wrs-vxworks*) targ_emul=sparcaout ;;
+sparc*-*-rtemself*) targ_emul=elf32_sparc ;;
+sparc*-*-rtems*) targ_emul=elf32_sparc
+ ;;
+tic30-*-*aout*) targ_emul=tic30aout ;;
+tic30-*-*coff*) targ_emul=tic30coff ;;
+tic4x-*-* | c4x-*-*) targ_emul=tic4xcoff ; targ_extra_emuls="tic3xcoff tic3xcoff_onchip" ;;
+tic54x-*-* | c54x*-*-*) targ_emul=tic54xcoff ;;
+tic80-*-*) targ_emul=tic80coff
+ ;;
+v850-*-*) targ_emul=v850 ;;
+v850e-*-*) targ_emul=v850 ;;
+v850ea-*-*) targ_emul=v850
+ ;;
+vax-dec-ultrix* | vax-dec-bsd*) targ_emul=vax ;;
+vax-*-netbsdelf*) targ_emul=elf32vax
+ targ_extra_emuls=vaxnbsd ;;
+vax-*-netbsdaout* | vax-*-netbsd*)
+ targ_emul=vaxnbsd
+ targ_extra_emuls=elf32vax ;;
+vax-*-linux-*) targ_emul=elf32vax
+ ;;
+w65-*-*) targ_emul=w65
+ ;;
+xstormy16-*-*) targ_emul=elf32xstormy16
+ ;;
+xtensa-*-*) targ_emul=elf32xtensa
+ ;;
+z8k-*-coff) targ_emul=z8002; targ_extra_emuls=z8001
+ ;;
+*-*-ieee*) targ_emul=vanilla
+ ;;
+*-tandem-none) targ_emul=st2000
+ ;;
*)
echo 2>&1 "*** ld does not support target ${targ}"
echo 2>&1 "*** see ld/configure.tgt for supported targets"
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 41f8a13..6e22f80 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -166,6 +166,7 @@ if test x${all_targets} = xfalse ; then
bfd_d30v_arch) ta="$ta d30v-dis.lo d30v-opc.lo" ;;
bfd_dlx_arch) ta="$ta dlx-dis.lo" ;;
bfd_fr30_arch) ta="$ta fr30-asm.lo fr30-desc.lo fr30-dis.lo fr30-ibld.lo fr30-opc.lo" using_cgen=yes ;;
+ bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;;
bfd_h8300_arch) ta="$ta h8300-dis.lo" ;;
bfd_h8500_arch) ta="$ta h8500-dis.lo" ;;
bfd_hppa_arch) ta="$ta hppa-dis.lo" ;;
@@ -176,6 +177,7 @@ if test x${all_targets} = xfalse ; then
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;;
bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;;
+ bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;;
bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
@@ -230,8 +232,6 @@ if test x${all_targets} = xfalse ; then
bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;;
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
bfd_z8k_arch) ta="$ta z8k-dis.lo" ;;
- bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;;
- bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;;
"") ;;
*) AC_MSG_ERROR(*** unknown target architecture $arch) ;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 997a359..377e64f 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -30,6 +30,8 @@
#define ARCH_d10v
#define ARCH_d30v
#define ARCH_dlx
+#define ARCH_fr30
+#define ARCH_frv
#define ARCH_h8300
#define ARCH_h8500
#define ARCH_hppa
@@ -37,13 +39,14 @@
#define ARCH_i386
#define ARCH_i860
#define ARCH_i960
-#define ARCH_ip2k
#define ARCH_ia64
-#define ARCH_fr30
+#define ARCH_ip2k
+#define ARCH_iq2000
+#define ARCH_m32c
#define ARCH_m32r
-#define ARCH_m68k
#define ARCH_m68hc11
#define ARCH_m68hc12
+#define ARCH_m68k
#define ARCH_m88k
#define ARCH_maxq
#define ARCH_mcore
@@ -73,9 +76,6 @@
#define ARCH_xstormy16
#define ARCH_xtensa
#define ARCH_z8k
-#define ARCH_frv
-#define ARCH_iq2000
-#define ARCH_m32c
#define INCLUDE_SHMEDIA
#endif
diff --git a/opcodes/m32c-asm.c b/opcodes/m32c-asm.c
index 991d007..60c1055 100644
--- a/opcodes/m32c-asm.c
+++ b/opcodes/m32c-asm.c
@@ -1,26 +1,27 @@
/* Assembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-asm.in isn't
+ THIS FILE IS MACHINE GENERATED WITH CGEN.
+ - the resultant file is machine generated, cgen-asm.in isn't
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+ Free Software Foundation, Inc.
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+ This file is part of the GNU Binutils and GDB, the GNU debugger.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@@ -48,7 +49,7 @@ static const char * parse_insn_normal
/* -- assembler routines inserted here. */
/* -- asm.c */
-#include <ctype.h>
+#include "safe-ctype.h"
#define MACH_M32C 5 /* Must match md_begin. */
@@ -76,25 +77,40 @@ m32c_cgen_isa_register (const char **strp)
return 0;
}
+#define PARSE_UNSIGNED \
+ do \
+ { \
+ /* Don't successfully parse literals beginning with '['. */ \
+ if (**strp == '[') \
+ return "Invalid literal"; /* Anything -- will not be seen. */ \
+ \
+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);\
+ if (errmsg) \
+ return errmsg; \
+ } \
+ while (0)
+
+#define PARSE_SIGNED \
+ do \
+ { \
+ /* Don't successfully parse literals beginning with '['. */ \
+ if (**strp == '[') \
+ return "Invalid literal"; /* Anything -- will not be seen. */ \
+ \
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); \
+ if (errmsg) \
+ return errmsg; \
+ } \
+ while (0)
+
static const char *
parse_unsigned6 (CGEN_CPU_DESC cd, const char **strp,
int opindex, unsigned long *valuep)
{
const char *errmsg = 0;
unsigned long value;
- long have_zero = 0;
-
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-
- if (strncmp (*strp, "0x0", 3) == 0
- || (**strp == '0' && *(*strp + 1) != 'x'))
- have_zero = 1;
- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
- if (errmsg)
- return errmsg;
+ PARSE_UNSIGNED;
if (value > 0x3f)
return _("imm:6 immediate is out of range");
@@ -111,17 +127,11 @@ parse_unsigned8 (CGEN_CPU_DESC cd, const char **strp,
unsigned long value;
long have_zero = 0;
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-
if (strncmp (*strp, "0x0", 3) == 0
|| (**strp == '0' && *(*strp + 1) != 'x'))
have_zero = 1;
- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
- if (errmsg)
- return errmsg;
+ PARSE_UNSIGNED;
if (value > 0xff)
return _("dsp:8 immediate is out of range");
@@ -141,18 +151,12 @@ parse_signed4 (CGEN_CPU_DESC cd, const char **strp,
const char *errmsg = 0;
signed long value;
long have_zero = 0;
-
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
if (strncmp (*strp, "0x0", 3) == 0
|| (**strp == '0' && *(*strp + 1) != 'x'))
have_zero = 1;
- errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
- if (errmsg)
- return errmsg;
+ PARSE_SIGNED;
if (value < -8 || value > 7)
return _("Immediate is out of range -8 to 7");
@@ -172,13 +176,7 @@ parse_signed8 (CGEN_CPU_DESC cd, const char **strp,
const char *errmsg = 0;
signed long value;
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-
- errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
- if (errmsg)
- return errmsg;
+ PARSE_SIGNED;
if (value <= 255 && value > 127)
value -= 0x100;
@@ -198,13 +196,13 @@ parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp,
unsigned long value;
long have_zero = 0;
- /* Don't successfully parse literals beginning with '[' */
+ /* Don't successfully parse literals beginning with '['. */
if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
+ return "Invalid literal"; /* Anything -- will not be seen. */
- /* Don't successfully parse register names */
+ /* Don't successfully parse register names. */
if (m32c_cgen_isa_register (strp))
- return "Invalid literal"; /* anything -- will not be seen */
+ return "Invalid literal"; /* Anything -- will not be seen. */
if (strncmp (*strp, "0x0", 3) == 0
|| (**strp == '0' && *(*strp + 1) != 'x'))
@@ -234,14 +232,8 @@ parse_signed16 (CGEN_CPU_DESC cd, const char **strp,
{
const char *errmsg = 0;
signed long value;
-
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
- errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
- if (errmsg)
- return errmsg;
+ PARSE_SIGNED;
if (value <= 65535 && value > 32767)
value -= 0x10000;
@@ -260,13 +252,13 @@ parse_unsigned20 (CGEN_CPU_DESC cd, const char **strp,
const char *errmsg = 0;
unsigned long value;
- /* Don't successfully parse literals beginning with '[' */
+ /* Don't successfully parse literals beginning with '['. */
if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
+ return "Invalid literal"; /* Anything -- will not be seen. */
- /* Don't successfully parse register names */
+ /* Don't successfully parse register names. */
if (m32c_cgen_isa_register (strp))
- return "Invalid literal"; /* anything -- will not be seen */
+ return "Invalid literal"; /* Anything -- will not be seen. */
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
if (errmsg)
@@ -286,13 +278,13 @@ parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp,
const char *errmsg = 0;
unsigned long value;
- /* Don't successfully parse literals beginning with '[' */
+ /* Don't successfully parse literals beginning with '['. */
if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
+ return "Invalid literal"; /* Anything -- will not be seen. */
- /* Don't successfully parse register names */
+ /* Don't successfully parse register names. */
if (m32c_cgen_isa_register (strp))
- return "Invalid literal"; /* anything -- will not be seen */
+ return "Invalid literal"; /* Anything -- will not be seen. */
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
if (errmsg)
@@ -307,21 +299,11 @@ parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp,
static const char *
parse_signed32 (CGEN_CPU_DESC cd, const char **strp,
- int opindex, signed long *valuep)
+ int opindex, signed long *valuep)
{
const char *errmsg = 0;
signed long value;
-#if 0
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-
- /* Don't successfully parse register names */
- if (m32c_cgen_isa_register (strp))
- return "Invalid literal"; /* anything -- will not be seen */
-#endif
-
errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
if (errmsg)
return errmsg;
@@ -336,18 +318,8 @@ parse_imm1_S (CGEN_CPU_DESC cd, const char **strp,
{
const char *errmsg = 0;
signed long value;
-
-#if 0
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
- /* Don't successfully parse register names */
- if (m32c_cgen_isa_register (strp))
- return "Invalid literal"; /* anything -- will not be seen */
-#endif
-
- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
if (errmsg)
return errmsg;
@@ -365,17 +337,7 @@ parse_imm3_S (CGEN_CPU_DESC cd, const char **strp,
const char *errmsg = 0;
signed long value;
-#if 0
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-
- /* Don't successfully parse register names */
- if (m32c_cgen_isa_register (strp))
- return "Invalid literal"; /* anything -- will not be seen */
-#endif
-
- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
if (errmsg)
return errmsg;
@@ -387,18 +349,48 @@ parse_imm3_S (CGEN_CPU_DESC cd, const char **strp,
}
static const char *
+parse_lab_5_3 (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex ATTRIBUTE_UNUSED,
+ int opinfo,
+ enum cgen_parse_operand_result *type_addr,
+ unsigned long *valuep)
+{
+ const char *errmsg = 0;
+ unsigned long value;
+ enum cgen_parse_operand_result op_res;
+
+ errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_5_3,
+ opinfo, & op_res, & value);
+
+ if (type_addr)
+ *type_addr = op_res;
+
+ if (op_res == CGEN_PARSE_OPERAND_ADDRESS)
+ {
+ /* This is a hack; the field cannot handle near-zero signed
+ offsets that CGEN wants to put in to indicate an "empty"
+ operand at first. */
+ *valuep = 2;
+ return 0;
+ }
+ if (errmsg)
+ return errmsg;
+
+ if (value < 2 || value > 9)
+ return _("immediate is out of range 2-9");
+
+ *valuep = value;
+ return 0;
+}
+
+static const char *
parse_Bitno16R (CGEN_CPU_DESC cd, const char **strp,
int opindex, unsigned long *valuep)
{
const char *errmsg = 0;
unsigned long value;
-#if 0
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-#endif
-
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);
if (errmsg)
return errmsg;
@@ -421,12 +413,6 @@ parse_unsigned_bitbase (CGEN_CPU_DESC cd, const char **strp,
const char *newp = *strp;
unsigned long long bitbase;
-#if 0
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-#endif
-
errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit);
if (errmsg)
return errmsg;
@@ -439,7 +425,7 @@ parse_unsigned_bitbase (CGEN_CPU_DESC cd, const char **strp,
if (errmsg)
return errmsg;
- bitbase = (unsigned long long)bit + ((unsigned long long)base * 8);
+ bitbase = (unsigned long long) bit + ((unsigned long long) base * 8);
if (bitbase >= (1ull << bits))
return _("bit,base is out of range");
@@ -461,12 +447,6 @@ parse_signed_bitbase (CGEN_CPU_DESC cd, const char **strp,
long long bitbase;
long long limit;
-#if 0
- /* Don't successfully parse literals beginning with '[' */
- if (**strp == '[')
- return "Invalid literal"; /* anything -- will not be seen */
-#endif
-
errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit);
if (errmsg)
return errmsg;
@@ -547,21 +527,22 @@ parse_signed_bitbase19 (CGEN_CPU_DESC cd, const char **strp,
}
/* Parse the suffix as :<char> or as nothing followed by a whitespace. */
+
static const char *
parse_suffix (const char **strp, char suffix)
{
const char *newp = *strp;
- if (**strp == ':' && tolower (*(*strp + 1)) == suffix)
+ if (**strp == ':' && TOLOWER (*(*strp + 1)) == suffix)
newp = *strp + 2;
- if (isspace (*newp))
+ if (ISSPACE (*newp))
{
*strp = newp;
return 0;
}
- return "Invalid suffix"; /* anything -- will not be seen */
+ return "Invalid suffix"; /* Anything -- will not be seen. */
}
static const char *
@@ -593,6 +574,7 @@ parse_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp,
}
/* Parse an empty suffix. Fail if the next char is ':'. */
+
static const char *
parse_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp,
int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED)
@@ -611,16 +593,16 @@ parse_r0l_r0h (CGEN_CPU_DESC cd, const char **strp,
signed long junk;
const char *newp = *strp;
- /* Parse r0[hl] */
+ /* Parse r0[hl]. */
errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0l_r0h, & value);
if (errmsg)
return errmsg;
if (*newp != ',')
- return "not a valid r0l/r0h pair";
+ return _("not a valid r0l/r0h pair");
++newp;
- /* Parse the second register in the pair */
+ /* Parse the second register in the pair. */
if (value == 0) /* r0l */
errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0h, & junk);
else
@@ -633,7 +615,8 @@ parse_r0l_r0h (CGEN_CPU_DESC cd, const char **strp,
return 0;
}
-/* Accept .b or .w in any case */
+/* Accept .b or .w in any case. */
+
static const char *
parse_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp,
int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED)
@@ -643,196 +626,14 @@ parse_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp,
|| *(*strp + 1) == 'w' || *(*strp + 1) == 'W'))
{
*strp += 2;
- return 0;
+ return NULL;
}
- return "Invalid size specifier";
+
+ return _("Invalid size specifier");
}
-/* static const char * parse_abs (CGEN_CPU_DESC, const char **, int, */
-/* unsigned long *, unsigned long); */
-/* static const char * parse_abs16 (CGEN_CPU_DESC, const char **, int, */
-/* int ATTRIBUTE_UNUSED, */
-/* enum cgen_parse_operand_result * ATTRIBUTE_UNUSED, */
-/* unsigned long * ); */
-/* static const char * parse_abs24 (CGEN_CPU_DESC, const char **, int, */
-/* int ATTRIBUTE_UNUSED, */
-/* enum cgen_parse_operand_result * ATTRIBUTE_UNUSED, */
-/* unsigned long *); */
-
-/* /\* Parse absolute *\/ */
-
-/* static const char * */
-/* parse_abs16 (CGEN_CPU_DESC cd, const char **strp, int opindex, */
-/* int reloc ATTRIBUTE_UNUSED, */
-/* enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED, */
-/* unsigned long *valuep) */
-/* { */
-/* return parse_abs (cd, strp, opindex, valuep, 16); */
-/* } */
-
-/* static const char * */
-/* parse_abs24 (CGEN_CPU_DESC cd, const char **strp, int opindex, */
-/* int reloc ATTRIBUTE_UNUSED, */
-/* enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED, */
-/* unsigned long *valuep) */
-/* { */
-/* return parse_abs (cd, strp, opindex, valuep, 24); */
-/* } */
-
-/* static const char * */
-/* parse_abs (CGEN_CPU_DESC cd, const char **strp, int opindex, */
-/* unsigned long *valuep, */
-/* unsigned long length) */
-/* { */
-/* const char *errmsg = 0; */
-/* const char *op; */
-/* int has_register = 0; */
-
-/* for (op = *strp; *op != '\0'; op++) */
-/* { */
-/* if (*op == '[') */
-/* { */
-/* has_register = 1; */
-/* break; */
-/* } */
-/* else if (*op == ',') */
-/* break; */
-/* } */
-
-/* if (has_register || m32c_cgen_isa_register (strp)) */
-/* errmsg = _("immediate value cannot be register"); */
-/* else */
-/* { */
-/* enum cgen_parse_operand_result result_type; */
-/* bfd_vma value; */
-/* const char *errmsg; */
-
-/* errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, */
-/* &result_type, &value); */
-/* *valuep = value; */
-/* } */
-/* return errmsg; */
-/* } */
-/* /\* Handle signed/unsigned literal. *\/ */
-
-/* static const char * */
-/* parse_imm8 (cd, strp, opindex, valuep) */
-/* CGEN_CPU_DESC cd; */
-/* const char **strp; */
-/* int opindex; */
-/* unsigned long *valuep; */
-/* { */
-/* const char *errmsg = 0; */
-/* long value; */
-/* long have_zero = 0; */
-
-/* if (strncmp (*strp, "0x0", 3) == 0 */
-/* || (**strp == '0' && *(*strp + 1) != 'x')) */
-/* have_zero = 1; */
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */
-/* *valuep = value; */
-/* /\* If this field may require a relocation then use larger dsp16. *\/ */
-/* if (! have_zero && value == 0) */
-/* errmsg = _("immediate value may not fit in dsp8 field"); */
-
-/* return errmsg; */
-/* } */
-
-/* static const char * */
-/* parse_imm16 (cd, strp, opindex, valuep) */
-/* CGEN_CPU_DESC cd; */
-/* const char **strp; */
-/* int opindex; */
-/* unsigned long *valuep; */
-/* { */
-/* const char *errmsg; */
-/* long value; */
-
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */
-/* *valuep = value; */
-/* return errmsg; */
-/* } */
-
-/* static const char * */
-/* parse_imm24 (cd, strp, opindex, valuep) */
-/* CGEN_CPU_DESC cd; */
-/* const char **strp; */
-/* int opindex; */
-/* unsigned long *valuep; */
-/* { */
-/* const char *errmsg; */
-/* long value; */
-
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */
-/* *valuep = value; */
-/* return errmsg; */
-/* } */
-
-/* static const char * */
-/* parse_imm32 (cd, strp, opindex, valuep) */
-/* CGEN_CPU_DESC cd; */
-/* const char **strp; */
-/* int opindex; */
-/* unsigned long *valuep; */
-/* { */
-/* const char *errmsg; */
-/* long value; */
-
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */
-/* *valuep = value; */
-/* return errmsg; */
-/* } */
-
-/* /\* Handle bitfields. *\/ */
-
-/* static const char * */
-/* parse_boff8 (cd, strp, opindex, valuep) */
-/* CGEN_CPU_DESC cd; */
-/* const char **strp; */
-/* int opindex; */
-/* unsigned long *valuep; */
-/* { */
-/* const char *errmsg; */
-/* long bit_value, value; */
-
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & bit_value); */
-/* if (errmsg == 0) */
-/* { */
-/* *strp = *strp + 1; */
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */
-/* } */
-/* value = value * 8 + bit_value; */
-/* *valuep = value; */
-/* if (value > 0x100) */
-/* errmsg = _("Operand out of range. Must be between 0 and 255."); */
-/* return errmsg; */
-/* } */
-
-/* static const char * */
-/* parse_boff16 (cd, strp, opindex, valuep) */
-/* CGEN_CPU_DESC cd; */
-/* const char **strp; */
-/* int opindex; */
-/* unsigned long *valuep; */
-/* { */
-/* const char *errmsg; */
-/* long bit_value, value; */
-
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & bit_value); */
-/* if (errmsg == 0) */
-/* { */
-/* *strp = *strp + 1; */
-/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */
-/* } */
-/* value = value * 8 + bit_value; */
-/* *valuep = value; */
-/* if (value > 0x1000) */
-/* errmsg = _("Operand out of range. Must be between 0 and 65535."); */
-/* return errmsg; */
-/* } */
-
-
-/* Special check to ensure that instruction exists for given machine */
+/* Special check to ensure that instruction exists for given machine. */
+
int
m32c_cgen_insn_supported (CGEN_CPU_DESC cd,
const CGEN_INSN *insn)
@@ -840,7 +641,7 @@ m32c_cgen_insn_supported (CGEN_CPU_DESC cd,
int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
int isas = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ISA);
- /* If attributes are absent, assume no restriction. */
+ /* If attributes are absent, assume no restriction. */
if (machs == 0)
machs = ~0;
@@ -855,8 +656,7 @@ parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
const char **strp,
int opindex ATTRIBUTE_UNUSED,
unsigned long *valuep,
- int push
- )
+ int push)
{
const char *errmsg = 0;
int regno = 0;
@@ -912,23 +712,23 @@ parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
return errmsg;
}
-#define POP 0
+#define POP 0
#define PUSH 1
static const char *
parse_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- unsigned long *valuep)
+ const char **strp,
+ int opindex ATTRIBUTE_UNUSED,
+ unsigned long *valuep)
{
return parse_regset (cd, strp, opindex, valuep, POP);
}
static const char *
parse_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- const char **strp,
- int opindex ATTRIBUTE_UNUSED,
- unsigned long *valuep)
+ const char **strp,
+ int opindex ATTRIBUTE_UNUSED,
+ unsigned long *valuep)
{
return parse_regset (cd, strp, opindex, valuep, PUSH);
}
@@ -936,7 +736,7 @@ parse_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* -- dis.c */
const char * m32c_cgen_parse_operand
- PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+ (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
/* Main entry point for operand parsing.
@@ -952,11 +752,10 @@ const char * m32c_cgen_parse_operand
the handlers. */
const char *
-m32c_cgen_parse_operand (cd, opindex, strp, fields)
- CGEN_CPU_DESC cd;
- int opindex;
- const char ** strp;
- CGEN_FIELDS * fields;
+m32c_cgen_parse_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ const char ** strp,
+ CGEN_FIELDS * fields)
{
const char * errmsg = NULL;
/* Used by scalar operands that still need to be parsed. */
@@ -992,7 +791,7 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields)
errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_dst32_rn_unprefixed_QI);
break;
case M32C_OPERAND_BITBASE16_16_S8 :
- errmsg = parse_signed_bitbase8 (cd, strp, M32C_OPERAND_BITBASE16_16_S8, (unsigned long *) (& fields->f_dsp_16_s8));
+ errmsg = parse_signed_bitbase8 (cd, strp, M32C_OPERAND_BITBASE16_16_S8, (long *) (& fields->f_dsp_16_s8));
break;
case M32C_OPERAND_BITBASE16_16_U16 :
errmsg = parse_unsigned_bitbase16 (cd, strp, M32C_OPERAND_BITBASE16_16_U16, (unsigned long *) (& fields->f_dsp_16_u16));
@@ -1001,7 +800,7 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields)
errmsg = parse_unsigned_bitbase8 (cd, strp, M32C_OPERAND_BITBASE16_16_U8, (unsigned long *) (& fields->f_dsp_16_u8));
break;
case M32C_OPERAND_BITBASE16_8_U11_S :
- errmsg = parse_unsigned_bitbase11 (cd, strp, M32C_OPERAND_BITBASE16_8_U11_S, (long *) (& fields->f_bitbase16_u11_S));
+ errmsg = parse_unsigned_bitbase11 (cd, strp, M32C_OPERAND_BITBASE16_8_U11_S, (unsigned long *) (& fields->f_bitbase16_u11_S));
break;
case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED :
errmsg = parse_signed_bitbase11 (cd, strp, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, (long *) (& fields->f_bitbase32_16_s11_unprefixed));
@@ -1100,10 +899,10 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields)
errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_32_U8, (unsigned long *) (& fields->f_dsp_32_u8));
break;
case M32C_OPERAND_DSP_40_S16 :
- errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_40_S16, (unsigned long *) (& fields->f_dsp_40_s16));
+ errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_40_S16, (long *) (& fields->f_dsp_40_s16));
break;
case M32C_OPERAND_DSP_40_S8 :
- errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_40_S8, (unsigned long *) (& fields->f_dsp_40_s8));
+ errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_40_S8, (long *) (& fields->f_dsp_40_s8));
break;
case M32C_OPERAND_DSP_40_U16 :
errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_40_U16, (unsigned long *) (& fields->f_dsp_40_u16));
@@ -1115,10 +914,10 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields)
errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_40_U8, (unsigned long *) (& fields->f_dsp_40_u8));
break;
case M32C_OPERAND_DSP_48_S16 :
- errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_48_S16, (unsigned long *) (& fields->f_dsp_48_s16));
+ errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_48_S16, (long *) (& fields->f_dsp_48_s16));
break;
case M32C_OPERAND_DSP_48_S8 :
- errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_48_S8, (unsigned long *) (& fields->f_dsp_48_s8));
+ errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_48_S8, (long *) (& fields->f_dsp_48_s8));
break;
case M32C_OPERAND_DSP_48_U16 :
errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_48_U16, (unsigned long *) (& fields->f_dsp_48_u16));
@@ -1135,6 +934,9 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields)
case M32C_OPERAND_DSP_8_U16 :
errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_8_U16, (unsigned long *) (& fields->f_dsp_8_u16));
break;
+ case M32C_OPERAND_DSP_8_U24 :
+ errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_8_U24, (unsigned long *) (& fields->f_dsp_8_u24));
+ break;
case M32C_OPERAND_DSP_8_U6 :
errmsg = parse_unsigned6 (cd, strp, M32C_OPERAND_DSP_8_U6, (unsigned long *) (& fields->f_dsp_8_u6));
break;
@@ -1238,7 +1040,7 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields)
errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_12_S4, (long *) (& fields->f_imm_12_s4));
break;
case M32C_OPERAND_IMM_13_U3 :
- errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_13_U3, (unsigned long *) (& fields->f_imm_13_u3));
+ errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_13_U3, (long *) (& fields->f_imm_13_u3));
break;
case M32C_OPERAND_IMM_16_HI :
errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_16_HI, (long *) (& fields->f_dsp_16_s16));
@@ -1352,7 +1154,7 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields)
case M32C_OPERAND_LAB_5_3 :
{
bfd_vma value = 0;
- errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_5_3, 0, NULL, & value);
+ errmsg = parse_lab_5_3 (cd, strp, M32C_OPERAND_LAB_5_3, 0, NULL, & value);
fields->f_lab_5_3 = value;
}
break;
@@ -1380,7 +1182,7 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields)
case M32C_OPERAND_LAB32_JMP_S :
{
bfd_vma value = 0;
- errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB32_JMP_S, 0, NULL, & value);
+ errmsg = parse_lab_5_3 (cd, strp, M32C_OPERAND_LAB32_JMP_S, 0, NULL, & value);
fields->f_lab32_jmp_s = value;
}
break;
@@ -1574,8 +1376,7 @@ cgen_parse_fn * const m32c_cgen_parse_handlers[] =
};
void
-m32c_cgen_init_asm (cd)
- CGEN_CPU_DESC cd;
+m32c_cgen_init_asm (CGEN_CPU_DESC cd)
{
m32c_cgen_init_opcode_table (cd);
m32c_cgen_init_ibld_table (cd);
@@ -1958,30 +1759,3 @@ m32c_cgen_assemble_insn (CGEN_CPU_DESC cd,
return NULL;
}
}
-
-#if 0 /* This calls back to GAS which we can't do without care. */
-
-/* Record each member of OPVALS in the assembler's symbol table.
- This lets GAS parse registers for us.
- ??? Interesting idea but not currently used. */
-
-/* Record each member of OPVALS in the assembler's symbol table.
- FIXME: Not currently used. */
-
-void
-m32c_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
-{
- CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
- const CGEN_KEYWORD_ENTRY * ke;
-
- while ((ke = cgen_keyword_search_next (& search)) != NULL)
- {
-#if 0 /* Unnecessary, should be done in the search routine. */
- if (! m32c_cgen_opval_supported (ke))
- continue;
-#endif
- cgen_asm_record_register (cd, ke->name, ke->value);
- }
-}
-
-#endif /* 0 */
diff --git a/opcodes/m32c-desc.c b/opcodes/m32c-desc.c
index e721d35..a86c086 100644
--- a/opcodes/m32c-desc.c
+++ b/opcodes/m32c-desc.c
@@ -824,6 +824,7 @@ const CGEN_IFLD m32c_cgen_ifld_table[] =
{ M32C_F_16_1, "f-16-1", 0, 32, 16, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
{ M32C_F_16_2, "f-16-2", 0, 32, 16, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
{ M32C_F_16_4, "f-16-4", 0, 32, 16, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
+ { M32C_F_16_8, "f-16-8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
{ M32C_F_18_1, "f-18-1", 0, 32, 18, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
{ M32C_F_18_2, "f-18-2", 0, 32, 18, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
{ M32C_F_18_3, "f-18-3", 0, 32, 18, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
@@ -833,6 +834,8 @@ const CGEN_IFLD m32c_cgen_ifld_table[] =
{ M32C_F_20_4, "f-20-4", 0, 32, 20, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
{ M32C_F_21_3, "f-21-3", 0, 32, 21, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
{ M32C_F_24_2, "f-24-2", 0, 32, 24, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
+ { M32C_F_24_8, "f-24-8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
+ { M32C_F_32_16, "f-32-16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
{ M32C_F_SRC16_RN, "f-src16-rn", 0, 32, 10, 2, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
{ M32C_F_SRC16_AN, "f-src16-an", 0, 32, 11, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
{ M32C_F_SRC32_AN_UNPREFIXED, "f-src32-an-unprefixed", 0, 32, 11, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
@@ -895,6 +898,7 @@ const CGEN_IFLD m32c_cgen_ifld_table[] =
{ M32C_F_DSP_48_U16, "f-dsp-48-u16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
{ M32C_F_DSP_48_S16, "f-dsp-48-s16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
{ M32C_F_DSP_64_U16, "f-dsp-64-u16", 64, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
+ { M32C_F_DSP_8_U24, "f-dsp-8-u24", 0, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
{ M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
{ M32C_F_DSP_24_U24, "f-dsp-24-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
{ M32C_F_DSP_32_U24, "f-dsp-32-u24", 32, 32, 0, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
@@ -1466,6 +1470,10 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
{ "Dsp-8-s8", M32C_OPERAND_DSP_8_S8, HW_H_SINT, 8, 8,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
+/* Dsp-8-u24: unsigned 24 bit displacement at offset 8 bits */
+ { "Dsp-8-u24", M32C_OPERAND_DSP_8_U24, HW_H_UINT, 8, 24,
+ { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U24] } },
+ { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Dsp-10-u6: unsigned 6 bit displacement at offset 10 bits */
{ "Dsp-10-u6", M32C_OPERAND_DSP_10_U6, HW_H_UINT, 10, 6,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_10_U6] } },
@@ -1547,7 +1555,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Dsp-40-s8: signed 8 bit displacement at offset 40 bits */
- { "Dsp-40-s8", M32C_OPERAND_DSP_40_S8, HW_H_UINT, 8, 8,
+ { "Dsp-40-s8", M32C_OPERAND_DSP_40_S8, HW_H_SINT, 8, 8,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Dsp-40-u16: unsigned 16 bit displacement at offset 40 bits */
@@ -1555,7 +1563,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U16] } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Dsp-40-s16: signed 16 bit displacement at offset 40 bits */
- { "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_UINT, 8, 16,
+ { "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_SINT, 8, 16,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Dsp-40-u24: unsigned 24 bit displacement at offset 40 bits */
@@ -1567,7 +1575,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U8] } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Dsp-48-s8: signed 8 bit displacement at offset 48 bits */
- { "Dsp-48-s8", M32C_OPERAND_DSP_48_S8, HW_H_UINT, 16, 8,
+ { "Dsp-48-s8", M32C_OPERAND_DSP_48_S8, HW_H_SINT, 16, 8,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Dsp-48-u16: unsigned 16 bit displacement at offset 48 bits */
@@ -1575,7 +1583,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Dsp-48-s16: signed 16 bit displacement at offset 48 bits */
- { "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_UINT, 16, 16,
+ { "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Dsp-48-u24: unsigned 24 bit displacement at offset 48 bits */
@@ -1607,7 +1615,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Imm-13-u3: signed 3 bit immediate at offset 13 bits */
- { "Imm-13-u3", M32C_OPERAND_IMM_13_U3, HW_H_UINT, 13, 3,
+ { "Imm-13-u3", M32C_OPERAND_IMM_13_U3, HW_H_SINT, 13, 3,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_13_U3] } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Imm-20-s4: signed 4 bit immediate at offset 20 bits */
@@ -1715,7 +1723,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
/* BitBase16-16-s8: signed bit,base:8 at offset 16for m16c */
- { "BitBase16-16-s8", M32C_OPERAND_BITBASE16_16_S8, HW_H_UINT, 16, 8,
+ { "BitBase16-16-s8", M32C_OPERAND_BITBASE16_16_S8, HW_H_SINT, 16, 8,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
/* BitBase16-16-u16: unsigned bit,base:16 at offset 16 for m16c */
@@ -1723,7 +1731,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
/* BitBase16-8-u11-S: signed bit,base:11 at offset 16 for m16c */
- { "BitBase16-8-u11-S", M32C_OPERAND_BITBASE16_8_U11_S, HW_H_SINT, 5, 11,
+ { "BitBase16-8-u11-S", M32C_OPERAND_BITBASE16_8_U11_S, HW_H_UINT, 5, 11,
{ 2, { (const PTR) &M32C_F_BITBASE16_U11_S_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C) } } },
/* BitBase32-16-u11-Unprefixed: unsigned bit,base:11 at offset 16 for m32c */
@@ -1769,19 +1777,19 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
/* Lab-5-3: 3 bit label */
{ "Lab-5-3", M32C_OPERAND_LAB_5_3, HW_H_IADDR, 5, 3,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_5_3] } },
- { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
+ { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Lab32-jmp-s: 3 bit label */
{ "Lab32-jmp-s", M32C_OPERAND_LAB32_JMP_S, HW_H_IADDR, 2, 3,
{ 2, { (const PTR) &M32C_F_LAB32_JMP_S_MULTI_IFIELD[0] } },
- { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
+ { 0|A(RELAX)|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Lab-8-8: 8 bit label */
{ "Lab-8-8", M32C_OPERAND_LAB_8_8, HW_H_IADDR, 8, 8,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_8] } },
- { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
+ { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Lab-8-16: 16 bit label */
{ "Lab-8-16", M32C_OPERAND_LAB_8_16, HW_H_IADDR, 8, 16,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_16] } },
- { 0|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
+ { 0|A(RELAX)|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Lab-8-24: 24 bit label */
{ "Lab-8-24", M32C_OPERAND_LAB_8_24, HW_H_IADDR, 8, 24,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_24] } },
@@ -1789,7 +1797,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
/* Lab-16-8: 8 bit label */
{ "Lab-16-8", M32C_OPERAND_LAB_16_8, HW_H_IADDR, 16, 8,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_16_8] } },
- { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
+ { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
/* Lab-24-8: 8 bit label */
{ "Lab-24-8", M32C_OPERAND_LAB_24_8, HW_H_IADDR, 24, 8,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_24_8] } },
@@ -29584,71 +29592,6 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-16-absolute-QI", "mov.b", 24,
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
},
-/* mov.b${S} #${Imm-8-QI},r0l */
- {
- M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 16,
- { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
- },
-/* mov.b${S} #${Imm-8-QI},r0h */
- {
- M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 16,
- { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
- },
-/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
- {
- M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "mov.b", 24,
- { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
- },
-/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
- {
- M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "mov.b", 24,
- { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
- },
-/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */
- {
- M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "mov.b", 32,
- { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
- },
-/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
- {
- M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 32,
- { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
- },
-/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
- {
- M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 32,
- { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
- },
-/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */
- {
- M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 40,
- { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
- },
-/* mov.w${S} #${Imm-8-HI},r0 */
- {
- M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 24,
- { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
- },
-/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
- {
- M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 24,
- { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
- },
-/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
- {
- M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 24,
- { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
- },
-/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */
- {
- M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 32,
- { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
- },
-/* mov.b${S} #${Imm-8-QI},r0l */
- {
- M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 16,
- { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
- },
/* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
{
M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
@@ -29859,6 +29802,71 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm4-Q-16-dst16-16-16-absolute-QI", "mov.b", 32,
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
},
+/* mov.b${S} #${Imm-8-QI},r0l */
+ {
+ M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+ },
+/* mov.b${S} #${Imm-8-QI},r0h */
+ {
+ M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+ },
+/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
+ {
+ M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "mov.b", 24,
+ { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+ },
+/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
+ {
+ M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "mov.b", 24,
+ { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+ },
+/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */
+ {
+ M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "mov.b", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
+ },
+/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
+ {
+ M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+ },
+/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
+ {
+ M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+ },
+/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */
+ {
+ M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 40,
+ { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+ },
+/* mov.w${S} #${Imm-8-HI},r0 */
+ {
+ M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 24,
+ { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+ },
+/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
+ {
+ M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 24,
+ { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+ },
+/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
+ {
+ M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 24,
+ { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+ },
+/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */
+ {
+ M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+ },
+/* mov.b${S} #${Imm-8-QI},r0l */
+ {
+ M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
+ },
/* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
{
M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "mov.l", 48,
@@ -61737,32 +61745,32 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
/* j$cond16j5 ${Lab-8-8} */
{
M32C_INSN_JCND16_5, "jcnd16-5", "j", 16,
- { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+ { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
},
/* j$cond16j ${Lab-16-8} */
{
M32C_INSN_JCND16, "jcnd16", "j", 24,
- { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+ { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
},
/* j$cond32j ${Lab-8-8} */
{
M32C_INSN_JCND32, "jcnd32", "j", 16,
- { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+ { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
},
/* jmp.s ${Lab-5-3} */
{
M32C_INSN_JMP16_S, "jmp16.s", "jmp.s", 8,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+ { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
},
/* jmp.b ${Lab-8-8} */
{
M32C_INSN_JMP16_B, "jmp16.b", "jmp.b", 16,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+ { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
},
/* jmp.w ${Lab-8-16} */
{
M32C_INSN_JMP16_W, "jmp16.w", "jmp.w", 24,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+ { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
},
/* jmp.a ${Lab-8-24} */
{
@@ -61777,17 +61785,17 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
/* jmp.s ${Lab32-jmp-s} */
{
M32C_INSN_JMP32_S, "jmp32.s", "jmp.s", 8,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+ { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
},
/* jmp.b ${Lab-8-8} */
{
M32C_INSN_JMP32_B, "jmp32.b", "jmp.b", 16,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+ { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
},
/* jmp.w ${Lab-8-16} */
{
M32C_INSN_JMP32_W, "jmp32.w", "jmp.w", 24,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+ { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
},
/* jmp.a ${Lab-8-24} */
{
@@ -61802,7 +61810,7 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
/* jsr.w ${Lab-8-16} */
{
M32C_INSN_JSR16_W, "jsr16.w", "jsr.w", 24,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
+ { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
},
/* jsr.a ${Lab-8-24} */
{
@@ -61812,7 +61820,7 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
/* jsr.w ${Lab-8-16} */
{
M32C_INSN_JSR32_W, "jsr32.w", "jsr.w", 24,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
+ { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
},
/* jsr.a ${Lab-8-24} */
{
@@ -61909,12 +61917,12 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
M32C_INSN_MOV32_W_A1, "mov32-w-a1", "mov.w", 24,
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
},
-/* mov.l$S #${Dsp-16-u24},a0 */
+/* mov.l$S #${Dsp-8-u24},a0 */
{
M32C_INSN_MOV32_L_A0, "mov32-l-a0", "mov.l", 32,
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
},
-/* mov.l$S #${Dsp-16-u24},a1 */
+/* mov.l$S #${Dsp-8-u24},a1 */
{
M32C_INSN_MOV32_L_A1, "mov32-l-a1", "mov.l", 32,
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
@@ -62265,27 +62273,23 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
#undef A
/* Initialize anything needed to be done once, before any cpu_open call. */
-static void init_tables PARAMS ((void));
static void
-init_tables ()
+init_tables (void)
{
}
-static const CGEN_MACH * lookup_mach_via_bfd_name
- PARAMS ((const CGEN_MACH *, const char *));
-static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
-static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
-static void m32c_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table (CGEN_CPU_TABLE *);
+static void build_ifield_table (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table (CGEN_CPU_TABLE *);
+static void m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *);
/* Subroutine of m32c_cgen_cpu_open to look up a mach via its bfd name. */
static const CGEN_MACH *
-lookup_mach_via_bfd_name (table, name)
- const CGEN_MACH *table;
- const char *name;
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
{
while (table->name)
{
@@ -62299,8 +62303,7 @@ lookup_mach_via_bfd_name (table, name)
/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
static void
-build_hw_table (cd)
- CGEN_CPU_TABLE *cd;
+build_hw_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@@ -62326,8 +62329,7 @@ build_hw_table (cd)
/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
static void
-build_ifield_table (cd)
- CGEN_CPU_TABLE *cd;
+build_ifield_table (CGEN_CPU_TABLE *cd)
{
cd->ifld_table = & m32c_cgen_ifld_table[0];
}
@@ -62335,8 +62337,7 @@ build_ifield_table (cd)
/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
static void
-build_operand_table (cd)
- CGEN_CPU_TABLE *cd;
+build_operand_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@@ -62344,8 +62345,7 @@ build_operand_table (cd)
/* MAX_OPERANDS is only an upper bound on the number of selected entries.
However each entry is indexed by it's enum so there can be holes in
the table. */
- const CGEN_OPERAND **selected =
- (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+ const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
cd->operand_table.init_entries = init;
cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@@ -62368,12 +62368,11 @@ build_operand_table (cd)
operand elements to be in the table [which they mightn't be]. */
static void
-build_insn_table (cd)
- CGEN_CPU_TABLE *cd;
+build_insn_table (CGEN_CPU_TABLE *cd)
{
int i;
const CGEN_IBASE *ib = & m32c_cgen_insn_table[0];
- CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+ CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
for (i = 0; i < MAX_INSNS; ++i)
@@ -62386,8 +62385,7 @@ build_insn_table (cd)
/* Subroutine of m32c_cgen_cpu_open to rebuild the tables. */
static void
-m32c_cgen_rebuild_tables (cd)
- CGEN_CPU_TABLE *cd;
+m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
{
int i;
unsigned int isas = cd->isas;
@@ -62399,7 +62397,7 @@ m32c_cgen_rebuild_tables (cd)
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
cd->default_insn_bitsize = UNSET;
cd->base_insn_bitsize = UNSET;
- cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+ cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
cd->max_insn_bitsize = 0;
for (i = 0; i < MAX_ISAS; ++i)
if (((1 << i) & isas) != 0)
@@ -62411,7 +62409,7 @@ m32c_cgen_rebuild_tables (cd)
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
- ; /* this is ok */
+ ; /* This is ok. */
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
@@ -62420,7 +62418,7 @@ m32c_cgen_rebuild_tables (cd)
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
- ; /* this is ok */
+ ; /* This is ok. */
else
cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
@@ -62532,12 +62530,12 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
}
va_end (ap);
- /* mach unspecified means "all" */
+ /* Mach unspecified means "all". */
if (machs == 0)
machs = (1 << MAX_MACHS) - 1;
- /* base mach is always selected */
+ /* Base mach is always selected. */
machs |= 1;
- /* isa unspecified means "all" */
+ /* ISA unspecified means "all". */
if (isas == 0)
isas = (1 << MAX_ISAS) - 1;
if (endian == CGEN_ENDIAN_UNKNOWN)
@@ -62570,9 +62568,7 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
MACH_NAME is the bfd name of the mach. */
CGEN_CPU_DESC
-m32c_cgen_cpu_open_1 (mach_name, endian)
- const char *mach_name;
- enum cgen_endian endian;
+m32c_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
{
return m32c_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
CGEN_CPU_OPEN_ENDIAN, endian,
@@ -62585,8 +62581,7 @@ m32c_cgen_cpu_open_1 (mach_name, endian)
place as some simulator ports use this but they don't use libopcodes. */
void
-m32c_cgen_cpu_close (cd)
- CGEN_CPU_DESC cd;
+m32c_cgen_cpu_close (CGEN_CPU_DESC cd)
{
unsigned int i;
const CGEN_INSN *insns;
@@ -62595,23 +62590,17 @@ m32c_cgen_cpu_close (cd)
{
insns = cd->macro_insn_table.init_entries;
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
- {
- if (CGEN_INSN_RX ((insns)))
- regfree (CGEN_INSN_RX (insns));
- }
+ if (CGEN_INSN_RX ((insns)))
+ regfree (CGEN_INSN_RX (insns));
}
if (cd->insn_table.init_entries)
{
insns = cd->insn_table.init_entries;
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
- {
- if (CGEN_INSN_RX (insns))
- regfree (CGEN_INSN_RX (insns));
- }
- }
-
-
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+ }
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
diff --git a/opcodes/m32c-desc.h b/opcodes/m32c-desc.h
index 277c90b..ef27541 100644
--- a/opcodes/m32c-desc.h
+++ b/opcodes/m32c-desc.h
@@ -104,24 +104,25 @@ typedef enum ifield_type {
, M32C_F_11_1, M32C_F_12_1, M32C_F_12_2, M32C_F_12_3
, M32C_F_12_4, M32C_F_12_6, M32C_F_13_3, M32C_F_14_1
, M32C_F_14_2, M32C_F_15_1, M32C_F_16_1, M32C_F_16_2
- , M32C_F_16_4, M32C_F_18_1, M32C_F_18_2, M32C_F_18_3
- , M32C_F_20_1, M32C_F_20_3, M32C_F_20_2, M32C_F_20_4
- , M32C_F_21_3, M32C_F_24_2, M32C_F_SRC16_RN, M32C_F_SRC16_AN
- , M32C_F_SRC32_AN_UNPREFIXED, M32C_F_SRC32_AN_PREFIXED, M32C_F_SRC32_RN_UNPREFIXED_QI, M32C_F_SRC32_RN_PREFIXED_QI
- , M32C_F_SRC32_RN_UNPREFIXED_HI, M32C_F_SRC32_RN_PREFIXED_HI, M32C_F_SRC32_RN_UNPREFIXED_SI, M32C_F_SRC32_RN_PREFIXED_SI
- , M32C_F_DST32_RN_EXT_UNPREFIXED, M32C_F_DST16_RN, M32C_F_DST16_RN_EXT, M32C_F_DST16_RN_QI_S
- , M32C_F_DST16_AN, M32C_F_DST16_AN_S, M32C_F_DST32_AN_UNPREFIXED, M32C_F_DST32_AN_PREFIXED
- , M32C_F_DST32_RN_UNPREFIXED_QI, M32C_F_DST32_RN_PREFIXED_QI, M32C_F_DST32_RN_UNPREFIXED_HI, M32C_F_DST32_RN_PREFIXED_HI
- , M32C_F_DST32_RN_UNPREFIXED_SI, M32C_F_DST32_RN_PREFIXED_SI, M32C_F_DST16_1_S, M32C_F_IMM_8_S4
- , M32C_F_IMM_12_S4, M32C_F_IMM_13_U3, M32C_F_IMM_20_S4, M32C_F_IMM1_S
- , M32C_F_IMM3_S, M32C_F_DSP_8_U6, M32C_F_DSP_8_U8, M32C_F_DSP_8_S8
- , M32C_F_DSP_10_U6, M32C_F_DSP_16_U8, M32C_F_DSP_16_S8, M32C_F_DSP_24_U8
- , M32C_F_DSP_24_S8, M32C_F_DSP_32_U8, M32C_F_DSP_32_S8, M32C_F_DSP_40_U8
- , M32C_F_DSP_40_S8, M32C_F_DSP_48_U8, M32C_F_DSP_48_S8, M32C_F_DSP_56_U8
- , M32C_F_DSP_56_S8, M32C_F_DSP_64_U8, M32C_F_DSP_64_S8, M32C_F_DSP_8_U16
- , M32C_F_DSP_8_S16, M32C_F_DSP_16_U16, M32C_F_DSP_16_S16, M32C_F_DSP_24_U16
- , M32C_F_DSP_24_S16, M32C_F_DSP_32_U16, M32C_F_DSP_32_S16, M32C_F_DSP_40_U16
- , M32C_F_DSP_40_S16, M32C_F_DSP_48_U16, M32C_F_DSP_48_S16, M32C_F_DSP_64_U16
+ , M32C_F_16_4, M32C_F_16_8, M32C_F_18_1, M32C_F_18_2
+ , M32C_F_18_3, M32C_F_20_1, M32C_F_20_3, M32C_F_20_2
+ , M32C_F_20_4, M32C_F_21_3, M32C_F_24_2, M32C_F_24_8
+ , M32C_F_32_16, M32C_F_SRC16_RN, M32C_F_SRC16_AN, M32C_F_SRC32_AN_UNPREFIXED
+ , M32C_F_SRC32_AN_PREFIXED, M32C_F_SRC32_RN_UNPREFIXED_QI, M32C_F_SRC32_RN_PREFIXED_QI, M32C_F_SRC32_RN_UNPREFIXED_HI
+ , M32C_F_SRC32_RN_PREFIXED_HI, M32C_F_SRC32_RN_UNPREFIXED_SI, M32C_F_SRC32_RN_PREFIXED_SI, M32C_F_DST32_RN_EXT_UNPREFIXED
+ , M32C_F_DST16_RN, M32C_F_DST16_RN_EXT, M32C_F_DST16_RN_QI_S, M32C_F_DST16_AN
+ , M32C_F_DST16_AN_S, M32C_F_DST32_AN_UNPREFIXED, M32C_F_DST32_AN_PREFIXED, M32C_F_DST32_RN_UNPREFIXED_QI
+ , M32C_F_DST32_RN_PREFIXED_QI, M32C_F_DST32_RN_UNPREFIXED_HI, M32C_F_DST32_RN_PREFIXED_HI, M32C_F_DST32_RN_UNPREFIXED_SI
+ , M32C_F_DST32_RN_PREFIXED_SI, M32C_F_DST16_1_S, M32C_F_IMM_8_S4, M32C_F_IMM_12_S4
+ , M32C_F_IMM_13_U3, M32C_F_IMM_20_S4, M32C_F_IMM1_S, M32C_F_IMM3_S
+ , M32C_F_DSP_8_U6, M32C_F_DSP_8_U8, M32C_F_DSP_8_S8, M32C_F_DSP_10_U6
+ , M32C_F_DSP_16_U8, M32C_F_DSP_16_S8, M32C_F_DSP_24_U8, M32C_F_DSP_24_S8
+ , M32C_F_DSP_32_U8, M32C_F_DSP_32_S8, M32C_F_DSP_40_U8, M32C_F_DSP_40_S8
+ , M32C_F_DSP_48_U8, M32C_F_DSP_48_S8, M32C_F_DSP_56_U8, M32C_F_DSP_56_S8
+ , M32C_F_DSP_64_U8, M32C_F_DSP_64_S8, M32C_F_DSP_8_U16, M32C_F_DSP_8_S16
+ , M32C_F_DSP_16_U16, M32C_F_DSP_16_S16, M32C_F_DSP_24_U16, M32C_F_DSP_24_S16
+ , M32C_F_DSP_32_U16, M32C_F_DSP_32_S16, M32C_F_DSP_40_U16, M32C_F_DSP_40_S16
+ , M32C_F_DSP_48_U16, M32C_F_DSP_48_S16, M32C_F_DSP_64_U16, M32C_F_DSP_8_U24
, M32C_F_DSP_16_U24, M32C_F_DSP_24_U24, M32C_F_DSP_32_U24, M32C_F_DSP_40_U24
, M32C_F_DSP_40_S32, M32C_F_DSP_48_U24, M32C_F_DSP_16_S32, M32C_F_DSP_24_S32
, M32C_F_DSP_32_S32, M32C_F_DSP_48_U32, M32C_F_DSP_48_S32, M32C_F_DSP_56_S16
@@ -208,209 +209,209 @@ typedef enum cgen_operand_type {
, M32C_OPERAND_BIT32ANUNPREFIXED, M32C_OPERAND_A0, M32C_OPERAND_A1, M32C_OPERAND_SB
, M32C_OPERAND_FB, M32C_OPERAND_SP, M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, M32C_OPERAND_REGSETPOP
, M32C_OPERAND_REGSETPUSH, M32C_OPERAND_RN16_PUSH_S, M32C_OPERAND_AN16_PUSH_S, M32C_OPERAND_DSP_8_U6
- , M32C_OPERAND_DSP_8_U8, M32C_OPERAND_DSP_8_U16, M32C_OPERAND_DSP_8_S8, M32C_OPERAND_DSP_10_U6
- , M32C_OPERAND_DSP_16_U8, M32C_OPERAND_DSP_16_U16, M32C_OPERAND_DSP_16_U20, M32C_OPERAND_DSP_16_U24
- , M32C_OPERAND_DSP_16_S8, M32C_OPERAND_DSP_16_S16, M32C_OPERAND_DSP_24_U8, M32C_OPERAND_DSP_24_U16
- , M32C_OPERAND_DSP_24_U20, M32C_OPERAND_DSP_24_U24, M32C_OPERAND_DSP_24_S8, M32C_OPERAND_DSP_24_S16
- , M32C_OPERAND_DSP_32_U8, M32C_OPERAND_DSP_32_U16, M32C_OPERAND_DSP_32_U24, M32C_OPERAND_DSP_32_U20
- , M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16, M32C_OPERAND_DSP_40_U8, M32C_OPERAND_DSP_40_S8
- , M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16, M32C_OPERAND_DSP_40_U24, M32C_OPERAND_DSP_48_U8
- , M32C_OPERAND_DSP_48_S8, M32C_OPERAND_DSP_48_U16, M32C_OPERAND_DSP_48_S16, M32C_OPERAND_DSP_48_U24
- , M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_SH_8_S4, M32C_OPERAND_IMM_8_QI, M32C_OPERAND_IMM_8_HI
- , M32C_OPERAND_IMM_12_S4, M32C_OPERAND_IMM_SH_12_S4, M32C_OPERAND_IMM_13_U3, M32C_OPERAND_IMM_20_S4
- , M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI, M32C_OPERAND_IMM_16_HI, M32C_OPERAND_IMM_16_SI
- , M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI, M32C_OPERAND_IMM_24_SI, M32C_OPERAND_IMM_32_QI
- , M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI, M32C_OPERAND_IMM_40_QI, M32C_OPERAND_IMM_40_HI
- , M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI, M32C_OPERAND_IMM_48_HI, M32C_OPERAND_IMM_48_SI
- , M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI, M32C_OPERAND_IMM_64_HI, M32C_OPERAND_IMM1_S
- , M32C_OPERAND_IMM3_S, M32C_OPERAND_BITNO16R, M32C_OPERAND_BITNO32PREFIXED, M32C_OPERAND_BITNO32UNPREFIXED
- , M32C_OPERAND_BITBASE16_16_U8, M32C_OPERAND_BITBASE16_16_S8, M32C_OPERAND_BITBASE16_16_U16, M32C_OPERAND_BITBASE16_8_U11_S
- , M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED
- , M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, M32C_OPERAND_BITBASE32_24_U11_PREFIXED, M32C_OPERAND_BITBASE32_24_S11_PREFIXED, M32C_OPERAND_BITBASE32_24_U19_PREFIXED
- , M32C_OPERAND_BITBASE32_24_S19_PREFIXED, M32C_OPERAND_BITBASE32_24_U27_PREFIXED, M32C_OPERAND_LAB_5_3, M32C_OPERAND_LAB32_JMP_S
- , M32C_OPERAND_LAB_8_8, M32C_OPERAND_LAB_8_16, M32C_OPERAND_LAB_8_24, M32C_OPERAND_LAB_16_8
- , M32C_OPERAND_LAB_24_8, M32C_OPERAND_LAB_32_8, M32C_OPERAND_LAB_40_8, M32C_OPERAND_SBIT
- , M32C_OPERAND_OBIT, M32C_OPERAND_ZBIT, M32C_OPERAND_CBIT, M32C_OPERAND_UBIT
- , M32C_OPERAND_IBIT, M32C_OPERAND_BBIT, M32C_OPERAND_DBIT, M32C_OPERAND_COND16_16
- , M32C_OPERAND_COND16_24, M32C_OPERAND_COND16_32, M32C_OPERAND_COND32_16, M32C_OPERAND_COND32_24
- , M32C_OPERAND_COND32_32, M32C_OPERAND_COND32_40, M32C_OPERAND_COND16C, M32C_OPERAND_COND16J
- , M32C_OPERAND_COND16J5, M32C_OPERAND_COND32, M32C_OPERAND_COND32J, M32C_OPERAND_SCCOND32
- , M32C_OPERAND_FLAGS16, M32C_OPERAND_FLAGS32, M32C_OPERAND_CR16, M32C_OPERAND_CR1_UNPREFIXED_32
- , M32C_OPERAND_CR1_PREFIXED_32, M32C_OPERAND_CR2_32, M32C_OPERAND_CR3_UNPREFIXED_32, M32C_OPERAND_CR3_PREFIXED_32
- , M32C_OPERAND_Z, M32C_OPERAND_S, M32C_OPERAND_Q, M32C_OPERAND_G
- , M32C_OPERAND_X, M32C_OPERAND_SIZE, M32C_OPERAND_BITINDEX, M32C_OPERAND_SRCINDEX
- , M32C_OPERAND_DSTINDEX, M32C_OPERAND_NOREMAINDER, M32C_OPERAND_SRC16_RN_DIRECT_QI, M32C_OPERAND_SRC16_RN_DIRECT_HI
- , M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI
- , M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_DIRECT_QI, M32C_OPERAND_SRC16_AN_DIRECT_HI
- , M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI
- , M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_INDIRECT_QI, M32C_OPERAND_SRC16_AN_INDIRECT_HI
- , M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI
- , M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI
- , M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI
- , M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI
- , M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI
- , M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI
- , M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI
- , M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI
- , M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI
- , M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI
- , M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI, M32C_OPERAND_DST16_RN_DIRECT_SI
- , M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI
- , M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI
- , M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI, M32C_OPERAND_DST16_AN_DIRECT_HI
- , M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI
- , M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_DST16_AN_INDIRECT_QI
- , M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI
- , M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI
- , M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI
- , M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI
- , M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI
- , M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI
- , M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI
- , M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI
- , M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI
- , M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI
- , M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI
- , M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI
- , M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI
- , M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI
- , M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI
- , M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI
- , M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI
- , M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI
- , M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI
- , M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI
- , M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI
- , M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI
- , M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI
- , M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI
- , M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI
- , M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI
- , M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI
- , M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI
- , M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI, M32C_OPERAND_DST16_32_16_ABSOLUTE_QI
- , M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI, M32C_OPERAND_DST16_24_16_ABSOLUTE_HI
- , M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_SI
- , M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI, M32C_OPERAND_DST16_48_16_ABSOLUTE_SI
- , M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI
- , M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI
- , M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI
- , M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI
- , M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI
- , M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI
- , M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI
- , M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI
- , M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED
- , M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_INDIRECT
- , M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE, M32C_OPERAND_BIT16_16_16_SB_RELATIVE
- , M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE, M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED
- , M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED
- , M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED
- , M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED
- , M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED, M32C_OPERAND_AN16_PUSH_S_DERIVED
- , M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED
- , M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI, M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI
- , M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI
- , M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI, M32C_OPERAND_DST32_2_S_R0_DIRECT_HI
- , M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI
- , M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI
- , M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI, M32C_OPERAND_SRC16_BASIC_QI
- , M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI
- , M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI, M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI
- , M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI, M32C_OPERAND_SRC16_16_16_HI
- , M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI
- , M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI
- , M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_PREFIXED_QI
- , M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_PREFIXED_SI
- , M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI, M32C_OPERAND_DST16_BASIC_HI
- , M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI
- , M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI, M32C_OPERAND_DST16_16_QI
- , M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_HI, M32C_OPERAND_DST16_16_8_HI
- , M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI, M32C_OPERAND_DST16_16_16_SI
- , M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI
- , M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI
- , M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI
- , M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI
- , M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI
- , M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_UNPREFIXED_QI
- , M32C_OPERAND_DST32_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_UNPREFIXED_HI
- , M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_UNPREFIXED_SI
- , M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI, M32C_OPERAND_DST16_24_QI
- , M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI, M32C_OPERAND_DST32_24_8_PREFIXED_QI
- , M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI, M32C_OPERAND_DST32_24_PREFIXED_HI
- , M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI, M32C_OPERAND_DST32_24_UNPREFIXED_SI
- , M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI, M32C_OPERAND_DST32_24_24_PREFIXED_SI
- , M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI, M32C_OPERAND_DST32_32_PREFIXED_QI
- , M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI, M32C_OPERAND_DST32_32_PREFIXED_SI
- , M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI, M32C_OPERAND_DST32_40_PREFIXED_HI
- , M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI, M32C_OPERAND_DST32_48_PREFIXED_HI
- , M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC, M32C_OPERAND_BIT16_16_8
- , M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED, M32C_OPERAND_BIT32_BASIC_UNPREFIXED
- , M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED, M32C_OPERAND_SRC16_2_S
- , M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8, M32C_OPERAND_DST16_3_S_16
- , M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI, M32C_OPERAND_DST32_2_S_8_QI
- , M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI, M32C_OPERAND_DST32_2_S_8_SI
- , M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S, M32C_OPERAND_RN16_PUSH_S_ANYOF
- , M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX
+ , M32C_OPERAND_DSP_8_U8, M32C_OPERAND_DSP_8_U16, M32C_OPERAND_DSP_8_S8, M32C_OPERAND_DSP_8_U24
+ , M32C_OPERAND_DSP_10_U6, M32C_OPERAND_DSP_16_U8, M32C_OPERAND_DSP_16_U16, M32C_OPERAND_DSP_16_U20
+ , M32C_OPERAND_DSP_16_U24, M32C_OPERAND_DSP_16_S8, M32C_OPERAND_DSP_16_S16, M32C_OPERAND_DSP_24_U8
+ , M32C_OPERAND_DSP_24_U16, M32C_OPERAND_DSP_24_U20, M32C_OPERAND_DSP_24_U24, M32C_OPERAND_DSP_24_S8
+ , M32C_OPERAND_DSP_24_S16, M32C_OPERAND_DSP_32_U8, M32C_OPERAND_DSP_32_U16, M32C_OPERAND_DSP_32_U24
+ , M32C_OPERAND_DSP_32_U20, M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16, M32C_OPERAND_DSP_40_U8
+ , M32C_OPERAND_DSP_40_S8, M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16, M32C_OPERAND_DSP_40_U24
+ , M32C_OPERAND_DSP_48_U8, M32C_OPERAND_DSP_48_S8, M32C_OPERAND_DSP_48_U16, M32C_OPERAND_DSP_48_S16
+ , M32C_OPERAND_DSP_48_U24, M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_SH_8_S4, M32C_OPERAND_IMM_8_QI
+ , M32C_OPERAND_IMM_8_HI, M32C_OPERAND_IMM_12_S4, M32C_OPERAND_IMM_SH_12_S4, M32C_OPERAND_IMM_13_U3
+ , M32C_OPERAND_IMM_20_S4, M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI, M32C_OPERAND_IMM_16_HI
+ , M32C_OPERAND_IMM_16_SI, M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI, M32C_OPERAND_IMM_24_SI
+ , M32C_OPERAND_IMM_32_QI, M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI, M32C_OPERAND_IMM_40_QI
+ , M32C_OPERAND_IMM_40_HI, M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI, M32C_OPERAND_IMM_48_HI
+ , M32C_OPERAND_IMM_48_SI, M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI, M32C_OPERAND_IMM_64_HI
+ , M32C_OPERAND_IMM1_S, M32C_OPERAND_IMM3_S, M32C_OPERAND_BITNO16R, M32C_OPERAND_BITNO32PREFIXED
+ , M32C_OPERAND_BITNO32UNPREFIXED, M32C_OPERAND_BITBASE16_16_U8, M32C_OPERAND_BITBASE16_16_S8, M32C_OPERAND_BITBASE16_16_U16
+ , M32C_OPERAND_BITBASE16_8_U11_S, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED
+ , M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, M32C_OPERAND_BITBASE32_24_U11_PREFIXED, M32C_OPERAND_BITBASE32_24_S11_PREFIXED
+ , M32C_OPERAND_BITBASE32_24_U19_PREFIXED, M32C_OPERAND_BITBASE32_24_S19_PREFIXED, M32C_OPERAND_BITBASE32_24_U27_PREFIXED, M32C_OPERAND_LAB_5_3
+ , M32C_OPERAND_LAB32_JMP_S, M32C_OPERAND_LAB_8_8, M32C_OPERAND_LAB_8_16, M32C_OPERAND_LAB_8_24
+ , M32C_OPERAND_LAB_16_8, M32C_OPERAND_LAB_24_8, M32C_OPERAND_LAB_32_8, M32C_OPERAND_LAB_40_8
+ , M32C_OPERAND_SBIT, M32C_OPERAND_OBIT, M32C_OPERAND_ZBIT, M32C_OPERAND_CBIT
+ , M32C_OPERAND_UBIT, M32C_OPERAND_IBIT, M32C_OPERAND_BBIT, M32C_OPERAND_DBIT
+ , M32C_OPERAND_COND16_16, M32C_OPERAND_COND16_24, M32C_OPERAND_COND16_32, M32C_OPERAND_COND32_16
+ , M32C_OPERAND_COND32_24, M32C_OPERAND_COND32_32, M32C_OPERAND_COND32_40, M32C_OPERAND_COND16C
+ , M32C_OPERAND_COND16J, M32C_OPERAND_COND16J5, M32C_OPERAND_COND32, M32C_OPERAND_COND32J
+ , M32C_OPERAND_SCCOND32, M32C_OPERAND_FLAGS16, M32C_OPERAND_FLAGS32, M32C_OPERAND_CR16
+ , M32C_OPERAND_CR1_UNPREFIXED_32, M32C_OPERAND_CR1_PREFIXED_32, M32C_OPERAND_CR2_32, M32C_OPERAND_CR3_UNPREFIXED_32
+ , M32C_OPERAND_CR3_PREFIXED_32, M32C_OPERAND_Z, M32C_OPERAND_S, M32C_OPERAND_Q
+ , M32C_OPERAND_G, M32C_OPERAND_X, M32C_OPERAND_SIZE, M32C_OPERAND_BITINDEX
+ , M32C_OPERAND_SRCINDEX, M32C_OPERAND_DSTINDEX, M32C_OPERAND_NOREMAINDER, M32C_OPERAND_SRC16_RN_DIRECT_QI
+ , M32C_OPERAND_SRC16_RN_DIRECT_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI
+ , M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_DIRECT_QI
+ , M32C_OPERAND_SRC16_AN_DIRECT_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI
+ , M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_INDIRECT_QI
+ , M32C_OPERAND_SRC16_AN_INDIRECT_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI
+ , M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI
+ , M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI
+ , M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI
+ , M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI
+ , M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI
+ , M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI
+ , M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI
+ , M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI
+ , M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI
+ , M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI
+ , M32C_OPERAND_DST16_RN_DIRECT_SI, M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI
+ , M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI
+ , M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI
+ , M32C_OPERAND_DST16_AN_DIRECT_HI, M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI
+ , M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI
+ , M32C_OPERAND_DST16_AN_INDIRECT_QI, M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI
+ , M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI
+ , M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI
+ , M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI
+ , M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI
+ , M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI
+ , M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI
+ , M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI
+ , M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI
+ , M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI
+ , M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI
+ , M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI
+ , M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI
+ , M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI
+ , M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI
+ , M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI
+ , M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI
+ , M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI
+ , M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI
+ , M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI
+ , M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI
+ , M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI
+ , M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI
+ , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI
+ , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI
+ , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI
+ , M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI
+ , M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI
+ , M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI
+ , M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI
+ , M32C_OPERAND_DST16_32_16_ABSOLUTE_QI, M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI
+ , M32C_OPERAND_DST16_24_16_ABSOLUTE_HI, M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI
+ , M32C_OPERAND_DST16_16_16_ABSOLUTE_SI, M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI
+ , M32C_OPERAND_DST16_48_16_ABSOLUTE_SI, M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI
+ , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI
+ , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI
+ , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI
+ , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI
+ , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI
+ , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI
+ , M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED
+ , M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED
+ , M32C_OPERAND_BIT16_AN_INDIRECT, M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE
+ , M32C_OPERAND_BIT16_16_16_SB_RELATIVE, M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE
+ , M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED
+ , M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED
+ , M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED
+ , M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED
+ , M32C_OPERAND_AN16_PUSH_S_DERIVED, M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED
+ , M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI
+ , M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI
+ , M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI
+ , M32C_OPERAND_DST32_2_S_R0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI
+ , M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI
+ , M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI
+ , M32C_OPERAND_SRC16_BASIC_QI, M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI
+ , M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI, M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI
+ , M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI, M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI
+ , M32C_OPERAND_SRC16_16_16_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI
+ , M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI
+ , M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI
+ , M32C_OPERAND_SRC32_24_24_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI
+ , M32C_OPERAND_SRC32_24_8_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI
+ , M32C_OPERAND_DST16_BASIC_HI, M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI
+ , M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI, M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI
+ , M32C_OPERAND_DST16_16_QI, M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_HI
+ , M32C_OPERAND_DST16_16_8_HI, M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI
+ , M32C_OPERAND_DST16_16_16_SI, M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI
+ , M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI
+ , M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI
+ , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI
+ , M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI
+ , M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_16_24_UNPREFIXED_QI, M32C_OPERAND_DST32_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_16_24_UNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_16_24_UNPREFIXED_SI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI
+ , M32C_OPERAND_DST16_24_QI, M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI
+ , M32C_OPERAND_DST32_24_8_PREFIXED_QI, M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_24_PREFIXED_HI, M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI
+ , M32C_OPERAND_DST32_24_UNPREFIXED_SI, M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI
+ , M32C_OPERAND_DST32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI
+ , M32C_OPERAND_DST32_32_PREFIXED_QI, M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI
+ , M32C_OPERAND_DST32_32_PREFIXED_SI, M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI
+ , M32C_OPERAND_DST32_40_PREFIXED_HI, M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI
+ , M32C_OPERAND_DST32_48_PREFIXED_HI, M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC
+ , M32C_OPERAND_BIT16_16_8, M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED
+ , M32C_OPERAND_BIT32_BASIC_UNPREFIXED, M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED
+ , M32C_OPERAND_SRC16_2_S, M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8
+ , M32C_OPERAND_DST16_3_S_16, M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI
+ , M32C_OPERAND_DST32_2_S_8_QI, M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI
+ , M32C_OPERAND_DST32_2_S_8_SI, M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S
+ , M32C_OPERAND_RN16_PUSH_S_ANYOF, M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
-#define MAX_OPERANDS 869
+#define MAX_OPERANDS 870
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8
diff --git a/opcodes/m32c-dis.c b/opcodes/m32c-dis.c
index c81a893..b2ddb16 100644
--- a/opcodes/m32c-dis.c
+++ b/opcodes/m32c-dis.c
@@ -1,27 +1,27 @@
/* Disassembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-- the resultant file is machine generated, cgen-dis.in isn't
+ THIS FILE IS MACHINE GENERATED WITH CGEN.
+ - the resultant file is machine generated, cgen-dis.in isn't
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
-Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+ Free Software Foundation, Inc.
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+ This file is part of the GNU Binutils and GDB, the GNU debugger.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@@ -56,24 +56,26 @@ static int read_insn
(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
unsigned long *);
-/* -- disassembler routines inserted here */
+/* -- disassembler routines inserted here. */
/* -- dis.c */
#include "elf/m32c.h"
#include "elf-bfd.h"
-/* Always print the short insn format suffix as ':<char>' */
+/* Always print the short insn format suffix as ':<char>'. */
+
static void
-print_suffix (PTR dis_info, char suffix)
+print_suffix (void * dis_info, char suffix)
{
disassemble_info *info = dis_info;
+
(*info->fprintf_func) (info->stream, ":%c", suffix);
}
static void
print_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
@@ -85,7 +87,7 @@ print_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
static void
print_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
@@ -96,7 +98,7 @@ print_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
static void
print_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
@@ -107,7 +109,7 @@ print_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
static void
print_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
@@ -116,10 +118,11 @@ print_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
print_suffix (dis_info, 'z');
}
-/* Print the empty suffix */
+/* Print the empty suffix. */
+
static void
print_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info ATTRIBUTE_UNUSED,
+ void * dis_info ATTRIBUTE_UNUSED,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
@@ -130,13 +133,14 @@ print_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
static void
print_r0l_r0h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = dis_info;
+
if (value == 0)
(*info->fprintf_func) (info->stream, "r0h,r0l");
else
@@ -145,62 +149,65 @@ print_r0l_r0h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
static void
print_unsigned_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
unsigned long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = dis_info;
+
(*info->fprintf_func) (info->stream, "%ld,0x%lx", value & 0x7, value >> 3);
}
static void
print_signed_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
signed long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = dis_info;
+
(*info->fprintf_func) (info->stream, "%ld,%ld", value & 0x7, value >> 3);
}
static void
print_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
+ void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
- /* Always print the size as '.w' */
+ /* Always print the size as '.w'. */
disassemble_info *info = dis_info;
+
(*info->fprintf_func) (info->stream, ".w");
}
-#define POP 0
+#define POP 0
#define PUSH 1
-static void print_pop_regset (CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int);
-static void print_push_regset (CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int);
+static void print_pop_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
+static void print_push_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
/* Print a set of registers, R0,R1,A0,A1,SB,FB. */
static void
print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
- long value,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED,
- int push)
+ void * dis_info,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED,
+ int push)
{
static char * m16c_register_names [] =
- {
- "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb"
- };
+ {
+ "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb"
+ };
disassemble_info *info = dis_info;
int mask;
int index = 0;
@@ -235,45 +242,28 @@ print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
static void
print_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
- long value,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
+ void * dis_info,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
{
print_regset (cd, dis_info, value, attrs, pc, length, POP);
}
static void
print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
- long value,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
+ void * dis_info,
+ long value,
+ unsigned int attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ int length ATTRIBUTE_UNUSED)
{
print_regset (cd, dis_info, value, attrs, pc, length, PUSH);
}
-#if 0 /* not used? */
-static void
-print_boff (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- PTR dis_info,
- long value,
- unsigned int attrs ATTRIBUTE_UNUSED,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = dis_info;
- if (value)
- info->fprintf_func (info->stream, "%d,%d", value % 16,
- (value / 16) * 2);
-}
-
-#endif /* not used? */
void m32c_cgen_print_operand
- PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
- void const *, bfd_vma, int));
+ (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@@ -291,16 +281,15 @@ void m32c_cgen_print_operand
the handlers. */
void
-m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
- CGEN_CPU_DESC cd;
- int opindex;
- PTR xinfo;
- CGEN_FIELDS *fields;
- void const *attrs ATTRIBUTE_UNUSED;
- bfd_vma pc;
- int length;
+m32c_cgen_print_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ void * xinfo,
+ CGEN_FIELDS *fields,
+ void const *attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc,
+ int length)
{
- disassemble_info *info = (disassemble_info *) xinfo;
+ disassemble_info *info = (disassemble_info *) xinfo;
switch (opindex)
{
@@ -332,7 +321,7 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_unprefixed_QI, 0);
break;
case M32C_OPERAND_BITBASE16_16_S8 :
- print_signed_bitbase (cd, info, fields->f_dsp_16_s8, 0, pc, length);
+ print_signed_bitbase (cd, info, fields->f_dsp_16_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case M32C_OPERAND_BITBASE16_16_U16 :
print_unsigned_bitbase (cd, info, fields->f_dsp_16_u16, 0, pc, length);
@@ -341,7 +330,7 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
print_unsigned_bitbase (cd, info, fields->f_dsp_16_u8, 0, pc, length);
break;
case M32C_OPERAND_BITBASE16_8_U11_S :
- print_unsigned_bitbase (cd, info, fields->f_bitbase16_u11_S, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ print_unsigned_bitbase (cd, info, fields->f_bitbase16_u11_S, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
break;
case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED :
print_signed_bitbase (cd, info, fields->f_bitbase32_16_s11_unprefixed, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
@@ -440,10 +429,10 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
print_normal (cd, info, fields->f_dsp_32_u8, 0, pc, length);
break;
case M32C_OPERAND_DSP_40_S16 :
- print_normal (cd, info, fields->f_dsp_40_s16, 0, pc, length);
+ print_normal (cd, info, fields->f_dsp_40_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case M32C_OPERAND_DSP_40_S8 :
- print_normal (cd, info, fields->f_dsp_40_s8, 0, pc, length);
+ print_normal (cd, info, fields->f_dsp_40_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case M32C_OPERAND_DSP_40_U16 :
print_normal (cd, info, fields->f_dsp_40_u16, 0, pc, length);
@@ -455,10 +444,10 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
print_normal (cd, info, fields->f_dsp_40_u8, 0, pc, length);
break;
case M32C_OPERAND_DSP_48_S16 :
- print_normal (cd, info, fields->f_dsp_48_s16, 0, pc, length);
+ print_normal (cd, info, fields->f_dsp_48_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case M32C_OPERAND_DSP_48_S8 :
- print_normal (cd, info, fields->f_dsp_48_s8, 0, pc, length);
+ print_normal (cd, info, fields->f_dsp_48_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case M32C_OPERAND_DSP_48_U16 :
print_normal (cd, info, fields->f_dsp_48_u16, 0, pc, length);
@@ -475,6 +464,9 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
case M32C_OPERAND_DSP_8_U16 :
print_normal (cd, info, fields->f_dsp_8_u16, 0, pc, length);
break;
+ case M32C_OPERAND_DSP_8_U24 :
+ print_normal (cd, info, fields->f_dsp_8_u24, 0, pc, length);
+ break;
case M32C_OPERAND_DSP_8_U6 :
print_normal (cd, info, fields->f_dsp_8_u6, 0, pc, length);
break;
@@ -578,7 +570,7 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
print_normal (cd, info, fields->f_imm_12_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case M32C_OPERAND_IMM_13_U3 :
- print_normal (cd, info, fields->f_imm_13_u3, 0, pc, length);
+ print_normal (cd, info, fields->f_imm_13_u3, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case M32C_OPERAND_IMM_16_HI :
print_normal (cd, info, fields->f_dsp_16_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
@@ -662,7 +654,7 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
print_normal (cd, info, fields->f_imm3_S, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
break;
case M32C_OPERAND_LAB_16_8 :
- print_address (cd, info, fields->f_lab_16_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ print_address (cd, info, fields->f_lab_16_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_24_8 :
print_address (cd, info, fields->f_lab_24_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
@@ -674,19 +666,19 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
print_address (cd, info, fields->f_lab_40_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_5_3 :
- print_address (cd, info, fields->f_lab_5_3, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ print_address (cd, info, fields->f_lab_5_3, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_8_16 :
- print_address (cd, info, fields->f_lab_8_16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ print_address (cd, info, fields->f_lab_8_16, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_8_24 :
print_address (cd, info, fields->f_lab_8_24, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_8_8 :
- print_address (cd, info, fields->f_lab_8_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ print_address (cd, info, fields->f_lab_8_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB32_JMP_S :
- print_address (cd, info, fields->f_lab32_jmp_s, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ print_address (cd, info, fields->f_lab32_jmp_s, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
break;
case M32C_OPERAND_Q :
print_Q (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
@@ -878,8 +870,7 @@ cgen_print_fn * const m32c_cgen_print_handlers[] =
void
-m32c_cgen_init_dis (cd)
- CGEN_CPU_DESC cd;
+m32c_cgen_init_dis (CGEN_CPU_DESC cd)
{
m32c_cgen_init_opcode_table (cd);
m32c_cgen_init_ibld_table (cd);
@@ -931,7 +922,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
- ; /* nothing to do */
+ ; /* Nothing to do. */
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
(*info->print_address_func) (value, info);
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@@ -1013,6 +1004,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
unsigned long *insn_value)
{
int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
@@ -1117,13 +1109,13 @@ print_insn (CGEN_CPU_DESC cd,
length = CGEN_EXTRACT_FN (cd, insn)
(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
- /* length < 0 -> error */
+ /* Length < 0 -> error. */
if (length < 0)
return length;
if (length > 0)
{
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
- /* length is in bits, result is in bytes */
+ /* Length is in bits, result is in bytes. */
return length / 8;
}
}
@@ -1173,7 +1165,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
-typedef struct cpu_desc_list {
+typedef struct cpu_desc_list
+{
struct cpu_desc_list *next;
int isa;
int mach;
@@ -1236,7 +1229,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info)
break;
}
}
- }
+ }
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
@@ -1258,7 +1251,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info)
if (!cd)
abort ();
- /* save this away for future reference */
+ /* Save this away for future reference. */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
cl->isa = isa;
diff --git a/opcodes/m32c-ibld.c b/opcodes/m32c-ibld.c
index 9692575..f5c2dc3 100644
--- a/opcodes/m32c-ibld.c
+++ b/opcodes/m32c-ibld.c
@@ -1,25 +1,26 @@
/* Instruction building/extraction support for m32c. -*- C -*-
-THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
-- the resultant file is machine generated, cgen-ibld.in isn't
+ THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+ - the resultant file is machine generated, cgen-ibld.in isn't
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+ Free Software Foundation, Inc.
-This file is part of the GNU Binutils and GDB, the GNU debugger.
+ This file is part of the GNU Binutils and GDB, the GNU debugger.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "opintl.h"
#include "safe-ctype.h"
-#undef min
+#undef min
#define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
+#undef max
#define max(a,b) ((a) > (b) ? (a) : (b))
/* Used by the ifield rtx function. */
@@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
if (length == 0)
return NULL;
-#if 0
- if (CGEN_INT_INSN_P
- && word_offset != 0)
- abort ();
-#endif
-
if (word_length > 32)
abort ();
@@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#if CGEN_INT_INSN_P
/* Cover function to store an insn value into an integral insn. Must go here
- because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
+ because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
static void
put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int shift = insn_length - length;
/* Written this way to avoid undefined behaviour. */
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
}
}
@@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
{
unsigned long x;
int shift;
-#if 0
- int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
-#endif
+
x = cgen_get_insn_value (cd, bufp, word_length);
if (CGEN_INSN_LSB0_P)
@@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
return 1;
}
-#if 0
- if (CGEN_INT_INSN_P
- && word_offset != 0)
- abort ();
-#endif
-
if (word_length > 32)
abort ();
@@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
return CGEN_INSN_BITSIZE (insn);
}
-/* machine generated code added here */
+/* Machine generated code added here. */
const char * m32c_cgen_insert_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+ (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
/* Main entry point for operand insertion.
@@ -559,12 +547,11 @@ const char * m32c_cgen_insert_operand
resolved during parsing. */
const char *
-m32c_cgen_insert_operand (cd, opindex, fields, buffer, pc)
- CGEN_CPU_DESC cd;
- int opindex;
- CGEN_FIELDS * fields;
- CGEN_INSN_BYTES_PTR buffer;
- bfd_vma pc ATTRIBUTE_UNUSED;
+m32c_cgen_insert_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ CGEN_FIELDS * fields,
+ CGEN_INSN_BYTES_PTR buffer,
+ bfd_vma pc ATTRIBUTE_UNUSED)
{
const char * errmsg = NULL;
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@@ -1050,6 +1037,13 @@ m32c_cgen_insert_operand (cd, opindex, fields, buffer, pc)
errmsg = insert_normal (cd, value, 0, 0, 8, 16, 32, total_length, buffer);
}
break;
+ case M32C_OPERAND_DSP_8_U24 :
+ {
+ long value = fields->f_dsp_8_u24;
+ value = ((((((unsigned int) (value) >> (16))) | (((value) & (65280))))) | (((((value) & (255))) << (16))));
+ errmsg = insert_normal (cd, value, 0, 0, 8, 24, 32, total_length, buffer);
+ }
+ break;
case M32C_OPERAND_DSP_8_U6 :
errmsg = insert_normal (cd, fields->f_dsp_8_u6, 0, 0, 8, 6, 32, total_length, buffer);
break;
@@ -1422,7 +1416,7 @@ m32c_cgen_insert_operand (cd, opindex, fields, buffer, pc)
{
long value = fields->f_lab_5_3;
value = ((value) - (((pc) + (2))));
- errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 3, 32, total_length, buffer);
+ errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 3, 32, total_length, buffer);
}
break;
case M32C_OPERAND_LAB_8_16 :
@@ -1449,8 +1443,10 @@ m32c_cgen_insert_operand (cd, opindex, fields, buffer, pc)
case M32C_OPERAND_LAB32_JMP_S :
{
{
- FLD (f_7_1) = ((((FLD (f_lab32_jmp_s)) - (pc))) & (1));
- FLD (f_2_2) = ((unsigned int) (((FLD (f_lab32_jmp_s)) - (pc))) >> (1));
+ SI tmp_val;
+ tmp_val = ((((FLD (f_lab32_jmp_s)) - (pc))) - (2));
+ FLD (f_7_1) = ((tmp_val) & (1));
+ FLD (f_2_2) = ((unsigned int) (tmp_val) >> (1));
}
errmsg = insert_normal (cd, fields->f_2_2, 0, 0, 2, 2, 32, total_length, buffer);
if (errmsg)
@@ -1678,8 +1674,7 @@ m32c_cgen_insert_operand (cd, opindex, fields, buffer, pc)
}
int m32c_cgen_extract_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
- CGEN_FIELDS *, bfd_vma));
+ (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
/* Main entry point for operand extraction.
The result is <= 0 for error, >0 for success.
@@ -1697,13 +1692,12 @@ int m32c_cgen_extract_operand
the handlers. */
int
-m32c_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
- CGEN_CPU_DESC cd;
- int opindex;
- CGEN_EXTRACT_INFO *ex_info;
- CGEN_INSN_INT insn_value;
- CGEN_FIELDS * fields;
- bfd_vma pc;
+m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ CGEN_EXTRACT_INFO *ex_info,
+ CGEN_INSN_INT insn_value,
+ CGEN_FIELDS * fields,
+ bfd_vma pc)
{
/* Assume success (for those operands that are nops). */
int length = 1;
@@ -2152,6 +2146,14 @@ m32c_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
fields->f_dsp_8_u16 = value;
}
break;
+ case M32C_OPERAND_DSP_8_U24 :
+ {
+ long value;
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 24, 32, total_length, pc, & value);
+ value = ((((((unsigned int) (value) >> (16))) | (((value) & (65280))))) | (((((value) & (255))) << (16))));
+ fields->f_dsp_8_u24 = value;
+ }
+ break;
case M32C_OPERAND_DSP_8_U6 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 6, 32, total_length, pc, & fields->f_dsp_8_u6);
break;
@@ -2526,7 +2528,7 @@ m32c_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
case M32C_OPERAND_LAB_5_3 :
{
long value;
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 3, 32, total_length, pc, & value);
+ length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 3, 32, total_length, pc, & value);
value = ((value) + (((pc) + (2))));
fields->f_lab_5_3 = value;
}
@@ -2793,10 +2795,8 @@ cgen_extract_fn * const m32c_cgen_extract_handlers[] =
extract_insn_normal,
};
-int m32c_cgen_get_int_operand
- PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
-bfd_vma m32c_cgen_get_vma_operand
- PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+int m32c_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma m32c_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
/* Getting values from cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they return.
@@ -2804,10 +2804,9 @@ bfd_vma m32c_cgen_get_vma_operand
not appropriate. */
int
-m32c_cgen_get_int_operand (cd, opindex, fields)
- CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
- int opindex;
- const CGEN_FIELDS * fields;
+m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ int opindex,
+ const CGEN_FIELDS * fields)
{
int value;
@@ -2984,6 +2983,9 @@ m32c_cgen_get_int_operand (cd, opindex, fields)
case M32C_OPERAND_DSP_8_U16 :
value = fields->f_dsp_8_u16;
break;
+ case M32C_OPERAND_DSP_8_U24 :
+ value = fields->f_dsp_8_u24;
+ break;
case M32C_OPERAND_DSP_8_U6 :
value = fields->f_dsp_8_u6;
break;
@@ -3383,10 +3385,9 @@ m32c_cgen_get_int_operand (cd, opindex, fields)
}
bfd_vma
-m32c_cgen_get_vma_operand (cd, opindex, fields)
- CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
- int opindex;
- const CGEN_FIELDS * fields;
+m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ int opindex,
+ const CGEN_FIELDS * fields)
{
bfd_vma value;
@@ -3563,6 +3564,9 @@ m32c_cgen_get_vma_operand (cd, opindex, fields)
case M32C_OPERAND_DSP_8_U16 :
value = fields->f_dsp_8_u16;
break;
+ case M32C_OPERAND_DSP_8_U24 :
+ value = fields->f_dsp_8_u24;
+ break;
case M32C_OPERAND_DSP_8_U6 :
value = fields->f_dsp_8_u6;
break;
@@ -3961,10 +3965,8 @@ m32c_cgen_get_vma_operand (cd, opindex, fields)
return value;
}
-void m32c_cgen_set_int_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
-void m32c_cgen_set_vma_operand
- PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+void m32c_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void m32c_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
/* Stuffing values in cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they accept.
@@ -3972,11 +3974,10 @@ void m32c_cgen_set_vma_operand
not appropriate. */
void
-m32c_cgen_set_int_operand (cd, opindex, fields, value)
- CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
- int opindex;
- CGEN_FIELDS * fields;
- int value;
+m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ int opindex,
+ CGEN_FIELDS * fields,
+ int value)
{
switch (opindex)
{
@@ -4149,6 +4150,9 @@ m32c_cgen_set_int_operand (cd, opindex, fields, value)
case M32C_OPERAND_DSP_8_U16 :
fields->f_dsp_8_u16 = value;
break;
+ case M32C_OPERAND_DSP_8_U24 :
+ fields->f_dsp_8_u24 = value;
+ break;
case M32C_OPERAND_DSP_8_U6 :
fields->f_dsp_8_u6 = value;
break;
@@ -4529,11 +4533,10 @@ m32c_cgen_set_int_operand (cd, opindex, fields, value)
}
void
-m32c_cgen_set_vma_operand (cd, opindex, fields, value)
- CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
- int opindex;
- CGEN_FIELDS * fields;
- bfd_vma value;
+m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+ int opindex,
+ CGEN_FIELDS * fields,
+ bfd_vma value)
{
switch (opindex)
{
@@ -4706,6 +4709,9 @@ m32c_cgen_set_vma_operand (cd, opindex, fields, value)
case M32C_OPERAND_DSP_8_U16 :
fields->f_dsp_8_u16 = value;
break;
+ case M32C_OPERAND_DSP_8_U24 :
+ fields->f_dsp_8_u24 = value;
+ break;
case M32C_OPERAND_DSP_8_U6 :
fields->f_dsp_8_u6 = value;
break;
@@ -5088,8 +5094,7 @@ m32c_cgen_set_vma_operand (cd, opindex, fields, value)
/* Function to call before using the instruction builder tables. */
void
-m32c_cgen_init_ibld_table (cd)
- CGEN_CPU_DESC cd;
+m32c_cgen_init_ibld_table (CGEN_CPU_DESC cd)
{
cd->insert_handlers = & m32c_cgen_insert_handlers[0];
cd->extract_handlers = & m32c_cgen_extract_handlers[0];
diff --git a/opcodes/m32c-opc.c b/opcodes/m32c-opc.c
index 9521183..eeb7321 100644
--- a/opcodes/m32c-opc.c
+++ b/opcodes/m32c-opc.c
@@ -53,10 +53,10 @@ m32c_asm_hash (const char *mnem)
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+static int asm_hash_insn_p (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
/* Instruction formats. */
@@ -7638,7 +7638,7 @@ static const CGEN_IFMT ifmt_mov16_w_S_imm_a0 ATTRIBUTE_UNUSED = {
};
static const CGEN_IFMT ifmt_mov32_l_a0 ATTRIBUTE_UNUSED = {
- 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_4_4) }, { 0 } }
+ 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_U24) }, { 0 } }
};
static const CGEN_IFMT ifmt_popc16_imm16 ATTRIBUTE_UNUSED = {
@@ -40026,84 +40026,6 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } },
& ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_16_absolute_QI, { 0xb70000 }
},
-/* mov.b${S} #${Imm-8-QI},r0l */
- {
- { 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
- & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xc400 }
- },
-/* mov.b${S} #${Imm-8-QI},r0h */
- {
- { 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
- & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xc300 }
- },
-/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
- & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xc50000 }
- },
-/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
- & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xc60000 }
- },
-/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
- & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xc7000000 }
- },
-/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
- & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x25000000 }
- },
-/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
- & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x35000000 }
- },
-/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
- & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x15000000 }
- },
-/* mov.w${S} #${Imm-8-HI},r0 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
- & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x50000 }
- },
-/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
- & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x240000 }
- },
-/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
- {
- { 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
- & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x340000 }
- },
-/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
- & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x14000000 }
- },
-/* mov.b${S} #${Imm-8-QI},r0l */
- {
- { 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
- & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x400 }
- },
/* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
{
{ 0, 0, 0, 0 },
@@ -40356,6 +40278,84 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } },
& ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_QI, { 0xd80f0000 }
},
+/* mov.b${S} #${Imm-8-QI},r0l */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
+ & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xc400 }
+ },
+/* mov.b${S} #${Imm-8-QI},r0h */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } },
+ & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xc300 }
+ },
+/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } },
+ & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xc50000 }
+ },
+/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } },
+ & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xc60000 }
+ },
+/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } },
+ & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xc7000000 }
+ },
+/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
+ & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x25000000 }
+ },
+/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
+ & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x35000000 }
+ },
+/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } },
+ & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x15000000 }
+ },
+/* mov.w${S} #${Imm-8-HI},r0 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } },
+ & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x50000 }
+ },
+/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } },
+ & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x240000 }
+ },
+/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } },
+ & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x340000 }
+ },
+/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } },
+ & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x14000000 }
+ },
+/* mov.b${S} #${Imm-8-QI},r0l */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } },
+ & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x400 }
+ },
/* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
{
{ 0, 0, 0, 0 },
@@ -78816,16 +78816,16 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '1', 0 } },
& ifmt_mov16_w_S_imm_a0, { 0x9d0000 }
},
-/* mov.l$S #${Dsp-16-u24},a0 */
+/* mov.l$S #${Dsp-8-u24},a0 */
{
{ 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (DSP_16_U24), ',', 'a', '0', 0 } },
+ { { MNEM, OP (S), ' ', '#', OP (DSP_8_U24), ',', 'a', '0', 0 } },
& ifmt_mov32_l_a0, { 0xbc000000 }
},
-/* mov.l$S #${Dsp-16-u24},a1 */
+/* mov.l$S #${Dsp-8-u24},a1 */
{
{ 0, 0, 0, 0 },
- { { MNEM, OP (S), ' ', '#', OP (DSP_16_U24), ',', 'a', '1', 0 } },
+ { { MNEM, OP (S), ' ', '#', OP (DSP_8_U24), ',', 'a', '1', 0 } },
& ifmt_mov32_l_a0, { 0xbd000000 }
},
/* mov.b$S r0l,a1 */
@@ -79353,14 +79353,10 @@ dis_hash_insn (buf, value)
return CGEN_DIS_HASH (buf, value);
}
-static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
-
/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
static void
-set_fields_bitsize (fields, size)
- CGEN_FIELDS *fields;
- int size;
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
{
CGEN_FIELDS_BITSIZE (fields) = size;
}
@@ -79369,15 +79365,15 @@ set_fields_bitsize (fields, size)
This plugs the opcode entries and macro instructions into the cpu table. */
void
-m32c_cgen_init_opcode_table (cd)
- CGEN_CPU_DESC cd;
+m32c_cgen_init_opcode_table (CGEN_CPU_DESC cd)
{
int i;
int num_macros = (sizeof (m32c_cgen_macro_insn_table) /
sizeof (m32c_cgen_macro_insn_table[0]));
const CGEN_IBASE *ib = & m32c_cgen_macro_insn_table[0];
const CGEN_OPCODE *oc = & m32c_cgen_macro_insn_opcode_table[0];
- CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
+ CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
memset (insns, 0, num_macros * sizeof (CGEN_INSN));
for (i = 0; i < num_macros; ++i)
{
diff --git a/opcodes/m32c-opc.h b/opcodes/m32c-opc.h
index 3fea93d..4e49ff4 100644
--- a/opcodes/m32c-opc.h
+++ b/opcodes/m32c-opc.h
@@ -1393,20 +1393,20 @@ typedef enum cgen_insn_type {
, M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI
, M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI
, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI
- , M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI
- , M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI
- , M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI
- , M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
- , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
- , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_QI
- , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI
- , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI
- , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI
- , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI
+ , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
+ , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI
+ , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
+ , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI
+ , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI
+ , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI
+ , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI
+ , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI
+ , M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI
+ , M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI
+ , M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI
, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
, M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
@@ -3080,6 +3080,7 @@ struct cgen_fields
long f_16_1;
long f_16_2;
long f_16_4;
+ long f_16_8;
long f_18_1;
long f_18_2;
long f_18_3;
@@ -3089,6 +3090,8 @@ struct cgen_fields
long f_20_4;
long f_21_3;
long f_24_2;
+ long f_24_8;
+ long f_32_16;
long f_src16_rn;
long f_src16_an;
long f_src32_an_unprefixed;
@@ -3151,6 +3154,7 @@ struct cgen_fields
long f_dsp_48_u16;
long f_dsp_48_s16;
long f_dsp_64_u16;
+ long f_dsp_8_u24;
long f_dsp_16_u24;
long f_dsp_24_u24;
long f_dsp_32_u24;
generated by cgit v1.1 at 2024-11-23 18:02:10 +0000