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-rw-r--r--gas/ChangeLog11
-rw-r--r--gas/testsuite/gas/aarch64/illegal-3.d35
-rw-r--r--gas/testsuite/gas/aarch64/illegal-3.s47
-rw-r--r--gas/testsuite/gas/aarch64/illegal.l4
-rw-r--r--gas/testsuite/gas/aarch64/illegal.s5
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/aarch64-tbl.h18
7 files changed, 123 insertions, 3 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index ac392b9..ca091bc 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,14 @@
+2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
+
+ PR 20319
+ * testsuite/gas/aarch64/illegal-3.s: Test if unallocated FMOV encodings
+ are detected as undefined.
+ * testsuite/gas/aarch64/illegal-3.d: Likewise.
+ * testsuite/gas/aarch64/illegal.s: Test if FMOV instructions that are
+ changing the size from 32 bits to 64 bits and vice versa trigger an
+ error.
+ * testsuite/gas/aarch64/illegal.l: Likewise.
+
2018-06-08 Tamar Christina <tamar.christina@arm.com>
PR binutils/21446
diff --git a/gas/testsuite/gas/aarch64/illegal-3.d b/gas/testsuite/gas/aarch64/illegal-3.d
index b073e20..5ab8956 100644
--- a/gas/testsuite/gas/aarch64/illegal-3.d
+++ b/gas/testsuite/gas/aarch64/illegal-3.d
@@ -12,3 +12,38 @@ Disassembly of section \.text:
4: 4de2d4fc .inst 0x4de2d4fc ; undefined
8: 4dc2f4ec .inst 0x4dc2f4ec ; undefined
c: 4de2f4fc .inst 0x4de2f4fc ; undefined
+ 10: 1ea04000 .inst 0x1ea04000 ; undefined
+ 14: 1ea01000 .inst 0x1ea01000 ; undefined
+ 18: 2f00f400 .inst 0x2f00f400 ; undefined
+ 1c: 1ea60000 .inst 0x1ea60000 ; undefined
+ 20: 1ea70000 .inst 0x1ea70000 ; undefined
+ 24: 9ea60000 .inst 0x9ea60000 ; undefined
+ 28: 9ea70000 .inst 0x9ea70000 ; undefined
+ 2c: 9e260000 .inst 0x9e260000 ; undefined
+ 30: 9e270000 .inst 0x9e270000 ; undefined
+ 34: 1e660000 .inst 0x1e660000 ; undefined
+ 38: 1e670000 .inst 0x1e670000 ; undefined
+ 3c: 1e2e0000 .inst 0x1e2e0000 ; undefined
+ 40: 1e2f0000 .inst 0x1e2f0000 ; undefined
+ 44: 1e6e0000 .inst 0x1e6e0000 ; undefined
+ 48: 1e6f0000 .inst 0x1e6f0000 ; undefined
+ 4c: 1eae0000 .inst 0x1eae0000 ; undefined
+ 50: 1eaf0000 .inst 0x1eaf0000 ; undefined
+ 54: 1eee0000 .inst 0x1eee0000 ; undefined
+ 58: 1eef0000 .inst 0x1eef0000 ; undefined
+ 5c: 1e2e0000 .inst 0x1e2e0000 ; undefined
+ 60: 1e2f0000 .inst 0x1e2f0000 ; undefined
+ 64: 1e6e0000 .inst 0x1e6e0000 ; undefined
+ 68: 1e6f0000 .inst 0x1e6f0000 ; undefined
+ 6c: 1eee0000 .inst 0x1eee0000 ; undefined
+ 70: 1eef0000 .inst 0x1eef0000 ; undefined
+ 74: 9e2e0000 .inst 0x9e2e0000 ; undefined
+ 78: 9e2f0000 .inst 0x9e2f0000 ; undefined
+ 7c: 9e6e0000 .inst 0x9e6e0000 ; undefined
+ 80: 9e6f0000 .inst 0x9e6f0000 ; undefined
+ 84: 9eee0000 .inst 0x9eee0000 ; undefined
+ 88: 9eef0000 .inst 0x9eef0000 ; undefined
+ 8c: 1ea60000 .inst 0x1ea60000 ; undefined
+ 90: 1ea70000 .inst 0x1ea70000 ; undefined
+ 94: 9ea60000 .inst 0x9ea60000 ; undefined
+ 98: 9ea70000 .inst 0x9ea70000 ; undefined
diff --git a/gas/testsuite/gas/aarch64/illegal-3.s b/gas/testsuite/gas/aarch64/illegal-3.s
index a8abe29..f1fc579 100644
--- a/gas/testsuite/gas/aarch64/illegal-3.s
+++ b/gas/testsuite/gas/aarch64/illegal-3.s
@@ -7,3 +7,50 @@
.inst 0x4dc2f4ec
.inst 0x4de2f4fc
+// PR 20319:
+ # Check FMOV for Unallocated Encodings
+ # FMOV (register): type == 0x10
+ .inst 0x1ea04000
+ # FMOV (scalar, immediate): type == 0x10
+ .inst 0x1ea01000
+ # FMOV (vector, immediate): Q == 0 && op == 1
+ .inst 0x2f00f400
+ # FMOV (general):
+ # type == 10 && rmode != 01
+ .inst 0x1ea60000
+ .inst 0x1ea70000
+ .inst 0x9ea60000
+ .inst 0x9ea70000
+ # rmode == 00 && fltsize != 16 && fltsize != intsize
+ .inst 0x9e260000
+ .inst 0x9e270000
+ .inst 0x1e660000
+ .inst 0x1e670000
+ # rmode == 01 && intsize != 64
+ .inst 0x1e2e0000
+ .inst 0x1e2f0000
+ .inst 0x1e6e0000
+ .inst 0x1e6f0000
+ .inst 0x1eae0000
+ .inst 0x1eaf0000
+ .inst 0x1eee0000
+ .inst 0x1eef0000
+ # rmode == 01 && fltsize != 128
+ .inst 0x1e2e0000
+ .inst 0x1e2f0000
+ .inst 0x1e6e0000
+ .inst 0x1e6f0000
+ .inst 0x1eee0000
+ .inst 0x1eef0000
+ .inst 0x9e2e0000
+ .inst 0x9e2f0000
+ .inst 0x9e6e0000
+ .inst 0x9e6f0000
+ .inst 0x9eee0000
+ .inst 0x9eef0000
+ # type == 10 && rmode != 01
+ .inst 0x1ea60000
+ .inst 0x1ea70000
+ .inst 0x9ea60000
+ .inst 0x9ea70000
+
diff --git a/gas/testsuite/gas/aarch64/illegal.l b/gas/testsuite/gas/aarch64/illegal.l
index a0985ce..0c90110 100644
--- a/gas/testsuite/gas/aarch64/illegal.l
+++ b/gas/testsuite/gas/aarch64/illegal.l
@@ -573,4 +573,6 @@
[^:]*:577: Error: .*`fmov d0,#0x8000000000000000'
[^:]*:582: Error: .*`fcmgt v0\.4s,v0\.4s,#-0\.0'
[^:]*:585: Error: .*`fcmgt v0\.2d,v0\.2d,#-0\.0'
-[^:]*:587: Error: .*
+[^:]*:589: Error: .*`fmov s9,x0'
+[^:]*:590: Error: .*`fmov d7,w1'
+[^:]*:592: Error: .*
diff --git a/gas/testsuite/gas/aarch64/illegal.s b/gas/testsuite/gas/aarch64/illegal.s
index 2002175..bf0fa84 100644
--- a/gas/testsuite/gas/aarch64/illegal.s
+++ b/gas/testsuite/gas/aarch64/illegal.s
@@ -584,4 +584,9 @@ one_label:
fcmgt v0.2d, v0.2d, #0 // OK
fcmgt v0.2d, v0.2d, #-0.0
+ # PR 20319: FMOV instructions changing the size from 32 bits
+ # to 64 bits and vice versa are illegal.
+ fmov s9, x0
+ fmov d7, w1
+
// End (for errors during literal pool generation)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8ad2f5d..3a9720d 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
+
+ PR 20319
+ * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
+ (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
+
2018-06-06 Alan Modra <amodra@gmail.com>
* xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index b416ded..1a35b3f 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -295,6 +295,13 @@
QLF2(S_S,X), \
}
+/* e.g. FMOV <Dd>, <Xn>. */
+#define QL_INT2FP_FMOV \
+{ \
+ QLF2(S_S,W), \
+ QLF2(S_D,X), \
+}
+
/* e.g. SCVTF <Hd>, <Wn>. */
#define QL_INT2FP_H \
{ \
@@ -311,6 +318,13 @@
QLF2(X,S_S), \
}
+/* e.g. FMOV <Xd>, <Dn>. */
+#define QL_FP2INT_FMOV \
+{ \
+ QLF2(W,S_S), \
+ QLF2(X,S_D), \
+}
+
/* e.g. FCVTNS <Hd>, <Wn>. */
#define QL_FP2INT_H \
{ \
@@ -3038,9 +3052,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
FF16_INSN ("fcvtas",0x1ee40000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
__FP_INSN ("fcvtau",0x1e250000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
FF16_INSN ("fcvtau",0x1ee50000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
- __FP_INSN ("fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
+ __FP_INSN ("fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT_FMOV, F_FPTYPE | F_SF),
FF16_INSN ("fmov", 0x1ee60000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
- __FP_INSN ("fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF),
+ __FP_INSN ("fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP_FMOV, F_FPTYPE | F_SF),
FF16_INSN ("fmov", 0x1ee70000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF),
__FP_INSN ("fcvtps",0x1e280000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
FF16_INSN ("fcvtps",0x1ee80000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
generated by cgit v1.1 at 2024-11-24 23:09:36 +0000