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-rw-r--r--gas/ChangeLog9
-rw-r--r--gas/config/bfin-parse.y40
-rw-r--r--gas/testsuite/ChangeLog6
-rw-r--r--gas/testsuite/gas/bfin/arithmetic.d73
-rw-r--r--gas/testsuite/gas/bfin/arithmetic.s1
-rw-r--r--gas/testsuite/gas/bfin/expected_errors.l4
-rw-r--r--gas/testsuite/gas/bfin/expected_errors.s5
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/bfin-dis.c2
9 files changed, 87 insertions, 57 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index cffe062..58c2524 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -11,6 +11,15 @@
option mode at the end of the second instruction of the vector.
(asm_1): Check option by calling check_macfunc_option.
+ * config/bfin-parse.y (check_macfunc_option): Allow (IU)
+ option for multiply and multiply-accumulate to data register
+ instruction.
+ (check_macfuncs): Don't check if accumulator matches the data register
+ here.
+ (assign_macfunc): Check if accumulator matches the
+ data register in each rule that moves to the data
+ register.
+
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* config/tc-s390.c (md_parse_option): z10 option added.
diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
index 6a36863..4a212ac 100644
--- a/gas/config/bfin-parse.y
+++ b/gas/config/bfin-parse.y
@@ -283,7 +283,7 @@ check_macfunc_option (Macfunc *a, Opt_mode *opt)
&& opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32)
|| (a->w == 1 && a->P == 1
&& opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_S2RND
- && opt->mod != M_ISS2)
+ && opt->mod != M_ISS2 && opt->mod != M_IU)
|| (a->w == 1 && a->P == 0
&& opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
&& opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
@@ -353,14 +353,6 @@ check_macfuncs (Macfunc *aa, Opt_mode *opa,
if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
return yyerror ("Destination Dregs must differ by one");
}
- /* We assign to full regs, thus obey even/odd rules. */
- else if ((aa->w && aa->P && IS_EVEN (aa->dst))
- || (ab->w && ab->P && !IS_EVEN (ab->dst)))
- return yyerror ("Even/Odd register assignment mismatch");
- /* We assign to half regs, thus obey hi/low rules. */
- else if ( (aa->w && !aa->P && !IS_H (aa->dst))
- || (ab->w && !aa->P && IS_H (ab->dst)))
- return yyerror ("High/Low register assignment mismatch");
/* Make sure mod flags get ORed, too. */
opb->mod |= opa->mod;
@@ -4006,6 +3998,11 @@ a_plusassign:
assign_macfunc:
REG ASSIGN REG_A
{
+ if (IS_A1 ($3) && IS_EVEN ($1))
+ return yyerror ("Cannot move A1 to even register");
+ else if (!IS_A1 ($3) && !IS_EVEN ($1))
+ return yyerror ("Cannot move A0 to odd register");
+
$$.w = 1;
$$.P = 1;
$$.n = IS_A1 ($3);
@@ -4013,11 +4010,6 @@ assign_macfunc:
$$.dst = $1;
$$.s0.regno = 0;
$$.s1.regno = 0;
-
- if (IS_A1 ($3) && IS_EVEN ($1))
- return yyerror ("Cannot move A1 to even register");
- else if (!IS_A1 ($3) && !IS_EVEN ($1))
- return yyerror ("Cannot move A0 to odd register");
}
| a_macfunc
{
@@ -4027,6 +4019,11 @@ assign_macfunc:
}
| REG ASSIGN LPAREN a_macfunc RPAREN
{
+ if ($4.n && IS_EVEN ($1))
+ return yyerror ("Cannot move A1 to even register");
+ else if (!$4.n && !IS_EVEN ($1))
+ return yyerror ("Cannot move A0 to odd register");
+
$$ = $4;
$$.w = 1;
$$.P = 1;
@@ -4035,6 +4032,11 @@ assign_macfunc:
| HALF_REG ASSIGN LPAREN a_macfunc RPAREN
{
+ if ($4.n && !IS_H ($1))
+ return yyerror ("Cannot move A1 to low half of register");
+ else if (!$4.n && IS_H ($1))
+ return yyerror ("Cannot move A0 to high half of register");
+
$$ = $4;
$$.w = 1;
$$.P = 0;
@@ -4043,6 +4045,11 @@ assign_macfunc:
| HALF_REG ASSIGN REG_A
{
+ if (IS_A1 ($3) && !IS_H ($1))
+ return yyerror ("Cannot move A1 to low half of register");
+ else if (!IS_A1 ($3) && IS_H ($1))
+ return yyerror ("Cannot move A0 to high half of register");
+
$$.w = 1;
$$.P = 0;
$$.n = IS_A1 ($3);
@@ -4050,11 +4057,6 @@ assign_macfunc:
$$.dst = $1;
$$.s0.regno = 0;
$$.s1.regno = 0;
-
- if (IS_A1 ($3) && !IS_H ($1))
- return yyerror ("Cannot move A1 to low half of register");
- else if (!IS_A1 ($3) && IS_H ($1))
- return yyerror ("Cannot move A0 to high half of register");
}
;
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index cdba7ae..11c0401 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -11,7 +11,11 @@
mode tests.
* gas/bfin/vector2.s: Add new vector instruction option mode test.
* gas/bfin/vector2.d: Adjust accordingly.
-
+ * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s:
+ Add check for mismatch of accumulator and data register.
+ * gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check
+ for IU option.
+
From Mike Frysinger <michael.frysinger@analog.com>
* gas/bfin/expected_errors.s, gas/bfin/expected_errors.l: Add test
for mismatched half registers in vector multipy-accumulate
diff --git a/gas/testsuite/gas/bfin/arithmetic.d b/gas/testsuite/gas/bfin/arithmetic.d
index a6c98f7..471b48c 100644
--- a/gas/testsuite/gas/bfin/arithmetic.d
+++ b/gas/testsuite/gas/bfin/arithmetic.d
@@ -141,39 +141,40 @@ Disassembly of section .text:
168: 2d c1 17 d8 R1 = \(a1 \+= R2.H \* R7.H\) \(ISS2\);
16c: 0e c0 80 58 R3 = \(a1 -= R0.L \* R0.H\);
170: 1e c1 17 59 R5 = \(a1 -= R2.L \* R7.H\) \(M, IS\);
-
-00000174 <negate>:
- 174: 85 43 R5=-R0;
- 176: 07 c4 10 ee R7=-R2\(S\);
- 17a: 07 c4 10 ce R7=-R2\(NS\);
- 17e: 0e c4 [0-3][[:xdigit:]] 00 A0=-A0;
- 182: 0e c4 [0-3][[:xdigit:]] 40 A0=-A1;
- 186: 2e c4 [0-3][[:xdigit:]] 00 A1=-A0;
- 18a: 2e c4 [0-3][[:xdigit:]] 40 A1=-A1;
- 18e: 0e c4 [0-3][[:xdigit:]] c0 A1=-A1,A0=-A0;
-
-00000192 <round_half>:
- 192: 0c c4 18 ca R5.L=R3\(RND\);
- 196: 2c c4 00 cc R6.H=R0\(RND\);
-
-0000019a <saturate>:
- 19a: 08 c4 [0-3][[:xdigit:]] 20 A0=A0\(S\);
- 19e: 08 c4 [0-3][[:xdigit:]] 60 A1=A1\(S\);
- 1a2: 08 c4 [0-3][[:xdigit:]] a0 A1=A1\(S\),A0=A0\(S\);
-
-000001a6 <signbits>:
- 1a6: 05 c6 00 0a R5.L=SIGNBITS R0;
- 1aa: 05 c6 07 80 R0.L=SIGNBITS R7.H;
- 1ae: 06 c6 00 06 R3.L=SIGNBITS A0;
- 1b2: 06 c6 00 4e R7.L=SIGNBITS A1;
-
-000001b6 <subtract>:
- 1b6: 43 53 R5=R3-R0;
- 1b8: 04 c4 38 6e R7=R7-R0 \(S\);
- 1bc: 04 c4 11 46 R3=R2-R1 \(NS\);
- 1c0: 03 c4 37 ea R5.L=R6.H-R7.H \(S\);
- 1c4: 23 c4 1b 40 R0.H=R3.L-R3.H \(NS\);
-
-000001c8 <subtract_immediate>:
- 1c8: 66 9f I2-=2;
- 1ca: 6c 9f I0-=4;
+ 174: 8d c1 8b d9 R7 = \(a1 \+= R1.H \* R3.H\) \(IU\);
+
+00000178 <negate>:
+ 178: 85 43 R5=-R0;
+ 17a: 07 c4 10 ee R7=-R2\(S\);
+ 17e: 07 c4 10 ce R7=-R2\(NS\);
+ 182: 0e c4 [0-3][[:xdigit:]] 00 A0=-A0;
+ 186: 0e c4 [0-3][[:xdigit:]] 40 A0=-A1;
+ 18a: 2e c4 [0-3][[:xdigit:]] 00 A1=-A0;
+ 18e: 2e c4 [0-3][[:xdigit:]] 40 A1=-A1;
+ 192: 0e c4 [0-3][[:xdigit:]] c0 A1=-A1,A0=-A0;
+
+00000196 <round_half>:
+ 196: 0c c4 18 ca R5.L=R3\(RND\);
+ 19a: 2c c4 00 cc R6.H=R0\(RND\);
+
+0000019e <saturate>:
+ 19e: 08 c4 [0-3][[:xdigit:]] 20 A0=A0\(S\);
+ 1a2: 08 c4 [0-3][[:xdigit:]] 60 A1=A1\(S\);
+ 1a6: 08 c4 [0-3][[:xdigit:]] a0 A1=A1\(S\),A0=A0\(S\);
+
+000001aa <signbits>:
+ 1aa: 05 c6 00 0a R5.L=SIGNBITS R0;
+ 1ae: 05 c6 07 80 R0.L=SIGNBITS R7.H;
+ 1b2: 06 c6 00 06 R3.L=SIGNBITS A0;
+ 1b6: 06 c6 00 4e R7.L=SIGNBITS A1;
+
+000001ba <subtract>:
+ 1ba: 43 53 R5=R3-R0;
+ 1bc: 04 c4 38 6e R7=R7-R0 \(S\);
+ 1c0: 04 c4 11 46 R3=R2-R1 \(NS\);
+ 1c4: 03 c4 37 ea R5.L=R6.H-R7.H \(S\);
+ 1c8: 23 c4 1b 40 R0.H=R3.L-R3.H \(NS\);
+
+000001cc <subtract_immediate>:
+ 1cc: 66 9f I2-=2;
+ 1ce: 6c 9f I0-=4;
diff --git a/gas/testsuite/gas/bfin/arithmetic.s b/gas/testsuite/gas/bfin/arithmetic.s
index 6c6300b..74ddc4e 100644
--- a/gas/testsuite/gas/bfin/arithmetic.s
+++ b/gas/testsuite/gas/bfin/arithmetic.s
@@ -173,6 +173,7 @@ multiply_accumulate_data_reg:
r1 = (a1 += r2.h * r7.h) (iss2);
r3 = (A1 -= r0.l * R0.H);
R5 = (a1 -= R2.l * R7.h) (m, is);
+ r7 = (a1+=r1.h*r3.h) (IU);
.text
.global negate
diff --git a/gas/testsuite/gas/bfin/expected_errors.l b/gas/testsuite/gas/bfin/expected_errors.l
index 1a0da39..9578e7b 100644
--- a/gas/testsuite/gas/bfin/expected_errors.l
+++ b/gas/testsuite/gas/bfin/expected_errors.l
@@ -17,3 +17,7 @@
.*:22: Error: bad option.
.*:23: Error: Bad opt mode.
.*:24: Error: Bad opt mode.
+.*:26: Error: Cannot move A1 to even register. Input text was \).
+.*:27: Error: Cannot move A1 to low half of register. Input text was \).
+.*:28: Error: Cannot move A0 to odd register. Input text was \).
+.*:29: Error: Cannot move A0 to high half of register. Input text was \).
diff --git a/gas/testsuite/gas/bfin/expected_errors.s b/gas/testsuite/gas/bfin/expected_errors.s
index 290fc47..fd5d4df 100644
--- a/gas/testsuite/gas/bfin/expected_errors.s
+++ b/gas/testsuite/gas/bfin/expected_errors.s
@@ -22,3 +22,8 @@
a0 += R2.L * R3.L (IH);
R0.H = (A1 = R4.L * R3.L) (T), A0 = R4.H * R3.L;
R0.L = (A0 = R7.L * R4.H) (T), A1 += R7.H * R4.H;
+
+ R0 = (A1 += R1.H * R3.H) (IU)
+ R0.L = (A1 += R1.H * R3.H) (IU)
+ R1 = (A0 += R1.H * R3.H) (IU)
+ R1.H = (A0 += R1.H * R3.H) (IU)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 95336e6..8360494 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -16,6 +16,10 @@
(get_allreg): New.
(decode_LDIMMhalf_0): Print out the whole register value.
+ From Jie Zhang <jie.zhang@analog.com>
+ * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
+ multiply and multiply-accumulate to data register instruction.
+
2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
* aclocal.m4: Regenerate.
diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c
index 09152ee..046027e 100644
--- a/opcodes/bfin-dis.c
+++ b/opcodes/bfin-dis.c
@@ -2755,7 +2755,7 @@ decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
if ((w1 || w0) && mmod == M_W32)
return 0;
- if (((1 << mmod) & (P ? 0x31b : 0x1b5f)) == 0)
+ if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
return 0;
if (w1 == 1 || op1 != 3)
generated by cgit v1.1 at 2024-12-05 01:18:03 +0000