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-rw-r--r--gas/ChangeLog6
-rw-r--r--gas/config/tc-ppc.c1
-rw-r--r--gas/doc/c-ppc.texi3
-rw-r--r--gas/testsuite/ChangeLog7
-rw-r--r--gas/testsuite/gas/ppc/a2.d579
-rw-r--r--gas/testsuite/gas/ppc/a2.s554
-rw-r--r--gas/testsuite/gas/ppc/ppc.exp1
-rw-r--r--include/opcode/ChangeLog4
-rw-r--r--include/opcode/ppc.h3
-rw-r--r--opcodes/ChangeLog13
-rw-r--r--opcodes/ppc-dis.c4
-rw-r--r--opcodes/ppc-opc.c211
12 files changed, 1301 insertions, 85 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index ca8ca31..675f523 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2009-09-21 Ben Elliston <bje@au.ibm.com>
+ Peter Bergner <bergner@vnet.ibm.com>
+
+ * config/tc-ppc.c (md_show_usage): Document -mpcca2.
+ * doc/c-ppc.texi (PowerPC-Opts): Document -mppca2.
+
2009-09-18 Nick Clifton <nickc@redhat.com>
* po/es.po: Updated Spanish translation.
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 80f64af..e6e6eaf 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1195,6 +1195,7 @@ PowerPC options:\n\
-mppc64, -m620 generate code for PowerPC 620/625/630\n\
-mppc64bridge generate code for PowerPC 64, including bridge insns\n\
-mbooke generate code for 32-bit PowerPC BookE\n\
+-mppca2 generate code for A2 architecture\n\
-mpower4 generate code for Power4 architecture\n\
-mpower5 generate code for Power5 architecture\n\
-mpower6 generate code for Power6 architecture\n\
diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi
index 4a19c9a..3267546 100644
--- a/gas/doc/c-ppc.texi
+++ b/gas/doc/c-ppc.texi
@@ -73,6 +73,9 @@ Generate code for PowerPC 64, including bridge insns.
@item -mbooke
Generate code for 32-bit BookE.
+@item -mppca2
+Generate code for A2 architecture.
+
@item -me300
Generate code for PowerPC e300 family.
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index f9dd967..c5b954b 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,4 +1,11 @@
2009-09-21 Ben Elliston <bje@au.ibm.com>
+ Peter Bergner <bergner@vnet.ibm.com>
+
+ * gas/ppc/a2.s: New.
+ * gas/ppc/a2.d: Likewise.
+ * gas/ppc/ppc.exp: Run the a2 dump test.
+
+2009-09-21 Ben Elliston <bje@au.ibm.com>
* gas/ppc/e500mc.d: Remove blank line at the end of file.
diff --git a/gas/testsuite/gas/ppc/a2.d b/gas/testsuite/gas/ppc/a2.d
new file mode 100644
index 0000000..a12c4a5
--- /dev/null
+++ b/gas/testsuite/gas/ppc/a2.d
@@ -0,0 +1,579 @@
+#as: -mppca2
+#objdump: -dr -Mppca2
+#name: PPCA2 tests
+
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+
+Disassembly of section \.text:
+
+0+00 <start>:
+ 0: 7c 85 32 15 add\. r4,r5,r6
+ 4: 7c 85 32 14 add r4,r5,r6
+ 8: 7c 85 30 15 addc\. r4,r5,r6
+ c: 7c 85 30 14 addc r4,r5,r6
+ 10: 7c 85 34 15 addco\. r4,r5,r6
+ 14: 7c 85 34 14 addco r4,r5,r6
+ 18: 7c 85 31 15 adde\. r4,r5,r6
+ 1c: 7c 85 31 14 adde r4,r5,r6
+ 20: 7c 85 35 15 addeo\. r4,r5,r6
+ 24: 7c 85 35 14 addeo r4,r5,r6
+ 28: 38 85 00 0d addi r4,r5,13
+ 2c: 38 85 ff f3 addi r4,r5,-13
+ 30: 34 85 00 0d addic\. r4,r5,13
+ 34: 34 85 ff f3 addic\. r4,r5,-13
+ 38: 30 85 00 0d addic r4,r5,13
+ 3c: 30 85 ff f3 addic r4,r5,-13
+ 40: 3c 85 00 17 addis r4,r5,23
+ 44: 3c 85 ff e9 addis r4,r5,-23
+ 48: 7c 85 01 d5 addme\. r4,r5
+ 4c: 7c 85 01 d4 addme r4,r5
+ 50: 7c 85 05 d5 addmeo\. r4,r5
+ 54: 7c 85 05 d4 addmeo r4,r5
+ 58: 7c 85 36 15 addo\. r4,r5,r6
+ 5c: 7c 85 36 14 addo r4,r5,r6
+ 60: 7c 85 01 95 addze\. r4,r5
+ 64: 7c 85 01 94 addze r4,r5
+ 68: 7c 85 05 95 addzeo\. r4,r5
+ 6c: 7c 85 05 94 addzeo r4,r5
+ 70: 7c a4 30 39 and\. r4,r5,r6
+ 74: 7c a4 30 38 and r4,r5,r6
+ 78: 7c a4 30 79 andc\. r4,r5,r6
+ 7c: 7c a4 30 78 andc r4,r5,r6
+ 80: 70 a4 00 06 andi\. r4,r5,6
+ 84: 74 a4 00 06 andis\. r4,r5,6
+ 88: 00 00 02 00 attn
+ 8c: 48 00 00 02 ba 0 <start>
+ 8c: R_PPC_ADDR24 label_abs
+ 90: 40 01 00 00 bdnzf gt,90 <start\+0x90>
+ 90: R_PPC_REL14 foo
+ 94: 40 01 00 00 bdnzf gt,94 <start\+0x94>
+ 94: R_PPC_REL14 foo
+ 98: 40 01 00 00 bdnzf gt,98 <start\+0x98>
+ 98: R_PPC_REL14 foo
+ 9c: 40 85 00 02 blea cr1,0 <start>
+ 9c: R_PPC_ADDR14 foo_abs
+ a0: 40 c5 00 02 blea- cr1,0 <start>
+ a0: R_PPC_ADDR14 foo_abs
+ a4: 40 e5 00 02 blea\+ cr1,0 <start>
+ a4: R_PPC_ADDR14 foo_abs
+ a8: 4c 86 0c 20 bcctr 4,4\*cr1\+eq,1
+ ac: 4c 86 04 20 bnectr cr1
+ b0: 4c a6 04 20 bcctr\+ 4,4\*cr1\+eq
+ b4: 4c 86 0c 21 bcctrl 4,4\*cr1\+eq,1
+ b8: 4c 86 04 21 bnectrl cr1
+ bc: 4c a6 04 21 bcctrl\+ 4,4\*cr1\+eq
+ c0: 40 01 00 01 bdnzfl gt,c0 <start\+0xc0>
+ c0: R_PPC_REL14 foo
+ c4: 40 01 00 01 bdnzfl gt,c4 <start\+0xc4>
+ c4: R_PPC_REL14 foo
+ c8: 40 01 00 01 bdnzfl gt,c8 <start\+0xc8>
+ c8: R_PPC_REL14 foo
+ cc: 40 85 00 03 blela cr1,0 <start>
+ cc: R_PPC_ADDR14 foo_abs
+ d0: 40 c5 00 03 blela- cr1,0 <start>
+ d0: R_PPC_ADDR14 foo_abs
+ d4: 40 e5 00 03 blela\+ cr1,0 <start>
+ d4: R_PPC_ADDR14 foo_abs
+ d8: 4c 86 08 20 bclr 4,4\*cr1\+eq,1
+ dc: 4c 86 00 20 bnelr cr1
+ e0: 4c a6 00 20 bclr\+ 4,4\*cr1\+eq
+ e4: 4c 86 08 21 bclrl 4,4\*cr1\+eq,1
+ e8: 4c 86 00 21 bnelrl cr1
+ ec: 4c a6 00 21 bclrl\+ 4,4\*cr1\+eq
+ f0: 48 00 00 00 b f0 <start\+0xf0>
+ f0: R_PPC_REL24 label
+ f4: 48 00 00 03 bla 0 <start>
+ f4: R_PPC_ADDR24 label_abs
+ f8: 48 00 00 01 bl f8 <start\+0xf8>
+ f8: R_PPC_REL24 label
+ fc: 7d 6a 61 f8 bpermd r10,r11,r12
+ 100: 7c a7 40 00 cmpd cr1,r7,r8
+ 104: 7d 6a 63 f8 cmpb r10,r11,r12
+ 108: 2c aa 00 0d cmpdi cr1,r10,13
+ 10c: 2c aa ff f3 cmpdi cr1,r10,-13
+ 110: 7c a7 40 40 cmpld cr1,r7,r8
+ 114: 28 aa 00 64 cmpldi cr1,r10,100
+ 118: 7e b4 00 75 cntlzd\. r20,r21
+ 11c: 7e b4 00 74 cntlzd r20,r21
+ 120: 7e b4 00 35 cntlzw\. r20,r21
+ 124: 7e b4 00 34 cntlzw r20,r21
+ 128: 4c 22 1a 02 crand gt,eq,so
+ 12c: 4c 22 19 02 crandc gt,eq,so
+ 130: 4c 22 1a 42 creqv gt,eq,so
+ 134: 4c 22 19 c2 crnand gt,eq,so
+ 138: 4c 22 18 42 crnor gt,eq,so
+ 13c: 4c 22 1b 82 cror gt,eq,so
+ 140: 4c 22 1b 42 crorc gt,eq,so
+ 144: 4c 22 19 82 crxor gt,eq,so
+ 148: 7c 0a 5d ec dcba r10,r11
+ 14c: 7c 0a 58 ac dcbf r10,r11
+ 150: 7c 2a 58 ac dcbfl r10,r11
+ 154: 7c 0a 58 fe dcbfep r10,r11
+ 158: 7c 0a 5b ac dcbi r10,r11
+ 15c: 7c 0a 5b 0c dcblc r10,r11
+ 160: 7c 2a 5b 0c dcblc 1,r10,r11
+ 164: 7c 0a 58 6c dcbst r10,r11
+ 168: 7c 0a 58 7e dcbstep r10,r11
+ 16c: 7c 0a 5a 2c dcbt r10,r11
+ 170: 7c 2a 5a 2c dcbt r10,r11,1
+ 174: 7d 4b 62 7e dcbtep r10,r11,r12
+ 178: 7c 0a 59 4c dcbtls r10,r11
+ 17c: 7c 2a 59 4c dcbtls 1,r10,r11
+ 180: 7c 0a 59 ec dcbtst r10,r11
+ 184: 7c 2a 59 ec dcbtst r10,r11,1
+ 188: 7d 4b 61 fe dcbtstep r10,r11,r12
+ 18c: 7c 0a 59 0c dcbtstls r10,r11
+ 190: 7c 2a 59 0c dcbtstls 1,r10,r11
+ 194: 7c 0a 5f ec dcbz r10,r11
+ 198: 7c 0a 5f fe dcbzep r10,r11
+ 19c: 7c 00 03 8c dci
+ 1a0: 7d 40 03 8c dci 10
+ 1a4: 7e 95 b3 d3 divd\. r20,r21,r22
+ 1a8: 7e 95 b3 d2 divd r20,r21,r22
+ 1ac: 7e 95 b7 d3 divdo\. r20,r21,r22
+ 1b0: 7e 95 b7 d2 divdo r20,r21,r22
+ 1b4: 7e 95 b3 93 divdu\. r20,r21,r22
+ 1b8: 7e 95 b3 92 divdu r20,r21,r22
+ 1bc: 7e 95 b7 93 divduo\. r20,r21,r22
+ 1c0: 7e 95 b7 92 divduo r20,r21,r22
+ 1c4: 7e 95 b3 d7 divw\. r20,r21,r22
+ 1c8: 7e 95 b3 d6 divw r20,r21,r22
+ 1cc: 7e 95 b7 d7 divwo\. r20,r21,r22
+ 1d0: 7e 95 b7 d6 divwo r20,r21,r22
+ 1d4: 7e 95 b3 97 divwu\. r20,r21,r22
+ 1d8: 7e 95 b3 96 divwu r20,r21,r22
+ 1dc: 7e 95 b7 97 divwuo\. r20,r21,r22
+ 1e0: 7e 95 b7 96 divwuo r20,r21,r22
+ 1e4: 7e b4 b2 39 eqv\. r20,r21,r22
+ 1e8: 7e b4 b2 38 eqv r20,r21,r22
+ 1ec: 7c 0a 58 66 eratilx 0,r10,r11
+ 1f0: 7c 2a 58 66 eratilx 1,r10,r11
+ 1f4: 7c ea 58 66 eratilx 7,r10,r11
+ 1f8: 7d 4b 66 66 erativax r10,r11,r12
+ 1fc: 7d 4b 01 66 eratre r10,r11,0
+ 200: 7d 4b 19 66 eratre r10,r11,3
+ 204: 7d 4b 61 27 eratsx\. r10,r11,r12
+ 208: 7d 4b 61 26 eratsx r10,r11,r12
+ 20c: 7d 4b 01 a6 eratwe r10,r11,0
+ 210: 7d 4b 19 a6 eratwe r10,r11,3
+ 214: 7d 6a 07 75 extsb\. r10,r11
+ 218: 7d 6a 07 74 extsb r10,r11
+ 21c: 7d 6a 07 35 extsh\. r10,r11
+ 220: 7d 6a 07 34 extsh r10,r11
+ 224: 7d 6a 07 b5 extsw\. r10,r11
+ 228: 7d 6a 07 b4 extsw r10,r11
+ 22c: fe 80 aa 11 fabs\. f20,f21
+ 230: fe 80 aa 10 fabs f20,f21
+ 234: fe 95 b0 2b fadd\. f20,f21,f22
+ 238: fe 95 b0 2a fadd f20,f21,f22
+ 23c: ee 95 b0 2b fadds\. f20,f21,f22
+ 240: ee 95 b0 2a fadds f20,f21,f22
+ 244: fe 80 ae 9d fcfid\. f20,f21
+ 248: fe 80 ae 9c fcfid f20,f21
+ 24c: fc 14 a8 40 fcmpo cr0,f20,f21
+ 250: fc 94 a8 40 fcmpo cr1,f20,f21
+ 254: fc 14 a8 00 fcmpu cr0,f20,f21
+ 258: fc 94 a8 00 fcmpu cr1,f20,f21
+ 25c: fe 95 b0 11 fcpsgn\. f20,f21,f22
+ 260: fe 95 b0 10 fcpsgn f20,f21,f22
+ 264: fe 80 ae 5d fctid\. f20,f21
+ 268: fe 80 ae 5c fctid f20,f21
+ 26c: fe 80 ae 5f fctidz\. f20,f21
+ 270: fe 80 ae 5e fctidz f20,f21
+ 274: fe 80 a8 1d fctiw\. f20,f21
+ 278: fe 80 a8 1c fctiw f20,f21
+ 27c: fe 80 a8 1f fctiwz\. f20,f21
+ 280: fe 80 a8 1e fctiwz f20,f21
+ 284: fe 95 b0 25 fdiv\. f20,f21,f22
+ 288: fe 95 b0 24 fdiv f20,f21,f22
+ 28c: ee 95 b0 25 fdivs\. f20,f21,f22
+ 290: ee 95 b0 24 fdivs f20,f21,f22
+ 294: fe 95 bd bb fmadd\. f20,f21,f22,f23
+ 298: fe 95 bd ba fmadd f20,f21,f22,f23
+ 29c: ee 95 bd bb fmadds\. f20,f21,f22,f23
+ 2a0: ee 95 bd ba fmadds f20,f21,f22,f23
+ 2a4: fe 80 a8 91 fmr\. f20,f21
+ 2a8: fe 80 a8 90 fmr f20,f21
+ 2ac: fe 95 bd b9 fmsub\. f20,f21,f22,f23
+ 2b0: fe 95 bd b8 fmsub f20,f21,f22,f23
+ 2b4: ee 95 bd b9 fmsubs\. f20,f21,f22,f23
+ 2b8: ee 95 bd b8 fmsubs f20,f21,f22,f23
+ 2bc: fe 95 05 b3 fmul\. f20,f21,f22
+ 2c0: fe 95 05 b2 fmul f20,f21,f22
+ 2c4: ee 95 05 b3 fmuls\. f20,f21,f22
+ 2c8: ee 95 05 b2 fmuls f20,f21,f22
+ 2cc: fe 80 a9 11 fnabs\. f20,f21
+ 2d0: fe 80 a9 10 fnabs f20,f21
+ 2d4: fe 80 a8 51 fneg\. f20,f21
+ 2d8: fe 80 a8 50 fneg f20,f21
+ 2dc: fe 95 bd bf fnmadd\. f20,f21,f22,f23
+ 2e0: fe 95 bd be fnmadd f20,f21,f22,f23
+ 2e4: ee 95 bd bf fnmadds\. f20,f21,f22,f23
+ 2e8: ee 95 bd be fnmadds f20,f21,f22,f23
+ 2ec: fe 95 bd bd fnmsub\. f20,f21,f22,f23
+ 2f0: fe 95 bd bc fnmsub f20,f21,f22,f23
+ 2f4: ee 95 bd bd fnmsubs\. f20,f21,f22,f23
+ 2f8: ee 95 bd bc fnmsubs f20,f21,f22,f23
+ 2fc: fe 80 a8 31 fre\. f20,f21
+ 300: fe 80 a8 30 fre f20,f21
+ 304: fe 80 a8 31 fre\. f20,f21
+ 308: fe 80 a8 30 fre f20,f21
+ 30c: fe 81 a8 31 fre\. f20,f21,1
+ 310: fe 81 a8 30 fre f20,f21,1
+ 314: ee 80 a8 31 fres\. f20,f21
+ 318: ee 80 a8 30 fres f20,f21
+ 31c: ee 80 a8 31 fres\. f20,f21
+ 320: ee 80 a8 30 fres f20,f21
+ 324: ee 81 a8 31 fres\. f20,f21,1
+ 328: ee 81 a8 30 fres f20,f21,1
+ 32c: fe 80 ab d1 frim\. f20,f21
+ 330: fe 80 ab d0 frim f20,f21
+ 334: fe 80 ab 11 frin\. f20,f21
+ 338: fe 80 ab 10 frin f20,f21
+ 33c: fe 80 ab 91 frip\. f20,f21
+ 340: fe 80 ab 90 frip f20,f21
+ 344: fe 80 ab 51 friz\. f20,f21
+ 348: fe 80 ab 50 friz f20,f21
+ 34c: fe 80 a8 19 frsp\. f20,f21
+ 350: fe 80 a8 18 frsp f20,f21
+ 354: fe 80 a8 35 frsqrte\. f20,f21
+ 358: fe 80 a8 34 frsqrte f20,f21
+ 35c: fe 80 a8 35 frsqrte\. f20,f21
+ 360: fe 80 a8 34 frsqrte f20,f21
+ 364: fe 81 a8 35 frsqrte\. f20,f21,1
+ 368: fe 81 a8 34 frsqrte f20,f21,1
+ 36c: ee 80 a8 34 frsqrtes f20,f21
+ 370: ee 80 a8 35 frsqrtes\. f20,f21
+ 374: ee 80 a8 34 frsqrtes f20,f21
+ 378: ee 80 a8 35 frsqrtes\. f20,f21
+ 37c: ee 81 a8 34 frsqrtes f20,f21,1
+ 380: ee 81 a8 35 frsqrtes\. f20,f21,1
+ 384: fe 95 bd af fsel\. f20,f21,f22,f23
+ 388: fe 95 bd ae fsel f20,f21,f22,f23
+ 38c: fe 80 a8 2d fsqrt\. f20,f21
+ 390: fe 80 a8 2c fsqrt f20,f21
+ 394: ee 80 a8 2d fsqrts\. f20,f21
+ 398: ee 80 a8 2c fsqrts f20,f21
+ 39c: fe 95 b0 29 fsub\. f20,f21,f22
+ 3a0: fe 95 b0 28 fsub f20,f21,f22
+ 3a4: ee 95 b0 29 fsubs\. f20,f21,f22
+ 3a8: ee 95 b0 28 fsubs f20,f21,f22
+ 3ac: 7c 0a 5f ac icbi r10,r11
+ 3b0: 7c 0a 5f be icbiep r10,r11
+ 3b4: 7c 0a 58 2c icbt r10,r11
+ 3b8: 7c ea 58 2c icbt 7,r10,r11
+ 3bc: 7c 0a 5b cc icbtls r10,r11
+ 3c0: 7c ea 5b cc icbtls 7,r10,r11
+ 3c4: 7d 40 07 8c ici 10
+ 3c8: 7d 4b 63 2d icswx\. r10,r11,r12
+ 3cc: 7d 4b 63 2c icswx r10,r11,r12
+ 3d0: 7d 4b 65 de isel r10,r11,r12,23
+ 3d4: 4c 00 01 2c isync
+ 3d8: 7d 4b 60 be lbepx r10,r11,r12
+ 3dc: 89 4b ff ef lbz r10,-17\(r11\)
+ 3e0: 89 4b 00 11 lbz r10,17\(r11\)
+ 3e4: 8d 4b ff ff lbzu r10,-1\(r11\)
+ 3e8: 8d 4b 00 01 lbzu r10,1\(r11\)
+ 3ec: 7d 4b 68 ee lbzux r10,r11,r13
+ 3f0: 7d 4b 68 ae lbzx r10,r11,r13
+ 3f4: e9 4b ff f8 ld r10,-8\(r11\)
+ 3f8: e9 4b 00 08 ld r10,8\(r11\)
+ 3fc: 7d 4b 60 a8 ldarx r10,r11,r12
+ 400: 7d 4b 60 a9 ldarx r10,r11,r12,1
+ 404: 7d 4b 64 28 ldbrx r10,r11,r12
+ 408: 7d 4b 60 3a ldepx r10,r11,r12
+ 40c: e9 4b ff f9 ldu r10,-8\(r11\)
+ 410: e9 4b 00 09 ldu r10,8\(r11\)
+ 414: 7d 4b 60 6a ldux r10,r11,r12
+ 418: 7d 4b 60 2a ldx r10,r11,r12
+ 41c: ca 8a ff f8 lfd f20,-8\(r10\)
+ 420: ca 8a 00 08 lfd f20,8\(r10\)
+ 424: 7e 8a 5c be lfdepx f20,r10,r11
+ 428: ce 8a ff f8 lfdu f20,-8\(r10\)
+ 42c: ce 8a 00 08 lfdu f20,8\(r10\)
+ 430: 7e 8a 5c ee lfdux f20,r10,r11
+ 434: 7e 8a 5c ae lfdx f20,r10,r11
+ 438: 7e 8a 5e ae lfiwax f20,r10,r11
+ 43c: 7e 8a 5e ee lfiwzx f20,r10,r11
+ 440: c2 8a ff fc lfs f20,-4\(r10\)
+ 444: c2 8a 00 04 lfs f20,4\(r10\)
+ 448: c6 8a ff fc lfsu f20,-4\(r10\)
+ 44c: c6 8a 00 04 lfsu f20,4\(r10\)
+ 450: 7e 8a 5c 6e lfsux f20,r10,r11
+ 454: 7e 8a 5c 2e lfsx f20,r10,r11
+ 458: a9 4b 00 02 lha r10,2\(r11\)
+ 45c: ad 4b ff fe lhau r10,-2\(r11\)
+ 460: 7d 4b 62 ee lhaux r10,r11,r12
+ 464: 7d 4b 62 ae lhax r10,r11,r12
+ 468: 7d 4b 66 2c lhbrx r10,r11,r12
+ 46c: 7d 4b 62 3e lhepx r10,r11,r12
+ 470: a1 4b ff fe lhz r10,-2\(r11\)
+ 474: a1 4b 00 02 lhz r10,2\(r11\)
+ 478: a5 4b ff fe lhzu r10,-2\(r11\)
+ 47c: a5 4b 00 02 lhzu r10,2\(r11\)
+ 480: 7d 4b 62 6e lhzux r10,r11,r12
+ 484: 7d 4b 62 2e lhzx r10,r11,r12
+ 488: ba 8a 00 10 lmw r20,16\(r10\)
+ 48c: 7d 4b 0c aa lswi r10,r11,1
+ 490: 7d 4b 04 aa lswi r10,r11,32
+ 494: 7d 4b 64 2a lswx r10,r11,r12
+ 498: e9 4b ff fe lwa r10,-4\(r11\)
+ 49c: e9 4b 00 06 lwa r10,4\(r11\)
+ 4a0: 7d 4b 60 28 lwarx r10,r11,r12
+ 4a4: 7d 4b 60 29 lwarx r10,r11,r12,1
+ 4a8: 7d 4b 62 ea lwaux r10,r11,r12
+ 4ac: 7d 4b 62 aa lwax r10,r11,r12
+ 4b0: 7d 4b 64 2c lwbrx r10,r11,r12
+ 4b4: 7d 4b 60 3e lwepx r10,r11,r12
+ 4b8: 81 4b ff fc lwz r10,-4\(r11\)
+ 4bc: 81 4b 00 04 lwz r10,4\(r11\)
+ 4c0: 85 4b ff fc lwzu r10,-4\(r11\)
+ 4c4: 85 4b 00 04 lwzu r10,4\(r11\)
+ 4c8: 7d 4b 60 6e lwzux r10,r11,r12
+ 4cc: 7d 4b 60 2e lwzx r10,r11,r12
+ 4d0: 7c 00 06 ac mbar
+ 4d4: 7c 00 06 ac mbar
+ 4d8: 7c 00 06 ac mbar
+ 4dc: 7c 20 06 ac mbar 1
+ 4e0: 4c 04 00 00 mcrf cr0,cr1
+ 4e4: fd 90 00 80 mcrfs cr3,cr4
+ 4e8: 7c 00 04 00 mcrxr cr0
+ 4ec: 7d 80 04 00 mcrxr cr3
+ 4f0: 7c 60 00 26 mfcr r3
+ 4f4: 7c 60 00 26 mfcr r3
+ 4f8: 7c 70 10 26 mfocrf r3,1
+ 4fc: 7c 78 00 26 mfocrf r3,128
+ 500: 7d 4a 3a 87 mfdcr\. r10,234
+ 504: 7d 4a 3a 86 mfdcr r10,234
+ 508: 7d 4b 02 07 mfdcrx\. r10,r11
+ 50c: 7d 4b 02 06 mfdcrx r10,r11
+ 510: fe 80 04 8f mffs\. f20
+ 514: fe 80 04 8e mffs f20
+ 518: 7d 40 00 a6 mfmsr r10
+ 51c: 7c 70 10 26 mfocrf r3,1
+ 520: 7c 78 00 26 mfocrf r3,128
+ 524: 7d 4a 3a a6 mfspr r10,234
+ 528: 7d 4c 42 e6 mftbl r10
+ 52c: 7d 4d 42 e6 mftbu r10
+ 530: 7c 00 51 dc msgclr r10
+ 534: 7c 00 51 9c msgsnd r10
+ 538: 7c 60 01 20 mtcrf 0,r3
+ 53c: 7c 70 11 20 mtocrf 1,r3
+ 540: 7c 78 01 20 mtocrf 128,r3
+ 544: 7c 6f f1 20 mtcr r3
+ 548: 7d 4a 3b 87 mtdcr\. 234,r10
+ 54c: 7d 4a 3b 86 mtdcr 234,r10
+ 550: 7d 6a 03 07 mtdcrx\. r10,r11
+ 554: 7d 6a 03 06 mtdcrx r10,r11
+ 558: fc 60 00 8d mtfsb0\. so
+ 55c: fc 60 00 8c mtfsb0 so
+ 560: fc 60 00 4d mtfsb1\. so
+ 564: fc 60 00 4c mtfsb1 so
+ 568: fc 0c a5 8f mtfsf\. 6,f20
+ 56c: fc 0c a5 8e mtfsf 6,f20
+ 570: fc 0c a5 8f mtfsf\. 6,f20
+ 574: fc 0c a5 8e mtfsf 6,f20
+ 578: fe 0d a5 8f mtfsf\. 6,f20,1,1
+ 57c: fe 0d a5 8e mtfsf 6,f20,1,1
+ 580: ff 00 01 0d mtfsfi\. 6,0
+ 584: ff 00 01 0c mtfsfi 6,0
+ 588: ff 00 d1 0d mtfsfi\. 6,13
+ 58c: ff 00 d1 0c mtfsfi 6,13
+ 590: ff 01 d1 0d mtfsfi\. 6,13,1
+ 594: ff 01 d1 0c mtfsfi 6,13,1
+ 598: 7d 40 01 24 mtmsr r10
+ 59c: 7d 40 01 24 mtmsr r10
+ 5a0: 7d 41 01 24 mtmsr r10,1
+ 5a4: 7c 70 11 20 mtocrf 1,r3
+ 5a8: 7c 78 01 20 mtocrf 128,r3
+ 5ac: 7d 4a 3b a6 mtspr 234,r10
+ 5b0: 7e 95 b0 93 mulhd\. r20,r21,r22
+ 5b4: 7e 95 b0 92 mulhd r20,r21,r22
+ 5b8: 7e 95 b0 13 mulhdu\. r20,r21,r22
+ 5bc: 7e 95 b0 12 mulhdu r20,r21,r22
+ 5c0: 7e 95 b0 97 mulhw\. r20,r21,r22
+ 5c4: 7e 95 b0 96 mulhw r20,r21,r22
+ 5c8: 7e 95 b0 17 mulhwu\. r20,r21,r22
+ 5cc: 7e 95 b0 16 mulhwu r20,r21,r22
+ 5d0: 7e 95 b1 d3 mulld\. r20,r21,r22
+ 5d4: 7e 95 b1 d2 mulld r20,r21,r22
+ 5d8: 7e 95 b5 d3 mulldo\. r20,r21,r22
+ 5dc: 7e 95 b5 d2 mulldo r20,r21,r22
+ 5e0: 1e 95 00 64 mulli r20,r21,100
+ 5e4: 1e 95 ff 9c mulli r20,r21,-100
+ 5e8: 7e 95 b1 d7 mullw\. r20,r21,r22
+ 5ec: 7e 95 b1 d6 mullw r20,r21,r22
+ 5f0: 7e 95 b5 d7 mullwo\. r20,r21,r22
+ 5f4: 7e 95 b5 d6 mullwo r20,r21,r22
+ 5f8: 7e b4 b3 b9 nand\. r20,r21,r22
+ 5fc: 7e b4 b3 b8 nand r20,r21,r22
+ 600: 7e 95 00 d1 neg\. r20,r21
+ 604: 7e 95 00 d0 neg r20,r21
+ 608: 7e 95 04 d1 nego\. r20,r21
+ 60c: 7e 95 04 d0 nego r20,r21
+ 610: 7e b4 b0 f9 nor\. r20,r21,r22
+ 614: 7e b4 b0 f8 nor r20,r21,r22
+ 618: 7e b4 b3 79 or\. r20,r21,r22
+ 61c: 7e b4 b3 78 or r20,r21,r22
+ 620: 7e b4 b3 39 orc\. r20,r21,r22
+ 624: 7e b4 b3 38 orc r20,r21,r22
+ 628: 62 b4 10 00 ori r20,r21,4096
+ 62c: 66 b4 10 00 oris r20,r21,4096
+ 630: 7d 6a 00 f4 popcntb r10,r11
+ 634: 7d 6a 03 f4 popcntd r10,r11
+ 638: 7d 6a 02 f4 popcntw r10,r11
+ 63c: 7d 6a 01 74 prtyd r10,r11
+ 640: 7d 6a 01 34 prtyw r10,r11
+ 644: 4c 00 00 66 rfci
+ 648: 4c 00 00 cc rfgi
+ 64c: 4c 00 00 64 rfi
+ 650: 4c 00 00 4c rfmci
+ 654: 79 6a 67 f1 rldcl\. r10,r11,r12,63
+ 658: 79 6a 67 f0 rldcl r10,r11,r12,63
+ 65c: 79 6a 67 f3 rldcr\. r10,r11,r12,63
+ 660: 79 6a 67 f2 rldcr r10,r11,r12,63
+ 664: 79 6a bf e9 rldic\. r10,r11,23,63
+ 668: 79 6a bf e8 rldic r10,r11,23,63
+ 66c: 79 6a bf e1 rldicl\. r10,r11,23,63
+ 670: 79 6a bf e0 rldicl r10,r11,23,63
+ 674: 79 6a bf e5 rldicr\. r10,r11,23,63
+ 678: 79 6a bf e4 rldicr r10,r11,23,63
+ 67c: 79 6a bf ed rldimi\. r10,r11,23,63
+ 680: 79 6a bf ec rldimi r10,r11,23,63
+ 684: 51 6a b8 3f rlwimi\. r10,r11,23,0,31
+ 688: 51 6a b8 3e rlwimi r10,r11,23,0,31
+ 68c: 55 6a b8 3f rotlwi\. r10,r11,23
+ 690: 55 6a b8 3e rotlwi r10,r11,23
+ 694: 5d 6a b8 3f rotlw\. r10,r11,r23
+ 698: 5d 6a b8 3e rotlw r10,r11,r23
+ 69c: 44 00 00 02 sc
+ 6a0: 44 00 0c 82 sc 100
+ 6a4: 7d 6a 60 37 sld\. r10,r11,r12
+ 6a8: 7d 6a 60 36 sld r10,r11,r12
+ 6ac: 7d 6a 60 31 slw\. r10,r11,r12
+ 6b0: 7d 6a 60 30 slw r10,r11,r12
+ 6b4: 7d 6a 66 35 srad\. r10,r11,r12
+ 6b8: 7d 6a 66 34 srad r10,r11,r12
+ 6bc: 7d 6a fe 77 sradi\. r10,r11,63
+ 6c0: 7d 6a fe 76 sradi r10,r11,63
+ 6c4: 7d 6a 66 31 sraw\. r10,r11,r12
+ 6c8: 7d 6a 66 30 sraw r10,r11,r12
+ 6cc: 7d 6a fe 71 srawi\. r10,r11,31
+ 6d0: 7d 6a fe 70 srawi r10,r11,31
+ 6d4: 7d 6a 64 37 srd\. r10,r11,r12
+ 6d8: 7d 6a 64 36 srd r10,r11,r12
+ 6dc: 7d 6a 64 31 srw\. r10,r11,r12
+ 6e0: 7d 6a 64 30 srw r10,r11,r12
+ 6e4: 99 4b ff ff stb r10,-1\(r11\)
+ 6e8: 99 4b 00 01 stb r10,1\(r11\)
+ 6ec: 7d 4b 61 be stbepx r10,r11,r12
+ 6f0: 9d 4b ff ff stbu r10,-1\(r11\)
+ 6f4: 9d 4b 00 01 stbu r10,1\(r11\)
+ 6f8: 7d 4b 61 ee stbux r10,r11,r12
+ 6fc: 7d 4b 61 ae stbx r10,r11,r12
+ 700: f9 4b ff f8 std r10,-8\(r11\)
+ 704: f9 4b 00 08 std r10,8\(r11\)
+ 708: 7d 4b 65 28 stdbrx r10,r11,r12
+ 70c: 7d 4b 61 ad stdcx\. r10,r11,r12
+ 710: 7d 4b 61 3a stdepx r10,r11,r12
+ 714: f9 4b ff f9 stdu r10,-8\(r11\)
+ 718: f9 4b 00 09 stdu r10,8\(r11\)
+ 71c: 7d 4b 61 6a stdux r10,r11,r12
+ 720: 7d 4b 61 2a stdx r10,r11,r12
+ 724: da 8a ff f8 stfd f20,-8\(r10\)
+ 728: da 8a 00 08 stfd f20,8\(r10\)
+ 72c: 7e 8a 5d be stfdepx f20,r10,r11
+ 730: de 8a ff f8 stfdu f20,-8\(r10\)
+ 734: de 8a 00 08 stfdu f20,8\(r10\)
+ 738: 7e 8a 5d ee stfdux f20,r10,r11
+ 73c: 7e 8a 5d ae stfdx f20,r10,r11
+ 740: 7e 8a 5f ae stfiwx f20,r10,r11
+ 744: d2 8a ff fc stfs f20,-4\(r10\)
+ 748: d2 8a 00 04 stfs f20,4\(r10\)
+ 74c: d6 8a ff fc stfsu f20,-4\(r10\)
+ 750: d6 8a 00 04 stfsu f20,4\(r10\)
+ 754: 7e 8a 5d 6e stfsux f20,r10,r11
+ 758: 7e 8a 5d 2e stfsx f20,r10,r11
+ 75c: b1 4b ff fe sth r10,-2\(r11\)
+ 760: b1 4b 00 02 sth r10,2\(r11\)
+ 764: b1 4b ff fc sth r10,-4\(r11\)
+ 768: b1 4b 00 04 sth r10,4\(r11\)
+ 76c: 7d 4b 67 2c sthbrx r10,r11,r12
+ 770: 7d 4b 63 3e sthepx r10,r11,r12
+ 774: b5 4b ff fe sthu r10,-2\(r11\)
+ 778: b5 4b 00 02 sthu r10,2\(r11\)
+ 77c: 7d 4b 63 6e sthux r10,r11,r12
+ 780: 7d 4b 63 2e sthx r10,r11,r12
+ 784: be 8a 00 10 stmw r20,16\(r10\)
+ 788: 7d 4b 0d aa stswi r10,r11,1
+ 78c: 7d 4b 05 aa stswi r10,r11,32
+ 790: 7d 4b 65 2a stswx r10,r11,r12
+ 794: 7d 4b 65 2c stwbrx r10,r11,r12
+ 798: 7d 4b 61 2d stwcx\. r10,r11,r12
+ 79c: 7d 4b 61 3e stwepx r10,r11,r12
+ 7a0: 95 4b ff fc stwu r10,-4\(r11\)
+ 7a4: 95 4b 00 04 stwu r10,4\(r11\)
+ 7a8: 7d 4b 61 6e stwux r10,r11,r12
+ 7ac: 7d 4b 61 2e stwx r10,r11,r12
+ 7b0: 7e 95 b0 51 subf\. r20,r21,r22
+ 7b4: 7e 95 b0 50 subf r20,r21,r22
+ 7b8: 7e 95 b0 11 subfc\. r20,r21,r22
+ 7bc: 7e 95 b0 10 subfc r20,r21,r22
+ 7c0: 7e 95 b4 11 subfco\. r20,r21,r22
+ 7c4: 7e 95 b4 10 subfco r20,r21,r22
+ 7c8: 7e 95 b1 11 subfe\. r20,r21,r22
+ 7cc: 7e 95 b1 10 subfe r20,r21,r22
+ 7d0: 7e 95 b5 11 subfeo\. r20,r21,r22
+ 7d4: 7e 95 b5 10 subfeo r20,r21,r22
+ 7d8: 22 95 00 64 subfic r20,r21,100
+ 7dc: 22 95 ff 9c subfic r20,r21,-100
+ 7e0: 7e 95 01 d1 subfme\. r20,r21
+ 7e4: 7e 95 01 d0 subfme r20,r21
+ 7e8: 7e 95 05 d1 subfmeo\. r20,r21
+ 7ec: 7e 95 05 d0 subfmeo r20,r21
+ 7f0: 7e 95 b4 51 subfo\. r20,r21,r22
+ 7f4: 7e 95 b4 50 subfo r20,r21,r22
+ 7f8: 7e 95 01 91 subfze\. r20,r21
+ 7fc: 7e 95 01 90 subfze r20,r21
+ 800: 7e 95 05 91 subfzeo\. r20,r21
+ 804: 7e 95 05 90 subfzeo r20,r21
+ 808: 7c 00 04 ac sync
+ 80c: 7c 00 04 ac sync
+ 810: 7c 00 04 ac sync
+ 814: 7c 20 04 ac lwsync
+ 818: 7c aa 58 88 tdlge r10,r11
+ 81c: 08 aa 00 64 tdlgei r10,100
+ 820: 08 aa ff 9c tdlgei r10,-100
+ 824: 7c 6a 58 24 tlbilxva r10,r11
+ 828: 7c 0a 5e 24 tlbivax r10,r11
+ 82c: 7c 00 07 64 tlbre
+ 830: 7d 4b 3f 64 tlbre r10,r11,7
+ 834: 7c 0a 5e a5 tlbsrx\. r10,r11
+ 838: 7d 4b 67 25 tlbsx\. r10,r11,r12
+ 83c: 7d 4b 67 24 tlbsx r10,r11,r12
+ 840: 7c 00 04 6c tlbsync
+ 844: 7c 00 07 a4 tlbwe
+ 848: 7d 4b 3f a4 tlbwe r10,r11,7
+ 84c: 7c aa 58 08 twlge r10,r11
+ 850: 0c aa 00 64 twlgei r10,100
+ 854: 0c aa ff 9c twlgei r10,-100
+ 858: 7c 00 00 7c wait
+ 85c: 7c 00 00 7c wait
+ 860: 7c 20 00 7c waitrsv
+ 864: 7c 40 00 7c waitimpl
+ 868: 7c 40 00 7c waitimpl
+ 86c: 7c 20 00 7c waitrsv
+ 870: 7c 00 01 6c wchkall
+ 874: 7c 00 01 6c wchkall
+ 878: 7d 80 01 6c wchkall cr3
+ 87c: 7c 2a 5d 6c wclr 1,r10,r11
+ 880: 7c 20 05 6c wclrall 1
+ 884: 7c 4a 5d 6c wclrone r10,r11
+ 888: 7d 40 01 06 wrtee r10
+ 88c: 7c 00 81 46 wrteei 1
+ 890: 7d 6a 62 79 xor\. r10,r11,r12
+ 894: 7d 6a 62 78 xor r10,r11,r12
+ 898: 69 6a 10 00 xori r10,r11,4096
+ 89c: 6d 6a 10 00 xoris r10,r11,4096
diff --git a/gas/testsuite/gas/ppc/a2.s b/gas/testsuite/gas/ppc/a2.s
new file mode 100644
index 0000000..0101ab9
--- /dev/null
+++ b/gas/testsuite/gas/ppc/a2.s
@@ -0,0 +1,554 @@
+ .section ".text"
+start:
+ add. 4,5,6
+ add 4,5,6
+ addc. 4,5,6
+ addc 4,5,6
+ addco. 4,5,6
+ addco 4,5,6
+ adde. 4,5,6
+ adde 4,5,6
+ addeo. 4,5,6
+ addeo 4,5,6
+ addi 4,5,13
+ addi 4,5,-13
+ addic. 4,5,13
+ addic. 4,5,-13
+ addic 4,5,13
+ addic 4,5,-13
+ addis 4,5,23
+ addis 4,5,-23
+ addme. 4,5
+ addme 4,5
+ addmeo. 4,5
+ addmeo 4,5
+ addo. 4,5,6
+ addo 4,5,6
+ addze. 4,5
+ addze 4,5
+ addzeo. 4,5
+ addzeo 4,5
+ and. 4,5,6
+ and 4,5,6
+ andc. 4,5,6
+ andc 4,5,6
+ andi. 4,5,6
+ andis. 4,5,6
+ attn
+ ba label_abs
+ bc 0,1,foo
+ bc- 0,1,foo
+ bc+ 0,1,foo
+ bca 4,5,foo_abs
+ bca- 4,5,foo_abs
+ bca+ 4,5,foo_abs
+ bcctr 4,6,1
+ bcctr- 4,6
+ bcctr+ 4,6
+ bcctrl 4,6,1
+ bcctrl- 4,6
+ bcctrl+ 4,6
+ bcl 0,1,foo
+ bcl- 0,1,foo
+ bcl+ 0,1,foo
+ bcla 4,5,foo_abs
+ bcla- 4,5,foo_abs
+ bcla+ 4,5,foo_abs
+ bclr 4,6,1
+ bclr- 4,6
+ bclr+ 4,6
+ bclrl 4,6,1
+ bclrl- 4,6
+ bclrl+ 4,6
+ b label
+ bla label_abs
+ bl label
+ bpermd 10,11,12
+ cmp 1,1,7,8
+ cmpb 10,11,12
+ cmpi 1,1,10,13
+ cmpi 1,1,10,-13
+ cmpl 1,1,7,8
+ cmpli 1,1,10,100
+ cntlzd. 20,21
+ cntlzd 20,21
+ cntlzw. 20,21
+ cntlzw 20,21
+ crand 1,2,3
+ crandc 1,2,3
+ creqv 1,2,3
+ crnand 1,2,3
+ crnor 1,2,3
+ cror 1,2,3
+ crorc 1,2,3
+ crxor 1,2,3
+ dcba 10,11
+ dcbf 10,11,0
+ dcbf 10,11,1
+ dcbfep 10,11
+ dcbi 10,11
+ dcblc 0,10,11
+ dcblc 1,10,11
+ dcbst 10,11
+ dcbstep 10,11
+ dcbt 10,11,0
+ dcbt 10,11,1
+ dcbtep 10,11,12
+ dcbtls 0,10,11
+ dcbtls 1,10,11
+ dcbtst 10,11,0
+ dcbtst 10,11,1
+ dcbtstep 10,11,12
+ dcbtstls 0,10,11
+ dcbtstls 1,10,11
+ dcbz 10,11
+ dcbzep 10,11
+ dci
+ dci 10
+ divd. 20,21,22
+ divd 20,21,22
+ divdo. 20,21,22
+ divdo 20,21,22
+ divdu. 20,21,22
+ divdu 20,21,22
+ divduo. 20,21,22
+ divduo 20,21,22
+ divw. 20,21,22
+ divw 20,21,22
+ divwo. 20,21,22
+ divwo 20,21,22
+ divwu. 20,21,22
+ divwu 20,21,22
+ divwuo. 20,21,22
+ divwuo 20,21,22
+ eqv. 20,21,22
+ eqv 20,21,22
+ eratilx 0,10,11
+ eratilx 1,10,11
+ eratilx 7,10,11
+ erativax 10,11,12
+ eratre 10,11,0
+ eratre 10,11,3
+ eratsx. 10,11,12
+ eratsx 10,11,12
+ eratwe 10,11,0
+ eratwe 10,11,3
+ extsb. 10,11
+ extsb 10,11
+ extsh. 10,11
+ extsh 10,11
+ extsw. 10,11
+ extsw 10,11
+ fabs. 20,21
+ fabs 20,21
+ fadd. 20,21,22
+ fadd 20,21,22
+ fadds. 20,21,22
+ fadds 20,21,22
+ fcfid. 20,21
+ fcfid 20,21
+ fcmpo 0,20,21
+ fcmpo 1,20,21
+ fcmpu 0,20,21
+ fcmpu 1,20,21
+ fcpsgn. 20,21,22
+ fcpsgn 20,21,22
+ fctid. 20,21
+ fctid 20,21
+ fctidz. 20,21
+ fctidz 20,21
+ fctiw. 20,21
+ fctiw 20,21
+ fctiwz. 20,21
+ fctiwz 20,21
+ fdiv. 20,21,22
+ fdiv 20,21,22
+ fdivs. 20,21,22
+ fdivs 20,21,22
+ fmadd. 20,21,22,23
+ fmadd 20,21,22,23
+ fmadds. 20,21,22,23
+ fmadds 20,21,22,23
+ fmr. 20,21
+ fmr 20,21
+ fmsub. 20,21,22,23
+ fmsub 20,21,22,23
+ fmsubs. 20,21,22,23
+ fmsubs 20,21,22,23
+ fmul. 20,21,22
+ fmul 20,21,22
+ fmuls. 20,21,22
+ fmuls 20,21,22
+ fnabs. 20,21
+ fnabs 20,21
+ fneg. 20,21
+ fneg 20,21
+ fnmadd. 20,21,22,23
+ fnmadd 20,21,22,23
+ fnmadds. 20,21,22,23
+ fnmadds 20,21,22,23
+ fnmsub. 20,21,22,23
+ fnmsub 20,21,22,23
+ fnmsubs. 20,21,22,23
+ fnmsubs 20,21,22,23
+ fre. 20,21
+ fre 20,21
+ fre. 20,21,0
+ fre 20,21,0
+ fre. 20,21,1
+ fre 20,21,1
+ fres. 20,21
+ fres 20,21
+ fres. 20,21,0
+ fres 20,21,0
+ fres. 20,21,1
+ fres 20,21,1
+ frim. 20,21
+ frim 20,21
+ frin. 20,21
+ frin 20,21
+ frip. 20,21
+ frip 20,21
+ friz. 20,21
+ friz 20,21
+ frsp. 20,21
+ frsp 20,21
+ frsqrte. 20,21
+ frsqrte 20,21
+ frsqrte. 20,21,0
+ frsqrte 20,21,0
+ frsqrte. 20,21,1
+ frsqrte 20,21,1
+ frsqrtes 20,21
+ frsqrtes. 20,21
+ frsqrtes 20,21,0
+ frsqrtes. 20,21,0
+ frsqrtes 20,21,1
+ frsqrtes. 20,21,1
+ fsel. 20,21,22,23
+ fsel 20,21,22,23
+ fsqrt. 20,21
+ fsqrt 20,21
+ fsqrts. 20,21
+ fsqrts 20,21
+ fsub. 20,21,22
+ fsub 20,21,22
+ fsubs. 20,21,22
+ fsubs 20,21,22
+ icbi 10,11
+ icbiep 10,11
+ icbt 0,10,11
+ icbt 7,10,11
+ icbtls 0,10,11
+ icbtls 7,10,11
+ ici 10
+ icswx. 10,11,12
+ icswx 10,11,12
+ isel 10,11,12,23
+ isync
+ lbepx 10,11,12
+ lbz 10,-17(11)
+ lbz 10,17(11)
+ lbzu 10,-1(11)
+ lbzu 10,1(11)
+ lbzux 10,11,13
+ lbzx 10,11,13
+ ld 10,-8(11)
+ ld 10,8(11)
+ ldarx 10,11,12,0
+ ldarx 10,11,12,1
+ ldbrx 10,11,12
+ ldepx 10,11,12
+ ldu 10,-8(11)
+ ldu 10,8(11)
+ ldux 10,11,12
+ ldx 10,11,12
+ lfd 20,-8(10)
+ lfd 20,8(10)
+ lfdepx 20,10,11
+ lfdu 20,-8(10)
+ lfdu 20,8(10)
+ lfdux 20,10,11
+ lfdx 20,10,11
+ lfiwax 20,10,11
+ lfiwzx 20,10,11
+ lfs 20,-4(10)
+ lfs 20,4(10)
+ lfsu 20,-4(10)
+ lfsu 20,4(10)
+ lfsux 20,10,11
+ lfsx 20,10,11
+ lha 10,2(11)
+ lhau 10,-2(11)
+ lhaux 10,11,12
+ lhax 10,11,12
+ lhbrx 10,11,12
+ lhepx 10,11,12
+ lhz 10,-2(11)
+ lhz 10,2(11)
+ lhzu 10,-2(11)
+ lhzu 10,2(11)
+ lhzux 10,11,12
+ lhzx 10,11,12
+ lmw 20,16(10)
+ lswi 10,11,1
+ lswi 10,11,32
+ lswx 10,11,12
+ lwa 10,-4(11)
+ lwa 10,4(11)
+ lwarx 10,11,12,0
+ lwarx 10,11,12,1
+ lwaux 10,11,12
+ lwax 10,11,12
+ lwbrx 10,11,12
+ lwepx 10,11,12
+ lwz 10,-4(11)
+ lwz 10,4(11)
+ lwzu 10,-4(11)
+ lwzu 10,4(11)
+ lwzux 10,11,12
+ lwzx 10,11,12
+ mbar
+ mbar 0
+ eieio
+ mbar 1
+ mcrf 0,1
+ mcrfs 3,4
+ mcrxr 0
+ mcrxr 3
+ mfcr 3
+ mfcr 3,0
+ mfcr 3,0x01
+ mfcr 3,0x80
+ mfdcr. 10,234
+ mfdcr 10,234
+ mfdcrx. 10,11
+ mfdcrx 10,11
+ mffs. 20
+ mffs 20
+ mfmsr 10
+ mfocrf 3,0x01
+ mfocrf 3,0x80
+ mfspr 10,234
+ mftb 10,268
+ mftb 10,269
+ msgclr 10
+ msgsnd 10
+ mtcrf 0x00,3
+ mtcrf 0x01,3
+ mtcrf 0x80,3
+ mtcrf 0xff,3
+ mtdcr. 234,10
+ mtdcr 234,10
+ mtdcrx. 10,11
+ mtdcrx 10,11
+ mtfsb0. 3
+ mtfsb0 3
+ mtfsb1. 3
+ mtfsb1 3
+ mtfsf. 6,20
+ mtfsf 6,20
+ mtfsf. 6,20,0,0
+ mtfsf 6,20,0,0
+ mtfsf. 6,20,1,1
+ mtfsf 6,20,1,1
+ mtfsfi. 6,0
+ mtfsfi 6,0
+ mtfsfi. 6,13,0
+ mtfsfi 6,13,0
+ mtfsfi. 6,13,1
+ mtfsfi 6,13,1
+ mtmsr 10
+ mtmsr 10,0
+ mtmsr 10,1
+ mtocrf 0x01,3
+ mtocrf 0x80,3
+ mtspr 234,10
+ mulhd. 20,21,22
+ mulhd 20,21,22
+ mulhdu. 20,21,22
+ mulhdu 20,21,22
+ mulhw. 20,21,22
+ mulhw 20,21,22
+ mulhwu. 20,21,22
+ mulhwu 20,21,22
+ mulld. 20,21,22
+ mulld 20,21,22
+ mulldo. 20,21,22
+ mulldo 20,21,22
+ mulli 20,21,100
+ mulli 20,21,-100
+ mullw. 20,21,22
+ mullw 20,21,22
+ mullwo. 20,21,22
+ mullwo 20,21,22
+ nand. 20,21,22
+ nand 20,21,22
+ neg. 20,21
+ neg 20,21
+ nego. 20,21
+ nego 20,21
+ nor. 20,21,22
+ nor 20,21,22
+ or. 20,21,22
+ or 20,21,22
+ orc. 20,21,22
+ orc 20,21,22
+ ori 20,21,0x1000
+ oris 20,21,0x1000
+ popcntb 10,11
+ popcntd 10,11
+ popcntw 10,11
+ prtyd 10,11
+ prtyw 10,11
+ rfci
+ rfgi
+ rfi
+ rfmci
+ rldcl. 10,11,12,0x3f
+ rldcl 10,11,12,0x3f
+ rldcr. 10,11,12,0x3f
+ rldcr 10,11,12,0x3f
+ rldic. 10,11,23,0x3f
+ rldic 10,11,23,0x3f
+ rldicl. 10,11,23,0x3f
+ rldicl 10,11,23,0x3f
+ rldicr. 10,11,23,0x3f
+ rldicr 10,11,23,0x3f
+ rldimi. 10,11,23,0x3f
+ rldimi 10,11,23,0x3f
+ rlwimi. 10,11,23,0,31
+ rlwimi 10,11,23,0,31
+ rlwinm. 10,11,23,0,31
+ rlwinm 10,11,23,0,31
+ rlwnm. 10,11,23,0,31
+ rlwnm 10,11,23,0,31
+ sc
+ sc 100
+ sld. 10,11,12
+ sld 10,11,12
+ slw. 10,11,12
+ slw 10,11,12
+ srad. 10,11,12
+ srad 10,11,12
+ sradi. 10,11,0x3f
+ sradi 10,11,0x3f
+ sraw. 10,11,12
+ sraw 10,11,12
+ srawi. 10,11,31
+ srawi 10,11,31
+ srd. 10,11,12
+ srd 10,11,12
+ srw. 10,11,12
+ srw 10,11,12
+ stb 10,-1(11)
+ stb 10,1(11)
+ stbepx 10,11,12
+ stbu 10,-1(11)
+ stbu 10,1(11)
+ stbux 10,11,12
+ stbx 10,11,12
+ std 10,-8(11)
+ std 10,8(11)
+ stdbrx 10,11,12
+ stdcx. 10,11,12
+ stdepx 10,11,12
+ stdu 10,-8(11)
+ stdu 10,8(11)
+ stdux 10,11,12
+ stdx 10,11,12
+ stfd 20,-8(10)
+ stfd 20,8(10)
+ stfdepx 20,10,11
+ stfdu 20,-8(10)
+ stfdu 20,8(10)
+ stfdux 20,10,11
+ stfdx 20,10,11
+ stfiwx 20,10,11
+ stfs 20,-4(10)
+ stfs 20,4(10)
+ stfsu 20,-4(10)
+ stfsu 20,4(10)
+ stfsux 20,10,11
+ stfsx 20,10,11
+ sth 10,-2(11)
+ sth 10,2(11)
+ sth 10,-4(11)
+ sth 10,4(11)
+ sthbrx 10,11,12
+ sthepx 10,11,12
+ sthu 10,-2(11)
+ sthu 10,2(11)
+ sthux 10,11,12
+ sthx 10,11,12
+ stmw 20,16(10)
+ stswi 10,11,1
+ stswi 10,11,32
+ stswx 10,11,12
+ stwbrx 10,11,12
+ stwcx. 10,11,12
+ stwepx 10,11,12
+ stwu 10,-4(11)
+ stwu 10,4(11)
+ stwux 10,11,12
+ stwx 10,11,12
+ subf. 20,21,22
+ subf 20,21,22
+ subfc. 20,21,22
+ subfc 20,21,22
+ subfco. 20,21,22
+ subfco 20,21,22
+ subfe. 20,21,22
+ subfe 20,21,22
+ subfeo. 20,21,22
+ subfeo 20,21,22
+ subfic 20,21,100
+ subfic 20,21,-100
+ subfme. 20,21
+ subfme 20,21
+ subfmeo. 20,21
+ subfmeo 20,21
+ subfo. 20,21,22
+ subfo 20,21,22
+ subfze. 20,21
+ subfze 20,21
+ subfzeo. 20,21
+ subfzeo 20,21
+ sync
+ msync
+ sync 0
+ sync 1
+ td 5,10,11
+ tdi 5,10,100
+ tdi 5,10,-100
+ tlbilx 3,10,11
+ tlbivax 10,11
+ tlbre
+ tlbre 10,11,7
+ tlbsrx. 10,11
+ tlbsx. 10,11,12
+ tlbsx 10,11,12
+ tlbsync
+ tlbwe
+ tlbwe 10,11,7
+ tw 5,10,11
+ twi 5,10,100
+ twi 5,10,-100
+ wait
+ wait 0
+ wait 1
+ wait 2
+ waitimpl
+ waitrsv
+ wchkall
+ wchkall 0
+ wchkall 3
+ wclr 1,10,11
+ wclrall 1
+ wclrone 10,11
+ wrtee 10
+ wrteei 1
+ xor. 10,11,12
+ xor 10,11,12
+ xori 10,11,0x1000
+ xoris 10,11,0x1000
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index a00d258..5c4af17 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -42,6 +42,7 @@ if { [istarget powerpc*-*-*] } then {
run_list_test "range" "-a32"
run_dump_test "ppc750ps"
run_dump_test "e500mc"
+ run_dump_test "a2"
run_dump_test "cell"
run_dump_test "common"
run_dump_test "power4_32"
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 476fdcf..0282c46 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2009-09-21 Ben Elliston <bje@au.ibm.com>
+
+ * ppc.h (PPC_OPCODE_PPCA2): New.
+
2009-09-05 Martin Thuresson <martin@mtme.org>
* ia64.h (struct ia64_operand): Renamed member class to op_class.
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index dc9a7ba..79b1562 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -165,6 +165,9 @@ extern const int powerpc_num_opcodes;
/* Opcode is supported by Vector-Scalar (VSX) Unit */
#define PPC_OPCODE_VSX 0x80000000
+/* Opcode is supported by A2. */
+#define PPC_OPCODE_PPCA2 0x100000000ULL
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d1b7770..7eeb118 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,16 @@
+2009-09-21 Ben Elliston <bje@au.ibm.com>
+ Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-dis.c (ppc_opts): Add "ppca2" entry.
+ * ppc-opc.c (powerpc_opcodes): Add eratilx, eratsx, eratsx.,
+ eratre, wchkall, eratwe, ldawx., mdfcrx., mfdcr. mtdcrx., icswx,
+ icswx., mtdcr., dci, wclrone, wclrall, wclr, erativax, tlbsrx.,
+ ici mnemonics.
+ (ERAT_T): New operand.
+ (XWC_MASK): New mask.
+ (XOPL2): New macro.
+ (PPCA2): Define.
+
2009-09-18 Nick Clifton <nickc@redhat.com>
* po/es.po: Updated Spanish translation.
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 8511345..70d2bee 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -141,6 +141,10 @@ struct ppc_mopt ppc_opts[] = {
{ "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64_BRIDGE
| PPC_OPCODE_64),
0 },
+ { "ppca2", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK
+ | PPC_OPCODE_64 | PPC_OPCODE_PPCA2),
+ 0 },
{ "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
0 },
{ "pwr", (PPC_OPCODE_POWER | PPC_OPCODE_32),
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 1a69d33..1d32ff0 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -638,6 +638,9 @@ const struct powerpc_operand powerpc_operands[] =
/* The UIM field in an XX2 form instruction. */
#define UIM DMEX + 1
{ 0x3, 16, NULL, NULL, 0 },
+
+#define ERAT_T UIM + 1
+ { 0x7, 21, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
@@ -1621,6 +1624,9 @@ extract_dm (unsigned long insn,
/* The mask for an X form instruction. */
#define X_MASK XRC (0x3f, 0x3ff, 1)
+/* An X form wait instruction with everything filled in except the WC field. */
+#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
+
/* The mask for an XX1 form instruction. */
#define XX1_MASK X (0x3f, 0x3ff)
@@ -1683,6 +1689,9 @@ extract_dm (unsigned long insn,
/* An X form instruction with the L bit specified. */
#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
+/* An X form instruction with the L bits specified. */
+#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
+
/* An X form instruction with RT fields specified */
#define XRT(op, xop, rt) (X ((op), (xop)) \
| ((((unsigned long)(rt)) & 0x1f) << 21))
@@ -1924,6 +1933,7 @@ extract_dm (unsigned long insn,
#define PPCCHLK PPC_OPCODE_CACHELCK
#define PPCRFMCI PPC_OPCODE_RFMCI
#define E500MC PPC_OPCODE_E500MC
+#define PPCA2 PPC_OPCODE_PPCA2
/* The opcode table.
@@ -1947,7 +1957,7 @@ extract_dm (unsigned long insn,
constrained otherwise by disassembler operation. */
const struct powerpc_opcode powerpc_opcodes[] = {
-{"attn", X(0,256), X_MASK, POWER4, PPCNONE, {0}},
+{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPCNONE, {0}},
{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
@@ -3140,15 +3150,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}},
{"crnor", XL(19,33), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
-{"rfmci", X(19,38), 0xffffffff, PPCRFMCI, PPCNONE, {0}},
+{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2, PPCNONE, {0}},
{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCNONE, {0}},
{"rfi", XL(19,50), 0xffffffff, COM, PPCNONE, {0}},
-{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300, PPCNONE, {0}},
+{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2, PPCNONE, {0}},
{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCNONE, {0}},
-{"rfgi", XL(19,102), 0xffffffff, E500MC, PPCNONE, {0}},
+{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
{"crandc", XL(19,129), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
@@ -3464,10 +3474,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
-{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC, PPCNONE, {0}},
-{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC, PPCNONE, {0}},
-{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC, PPCNONE, {RA0, RB}},
-{"tlbilx", X(31,18), X_MASK, E500MC, PPCNONE, {T, RA0, RB}},
+{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}},
+{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}},
+{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, PPCNONE, {RA0, RB}},
+{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, PPCNONE, {T, RA0, RB}},
{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}},
{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM, POWER4, {RT}},
@@ -3477,7 +3487,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"ldx", X(31,21), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}},
-{"icbt", X(31,22), X_MASK, BOOKE|PPCE300, PPCNONE, {CT, RA, RB}},
+{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2, PPCNONE, {CT, RA, RB}},
{"lwzx", X(31,23), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
{"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
@@ -3498,11 +3508,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"and", XRC(31,28,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
{"and.", XRC(31,28,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"maskg", XRC(31,29,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-{"maskg.", XRC(31,29,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
+{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
+{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
-{"ldepx", X(31,29), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
-{"lwepx", X(31,31), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
+{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
+{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
@@ -3528,6 +3538,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"subf.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
{"sub.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}},
+{"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
+
{"lbarx", X(31,52), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
{"ldux", X(31,53), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
@@ -3543,11 +3555,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"andc", XRC(31,60,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
{"andc.", XRC(31,60,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC, PPCNONE, {0}},
-{"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC, PPCNONE, {0}},
-{"wait", X(31,62), XWC_MASK, POWER7|E500MC, PPCNONE, {WC}},
+{"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
+{"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
+{"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2, PPCNONE, {WC}},
-{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
+{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}},
@@ -3586,7 +3598,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lbzx", X(31,87), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
-{"lbepx", X(31,95), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
+{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
{"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
@@ -3612,9 +3624,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"not.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
{"nor.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
+{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
-{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, PPCNONE, {RS}},
+{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {RS}},
{"dcbtstls", X(31,134), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
@@ -3639,6 +3651,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mtmsr", X(31,146), XRLARB_MASK, COM, PPCNONE, {RS, A_L}},
+{"eratsx", XRC(31,147,0), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
+{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
+
{"stdx", X(31,149), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}},
{"stwcx.", XRC(31,150,1), X_MASK, PPC, PPCNONE, {RS, RA0, RB}},
@@ -3652,13 +3667,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"sle", XRC(31,153,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"sle.", XRC(31,153,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-{"prtyw", X(31,154), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
+{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}},
-{"stdepx", X(31,157), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
+{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
-{"stwepx", X(31,159), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
+{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
-{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE, PPCNONE, {E}},
+{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {E}},
{"dcbtls", X(31,166), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
@@ -3669,15 +3684,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}},
+{"eratre", X(31,179), X_MASK, PPCA2, PPCNONE, {RT, RA, WS}},
+
{"stdux", X(31,181), X_MASK, PPC64, PPCNONE, {RS, RAS, RB}},
+{"wchkall", X(31,182), X_MASK, PPCA2, PPCNONE, {OBF}},
+
{"stwux", X(31,183), X_MASK, PPCCOM, PPCNONE, {RS, RAS, RB}},
{"stux", X(31,183), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
{"sliq", XRC(31,184,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
{"sliq.", XRC(31,184,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-{"prtyd", X(31,186), XRB_MASK, POWER6, PPCNONE, {RA, RS}},
+{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}},
{"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
@@ -3692,10 +3711,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"msgsnd", XRTRA(31,206,0,0),XRTRA_MASK,E500MC, PPCNONE, {RB}},
+{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE, {RB}},
{"mtsr", X(31,210), XRB_MASK|(1<<20), COM32, PPCNONE, {SR, RS}},
+{"eratwe", X(31,211), X_MASK, PPCA2, PPCNONE, {RS, RA, WS}},
+
+{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
+
{"stdcx.", XRC(31,214,1), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}},
{"stbx", X(31,215), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
@@ -3706,7 +3729,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
-{"stbepx", X(31,223), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
+{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
{"icblc", X(31,230), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
@@ -3731,8 +3754,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
-{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC, PPCNONE, {RB}},
+{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
+{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE, {RB}},
{"mtsrin", X(31,242), XRA_MASK, PPC32, PPCNONE, {RS, RB}},
{"mtsri", X(31,242), XRA_MASK, POWER32, PPCNONE, {RS, RB}},
@@ -3745,11 +3768,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
{"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
-{"bpermd", X(31,252), X_MASK, POWER7, PPCNONE, {RA, RS, RB}},
+{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, PPCNONE, {RA, RS, RB}},
-{"dcbtstep", XRT(31,255,0), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
+{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
-{"mfdcrx", X(31,259), X_MASK, BOOKE, PPCNONE, {RS, RA}},
+{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2, PPCNONE, {RS, RA}},
+{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}},
{"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}},
@@ -3762,7 +3786,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"ehpriv", X(31,270), 0xffffffff, E500MC, PPCNONE, {0}},
+{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}},
{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPCNONE, {RB, L}},
@@ -3782,7 +3806,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"eqv", XRC(31,284,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
{"eqv.", XRC(31,284,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"lhepx", X(31,287), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
+{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
{"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}},
@@ -3798,7 +3822,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"xor", XRC(31,316,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
{"xor.", XRC(31,316,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"dcbtep", XRT(31,319,0), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
+{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, PPCNONE, {RT}},
{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, PPCNONE, {RT}},
@@ -3834,7 +3858,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}},
{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}},
{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}},
-{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE, PPCNONE, {RT, SPR}},
+{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {RT, SPR}},
+{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}},
{"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
{"div.", XO(31,331,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
@@ -4047,7 +4072,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, PPCNONE, {RT}},
{"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, PPCNONE, {RT}},
-{"mftb", X(31,371), X_MASK, CLASSIC, POWER7, {RT, TBR}},
+{"mftb", X(31,371), X_MASK, CLASSIC|PPCA2, POWER7, {RT, TBR}},
{"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
@@ -4055,9 +4080,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lhaux", X(31,375), X_MASK, COM, PPCNONE, {RT, RAL, RB}},
-{"popcntw", X(31,378), XRB_MASK, POWER7, PPCNONE, {RA, RS}},
+{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}},
-{"mtdcrx", X(31,387), X_MASK, BOOKE, PPCNONE, {RA, RS}},
+{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2, PPCNONE, {RA, RS}},
+{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}},
{"dcblc", X(31,390), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
@@ -4071,12 +4097,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
+{"icswx", XRC(31,406,0), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}},
+{"icswx.", XRC(31,406,1), X_MASK, PPCA2, PPCNONE, {RS, RA, RB}},
+
{"sthx", X(31,407), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
{"orc", XRC(31,412,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
{"orc.", XRC(31,412,1), X_MASK, COM, PPCNONE, {RA, RS, RB}},
-{"sthepx", X(31,415), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
+{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}},
{"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}},
@@ -4132,9 +4161,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}},
{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}},
{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}},
-{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE, PPCNONE, {SPR, RS}},
+{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {SPR, RS}},
+{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}},
-{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}},
+{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, PPCA2, {RA, RB}},
+{"dci", X(31,454), XRARB_MASK, PPCA2, PPCNONE, {CT}},
{"divdu", XO(31,457,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
@@ -4305,7 +4336,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"dsn", X(31,483), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
-{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCNONE, {RT, RA, RB}},
+{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA, RB}},
{"icbtls", X(31,486), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
@@ -4326,9 +4357,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}},
-{"popcntd", X(31,506), XRB_MASK, POWER7, PPCNONE, {RA, RS}},
+{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}},
-{"cmpb", X(31,508), X_MASK, POWER6, PPCNONE, {RA, RS, RB}},
+{"cmpb", X(31,508), X_MASK, POWER6|PPCA2, PPCNONE, {RA, RS, RB}},
{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, POWER7, {BF}},
@@ -4353,7 +4384,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}},
-{"ldbrx", X(31,532), X_MASK, CELL|POWER7, PPCNONE, {RT, RA0, RB}},
+{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RT, RA0, RB}},
{"lswx", X(31,533), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
{"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
@@ -4407,13 +4438,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, PPCNONE, {0}},
{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE, {LS}},
-{"msync", X(31,598), 0xffffffff, BOOKE, PPCNONE, {0}},
+{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2, PPCNONE, {0}},
{"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}},
{"lfdx", X(31,599), X_MASK, COM, PPCNONE, {FRT, RA0, RB}},
{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
-{"lfdepx", X(31,607), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}},
+{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, PPCNONE, {FRT, RA, RB}},
{"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
@@ -4450,7 +4481,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mfsrin", X(31,659), XRA_MASK, PPC32, PPCNONE, {RT, RB}},
-{"stdbrx", X(31,660), X_MASK, CELL|POWER7, PPCNONE, {RS, RA0, RB}},
+{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RS, RA0, RB}},
{"stswx", X(31,661), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
{"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
@@ -4471,6 +4502,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
+{"wclrone", XOPL2(31,694,2),XRT_MASK, PPCA2, PPCNONE, {RA0, RB}},
+{"wclrall", X(31,694), XRARB_MASK, PPCA2, PPCNONE, {L}},
+{"wclr", X(31,694), X_MASK, PPCA2, PPCNONE, {L, RA0, RB}},
+
{"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
{"stfsux", X(31,695), X_MASK, COM, PPCNONE, {FRS, RAS, RB}},
@@ -4508,7 +4543,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
-{"stfdepx", X(31,735), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}},
+{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, PPCNONE, {FRS, RA, RB}},
{"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
@@ -4534,7 +4569,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
-{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, PPCNONE, {RA, RB}},
+{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2, PPCNONE, {RA, RB}},
{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
{"stfdux", X(31,759), X_MASK, COM, PPCNONE, {FRS, RAS, RB}},
@@ -4555,7 +4590,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
-{"tlbivax", X(31,786), XRT_MASK, BOOKE, PPCNONE, {RA, RB}},
+{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2, PPCNONE, {RA, RB}},
{"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
@@ -4580,6 +4615,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rac", X(31,818), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+{"erativax", X(31,819), X_MASK, PPCA2, PPCNONE, {RS, RA0, RB}},
+
{"lhzcix", X(31,821), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, PPCNONE, {STRM}},
@@ -4599,14 +4636,17 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
+{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, PPCNONE, {RA, RB}},
+
{"slbmfev", X(31,851), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
{"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
-{"eieio", X(31,854), 0xffffffff, PPC, BOOKE, {0}},
-{"mbar", X(31,854), X_MASK, BOOKE, PPCNONE, {MO}},
+{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2, {0}},
+{"mbar", X(31,854), X_MASK, BOOKE|PPCA2, PPCNONE, {MO}},
+{"eieio", X(31,854), 0xffffffff, PPCA2, PPCNONE, {0}},
-{"lfiwax", X(31,855), X_MASK, POWER6, PPCNONE, {FRT, RA0, RB}},
+{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2, PPCNONE, {FRT, RA0, RB}},
{"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
{"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
@@ -4618,7 +4658,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},
-{"lfiwzx", X(31,887), X_MASK, POWER7, PPCNONE, {FRT, RA0, RB}},
+{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, PPCNONE, {FRT, RA0, RB}},
{"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
@@ -4630,8 +4670,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
-{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, PPCNONE, {RTO, RA, RB}},
-{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, PPCNONE, {RTO, RA, RB}},
+{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {RTO, RA, RB}},
+{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {RTO, RA, RB}},
{"slbmfee", X(31,915), XRA_MASK, PPC64, PPCNONE, {RT, RB}},
@@ -4664,9 +4704,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stxvw4ux", X(31,940), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
-{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
-{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
-{"tlbre", X(31,946), X_MASK, PPC403|BOOKE, PPCNONE, {RSO, RAOPT, SHO}},
+{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
+{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
+{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {RSO, RAOPT, SHO}},
{"sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
@@ -4679,6 +4719,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}},
{"iccci", X(31,966), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}},
+{"ici", X(31,966), XRARB_MASK, PPCA2, PPCNONE, {CT}},
{"divduo", XO(31,457,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}},
@@ -4688,10 +4729,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
-{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE, {RB}},
+{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2, {RB}},
{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
-{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE, PPCNONE, {RSO, RAOPT, SHO}},
+{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2, PPCNONE, {RSO, RAOPT, SHO}},
{"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}},
@@ -4702,7 +4743,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"extsw", XRC(31,986,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}},
-{"icbiep", XRT(31,991,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
+{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
{"icread", X(31,998), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}},
@@ -4724,7 +4765,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"dcbz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}},
{"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}},
-{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}},
+{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPCNONE, {RA, RB}},
@@ -4908,14 +4949,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}},
-{"fcfids", XRC(59,846,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
+{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
{"diex", XRC(59,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
+{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}},
{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}},
@@ -5078,8 +5119,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}},
-{"fcpsgn", XRC(63,8,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
+{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2, PPCNONE, {FRT, FRA, FRB}},
+{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2, PPCNONE, {FRT, FRA, FRB}},
{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
@@ -5188,10 +5229,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
-{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE, {BFF, U, W}},
-{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6, {BFF, U}},
-{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE, {BFF, U, W}},
-{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6, {BFF, U}},
+{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2, PPCNONE, {BFF, U, W}},
+{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2, {BFF, U}},
+{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2, PPCNONE, {BFF, U, W}},
+{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2, {BFF, U}},
{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}},
@@ -5247,10 +5288,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}},
-{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6, PPCNONE, {FLM, FRB, XFL_L, W}},
-{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6, {FLM, FRB}},
-{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6, PPCNONE, {FLM, FRB, XFL_L, W}},
-{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6, {FLM, FRB}},
+{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2, PPCNONE, {FLM, FRB, XFL_L, W}},
+{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2, {FLM, FRB}},
+{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2, PPCNONE, {FLM, FRB, XFL_L, W}},
+{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2, {FLM, FRB}},
{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}},
@@ -5273,14 +5314,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}},
-{"fctidu", XRC(63,942,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
+{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
-{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
+{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
-{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
+{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
};
const int powerpc_num_opcodes =
generated by cgit v1.1 at 2024-11-24 04:34:22 +0000