diff options
| -rw-r--r-- | opcodes/ChangeLog | 12 | ||||
| -rw-r--r-- | opcodes/cgen-dis.in | 12 | ||||
| -rw-r--r-- | opcodes/fr30-desc.c | 2 | ||||
| -rw-r--r-- | opcodes/fr30-dis.c | 12 | ||||
| -rw-r--r-- | opcodes/fr30-opc.h | 4 | ||||
| -rw-r--r-- | opcodes/m32r-desc.c | 2 | ||||
| -rw-r--r-- | opcodes/m32r-dis.c | 12 | ||||
| -rw-r--r-- | opcodes/m32r-opc.h | 4 | ||||
| -rw-r--r-- | opcodes/m32r-opinst.c | 2 |
9 files changed, 43 insertions, 19 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index dda0f0d..692a029 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,15 @@ +2001-03-20 Patrick Macdonald <patrickm@redhat.com> + + * cgen-dis.in (print_insn_@arch@): Add support for target machine + determination via CGEN_COMPUTE_MACH. + * fr30-desc.c: Regenerate. + * fr30-dis.c: Regenerate. + * fr30-opc.h: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + 2001-03-20 H.J. Lu <hjl@gnu.org> * configure.in: Remove the redundent AC_ARG_PROGRAM. diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in index 0e7c35a..1cb8ea3 100644 --- a/opcodes/cgen-dis.in +++ b/opcodes/cgen-dis.in @@ -358,17 +358,21 @@ print_insn_@arch@ (pc, info) arch = info->arch; if (arch == bfd_arch_unknown) arch = CGEN_BFD_ARCH; - - /* There's no standard way to compute the isa number (e.g. for arm thumb) + + /* There's no standard way to compute the machine or isa number so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + #ifdef CGEN_COMPUTE_ISA isa = CGEN_COMPUTE_ISA (info); #else isa = 0; #endif - mach = info->mach; - /* If we've switched cpu's, close the current table and open a new one. */ if (cd && (isa != prev_isa diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c index 00c3700..4223833 100644 --- a/opcodes/fr30-desc.c +++ b/opcodes/fr30-desc.c @@ -1600,7 +1600,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) const CGEN_MACH *mach = lookup_mach_via_bfd_name (fr30_cgen_mach_table, name); - machs |= mach->num << 1; + machs |= 1 << mach->num; break; } case CGEN_CPU_OPEN_ENDIAN : diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c index e75944d..f389dcc 100644 --- a/opcodes/fr30-dis.c +++ b/opcodes/fr30-dis.c @@ -624,17 +624,21 @@ print_insn_fr30 (pc, info) arch = info->arch; if (arch == bfd_arch_unknown) arch = CGEN_BFD_ARCH; - - /* There's no standard way to compute the isa number (e.g. for arm thumb) + + /* There's no standard way to compute the machine or isa number so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + #ifdef CGEN_COMPUTE_ISA isa = CGEN_COMPUTE_ISA (info); #else isa = 0; #endif - mach = info->mach; - /* If we've switched cpu's, close the current table and open a new one. */ if (cd && (isa != prev_isa diff --git a/opcodes/fr30-opc.h b/opcodes/fr30-opc.h index 33d3094..623501d 100644 --- a/opcodes/fr30-opc.h +++ b/opcodes/fr30-opc.h @@ -77,14 +77,14 @@ typedef enum cgen_insn_type { , FR30_INSN_ORCCR, FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB , FR30_INSN_EXTUB, FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_LDM0 , FR30_INSN_LDM1, FR30_INSN_STM0, FR30_INSN_STM1, FR30_INSN_ENTER - , FR30_INSN_LEAVE, FR30_INSN_XCHB, FR30_INSN_MAX + , FR30_INSN_LEAVE, FR30_INSN_XCHB } CGEN_INSN_TYPE; /* Index of `invalid' insn place holder. */ #define CGEN_INSN_INVALID FR30_INSN_INVALID /* Total number of insns in table. */ -#define MAX_INSNS ((int) FR30_INSN_MAX) +#define MAX_INSNS ((int) FR30_INSN_XCHB + 1) /* This struct records data prior to insertion or after extraction. */ struct cgen_fields diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c index 111eb2d..8bcd790 100644 --- a/opcodes/m32r-desc.c +++ b/opcodes/m32r-desc.c @@ -1324,7 +1324,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) const CGEN_MACH *mach = lookup_mach_via_bfd_name (m32r_cgen_mach_table, name); - machs |= mach->num << 1; + machs |= 1 << mach->num; break; } case CGEN_CPU_OPEN_ENDIAN : diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c index 8ffce7c..7164a40 100644 --- a/opcodes/m32r-dis.c +++ b/opcodes/m32r-dis.c @@ -563,17 +563,21 @@ print_insn_m32r (pc, info) arch = info->arch; if (arch == bfd_arch_unknown) arch = CGEN_BFD_ARCH; - - /* There's no standard way to compute the isa number (e.g. for arm thumb) + + /* There's no standard way to compute the machine or isa number so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + #ifdef CGEN_COMPUTE_ISA isa = CGEN_COMPUTE_ISA (info); #else isa = 0; #endif - mach = info->mach; - /* If we've switched cpu's, close the current table and open a new one. */ if (cd && (isa != prev_isa diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h index 68fad09..f3eb139 100644 --- a/opcodes/m32r-opc.h +++ b/opcodes/m32r-opc.h @@ -74,14 +74,14 @@ typedef enum cgen_insn_type { , M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK , M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT, M32R_INSN_PCMPBZ , M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO, M32R_INSN_MULWU1 - , M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC, M32R_INSN_MAX + , M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC } CGEN_INSN_TYPE; /* Index of `invalid' insn place holder. */ #define CGEN_INSN_INVALID M32R_INSN_INVALID /* Total number of insns in table. */ -#define MAX_INSNS ((int) M32R_INSN_MAX) +#define MAX_INSNS ((int) M32R_INSN_SNC + 1) /* This struct records data prior to insertion or after extraction. */ struct cgen_fields diff --git a/opcodes/m32r-opinst.c b/opcodes/m32r-opinst.c index 5dbcd12..55e7e4f 100644 --- a/opcodes/m32r-opinst.c +++ b/opcodes/m32r-opinst.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2001 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. |