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-rw-r--r--sim/frv/ChangeLog10
-rw-r--r--sim/frv/Makefile.in9
-rw-r--r--sim/frv/arch.c3
-rw-r--r--sim/frv/arch.h68
-rw-r--r--sim/frv/cache.c116
-rw-r--r--sim/frv/cache.h17
-rw-r--r--sim/frv/cpu.c16
-rw-r--r--sim/frv/cpu.h125
-rw-r--r--sim/frv/cpuall.h1
-rw-r--r--sim/frv/decode.c112
-rw-r--r--sim/frv/decode.h548
-rw-r--r--sim/frv/frv-sim.h21
-rw-r--r--sim/frv/frv.c71
-rw-r--r--sim/frv/interrupts.c121
-rw-r--r--sim/frv/memory.c325
-rw-r--r--sim/frv/mloop.in8
-rw-r--r--sim/frv/model.c18480
-rw-r--r--sim/frv/pipeline.c2
-rw-r--r--sim/frv/profile-fr550.c2664
-rw-r--r--sim/frv/profile-fr550.h27
-rw-r--r--sim/frv/profile.c122
-rw-r--r--sim/frv/profile.h12
-rw-r--r--sim/frv/registers.c1212
-rw-r--r--sim/frv/sem.c335
-rw-r--r--sim/frv/traps.c100
25 files changed, 24030 insertions, 495 deletions
diff --git a/sim/frv/ChangeLog b/sim/frv/ChangeLog
index 277d6f8..68dde23 100644
--- a/sim/frv/ChangeLog
+++ b/sim/frv/ChangeLog
@@ -1,3 +1,13 @@
+2003-10-06 Dave Brolley <brolley@redhat.com>
+
+ * profile-fr550.[ch]: New files.
+ * configure.in: Move frv handling to alphabetically correct placement.
+ * Makefile.in: Add fr550 support.
+ * frv-sim.h,frv.c,interrups.c,memory.c,mloop.in,pipeline.c,
+ profile.[ch],registers.c,traps.c: Add fr550 support.
+ * arch.c,arch.h,cpu.c,cpu.h,cpuall.h,model.h,decode.c,decode.h,sem.c:
+ Regenerate.
+
2003-09-25 Dave Brolley <brolley@redhat.com>
* reset.c (frv_initialize): Call frv_register_control_init first.
diff --git a/sim/frv/Makefile.in b/sim/frv/Makefile.in
index e936c88..adc11ca 100644
--- a/sim/frv/Makefile.in
+++ b/sim/frv/Makefile.in
@@ -1,5 +1,5 @@
# Makefile template for Configure for the frv simulator
-# Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+# Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
# Contributed by Red Hat.
#
# This program is free software; you can redistribute it and/or modify
@@ -35,7 +35,7 @@ SIM_OBJS = \
sim-if.o arch.o \
$(FRV_OBJS) \
traps.o interrupts.o memory.o cache.o pipeline.o \
- profile.o profile-fr400.o profile-fr500.o options.o \
+ profile.o profile-fr400.o profile-fr500.o profile-fr550.o options.o \
devices.o reset.o registers.o \
$(CONFIG_DEVICES)
@@ -78,9 +78,10 @@ cache.o: cache.c $(FRVBF_INCLUDE_DEPS)
options.o: options.c $(FRVBF_INCLUDE_DEPS)
reset.o: reset.c $(FRVBF_INCLUDE_DEPS)
registers.o: registers.c $(FRVBF_INCLUDE_DEPS)
-profile.o: profile.c profile-fr400.h profile-fr500.h $(FRVBF_INCLUDE_DEPS)
+profile.o: profile.c profile-fr400.h profile-fr500.h profile-fr550.h $(FRVBF_INCLUDE_DEPS)
profile-fr400.o: profile-fr400.c profile-fr400.h $(FRVBF_INCLUDE_DEPS)
profile-fr500.o: profile-fr500.c profile-fr500.h $(FRVBF_INCLUDE_DEPS)
+profile-fr550.o: profile-fr550.c profile-fr550.h $(FRVBF_INCLUDE_DEPS)
sim-if.o: sim-if.c $(FRVBF_INCLUDE_DEPS) $(srcdir)/../common/sim-core.h eng.h
@@ -120,7 +121,7 @@ arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srcdir)/../../cpu/frv.cpu
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
- cpu=frvbf mach=frv,fr500,fr400,tomcat,simple SUFFIX= \
+ cpu=frvbf mach=frv,fr550,fr500,fr400,tomcat,simple SUFFIX= \
archfile=$(srcdir)/../../cpu/frv.cpu \
FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" \
EXTRAFILES="$(CGEN_CPU_SEM)"
diff --git a/sim/frv/arch.c b/sim/frv/arch.c
index 5161fb2..d0ac82f 100644
--- a/sim/frv/arch.c
+++ b/sim/frv/arch.c
@@ -31,6 +31,9 @@ const MACH *sim_machs[] =
& frv_mach,
#endif
#ifdef HAVE_CPU_FRVBF
+ & fr550_mach,
+#endif
+#ifdef HAVE_CPU_FRVBF
& fr500_mach,
#endif
#ifdef HAVE_CPU_FRVBF
diff --git a/sim/frv/arch.h b/sim/frv/arch.h
index 5a32e49..6f26965 100644
--- a/sim/frv/arch.h
+++ b/sim/frv/arch.h
@@ -29,40 +29,52 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* Enum declaration for model types. */
typedef enum model_type {
- MODEL_FRV, MODEL_FR500, MODEL_TOMCAT, MODEL_FR400
- , MODEL_SIMPLE, MODEL_MAX
+ MODEL_FRV, MODEL_FR550, MODEL_FR500, MODEL_TOMCAT
+ , MODEL_FR400, MODEL_SIMPLE, MODEL_MAX
} MODEL_TYPE;
#define MAX_MODELS ((int) MODEL_MAX)
/* Enum declaration for unit types. */
typedef enum unit_type {
- UNIT_NONE, UNIT_FRV_U_EXEC, UNIT_FR500_U_COMMIT, UNIT_FR500_U_DCUL
- , UNIT_FR500_U_ICUL, UNIT_FR500_U_DCPL, UNIT_FR500_U_ICPL, UNIT_FR500_U_DCF
- , UNIT_FR500_U_DCI, UNIT_FR500_U_ICI, UNIT_FR500_U_MEMBAR, UNIT_FR500_U_BARRIER
- , UNIT_FR500_U_MEDIA_DUAL_BTOHE, UNIT_FR500_U_MEDIA_DUAL_HTOB, UNIT_FR500_U_MEDIA_DUAL_BTOH, UNIT_FR500_U_MEDIA_DUAL_UNPACK
- , UNIT_FR500_U_MEDIA_DUAL_EXPAND, UNIT_FR500_U_MEDIA_QUAD_COMPLEX, UNIT_FR500_U_MEDIA_QUAD_MUL, UNIT_FR500_U_MEDIA_DUAL_MUL
- , UNIT_FR500_U_MEDIA_QUAD_ARITH, UNIT_FR500_U_MEDIA, UNIT_FR500_U_FLOAT_DUAL_CONVERT, UNIT_FR500_U_FLOAT_CONVERT
- , UNIT_FR500_U_FLOAT_DUAL_COMPARE, UNIT_FR500_U_FLOAT_COMPARE, UNIT_FR500_U_FLOAT_DUAL_SQRT, UNIT_FR500_U_FLOAT_SQRT
- , UNIT_FR500_U_FLOAT_DIV, UNIT_FR500_U_FLOAT_DUAL_ARITH, UNIT_FR500_U_FLOAT_ARITH, UNIT_FR500_U_GR2SPR
- , UNIT_FR500_U_GR2FR, UNIT_FR500_U_SPR2GR, UNIT_FR500_U_FR2GR, UNIT_FR500_U_FR2FR
- , UNIT_FR500_U_SWAP, UNIT_FR500_U_FR_R_STORE, UNIT_FR500_U_FR_STORE, UNIT_FR500_U_FR_LOAD
- , UNIT_FR500_U_GR_R_STORE, UNIT_FR500_U_GR_STORE, UNIT_FR500_U_GR_LOAD, UNIT_FR500_U_SET_HILO
- , UNIT_FR500_U_CLRFR, UNIT_FR500_U_CLRGR, UNIT_FR500_U_CHECK, UNIT_FR500_U_TRAP
- , UNIT_FR500_U_BRANCH, UNIT_FR500_U_IDIV, UNIT_FR500_U_IMUL, UNIT_FR500_U_INTEGER
- , UNIT_FR500_U_EXEC, UNIT_TOMCAT_U_EXEC, UNIT_FR400_U_DCUL, UNIT_FR400_U_ICUL
- , UNIT_FR400_U_DCPL, UNIT_FR400_U_ICPL, UNIT_FR400_U_DCF, UNIT_FR400_U_DCI
- , UNIT_FR400_U_ICI, UNIT_FR400_U_MEMBAR, UNIT_FR400_U_BARRIER, UNIT_FR400_U_MEDIA_DUAL_HTOB
- , UNIT_FR400_U_MEDIA_DUAL_EXPAND, UNIT_FR400_U_MEDIA_7, UNIT_FR400_U_MEDIA_6, UNIT_FR400_U_MEDIA_4_ACC_DUAL
- , UNIT_FR400_U_MEDIA_4_ACCG, UNIT_FR400_U_MEDIA_4, UNIT_FR400_U_MEDIA_3_QUAD, UNIT_FR400_U_MEDIA_3_DUAL
- , UNIT_FR400_U_MEDIA_3, UNIT_FR400_U_MEDIA_2_ADD_SUB_DUAL, UNIT_FR400_U_MEDIA_2_ADD_SUB, UNIT_FR400_U_MEDIA_2_ACC_DUAL
- , UNIT_FR400_U_MEDIA_2_ACC, UNIT_FR400_U_MEDIA_2_QUAD, UNIT_FR400_U_MEDIA_2, UNIT_FR400_U_MEDIA_HILO
- , UNIT_FR400_U_MEDIA_1_QUAD, UNIT_FR400_U_MEDIA_1, UNIT_FR400_U_GR2SPR, UNIT_FR400_U_GR2FR
- , UNIT_FR400_U_SPR2GR, UNIT_FR400_U_FR2GR, UNIT_FR400_U_SWAP, UNIT_FR400_U_FR_STORE
- , UNIT_FR400_U_FR_LOAD, UNIT_FR400_U_GR_STORE, UNIT_FR400_U_GR_LOAD, UNIT_FR400_U_SET_HILO
- , UNIT_FR400_U_CHECK, UNIT_FR400_U_TRAP, UNIT_FR400_U_BRANCH, UNIT_FR400_U_IDIV
- , UNIT_FR400_U_IMUL, UNIT_FR400_U_INTEGER, UNIT_FR400_U_EXEC, UNIT_SIMPLE_U_EXEC
- , UNIT_MAX
+ UNIT_NONE, UNIT_FRV_U_EXEC, UNIT_FR550_U_MEDIA_4_QUAD, UNIT_FR550_U_MEDIA_4_ADD_SUB_DUAL
+ , UNIT_FR550_U_MEDIA_4_ADD_SUB, UNIT_FR550_U_MEDIA_4_ACC_DUAL, UNIT_FR550_U_MEDIA_4_ACC, UNIT_FR550_U_MEDIA_4
+ , UNIT_FR550_U_MEDIA_SET, UNIT_FR550_U_MEDIA_3_MCLRACC, UNIT_FR550_U_MEDIA_3_WTACC, UNIT_FR550_U_MEDIA_3_ACC_DUAL
+ , UNIT_FR550_U_MEDIA_3_ACC, UNIT_FR550_U_MEDIA_3_DUAL, UNIT_FR550_U_MEDIA_DUAL_EXPAND, UNIT_FR550_U_MEDIA_QUAD
+ , UNIT_FR550_U_MEDIA, UNIT_FR550_U_FLOAT_CONVERT, UNIT_FR550_U_COMMIT, UNIT_FR550_U_DCUL
+ , UNIT_FR550_U_ICUL, UNIT_FR550_U_DCPL, UNIT_FR550_U_ICPL, UNIT_FR550_U_DCF
+ , UNIT_FR550_U_DCI, UNIT_FR550_U_ICI, UNIT_FR550_U_CLRFR, UNIT_FR550_U_CLRGR
+ , UNIT_FR550_U_FR2FR, UNIT_FR550_U_SWAP, UNIT_FR550_U_FR_STORE, UNIT_FR550_U_FR_LOAD
+ , UNIT_FR550_U_GR_STORE, UNIT_FR550_U_GR_LOAD, UNIT_FR550_U_SET_HILO, UNIT_FR550_U_GR2SPR
+ , UNIT_FR550_U_SPR2GR, UNIT_FR550_U_GR2FR, UNIT_FR550_U_FR2GR, UNIT_FR550_U_FLOAT_DUAL_COMPARE
+ , UNIT_FR550_U_FLOAT_COMPARE, UNIT_FR550_U_FLOAT_SQRT, UNIT_FR550_U_FLOAT_DIV, UNIT_FR550_U_FLOAT_DUAL_ARITH
+ , UNIT_FR550_U_FLOAT_ARITH, UNIT_FR550_U_CHECK, UNIT_FR550_U_TRAP, UNIT_FR550_U_BRANCH
+ , UNIT_FR550_U_IDIV, UNIT_FR550_U_IMUL, UNIT_FR550_U_INTEGER, UNIT_FR550_U_EXEC
+ , UNIT_FR500_U_COMMIT, UNIT_FR500_U_DCUL, UNIT_FR500_U_ICUL, UNIT_FR500_U_DCPL
+ , UNIT_FR500_U_ICPL, UNIT_FR500_U_DCF, UNIT_FR500_U_DCI, UNIT_FR500_U_ICI
+ , UNIT_FR500_U_MEMBAR, UNIT_FR500_U_BARRIER, UNIT_FR500_U_MEDIA_DUAL_BTOHE, UNIT_FR500_U_MEDIA_DUAL_HTOB
+ , UNIT_FR500_U_MEDIA_DUAL_BTOH, UNIT_FR500_U_MEDIA_DUAL_UNPACK, UNIT_FR500_U_MEDIA_DUAL_EXPAND, UNIT_FR500_U_MEDIA_QUAD_COMPLEX
+ , UNIT_FR500_U_MEDIA_QUAD_MUL, UNIT_FR500_U_MEDIA_DUAL_MUL, UNIT_FR500_U_MEDIA_QUAD_ARITH, UNIT_FR500_U_MEDIA
+ , UNIT_FR500_U_FLOAT_DUAL_CONVERT, UNIT_FR500_U_FLOAT_CONVERT, UNIT_FR500_U_FLOAT_DUAL_COMPARE, UNIT_FR500_U_FLOAT_COMPARE
+ , UNIT_FR500_U_FLOAT_DUAL_SQRT, UNIT_FR500_U_FLOAT_SQRT, UNIT_FR500_U_FLOAT_DIV, UNIT_FR500_U_FLOAT_DUAL_ARITH
+ , UNIT_FR500_U_FLOAT_ARITH, UNIT_FR500_U_GR2SPR, UNIT_FR500_U_GR2FR, UNIT_FR500_U_SPR2GR
+ , UNIT_FR500_U_FR2GR, UNIT_FR500_U_FR2FR, UNIT_FR500_U_SWAP, UNIT_FR500_U_FR_R_STORE
+ , UNIT_FR500_U_FR_STORE, UNIT_FR500_U_FR_LOAD, UNIT_FR500_U_GR_R_STORE, UNIT_FR500_U_GR_STORE
+ , UNIT_FR500_U_GR_LOAD, UNIT_FR500_U_SET_HILO, UNIT_FR500_U_CLRFR, UNIT_FR500_U_CLRGR
+ , UNIT_FR500_U_CHECK, UNIT_FR500_U_TRAP, UNIT_FR500_U_BRANCH, UNIT_FR500_U_IDIV
+ , UNIT_FR500_U_IMUL, UNIT_FR500_U_INTEGER, UNIT_FR500_U_EXEC, UNIT_TOMCAT_U_EXEC
+ , UNIT_FR400_U_DCUL, UNIT_FR400_U_ICUL, UNIT_FR400_U_DCPL, UNIT_FR400_U_ICPL
+ , UNIT_FR400_U_DCF, UNIT_FR400_U_DCI, UNIT_FR400_U_ICI, UNIT_FR400_U_MEMBAR
+ , UNIT_FR400_U_BARRIER, UNIT_FR400_U_MEDIA_DUAL_HTOB, UNIT_FR400_U_MEDIA_DUAL_EXPAND, UNIT_FR400_U_MEDIA_7
+ , UNIT_FR400_U_MEDIA_6, UNIT_FR400_U_MEDIA_4_ACC_DUAL, UNIT_FR400_U_MEDIA_4_ACCG, UNIT_FR400_U_MEDIA_4
+ , UNIT_FR400_U_MEDIA_3_QUAD, UNIT_FR400_U_MEDIA_3_DUAL, UNIT_FR400_U_MEDIA_3, UNIT_FR400_U_MEDIA_2_ADD_SUB_DUAL
+ , UNIT_FR400_U_MEDIA_2_ADD_SUB, UNIT_FR400_U_MEDIA_2_ACC_DUAL, UNIT_FR400_U_MEDIA_2_ACC, UNIT_FR400_U_MEDIA_2_QUAD
+ , UNIT_FR400_U_MEDIA_2, UNIT_FR400_U_MEDIA_HILO, UNIT_FR400_U_MEDIA_1_QUAD, UNIT_FR400_U_MEDIA_1
+ , UNIT_FR400_U_GR2SPR, UNIT_FR400_U_GR2FR, UNIT_FR400_U_SPR2GR, UNIT_FR400_U_FR2GR
+ , UNIT_FR400_U_SWAP, UNIT_FR400_U_FR_STORE, UNIT_FR400_U_FR_LOAD, UNIT_FR400_U_GR_STORE
+ , UNIT_FR400_U_GR_LOAD, UNIT_FR400_U_SET_HILO, UNIT_FR400_U_CHECK, UNIT_FR400_U_TRAP
+ , UNIT_FR400_U_BRANCH, UNIT_FR400_U_IDIV, UNIT_FR400_U_IMUL, UNIT_FR400_U_INTEGER
+ , UNIT_FR400_U_EXEC, UNIT_SIMPLE_U_EXEC, UNIT_MAX
} UNIT_TYPE;
#define MAX_UNITS (1)
diff --git a/sim/frv/cache.c b/sim/frv/cache.c
index 5093f16..bfefa87 100644
--- a/sim/frv/cache.c
+++ b/sim/frv/cache.c
@@ -1,5 +1,5 @@
/* frv cache model.
- Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
+ Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU simulators.
@@ -38,20 +38,30 @@ frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
- if (cache->sets == 0)
- cache->sets = 128;
- if (cache->ways == 0)
- cache->ways = 2;
+ if (cache->configured_sets == 0)
+ cache->configured_sets = 128;
+ if (cache->configured_ways == 0)
+ cache->configured_ways = 2;
if (cache->line_size == 0)
cache->line_size = 32;
if (cache->memory_latency == 0)
cache->memory_latency = 20;
break;
+ case bfd_mach_fr550:
+ if (cache->configured_sets == 0)
+ cache->configured_sets = 128;
+ if (cache->configured_ways == 0)
+ cache->configured_ways = 4;
+ if (cache->line_size == 0)
+ cache->line_size = 64;
+ if (cache->memory_latency == 0)
+ cache->memory_latency = 20;
+ break;
default:
- if (cache->sets == 0)
- cache->sets = 64;
- if (cache->ways == 0)
- cache->ways = 4;
+ if (cache->configured_sets == 0)
+ cache->configured_sets = 64;
+ if (cache->configured_ways == 0)
+ cache->configured_ways = 4;
if (cache->line_size == 0)
cache->line_size = 64;
if (cache->memory_latency == 0)
@@ -59,6 +69,8 @@ frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache)
break;
}
+ frv_cache_reconfigure (cpu, cache);
+
/* First allocate the cache storage based on the given dimensions. */
elements = cache->sets * cache->ways;
cache->tag_storage = (FRV_CACHE_TAG *)
@@ -95,6 +107,40 @@ frv_cache_term (FRV_CACHE *cache)
free (cache->pipeline[LD].status.return_buffer.data);
}
+/* Reset the cache configuration based on registers in the cpu. */
+void
+frv_cache_reconfigure (SIM_CPU *current_cpu, FRV_CACHE *cache)
+{
+ int ihsr8;
+ int icdm;
+ SIM_DESC sd;
+
+ /* Set defaults for fields which are not initialized. */
+ sd = CPU_STATE (current_cpu);
+ switch (STATE_ARCHITECTURE (sd)->mach)
+ {
+ case bfd_mach_fr550:
+ if (cache == CPU_INSN_CACHE (current_cpu))
+ {
+ ihsr8 = GET_IHSR8 ();
+ icdm = GET_IHSR8_ICDM (ihsr8);
+ /* If IHSR8.ICDM is set, then the cache becomes a one way cache. */
+ if (icdm)
+ {
+ cache->sets = cache->sets * cache->ways;
+ cache->ways = 1;
+ break;
+ }
+ }
+ /* fall through */
+ default:
+ /* Set the cache to its original settings. */
+ cache->sets = cache->configured_sets;
+ cache->ways = cache->configured_ways;
+ break;
+ }
+}
+
/* Determine whether the given cache is enabled. */
int
frv_cache_enabled (FRV_CACHE *cache)
@@ -108,6 +154,44 @@ frv_cache_enabled (FRV_CACHE *cache)
return 0;
}
+/* Determine whether the given address is RAM access, assuming that HSR0.RME
+ is set. */
+static int
+ram_access (FRV_CACHE *cache, USI address)
+{
+ int ihsr8;
+ int cwe;
+ USI start, end, way_size;
+ SIM_CPU *current_cpu = cache->cpu;
+ SIM_DESC sd = CPU_STATE (current_cpu);
+
+ switch (STATE_ARCHITECTURE (sd)->mach)
+ {
+ case bfd_mach_fr550:
+ /* IHSR8.DCWE or IHSR8.ICWE deternines which ways get RAM access. */
+ ihsr8 = GET_IHSR8 ();
+ if (cache == CPU_INSN_CACHE (current_cpu))
+ {
+ start = 0xfe000000;
+ end = 0xfe008000;
+ cwe = GET_IHSR8_ICWE (ihsr8);
+ }
+ else
+ {
+ start = 0xfe400000;
+ end = 0xfe408000;
+ cwe = GET_IHSR8_DCWE (ihsr8);
+ }
+ way_size = (end - start) / 4;
+ end -= way_size * cwe;
+ return address >= start && address < end;
+ default:
+ break;
+ }
+
+ return 1; /* RAM access */
+}
+
/* Determine whether the given address should be accessed without using
the cache. */
static int
@@ -124,6 +208,17 @@ non_cache_access (FRV_CACHE *cache, USI address)
if (address >= 0xff000000
|| address >= 0xfe000000 && address <= 0xfeffffff)
return 1; /* non-cache access */
+ case bfd_mach_fr550:
+ if (address >= 0xff000000
+ || address >= 0xfeff0000 && address <= 0xfeffffff)
+ return 1; /* non-cache access */
+ if (cache == CPU_INSN_CACHE (current_cpu))
+ {
+ if (address >= 0xfe000000 && address <= 0xfe007fff)
+ return 1; /* non-cache access */
+ }
+ else if (address >= 0xfe400000 && address <= 0xfe407fff)
+ return 1; /* non-cache access */
default:
if (address >= 0xff000000
|| address >= 0xfeff0000 && address <= 0xfeffffff)
@@ -139,7 +234,7 @@ non_cache_access (FRV_CACHE *cache, USI address)
hsr0 = GET_HSR0 ();
if (GET_HSR0_RME (hsr0))
- return 1; /* non-cache access */
+ return ram_access (cache, address);
return 0; /* cache-access */
}
@@ -1531,7 +1626,6 @@ frv_cache_read_passive_SI (FRV_CACHE *cache, SI address, SI *value)
/* A cache line was available for the data.
Extract the target data from the line. */
offset = address & (cache->line_size - 1);
- offset &= ~3;
*value = T2H_4 (*(SI *)(tag->line + offset));
return 1;
}
diff --git a/sim/frv/cache.h b/sim/frv/cache.h
index e45ae94..2d17514 100644
--- a/sim/frv/cache.h
+++ b/sim/frv/cache.h
@@ -1,5 +1,5 @@
/* Cache support for the FRV simulator
- Copyright (C) 1999, 2000 Free Software Foundation, Inc.
+ Copyright (C) 1999, 2000, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU Simulators.
@@ -165,6 +165,8 @@ typedef struct {
*/
typedef struct {
SIM_CPU *cpu;
+ unsigned configured_ways; /* Number of ways configured in each set. */
+ unsigned configured_sets; /* Number of sets configured in the cache. */
unsigned ways; /* Number of ways in each set. */
unsigned sets; /* Number of sets in the cache. */
unsigned line_size; /* Size of each cache line. */
@@ -200,14 +202,15 @@ typedef struct {
#define CACHE_RETURN_DATA(cache, slot, address, mode, N) ( \
T2H_##N (*(mode *)(& (cache)->pipeline[slot].status.return_buffer.data \
- [((address) & ((cache)->line_size - 1) \
- & ~(sizeof (mode) - 1))])) \
+ [((address) & ((cache)->line_size - 1))])) \
)
-
#define CACHE_RETURN_DATA_ADDRESS(cache, slot, address, N) ( \
((void *)& (cache)->pipeline[slot].status.return_buffer.data[(address) \
- & ((cache)->line_size - 1) \
- & ~((N) - 1)]) \
+ & ((cache)->line_size - 1)]) \
+)
+
+#define DATA_CROSSES_CACHE_LINE(cache, address, size) ( \
+ ((address) & ((cache)->line_size - 1)) + (size) > (cache)->line_size \
)
#define CACHE_INITIALIZED(cache) ((cache)->data_storage != NULL)
@@ -217,6 +220,8 @@ void
frv_cache_init (SIM_CPU *, FRV_CACHE *);
void
frv_cache_term (FRV_CACHE *);
+void
+frv_cache_reconfigure (SIM_CPU *, FRV_CACHE *);
int
frv_cache_enabled (FRV_CACHE *);
diff --git a/sim/frv/cpu.c b/sim/frv/cpu.c
index 08e3a2c..1b4b4a1 100644
--- a/sim/frv/cpu.c
+++ b/sim/frv/cpu.c
@@ -620,6 +620,22 @@ frvbf_h_acc40U_set (SIM_CPU *current_cpu, UINT regno, UDI newval)
SET_H_ACC40U (regno, newval);
}
+/* Get the value of h-iacc0. */
+
+DI
+frvbf_h_iacc0_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_IACC0 (regno);
+}
+
+/* Set a value for h-iacc0. */
+
+void
+frvbf_h_iacc0_set (SIM_CPU *current_cpu, UINT regno, DI newval)
+{
+ SET_H_IACC0 (regno, newval);
+}
+
/* Get the value of h-iccr. */
UQI
diff --git a/sim/frv/cpu.h b/sim/frv/cpu.h
index 1b0a4fd..7271b1a 100644
--- a/sim/frv/cpu.h
+++ b/sim/frv/cpu.h
@@ -30,7 +30,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define MAX_LIW_INSNS 1
/* Maximum number of instructions that can be executed in parallel. */
-#define MAX_PARALLEL_INSNS 4
+#define MAX_PARALLEL_INSNS 8
/* CPU state information. */
typedef struct {
@@ -257,6 +257,14 @@ CPU (h_spr[(((index)) + (1472))]) = ANDDI (SRLDI ((x), 32), 255);\
CPU (h_spr[(((index)) + (1408))]) = TRUNCDISI ((x));\
}\
;} while (0)
+#define GET_H_IACC0(index) ORDI (SLLDI (EXTSIDI (GET_H_SPR (((UINT) 280))), 32), ZEXTSIDI (GET_H_SPR (((UINT) 281))))
+#define SET_H_IACC0(index, x) \
+do { \
+{\
+SET_H_SPR (((UINT) 280), TRUNCDISI (SRLDI ((x), 32)));\
+SET_H_SPR (((UINT) 281), TRUNCDISI ((x)));\
+}\
+;} while (0)
/* Cover fns for register access. */
USI frvbf_h_pc_get (SIM_CPU *);
@@ -333,6 +341,8 @@ DI frvbf_h_acc40S_get (SIM_CPU *, UINT);
void frvbf_h_acc40S_set (SIM_CPU *, UINT, DI);
UDI frvbf_h_acc40U_get (SIM_CPU *, UINT);
void frvbf_h_acc40U_set (SIM_CPU *, UINT, UDI);
+DI frvbf_h_iacc0_get (SIM_CPU *, UINT);
+void frvbf_h_iacc0_set (SIM_CPU *, UINT, DI);
UQI frvbf_h_iccr_get (SIM_CPU *, UINT);
void frvbf_h_iccr_set (SIM_CPU *, UINT, UQI);
UQI frvbf_h_fccr_get (SIM_CPU *, UINT);
@@ -349,6 +359,19 @@ typedef struct {
} MODEL_FRV_DATA;
typedef struct {
+ DI prev_fr_load;
+ DI prev_fr_complex_1;
+ DI prev_fr_complex_2;
+ DI prev_ccr_complex;
+ DI prev_acc_mmac;
+ DI cur_fr_load;
+ DI cur_fr_complex_1;
+ DI cur_fr_complex_2;
+ SI cur_ccr_complex;
+ DI cur_acc_mmac;
+} MODEL_FR550_DATA;
+
+typedef struct {
DI prev_fpop;
DI prev_media;
DI prev_cc_complex;
@@ -549,6 +572,13 @@ union sem_fields {
unsigned char out_GRdoublek;
} sfmt_smuli;
struct { /* */
+ UINT f_GRj;
+ UINT f_GRk;
+ unsigned char in_GRj;
+ unsigned char in_h_iacc0_DI_0;
+ unsigned char out_GRk;
+ } sfmt_scutss;
+ struct { /* */
UINT f_ACC40Si;
UINT f_FRj;
UINT f_FRk;
@@ -613,6 +643,14 @@ union sem_fields {
unsigned char out_GRk;
} sfmt_swapi;
struct { /* */
+ UINT f_GRi;
+ UINT f_GRj;
+ unsigned char in_GRi;
+ unsigned char in_GRj;
+ unsigned char in_h_iacc0_DI_0;
+ unsigned char out_h_iacc0_DI_0;
+ } sfmt_smass;
+ struct { /* */
INT f_s6;
UINT f_FRi;
UINT f_FRk;
@@ -1571,6 +1609,57 @@ struct scache {
f_ope2 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+#define EXTRACT_IFMT_SMU_VARS \
+ UINT f_pack; \
+ UINT f_rd_null; \
+ UINT f_op; \
+ UINT f_GRi; \
+ UINT f_ope1; \
+ UINT f_GRj; \
+ unsigned int length;
+#define EXTRACT_IFMT_SMU_CODE \
+ length = 4; \
+ f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+ f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+ f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+ f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+ f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_SLASS_VARS \
+ UINT f_pack; \
+ UINT f_GRk; \
+ UINT f_op; \
+ UINT f_GRi; \
+ UINT f_ope1; \
+ UINT f_GRj; \
+ unsigned int length;
+#define EXTRACT_IFMT_SLASS_CODE \
+ length = 4; \
+ f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+ f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+ f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+ f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+ f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_SCUTSS_VARS \
+ UINT f_pack; \
+ UINT f_GRk; \
+ UINT f_op; \
+ UINT f_rs_null; \
+ UINT f_ope1; \
+ UINT f_GRj; \
+ unsigned int length;
+#define EXTRACT_IFMT_SCUTSS_CODE \
+ length = 4; \
+ f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+ f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+ f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+ f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+ f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
#define EXTRACT_IFMT_CADD_VARS \
UINT f_pack; \
UINT f_GRk; \
@@ -1800,23 +1889,6 @@ struct scache {
f_misc_null_4 = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
f_s16 = EXTRACT_LSB0_INT (insn, 32, 15, 16); \
-#define EXTRACT_IFMT_LDSB_VARS \
- UINT f_pack; \
- UINT f_GRk; \
- UINT f_op; \
- UINT f_GRi; \
- UINT f_ope1; \
- UINT f_GRj; \
- unsigned int length;
-#define EXTRACT_IFMT_LDSB_CODE \
- length = 4; \
- f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
- f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
- f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
- f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
- f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
- f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
-
#define EXTRACT_IFMT_LDBF_VARS \
UINT f_pack; \
UINT f_FRk; \
@@ -3058,23 +3130,6 @@ struct scache {
f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
-#define EXTRACT_IFMT_ICI_VARS \
- UINT f_pack; \
- UINT f_rd_null; \
- UINT f_op; \
- UINT f_GRi; \
- UINT f_ope1; \
- UINT f_GRj; \
- unsigned int length;
-#define EXTRACT_IFMT_ICI_CODE \
- length = 4; \
- f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
- f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
- f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
- f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
- f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
- f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
-
#define EXTRACT_IFMT_ICEI_VARS \
UINT f_pack; \
UINT f_misc_null_1; \
diff --git a/sim/frv/cpuall.h b/sim/frv/cpuall.h
index 9403439..4d1cb68 100644
--- a/sim/frv/cpuall.h
+++ b/sim/frv/cpuall.h
@@ -35,6 +35,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#endif
extern const MACH frv_mach;
+extern const MACH fr550_mach;
extern const MACH fr500_mach;
extern const MACH tomcat_mach;
extern const MACH fr400_mach;
diff --git a/sim/frv/decode.c b/sim/frv/decode.c
index 0fe1a17..ef6be5a 100644
--- a/sim/frv/decode.c
+++ b/sim/frv/decode.c
@@ -58,9 +58,14 @@ static const struct insn_sem frvbf_insn_sem[] =
{ FRV_INSN_NUDIV, FRVBF_INSN_NUDIV, FRVBF_SFMT_SDIV },
{ FRV_INSN_SMUL, FRVBF_INSN_SMUL, FRVBF_SFMT_SMUL },
{ FRV_INSN_UMUL, FRVBF_INSN_UMUL, FRVBF_SFMT_SMUL },
+ { FRV_INSN_SMU, FRVBF_INSN_SMU, FRVBF_SFMT_SMU },
+ { FRV_INSN_SMASS, FRVBF_INSN_SMASS, FRVBF_SFMT_SMASS },
+ { FRV_INSN_SMSSS, FRVBF_INSN_SMSSS, FRVBF_SFMT_SMASS },
{ FRV_INSN_SLL, FRVBF_INSN_SLL, FRVBF_SFMT_ADD },
{ FRV_INSN_SRL, FRVBF_INSN_SRL, FRVBF_SFMT_ADD },
{ FRV_INSN_SRA, FRVBF_INSN_SRA, FRVBF_SFMT_ADD },
+ { FRV_INSN_SLASS, FRVBF_INSN_SLASS, FRVBF_SFMT_ADD },
+ { FRV_INSN_SCUTSS, FRVBF_INSN_SCUTSS, FRVBF_SFMT_SCUTSS },
{ FRV_INSN_SCAN, FRVBF_INSN_SCAN, FRVBF_SFMT_ADD },
{ FRV_INSN_CADD, FRVBF_INSN_CADD, FRVBF_SFMT_CADD },
{ FRV_INSN_CSUB, FRVBF_INSN_CSUB, FRVBF_SFMT_CADD },
@@ -98,6 +103,8 @@ static const struct insn_sem frvbf_insn_sem[] =
{ FRV_INSN_SUBX, FRVBF_INSN_SUBX, FRVBF_SFMT_ADDX },
{ FRV_INSN_ADDXCC, FRVBF_INSN_ADDXCC, FRVBF_SFMT_ADDCC },
{ FRV_INSN_SUBXCC, FRVBF_INSN_SUBXCC, FRVBF_SFMT_ADDCC },
+ { FRV_INSN_ADDSS, FRVBF_INSN_ADDSS, FRVBF_SFMT_ADD },
+ { FRV_INSN_SUBSS, FRVBF_INSN_SUBSS, FRVBF_SFMT_ADD },
{ FRV_INSN_ADDI, FRVBF_INSN_ADDI, FRVBF_SFMT_ADDI },
{ FRV_INSN_SUBI, FRVBF_INSN_SUBI, FRVBF_SFMT_ADDI },
{ FRV_INSN_ANDI, FRVBF_INSN_ANDI, FRVBF_SFMT_ADDI },
@@ -1408,6 +1415,21 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
case 67 : itype = FRVBF_INSN_NLDUHI; goto extract_sfmt_nldsbi;
case 68 : itype = FRVBF_INSN_NLDI; goto extract_sfmt_nldsbi;
case 69 : itype = FRVBF_INSN_NLDDI; goto extract_sfmt_nlddi;
+ case 70 :
+ {
+ unsigned int val = (((insn >> 6) & (7 << 0)));
+ switch (val)
+ {
+ case 0 : itype = FRVBF_INSN_ADDSS; goto extract_sfmt_add;
+ case 1 : itype = FRVBF_INSN_SUBSS; goto extract_sfmt_add;
+ case 2 : itype = FRVBF_INSN_SLASS; goto extract_sfmt_add;
+ case 4 : itype = FRVBF_INSN_SCUTSS; goto extract_sfmt_scutss;
+ case 5 : itype = FRVBF_INSN_SMU; goto extract_sfmt_smu;
+ case 6 : itype = FRVBF_INSN_SMASS; goto extract_sfmt_smass;
+ case 7 : itype = FRVBF_INSN_SMSSS; goto extract_sfmt_smass;
+ default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
case 71 : itype = FRVBF_INSN_SCANI; goto extract_sfmt_addi;
case 72 : itype = FRVBF_INSN_NLDBFI; goto extract_sfmt_nldbfi;
case 73 : itype = FRVBF_INSN_NLDHFI; goto extract_sfmt_nldbfi;
@@ -2290,7 +2312,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
{
const IDESC *idesc = &frvbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addcc.f
+#define FLD(f) abuf->fields.sfmt_scutss.f
UINT f_GRk;
UINT f_GRj;
@@ -2378,6 +2400,94 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc;
}
+ extract_sfmt_smu:
+ {
+ const IDESC *idesc = &frvbf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_smass.f
+ UINT f_GRi;
+ UINT f_GRj;
+
+ f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+ f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_GRi) = f_GRi;
+ FLD (f_GRj) = f_GRj;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_smu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_GRi) = f_GRi;
+ FLD (in_GRj) = f_GRj;
+ FLD (out_h_iacc0_DI_0) = 0;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_smass:
+ {
+ const IDESC *idesc = &frvbf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_smass.f
+ UINT f_GRi;
+ UINT f_GRj;
+
+ f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+ f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_GRi) = f_GRi;
+ FLD (f_GRj) = f_GRj;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_smass", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_GRi) = f_GRi;
+ FLD (in_GRj) = f_GRj;
+ FLD (in_h_iacc0_DI_0) = 0;
+ FLD (out_h_iacc0_DI_0) = 0;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_scutss:
+ {
+ const IDESC *idesc = &frvbf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_scutss.f
+ UINT f_GRk;
+ UINT f_GRj;
+
+ f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+ f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_GRj) = f_GRj;
+ FLD (f_GRk) = f_GRk;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_scutss", "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_GRj) = f_GRj;
+ FLD (in_h_iacc0_DI_0) = 0;
+ FLD (out_GRk) = f_GRk;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
extract_sfmt_cadd:
{
const IDESC *idesc = &frvbf_insn_data[itype];
diff --git a/sim/frv/decode.h b/sim/frv/decode.h
index 93d2367..9741d36 100644
--- a/sim/frv/decode.h
+++ b/sim/frv/decode.h
@@ -38,264 +38,316 @@ typedef enum frvbf_insn_type {
, FRVBF_INSN_X_CHAIN, FRVBF_INSN_X_BEGIN, FRVBF_INSN_ADD, FRVBF_INSN_SUB
, FRVBF_INSN_AND, FRVBF_INSN_OR, FRVBF_INSN_XOR, FRVBF_INSN_NOT
, FRVBF_INSN_SDIV, FRVBF_INSN_NSDIV, FRVBF_INSN_UDIV, FRVBF_INSN_NUDIV
- , FRVBF_INSN_SMUL, FRVBF_INSN_UMUL, FRVBF_INSN_SLL, FRVBF_INSN_SRL
- , FRVBF_INSN_SRA, FRVBF_INSN_SCAN, FRVBF_INSN_CADD, FRVBF_INSN_CSUB
- , FRVBF_INSN_CAND, FRVBF_INSN_COR, FRVBF_INSN_CXOR, FRVBF_INSN_CNOT
- , FRVBF_INSN_CSMUL, FRVBF_INSN_CSDIV, FRVBF_INSN_CUDIV, FRVBF_INSN_CSLL
- , FRVBF_INSN_CSRL, FRVBF_INSN_CSRA, FRVBF_INSN_CSCAN, FRVBF_INSN_ADDCC
- , FRVBF_INSN_SUBCC, FRVBF_INSN_ANDCC, FRVBF_INSN_ORCC, FRVBF_INSN_XORCC
- , FRVBF_INSN_SLLCC, FRVBF_INSN_SRLCC, FRVBF_INSN_SRACC, FRVBF_INSN_SMULCC
- , FRVBF_INSN_UMULCC, FRVBF_INSN_CADDCC, FRVBF_INSN_CSUBCC, FRVBF_INSN_CSMULCC
- , FRVBF_INSN_CANDCC, FRVBF_INSN_CORCC, FRVBF_INSN_CXORCC, FRVBF_INSN_CSLLCC
- , FRVBF_INSN_CSRLCC, FRVBF_INSN_CSRACC, FRVBF_INSN_ADDX, FRVBF_INSN_SUBX
- , FRVBF_INSN_ADDXCC, FRVBF_INSN_SUBXCC, FRVBF_INSN_ADDI, FRVBF_INSN_SUBI
- , FRVBF_INSN_ANDI, FRVBF_INSN_ORI, FRVBF_INSN_XORI, FRVBF_INSN_SDIVI
- , FRVBF_INSN_NSDIVI, FRVBF_INSN_UDIVI, FRVBF_INSN_NUDIVI, FRVBF_INSN_SMULI
- , FRVBF_INSN_UMULI, FRVBF_INSN_SLLI, FRVBF_INSN_SRLI, FRVBF_INSN_SRAI
- , FRVBF_INSN_SCANI, FRVBF_INSN_ADDICC, FRVBF_INSN_SUBICC, FRVBF_INSN_ANDICC
- , FRVBF_INSN_ORICC, FRVBF_INSN_XORICC, FRVBF_INSN_SMULICC, FRVBF_INSN_UMULICC
- , FRVBF_INSN_SLLICC, FRVBF_INSN_SRLICC, FRVBF_INSN_SRAICC, FRVBF_INSN_ADDXI
- , FRVBF_INSN_SUBXI, FRVBF_INSN_ADDXICC, FRVBF_INSN_SUBXICC, FRVBF_INSN_CMPB
- , FRVBF_INSN_CMPBA, FRVBF_INSN_SETLO, FRVBF_INSN_SETHI, FRVBF_INSN_SETLOS
- , FRVBF_INSN_LDSB, FRVBF_INSN_LDUB, FRVBF_INSN_LDSH, FRVBF_INSN_LDUH
- , FRVBF_INSN_LD, FRVBF_INSN_LDBF, FRVBF_INSN_LDHF, FRVBF_INSN_LDF
- , FRVBF_INSN_LDC, FRVBF_INSN_NLDSB, FRVBF_INSN_NLDUB, FRVBF_INSN_NLDSH
- , FRVBF_INSN_NLDUH, FRVBF_INSN_NLD, FRVBF_INSN_NLDBF, FRVBF_INSN_NLDHF
- , FRVBF_INSN_NLDF, FRVBF_INSN_LDD, FRVBF_INSN_LDDF, FRVBF_INSN_LDDC
- , FRVBF_INSN_NLDD, FRVBF_INSN_NLDDF, FRVBF_INSN_LDQ, FRVBF_INSN_LDQF
- , FRVBF_INSN_LDQC, FRVBF_INSN_NLDQ, FRVBF_INSN_NLDQF, FRVBF_INSN_LDSBU
- , FRVBF_INSN_LDUBU, FRVBF_INSN_LDSHU, FRVBF_INSN_LDUHU, FRVBF_INSN_LDU
- , FRVBF_INSN_NLDSBU, FRVBF_INSN_NLDUBU, FRVBF_INSN_NLDSHU, FRVBF_INSN_NLDUHU
- , FRVBF_INSN_NLDU, FRVBF_INSN_LDBFU, FRVBF_INSN_LDHFU, FRVBF_INSN_LDFU
- , FRVBF_INSN_LDCU, FRVBF_INSN_NLDBFU, FRVBF_INSN_NLDHFU, FRVBF_INSN_NLDFU
- , FRVBF_INSN_LDDU, FRVBF_INSN_NLDDU, FRVBF_INSN_LDDFU, FRVBF_INSN_LDDCU
- , FRVBF_INSN_NLDDFU, FRVBF_INSN_LDQU, FRVBF_INSN_NLDQU, FRVBF_INSN_LDQFU
- , FRVBF_INSN_LDQCU, FRVBF_INSN_NLDQFU, FRVBF_INSN_LDSBI, FRVBF_INSN_LDSHI
- , FRVBF_INSN_LDI, FRVBF_INSN_LDUBI, FRVBF_INSN_LDUHI, FRVBF_INSN_LDBFI
- , FRVBF_INSN_LDHFI, FRVBF_INSN_LDFI, FRVBF_INSN_NLDSBI, FRVBF_INSN_NLDUBI
- , FRVBF_INSN_NLDSHI, FRVBF_INSN_NLDUHI, FRVBF_INSN_NLDI, FRVBF_INSN_NLDBFI
- , FRVBF_INSN_NLDHFI, FRVBF_INSN_NLDFI, FRVBF_INSN_LDDI, FRVBF_INSN_LDDFI
- , FRVBF_INSN_NLDDI, FRVBF_INSN_NLDDFI, FRVBF_INSN_LDQI, FRVBF_INSN_LDQFI
- , FRVBF_INSN_NLDQFI, FRVBF_INSN_STB, FRVBF_INSN_STH, FRVBF_INSN_ST
- , FRVBF_INSN_STBF, FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC
- , FRVBF_INSN_RSTB, FRVBF_INSN_RSTH, FRVBF_INSN_RST, FRVBF_INSN_RSTBF
- , FRVBF_INSN_RSTHF, FRVBF_INSN_RSTF, FRVBF_INSN_STD, FRVBF_INSN_STDF
- , FRVBF_INSN_STDC, FRVBF_INSN_RSTD, FRVBF_INSN_RSTDF, FRVBF_INSN_STQ
- , FRVBF_INSN_STQF, FRVBF_INSN_STQC, FRVBF_INSN_RSTQ, FRVBF_INSN_RSTQF
- , FRVBF_INSN_STBU, FRVBF_INSN_STHU, FRVBF_INSN_STU, FRVBF_INSN_STBFU
- , FRVBF_INSN_STHFU, FRVBF_INSN_STFU, FRVBF_INSN_STCU, FRVBF_INSN_STDU
- , FRVBF_INSN_STDFU, FRVBF_INSN_STDCU, FRVBF_INSN_STQU, FRVBF_INSN_STQFU
- , FRVBF_INSN_STQCU, FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB, FRVBF_INSN_CLDSH
- , FRVBF_INSN_CLDUH, FRVBF_INSN_CLD, FRVBF_INSN_CLDBF, FRVBF_INSN_CLDHF
- , FRVBF_INSN_CLDF, FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF, FRVBF_INSN_CLDQ
- , FRVBF_INSN_CLDSBU, FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU, FRVBF_INSN_CLDUHU
- , FRVBF_INSN_CLDU, FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU, FRVBF_INSN_CLDFU
- , FRVBF_INSN_CLDDU, FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU, FRVBF_INSN_CSTB
- , FRVBF_INSN_CSTH, FRVBF_INSN_CST, FRVBF_INSN_CSTBF, FRVBF_INSN_CSTHF
- , FRVBF_INSN_CSTF, FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF, FRVBF_INSN_CSTQ
- , FRVBF_INSN_CSTBU, FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU, FRVBF_INSN_CSTBFU
- , FRVBF_INSN_CSTHFU, FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU, FRVBF_INSN_CSTDFU
- , FRVBF_INSN_STBI, FRVBF_INSN_STHI, FRVBF_INSN_STI, FRVBF_INSN_STBFI
- , FRVBF_INSN_STHFI, FRVBF_INSN_STFI, FRVBF_INSN_STDI, FRVBF_INSN_STDFI
- , FRVBF_INSN_STQI, FRVBF_INSN_STQFI, FRVBF_INSN_SWAP, FRVBF_INSN_SWAPI
- , FRVBF_INSN_CSWAP, FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG, FRVBF_INSN_MOVGFD
- , FRVBF_INSN_MOVFGD, FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ, FRVBF_INSN_CMOVGF
- , FRVBF_INSN_CMOVFG, FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD, FRVBF_INSN_MOVGS
- , FRVBF_INSN_MOVSG, FRVBF_INSN_BRA, FRVBF_INSN_BNO, FRVBF_INSN_BEQ
- , FRVBF_INSN_BNE, FRVBF_INSN_BLE, FRVBF_INSN_BGT, FRVBF_INSN_BLT
- , FRVBF_INSN_BGE, FRVBF_INSN_BLS, FRVBF_INSN_BHI, FRVBF_INSN_BC
- , FRVBF_INSN_BNC, FRVBF_INSN_BN, FRVBF_INSN_BP, FRVBF_INSN_BV
- , FRVBF_INSN_BNV, FRVBF_INSN_FBRA, FRVBF_INSN_FBNO, FRVBF_INSN_FBNE
- , FRVBF_INSN_FBEQ, FRVBF_INSN_FBLG, FRVBF_INSN_FBUE, FRVBF_INSN_FBUL
- , FRVBF_INSN_FBGE, FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE, FRVBF_INSN_FBUG
- , FRVBF_INSN_FBLE, FRVBF_INSN_FBGT, FRVBF_INSN_FBULE, FRVBF_INSN_FBU
- , FRVBF_INSN_FBO, FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR, FRVBF_INSN_BNOLR
- , FRVBF_INSN_BEQLR, FRVBF_INSN_BNELR, FRVBF_INSN_BLELR, FRVBF_INSN_BGTLR
- , FRVBF_INSN_BLTLR, FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR, FRVBF_INSN_BHILR
- , FRVBF_INSN_BCLR, FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR, FRVBF_INSN_BPLR
- , FRVBF_INSN_BVLR, FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR, FRVBF_INSN_FBNOLR
- , FRVBF_INSN_FBEQLR, FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR, FRVBF_INSN_FBUELR
- , FRVBF_INSN_FBULLR, FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR, FRVBF_INSN_FBUGELR
- , FRVBF_INSN_FBUGLR, FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR, FRVBF_INSN_FBULELR
- , FRVBF_INSN_FBULR, FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR, FRVBF_INSN_BCNOLR
- , FRVBF_INSN_BCEQLR, FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR, FRVBF_INSN_BCGTLR
- , FRVBF_INSN_BCLTLR, FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR, FRVBF_INSN_BCHILR
- , FRVBF_INSN_BCCLR, FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR, FRVBF_INSN_BCPLR
- , FRVBF_INSN_BCVLR, FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR, FRVBF_INSN_FCBNOLR
- , FRVBF_INSN_FCBEQLR, FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR, FRVBF_INSN_FCBUELR
- , FRVBF_INSN_FCBULLR, FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR, FRVBF_INSN_FCBUGELR
- , FRVBF_INSN_FCBUGLR, FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR, FRVBF_INSN_FCBULELR
- , FRVBF_INSN_FCBULR, FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL, FRVBF_INSN_CALLL
- , FRVBF_INSN_JMPIL, FRVBF_INSN_CALLIL, FRVBF_INSN_CALL, FRVBF_INSN_RETT
- , FRVBF_INSN_REI, FRVBF_INSN_TRA, FRVBF_INSN_TNO, FRVBF_INSN_TEQ
- , FRVBF_INSN_TNE, FRVBF_INSN_TLE, FRVBF_INSN_TGT, FRVBF_INSN_TLT
- , FRVBF_INSN_TGE, FRVBF_INSN_TLS, FRVBF_INSN_THI, FRVBF_INSN_TC
- , FRVBF_INSN_TNC, FRVBF_INSN_TN, FRVBF_INSN_TP, FRVBF_INSN_TV
- , FRVBF_INSN_TNV, FRVBF_INSN_FTRA, FRVBF_INSN_FTNO, FRVBF_INSN_FTNE
- , FRVBF_INSN_FTEQ, FRVBF_INSN_FTLG, FRVBF_INSN_FTUE, FRVBF_INSN_FTUL
- , FRVBF_INSN_FTGE, FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE, FRVBF_INSN_FTUG
- , FRVBF_INSN_FTLE, FRVBF_INSN_FTGT, FRVBF_INSN_FTULE, FRVBF_INSN_FTU
- , FRVBF_INSN_FTO, FRVBF_INSN_TIRA, FRVBF_INSN_TINO, FRVBF_INSN_TIEQ
- , FRVBF_INSN_TINE, FRVBF_INSN_TILE, FRVBF_INSN_TIGT, FRVBF_INSN_TILT
- , FRVBF_INSN_TIGE, FRVBF_INSN_TILS, FRVBF_INSN_TIHI, FRVBF_INSN_TIC
- , FRVBF_INSN_TINC, FRVBF_INSN_TIN, FRVBF_INSN_TIP, FRVBF_INSN_TIV
- , FRVBF_INSN_TINV, FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO, FRVBF_INSN_FTINE
- , FRVBF_INSN_FTIEQ, FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE, FRVBF_INSN_FTIUL
- , FRVBF_INSN_FTIGE, FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE, FRVBF_INSN_FTIUG
- , FRVBF_INSN_FTILE, FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE, FRVBF_INSN_FTIU
- , FRVBF_INSN_FTIO, FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP, FRVBF_INSN_ANDCR
- , FRVBF_INSN_ORCR, FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR, FRVBF_INSN_NORCR
- , FRVBF_INSN_ANDNCR, FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR, FRVBF_INSN_NORNCR
- , FRVBF_INSN_NOTCR, FRVBF_INSN_CKRA, FRVBF_INSN_CKNO, FRVBF_INSN_CKEQ
- , FRVBF_INSN_CKNE, FRVBF_INSN_CKLE, FRVBF_INSN_CKGT, FRVBF_INSN_CKLT
- , FRVBF_INSN_CKGE, FRVBF_INSN_CKLS, FRVBF_INSN_CKHI, FRVBF_INSN_CKC
- , FRVBF_INSN_CKNC, FRVBF_INSN_CKN, FRVBF_INSN_CKP, FRVBF_INSN_CKV
- , FRVBF_INSN_CKNV, FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO, FRVBF_INSN_FCKNE
- , FRVBF_INSN_FCKEQ, FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE, FRVBF_INSN_FCKUL
- , FRVBF_INSN_FCKGE, FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE, FRVBF_INSN_FCKUG
- , FRVBF_INSN_FCKLE, FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE, FRVBF_INSN_FCKU
- , FRVBF_INSN_FCKO, FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO, FRVBF_INSN_CCKEQ
- , FRVBF_INSN_CCKNE, FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT, FRVBF_INSN_CCKLT
- , FRVBF_INSN_CCKGE, FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI, FRVBF_INSN_CCKC
- , FRVBF_INSN_CCKNC, FRVBF_INSN_CCKN, FRVBF_INSN_CCKP, FRVBF_INSN_CCKV
- , FRVBF_INSN_CCKNV, FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO, FRVBF_INSN_CFCKNE
- , FRVBF_INSN_CFCKEQ, FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE, FRVBF_INSN_CFCKUL
- , FRVBF_INSN_CFCKGE, FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE, FRVBF_INSN_CFCKUG
- , FRVBF_INSN_CFCKLE, FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE, FRVBF_INSN_CFCKU
- , FRVBF_INSN_CFCKO, FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL, FRVBF_INSN_ICI
- , FRVBF_INSN_DCI, FRVBF_INSN_ICEI, FRVBF_INSN_DCEI, FRVBF_INSN_DCF
- , FRVBF_INSN_DCEF, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB, FRVBF_INSN_ITLBI
- , FRVBF_INSN_DTLBI, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL, FRVBF_INSN_ICUL
- , FRVBF_INSN_DCUL, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR, FRVBF_INSN_COP1
- , FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA
- , FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA
- , FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD
- , FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS
- , FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS
- , FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS
- , FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS
- , FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS
- , FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS
- , FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS
- , FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD
- , FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS
- , FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS
- , FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS
- , FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS
- , FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS
- , FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS
- , FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS
- , FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS
- , FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS
- , FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS
- , FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS
- , FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS
- , FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS
- , FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH
- , FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND
- , FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT
- , FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI
- , FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI
- , FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI
- , FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI
- , FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH
- , FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS
- , FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS
- , FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS
- , FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS
- , FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS
- , FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS
- , FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU
- , FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU
- , FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU
- , FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU
- , FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU
- , FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS
- , FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS
- , FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS
- , FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS
- , FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD
- , FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH
- , FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB
- , FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP
- , FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG
- , FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2
- , FRVBF_INSN_FNOP, FRVBF_INSN__MAX
+ , FRVBF_INSN_SMUL, FRVBF_INSN_UMUL, FRVBF_INSN_SMU, FRVBF_INSN_SMASS
+ , FRVBF_INSN_SMSSS, FRVBF_INSN_SLL, FRVBF_INSN_SRL, FRVBF_INSN_SRA
+ , FRVBF_INSN_SLASS, FRVBF_INSN_SCUTSS, FRVBF_INSN_SCAN, FRVBF_INSN_CADD
+ , FRVBF_INSN_CSUB, FRVBF_INSN_CAND, FRVBF_INSN_COR, FRVBF_INSN_CXOR
+ , FRVBF_INSN_CNOT, FRVBF_INSN_CSMUL, FRVBF_INSN_CSDIV, FRVBF_INSN_CUDIV
+ , FRVBF_INSN_CSLL, FRVBF_INSN_CSRL, FRVBF_INSN_CSRA, FRVBF_INSN_CSCAN
+ , FRVBF_INSN_ADDCC, FRVBF_INSN_SUBCC, FRVBF_INSN_ANDCC, FRVBF_INSN_ORCC
+ , FRVBF_INSN_XORCC, FRVBF_INSN_SLLCC, FRVBF_INSN_SRLCC, FRVBF_INSN_SRACC
+ , FRVBF_INSN_SMULCC, FRVBF_INSN_UMULCC, FRVBF_INSN_CADDCC, FRVBF_INSN_CSUBCC
+ , FRVBF_INSN_CSMULCC, FRVBF_INSN_CANDCC, FRVBF_INSN_CORCC, FRVBF_INSN_CXORCC
+ , FRVBF_INSN_CSLLCC, FRVBF_INSN_CSRLCC, FRVBF_INSN_CSRACC, FRVBF_INSN_ADDX
+ , FRVBF_INSN_SUBX, FRVBF_INSN_ADDXCC, FRVBF_INSN_SUBXCC, FRVBF_INSN_ADDSS
+ , FRVBF_INSN_SUBSS, FRVBF_INSN_ADDI, FRVBF_INSN_SUBI, FRVBF_INSN_ANDI
+ , FRVBF_INSN_ORI, FRVBF_INSN_XORI, FRVBF_INSN_SDIVI, FRVBF_INSN_NSDIVI
+ , FRVBF_INSN_UDIVI, FRVBF_INSN_NUDIVI, FRVBF_INSN_SMULI, FRVBF_INSN_UMULI
+ , FRVBF_INSN_SLLI, FRVBF_INSN_SRLI, FRVBF_INSN_SRAI, FRVBF_INSN_SCANI
+ , FRVBF_INSN_ADDICC, FRVBF_INSN_SUBICC, FRVBF_INSN_ANDICC, FRVBF_INSN_ORICC
+ , FRVBF_INSN_XORICC, FRVBF_INSN_SMULICC, FRVBF_INSN_UMULICC, FRVBF_INSN_SLLICC
+ , FRVBF_INSN_SRLICC, FRVBF_INSN_SRAICC, FRVBF_INSN_ADDXI, FRVBF_INSN_SUBXI
+ , FRVBF_INSN_ADDXICC, FRVBF_INSN_SUBXICC, FRVBF_INSN_CMPB, FRVBF_INSN_CMPBA
+ , FRVBF_INSN_SETLO, FRVBF_INSN_SETHI, FRVBF_INSN_SETLOS, FRVBF_INSN_LDSB
+ , FRVBF_INSN_LDUB, FRVBF_INSN_LDSH, FRVBF_INSN_LDUH, FRVBF_INSN_LD
+ , FRVBF_INSN_LDBF, FRVBF_INSN_LDHF, FRVBF_INSN_LDF, FRVBF_INSN_LDC
+ , FRVBF_INSN_NLDSB, FRVBF_INSN_NLDUB, FRVBF_INSN_NLDSH, FRVBF_INSN_NLDUH
+ , FRVBF_INSN_NLD, FRVBF_INSN_NLDBF, FRVBF_INSN_NLDHF, FRVBF_INSN_NLDF
+ , FRVBF_INSN_LDD, FRVBF_INSN_LDDF, FRVBF_INSN_LDDC, FRVBF_INSN_NLDD
+ , FRVBF_INSN_NLDDF, FRVBF_INSN_LDQ, FRVBF_INSN_LDQF, FRVBF_INSN_LDQC
+ , FRVBF_INSN_NLDQ, FRVBF_INSN_NLDQF, FRVBF_INSN_LDSBU, FRVBF_INSN_LDUBU
+ , FRVBF_INSN_LDSHU, FRVBF_INSN_LDUHU, FRVBF_INSN_LDU, FRVBF_INSN_NLDSBU
+ , FRVBF_INSN_NLDUBU, FRVBF_INSN_NLDSHU, FRVBF_INSN_NLDUHU, FRVBF_INSN_NLDU
+ , FRVBF_INSN_LDBFU, FRVBF_INSN_LDHFU, FRVBF_INSN_LDFU, FRVBF_INSN_LDCU
+ , FRVBF_INSN_NLDBFU, FRVBF_INSN_NLDHFU, FRVBF_INSN_NLDFU, FRVBF_INSN_LDDU
+ , FRVBF_INSN_NLDDU, FRVBF_INSN_LDDFU, FRVBF_INSN_LDDCU, FRVBF_INSN_NLDDFU
+ , FRVBF_INSN_LDQU, FRVBF_INSN_NLDQU, FRVBF_INSN_LDQFU, FRVBF_INSN_LDQCU
+ , FRVBF_INSN_NLDQFU, FRVBF_INSN_LDSBI, FRVBF_INSN_LDSHI, FRVBF_INSN_LDI
+ , FRVBF_INSN_LDUBI, FRVBF_INSN_LDUHI, FRVBF_INSN_LDBFI, FRVBF_INSN_LDHFI
+ , FRVBF_INSN_LDFI, FRVBF_INSN_NLDSBI, FRVBF_INSN_NLDUBI, FRVBF_INSN_NLDSHI
+ , FRVBF_INSN_NLDUHI, FRVBF_INSN_NLDI, FRVBF_INSN_NLDBFI, FRVBF_INSN_NLDHFI
+ , FRVBF_INSN_NLDFI, FRVBF_INSN_LDDI, FRVBF_INSN_LDDFI, FRVBF_INSN_NLDDI
+ , FRVBF_INSN_NLDDFI, FRVBF_INSN_LDQI, FRVBF_INSN_LDQFI, FRVBF_INSN_NLDQFI
+ , FRVBF_INSN_STB, FRVBF_INSN_STH, FRVBF_INSN_ST, FRVBF_INSN_STBF
+ , FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC, FRVBF_INSN_RSTB
+ , FRVBF_INSN_RSTH, FRVBF_INSN_RST, FRVBF_INSN_RSTBF, FRVBF_INSN_RSTHF
+ , FRVBF_INSN_RSTF, FRVBF_INSN_STD, FRVBF_INSN_STDF, FRVBF_INSN_STDC
+ , FRVBF_INSN_RSTD, FRVBF_INSN_RSTDF, FRVBF_INSN_STQ, FRVBF_INSN_STQF
+ , FRVBF_INSN_STQC, FRVBF_INSN_RSTQ, FRVBF_INSN_RSTQF, FRVBF_INSN_STBU
+ , FRVBF_INSN_STHU, FRVBF_INSN_STU, FRVBF_INSN_STBFU, FRVBF_INSN_STHFU
+ , FRVBF_INSN_STFU, FRVBF_INSN_STCU, FRVBF_INSN_STDU, FRVBF_INSN_STDFU
+ , FRVBF_INSN_STDCU, FRVBF_INSN_STQU, FRVBF_INSN_STQFU, FRVBF_INSN_STQCU
+ , FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB, FRVBF_INSN_CLDSH, FRVBF_INSN_CLDUH
+ , FRVBF_INSN_CLD, FRVBF_INSN_CLDBF, FRVBF_INSN_CLDHF, FRVBF_INSN_CLDF
+ , FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF, FRVBF_INSN_CLDQ, FRVBF_INSN_CLDSBU
+ , FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU, FRVBF_INSN_CLDUHU, FRVBF_INSN_CLDU
+ , FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU, FRVBF_INSN_CLDFU, FRVBF_INSN_CLDDU
+ , FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU, FRVBF_INSN_CSTB, FRVBF_INSN_CSTH
+ , FRVBF_INSN_CST, FRVBF_INSN_CSTBF, FRVBF_INSN_CSTHF, FRVBF_INSN_CSTF
+ , FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF, FRVBF_INSN_CSTQ, FRVBF_INSN_CSTBU
+ , FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU, FRVBF_INSN_CSTBFU, FRVBF_INSN_CSTHFU
+ , FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU, FRVBF_INSN_CSTDFU, FRVBF_INSN_STBI
+ , FRVBF_INSN_STHI, FRVBF_INSN_STI, FRVBF_INSN_STBFI, FRVBF_INSN_STHFI
+ , FRVBF_INSN_STFI, FRVBF_INSN_STDI, FRVBF_INSN_STDFI, FRVBF_INSN_STQI
+ , FRVBF_INSN_STQFI, FRVBF_INSN_SWAP, FRVBF_INSN_SWAPI, FRVBF_INSN_CSWAP
+ , FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG, FRVBF_INSN_MOVGFD, FRVBF_INSN_MOVFGD
+ , FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ, FRVBF_INSN_CMOVGF, FRVBF_INSN_CMOVFG
+ , FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD, FRVBF_INSN_MOVGS, FRVBF_INSN_MOVSG
+ , FRVBF_INSN_BRA, FRVBF_INSN_BNO, FRVBF_INSN_BEQ, FRVBF_INSN_BNE
+ , FRVBF_INSN_BLE, FRVBF_INSN_BGT, FRVBF_INSN_BLT, FRVBF_INSN_BGE
+ , FRVBF_INSN_BLS, FRVBF_INSN_BHI, FRVBF_INSN_BC, FRVBF_INSN_BNC
+ , FRVBF_INSN_BN, FRVBF_INSN_BP, FRVBF_INSN_BV, FRVBF_INSN_BNV
+ , FRVBF_INSN_FBRA, FRVBF_INSN_FBNO, FRVBF_INSN_FBNE, FRVBF_INSN_FBEQ
+ , FRVBF_INSN_FBLG, FRVBF_INSN_FBUE, FRVBF_INSN_FBUL, FRVBF_INSN_FBGE
+ , FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE, FRVBF_INSN_FBUG, FRVBF_INSN_FBLE
+ , FRVBF_INSN_FBGT, FRVBF_INSN_FBULE, FRVBF_INSN_FBU, FRVBF_INSN_FBO
+ , FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR, FRVBF_INSN_BNOLR, FRVBF_INSN_BEQLR
+ , FRVBF_INSN_BNELR, FRVBF_INSN_BLELR, FRVBF_INSN_BGTLR, FRVBF_INSN_BLTLR
+ , FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR, FRVBF_INSN_BHILR, FRVBF_INSN_BCLR
+ , FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR, FRVBF_INSN_BPLR, FRVBF_INSN_BVLR
+ , FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR, FRVBF_INSN_FBNOLR, FRVBF_INSN_FBEQLR
+ , FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR, FRVBF_INSN_FBUELR, FRVBF_INSN_FBULLR
+ , FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR, FRVBF_INSN_FBUGELR, FRVBF_INSN_FBUGLR
+ , FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR, FRVBF_INSN_FBULELR, FRVBF_INSN_FBULR
+ , FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR, FRVBF_INSN_BCNOLR, FRVBF_INSN_BCEQLR
+ , FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR, FRVBF_INSN_BCGTLR, FRVBF_INSN_BCLTLR
+ , FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR, FRVBF_INSN_BCHILR, FRVBF_INSN_BCCLR
+ , FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR, FRVBF_INSN_BCPLR, FRVBF_INSN_BCVLR
+ , FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR, FRVBF_INSN_FCBNOLR, FRVBF_INSN_FCBEQLR
+ , FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR, FRVBF_INSN_FCBUELR, FRVBF_INSN_FCBULLR
+ , FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR, FRVBF_INSN_FCBUGELR, FRVBF_INSN_FCBUGLR
+ , FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR, FRVBF_INSN_FCBULELR, FRVBF_INSN_FCBULR
+ , FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL, FRVBF_INSN_CALLL, FRVBF_INSN_JMPIL
+ , FRVBF_INSN_CALLIL, FRVBF_INSN_CALL, FRVBF_INSN_RETT, FRVBF_INSN_REI
+ , FRVBF_INSN_TRA, FRVBF_INSN_TNO, FRVBF_INSN_TEQ, FRVBF_INSN_TNE
+ , FRVBF_INSN_TLE, FRVBF_INSN_TGT, FRVBF_INSN_TLT, FRVBF_INSN_TGE
+ , FRVBF_INSN_TLS, FRVBF_INSN_THI, FRVBF_INSN_TC, FRVBF_INSN_TNC
+ , FRVBF_INSN_TN, FRVBF_INSN_TP, FRVBF_INSN_TV, FRVBF_INSN_TNV
+ , FRVBF_INSN_FTRA, FRVBF_INSN_FTNO, FRVBF_INSN_FTNE, FRVBF_INSN_FTEQ
+ , FRVBF_INSN_FTLG, FRVBF_INSN_FTUE, FRVBF_INSN_FTUL, FRVBF_INSN_FTGE
+ , FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE, FRVBF_INSN_FTUG, FRVBF_INSN_FTLE
+ , FRVBF_INSN_FTGT, FRVBF_INSN_FTULE, FRVBF_INSN_FTU, FRVBF_INSN_FTO
+ , FRVBF_INSN_TIRA, FRVBF_INSN_TINO, FRVBF_INSN_TIEQ, FRVBF_INSN_TINE
+ , FRVBF_INSN_TILE, FRVBF_INSN_TIGT, FRVBF_INSN_TILT, FRVBF_INSN_TIGE
+ , FRVBF_INSN_TILS, FRVBF_INSN_TIHI, FRVBF_INSN_TIC, FRVBF_INSN_TINC
+ , FRVBF_INSN_TIN, FRVBF_INSN_TIP, FRVBF_INSN_TIV, FRVBF_INSN_TINV
+ , FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO, FRVBF_INSN_FTINE, FRVBF_INSN_FTIEQ
+ , FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE, FRVBF_INSN_FTIUL, FRVBF_INSN_FTIGE
+ , FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE, FRVBF_INSN_FTIUG, FRVBF_INSN_FTILE
+ , FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE, FRVBF_INSN_FTIU, FRVBF_INSN_FTIO
+ , FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP, FRVBF_INSN_ANDCR, FRVBF_INSN_ORCR
+ , FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR, FRVBF_INSN_NORCR, FRVBF_INSN_ANDNCR
+ , FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR, FRVBF_INSN_NORNCR, FRVBF_INSN_NOTCR
+ , FRVBF_INSN_CKRA, FRVBF_INSN_CKNO, FRVBF_INSN_CKEQ, FRVBF_INSN_CKNE
+ , FRVBF_INSN_CKLE, FRVBF_INSN_CKGT, FRVBF_INSN_CKLT, FRVBF_INSN_CKGE
+ , FRVBF_INSN_CKLS, FRVBF_INSN_CKHI, FRVBF_INSN_CKC, FRVBF_INSN_CKNC
+ , FRVBF_INSN_CKN, FRVBF_INSN_CKP, FRVBF_INSN_CKV, FRVBF_INSN_CKNV
+ , FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO, FRVBF_INSN_FCKNE, FRVBF_INSN_FCKEQ
+ , FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE, FRVBF_INSN_FCKUL, FRVBF_INSN_FCKGE
+ , FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE, FRVBF_INSN_FCKUG, FRVBF_INSN_FCKLE
+ , FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE, FRVBF_INSN_FCKU, FRVBF_INSN_FCKO
+ , FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO, FRVBF_INSN_CCKEQ, FRVBF_INSN_CCKNE
+ , FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT, FRVBF_INSN_CCKLT, FRVBF_INSN_CCKGE
+ , FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI, FRVBF_INSN_CCKC, FRVBF_INSN_CCKNC
+ , FRVBF_INSN_CCKN, FRVBF_INSN_CCKP, FRVBF_INSN_CCKV, FRVBF_INSN_CCKNV
+ , FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO, FRVBF_INSN_CFCKNE, FRVBF_INSN_CFCKEQ
+ , FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE, FRVBF_INSN_CFCKUL, FRVBF_INSN_CFCKGE
+ , FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE, FRVBF_INSN_CFCKUG, FRVBF_INSN_CFCKLE
+ , FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE, FRVBF_INSN_CFCKU, FRVBF_INSN_CFCKO
+ , FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL, FRVBF_INSN_ICI, FRVBF_INSN_DCI
+ , FRVBF_INSN_ICEI, FRVBF_INSN_DCEI, FRVBF_INSN_DCF, FRVBF_INSN_DCEF
+ , FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB, FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI
+ , FRVBF_INSN_ICPL, FRVBF_INSN_DCPL, FRVBF_INSN_ICUL, FRVBF_INSN_DCUL
+ , FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR, FRVBF_INSN_COP1, FRVBF_INSN_COP2
+ , FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA, FRVBF_INSN_CLRFA
+ , FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA, FRVBF_INSN_COMMITFA
+ , FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD, FRVBF_INSN_FDTOI
+ , FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS, FRVBF_INSN_NFDSTOI
+ , FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS, FRVBF_INSN_NFSTOI
+ , FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS, FRVBF_INSN_CFMOVS
+ , FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS, FRVBF_INSN_CFNEGS
+ , FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS, FRVBF_INSN_CFABSS
+ , FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS, FRVBF_INSN_FSQRTD
+ , FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS, FRVBF_INSN_FSUBS
+ , FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD, FRVBF_INSN_FSUBD
+ , FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS, FRVBF_INSN_CFSUBS
+ , FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS, FRVBF_INSN_NFSUBS
+ , FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS, FRVBF_INSN_FCMPD
+ , FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS, FRVBF_INSN_FMSUBS
+ , FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS, FRVBF_INSN_NFDMADDS
+ , FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS, FRVBF_INSN_NFMSUBS
+ , FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS, FRVBF_INSN_FDMSS
+ , FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS, FRVBF_INSN_CFMSS
+ , FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS, FRVBF_INSN_NFMSS
+ , FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS, FRVBF_INSN_FDDIVS
+ , FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS, FRVBF_INSN_NFDADDS
+ , FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS, FRVBF_INSN_NFDSADS
+ , FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS, FRVBF_INSN_MHDSETS
+ , FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH, FRVBF_INSN_MAND
+ , FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND, FRVBF_INSN_CMOR
+ , FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT, FRVBF_INSN_MROTLI
+ , FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI, FRVBF_INSN_MCUT
+ , FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI, FRVBF_INSN_MDCUTSSI
+ , FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI, FRVBF_INSN_MSRAHI
+ , FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI, FRVBF_INSN_MSATHS
+ , FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH, FRVBF_INSN_MCMPUH
+ , FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS, FRVBF_INSN_MSUBHSS
+ , FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS, FRVBF_INSN_CMSUBHSS
+ , FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS, FRVBF_INSN_MQSUBHSS
+ , FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS, FRVBF_INSN_CMQSUBHSS
+ , FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS, FRVBF_INSN_MDADDACCS
+ , FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS, FRVBF_INSN_MMULHS
+ , FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU, FRVBF_INSN_CMMULHS
+ , FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU, FRVBF_INSN_MQMULXHS
+ , FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU, FRVBF_INSN_MMACHS
+ , FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU, FRVBF_INSN_CMMACHS
+ , FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU, FRVBF_INSN_CMQMACHS
+ , FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS, FRVBF_INSN_MQMACXHS
+ , FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS, FRVBF_INSN_MCPXIU
+ , FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS, FRVBF_INSN_CMCPXIU
+ , FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS, FRVBF_INSN_MQCPXIU
+ , FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD
+ , FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH
+ , FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB
+ , FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP, FRVBF_INSN_MCLRACC_0
+ , FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC
+ , FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP
+ , FRVBF_INSN__MAX
} FRVBF_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family frvbf. */
typedef enum frvbf_sfmt_type {
FRVBF_SFMT_EMPTY, FRVBF_SFMT_ADD, FRVBF_SFMT_NOT, FRVBF_SFMT_SDIV
- , FRVBF_SFMT_SMUL, FRVBF_SFMT_CADD, FRVBF_SFMT_CNOT, FRVBF_SFMT_CSMUL
- , FRVBF_SFMT_CSDIV, FRVBF_SFMT_ADDCC, FRVBF_SFMT_ANDCC, FRVBF_SFMT_SMULCC
- , FRVBF_SFMT_CADDCC, FRVBF_SFMT_CSMULCC, FRVBF_SFMT_ADDX, FRVBF_SFMT_ADDI
- , FRVBF_SFMT_SDIVI, FRVBF_SFMT_SMULI, FRVBF_SFMT_ADDICC, FRVBF_SFMT_ANDICC
- , FRVBF_SFMT_SMULICC, FRVBF_SFMT_ADDXI, FRVBF_SFMT_CMPB, FRVBF_SFMT_SETLO
- , FRVBF_SFMT_SETHI, FRVBF_SFMT_SETLOS, FRVBF_SFMT_LDSB, FRVBF_SFMT_LDBF
- , FRVBF_SFMT_LDC, FRVBF_SFMT_NLDSB, FRVBF_SFMT_NLDBF, FRVBF_SFMT_LDD
- , FRVBF_SFMT_LDDF, FRVBF_SFMT_LDDC, FRVBF_SFMT_NLDD, FRVBF_SFMT_NLDDF
- , FRVBF_SFMT_LDQ, FRVBF_SFMT_LDQF, FRVBF_SFMT_LDQC, FRVBF_SFMT_NLDQ
- , FRVBF_SFMT_NLDQF, FRVBF_SFMT_LDSBU, FRVBF_SFMT_NLDSBU, FRVBF_SFMT_LDBFU
- , FRVBF_SFMT_LDCU, FRVBF_SFMT_NLDBFU, FRVBF_SFMT_LDDU, FRVBF_SFMT_NLDDU
- , FRVBF_SFMT_LDDFU, FRVBF_SFMT_LDDCU, FRVBF_SFMT_NLDDFU, FRVBF_SFMT_LDQU
- , FRVBF_SFMT_NLDQU, FRVBF_SFMT_LDQFU, FRVBF_SFMT_LDQCU, FRVBF_SFMT_NLDQFU
- , FRVBF_SFMT_LDSBI, FRVBF_SFMT_LDBFI, FRVBF_SFMT_NLDSBI, FRVBF_SFMT_NLDBFI
- , FRVBF_SFMT_LDDI, FRVBF_SFMT_LDDFI, FRVBF_SFMT_NLDDI, FRVBF_SFMT_NLDDFI
- , FRVBF_SFMT_LDQI, FRVBF_SFMT_LDQFI, FRVBF_SFMT_NLDQFI, FRVBF_SFMT_STB
- , FRVBF_SFMT_STBF, FRVBF_SFMT_STC, FRVBF_SFMT_RSTB, FRVBF_SFMT_RSTBF
- , FRVBF_SFMT_STD, FRVBF_SFMT_STDF, FRVBF_SFMT_STDC, FRVBF_SFMT_RSTD
- , FRVBF_SFMT_RSTDF, FRVBF_SFMT_STBU, FRVBF_SFMT_STBFU, FRVBF_SFMT_STCU
- , FRVBF_SFMT_STDU, FRVBF_SFMT_STDFU, FRVBF_SFMT_STDCU, FRVBF_SFMT_STQU
- , FRVBF_SFMT_CLDSB, FRVBF_SFMT_CLDBF, FRVBF_SFMT_CLDD, FRVBF_SFMT_CLDDF
- , FRVBF_SFMT_CLDQ, FRVBF_SFMT_CLDSBU, FRVBF_SFMT_CLDBFU, FRVBF_SFMT_CLDDU
- , FRVBF_SFMT_CLDDFU, FRVBF_SFMT_CLDQU, FRVBF_SFMT_CSTB, FRVBF_SFMT_CSTBF
- , FRVBF_SFMT_CSTD, FRVBF_SFMT_CSTDF, FRVBF_SFMT_CSTBU, FRVBF_SFMT_CSTBFU
- , FRVBF_SFMT_CSTDU, FRVBF_SFMT_CSTDFU, FRVBF_SFMT_STBI, FRVBF_SFMT_STBFI
- , FRVBF_SFMT_STDI, FRVBF_SFMT_STDFI, FRVBF_SFMT_SWAP, FRVBF_SFMT_SWAPI
- , FRVBF_SFMT_CSWAP, FRVBF_SFMT_MOVGF, FRVBF_SFMT_MOVFG, FRVBF_SFMT_MOVGFD
- , FRVBF_SFMT_MOVFGD, FRVBF_SFMT_MOVGFQ, FRVBF_SFMT_MOVFGQ, FRVBF_SFMT_CMOVGF
- , FRVBF_SFMT_CMOVFG, FRVBF_SFMT_CMOVGFD, FRVBF_SFMT_CMOVFGD, FRVBF_SFMT_MOVGS
- , FRVBF_SFMT_MOVSG, FRVBF_SFMT_BRA, FRVBF_SFMT_BNO, FRVBF_SFMT_BEQ
- , FRVBF_SFMT_FBNE, FRVBF_SFMT_BCTRLR, FRVBF_SFMT_BRALR, FRVBF_SFMT_BNOLR
- , FRVBF_SFMT_BEQLR, FRVBF_SFMT_FBEQLR, FRVBF_SFMT_BCRALR, FRVBF_SFMT_BCNOLR
- , FRVBF_SFMT_BCEQLR, FRVBF_SFMT_FCBEQLR, FRVBF_SFMT_JMPL, FRVBF_SFMT_JMPIL
- , FRVBF_SFMT_CALL, FRVBF_SFMT_RETT, FRVBF_SFMT_REI, FRVBF_SFMT_TRA
- , FRVBF_SFMT_TEQ, FRVBF_SFMT_FTNE, FRVBF_SFMT_TIRA, FRVBF_SFMT_TIEQ
- , FRVBF_SFMT_FTINE, FRVBF_SFMT_BREAK, FRVBF_SFMT_ANDCR, FRVBF_SFMT_NOTCR
- , FRVBF_SFMT_CKRA, FRVBF_SFMT_CKEQ, FRVBF_SFMT_FCKRA, FRVBF_SFMT_FCKNE
- , FRVBF_SFMT_CCKRA, FRVBF_SFMT_CCKEQ, FRVBF_SFMT_CFCKRA, FRVBF_SFMT_CFCKNE
- , FRVBF_SFMT_CJMPL, FRVBF_SFMT_ICI, FRVBF_SFMT_ICEI, FRVBF_SFMT_ICPL
- , FRVBF_SFMT_ICUL, FRVBF_SFMT_CLRGR, FRVBF_SFMT_CLRFR, FRVBF_SFMT_COMMITGR
- , FRVBF_SFMT_COMMITFR, FRVBF_SFMT_FITOS, FRVBF_SFMT_FSTOI, FRVBF_SFMT_FITOD
- , FRVBF_SFMT_FDTOI, FRVBF_SFMT_FDITOS, FRVBF_SFMT_FDSTOI, FRVBF_SFMT_CFITOS
- , FRVBF_SFMT_CFSTOI, FRVBF_SFMT_NFITOS, FRVBF_SFMT_NFSTOI, FRVBF_SFMT_FMOVS
- , FRVBF_SFMT_FMOVD, FRVBF_SFMT_FDMOVS, FRVBF_SFMT_CFMOVS, FRVBF_SFMT_NFSQRTS
- , FRVBF_SFMT_FADDS, FRVBF_SFMT_FADDD, FRVBF_SFMT_CFADDS, FRVBF_SFMT_NFADDS
- , FRVBF_SFMT_FCMPS, FRVBF_SFMT_FCMPD, FRVBF_SFMT_CFCMPS, FRVBF_SFMT_FDCMPS
- , FRVBF_SFMT_FMADDS, FRVBF_SFMT_FMADDD, FRVBF_SFMT_FDMADDS, FRVBF_SFMT_CFMADDS
- , FRVBF_SFMT_NFMADDS, FRVBF_SFMT_FMAS, FRVBF_SFMT_FDMAS, FRVBF_SFMT_CFMAS
- , FRVBF_SFMT_NFDCMPS, FRVBF_SFMT_MHSETLOS, FRVBF_SFMT_MHSETHIS, FRVBF_SFMT_MHDSETS
- , FRVBF_SFMT_MHSETLOH, FRVBF_SFMT_MHSETHIH, FRVBF_SFMT_MHDSETH, FRVBF_SFMT_MAND
- , FRVBF_SFMT_CMAND, FRVBF_SFMT_MNOT, FRVBF_SFMT_CMNOT, FRVBF_SFMT_MROTLI
- , FRVBF_SFMT_MWCUT, FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT, FRVBF_SFMT_MCUTI
- , FRVBF_SFMT_MDCUTSSI, FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI, FRVBF_SFMT_MCPLHI
- , FRVBF_SFMT_MCPLI, FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS, FRVBF_SFMT_MCMPSH
- , FRVBF_SFMT_MABSHS, FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MADDACCS
- , FRVBF_SFMT_MDADDACCS, FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS
- , FRVBF_SFMT_CMMULHS, FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS
- , FRVBF_SFMT_MMACHU, FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS
- , FRVBF_SFMT_MQMACHU, FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS
- , FRVBF_SFMT_CMCPXRS, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW
- , FRVBF_SFMT_MEXPDHD, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH
- , FRVBF_SFMT_MUNPACKH, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH
- , FRVBF_SFMT_MHTOB, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE
- , FRVBF_SFMT_MCLRACC_0, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC
- , FRVBF_SFMT_MWTACCG
+ , FRVBF_SFMT_SMUL, FRVBF_SFMT_SMU, FRVBF_SFMT_SMASS, FRVBF_SFMT_SCUTSS
+ , FRVBF_SFMT_CADD, FRVBF_SFMT_CNOT, FRVBF_SFMT_CSMUL, FRVBF_SFMT_CSDIV
+ , FRVBF_SFMT_ADDCC, FRVBF_SFMT_ANDCC, FRVBF_SFMT_SMULCC, FRVBF_SFMT_CADDCC
+ , FRVBF_SFMT_CSMULCC, FRVBF_SFMT_ADDX, FRVBF_SFMT_ADDI, FRVBF_SFMT_SDIVI
+ , FRVBF_SFMT_SMULI, FRVBF_SFMT_ADDICC, FRVBF_SFMT_ANDICC, FRVBF_SFMT_SMULICC
+ , FRVBF_SFMT_ADDXI, FRVBF_SFMT_CMPB, FRVBF_SFMT_SETLO, FRVBF_SFMT_SETHI
+ , FRVBF_SFMT_SETLOS, FRVBF_SFMT_LDSB, FRVBF_SFMT_LDBF, FRVBF_SFMT_LDC
+ , FRVBF_SFMT_NLDSB, FRVBF_SFMT_NLDBF, FRVBF_SFMT_LDD, FRVBF_SFMT_LDDF
+ , FRVBF_SFMT_LDDC, FRVBF_SFMT_NLDD, FRVBF_SFMT_NLDDF, FRVBF_SFMT_LDQ
+ , FRVBF_SFMT_LDQF, FRVBF_SFMT_LDQC, FRVBF_SFMT_NLDQ, FRVBF_SFMT_NLDQF
+ , FRVBF_SFMT_LDSBU, FRVBF_SFMT_NLDSBU, FRVBF_SFMT_LDBFU, FRVBF_SFMT_LDCU
+ , FRVBF_SFMT_NLDBFU, FRVBF_SFMT_LDDU, FRVBF_SFMT_NLDDU, FRVBF_SFMT_LDDFU
+ , FRVBF_SFMT_LDDCU, FRVBF_SFMT_NLDDFU, FRVBF_SFMT_LDQU, FRVBF_SFMT_NLDQU
+ , FRVBF_SFMT_LDQFU, FRVBF_SFMT_LDQCU, FRVBF_SFMT_NLDQFU, FRVBF_SFMT_LDSBI
+ , FRVBF_SFMT_LDBFI, FRVBF_SFMT_NLDSBI, FRVBF_SFMT_NLDBFI, FRVBF_SFMT_LDDI
+ , FRVBF_SFMT_LDDFI, FRVBF_SFMT_NLDDI, FRVBF_SFMT_NLDDFI, FRVBF_SFMT_LDQI
+ , FRVBF_SFMT_LDQFI, FRVBF_SFMT_NLDQFI, FRVBF_SFMT_STB, FRVBF_SFMT_STBF
+ , FRVBF_SFMT_STC, FRVBF_SFMT_RSTB, FRVBF_SFMT_RSTBF, FRVBF_SFMT_STD
+ , FRVBF_SFMT_STDF, FRVBF_SFMT_STDC, FRVBF_SFMT_RSTD, FRVBF_SFMT_RSTDF
+ , FRVBF_SFMT_STBU, FRVBF_SFMT_STBFU, FRVBF_SFMT_STCU, FRVBF_SFMT_STDU
+ , FRVBF_SFMT_STDFU, FRVBF_SFMT_STDCU, FRVBF_SFMT_STQU, FRVBF_SFMT_CLDSB
+ , FRVBF_SFMT_CLDBF, FRVBF_SFMT_CLDD, FRVBF_SFMT_CLDDF, FRVBF_SFMT_CLDQ
+ , FRVBF_SFMT_CLDSBU, FRVBF_SFMT_CLDBFU, FRVBF_SFMT_CLDDU, FRVBF_SFMT_CLDDFU
+ , FRVBF_SFMT_CLDQU, FRVBF_SFMT_CSTB, FRVBF_SFMT_CSTBF, FRVBF_SFMT_CSTD
+ , FRVBF_SFMT_CSTDF, FRVBF_SFMT_CSTBU, FRVBF_SFMT_CSTBFU, FRVBF_SFMT_CSTDU
+ , FRVBF_SFMT_CSTDFU, FRVBF_SFMT_STBI, FRVBF_SFMT_STBFI, FRVBF_SFMT_STDI
+ , FRVBF_SFMT_STDFI, FRVBF_SFMT_SWAP, FRVBF_SFMT_SWAPI, FRVBF_SFMT_CSWAP
+ , FRVBF_SFMT_MOVGF, FRVBF_SFMT_MOVFG, FRVBF_SFMT_MOVGFD, FRVBF_SFMT_MOVFGD
+ , FRVBF_SFMT_MOVGFQ, FRVBF_SFMT_MOVFGQ, FRVBF_SFMT_CMOVGF, FRVBF_SFMT_CMOVFG
+ , FRVBF_SFMT_CMOVGFD, FRVBF_SFMT_CMOVFGD, FRVBF_SFMT_MOVGS, FRVBF_SFMT_MOVSG
+ , FRVBF_SFMT_BRA, FRVBF_SFMT_BNO, FRVBF_SFMT_BEQ, FRVBF_SFMT_FBNE
+ , FRVBF_SFMT_BCTRLR, FRVBF_SFMT_BRALR, FRVBF_SFMT_BNOLR, FRVBF_SFMT_BEQLR
+ , FRVBF_SFMT_FBEQLR, FRVBF_SFMT_BCRALR, FRVBF_SFMT_BCNOLR, FRVBF_SFMT_BCEQLR
+ , FRVBF_SFMT_FCBEQLR, FRVBF_SFMT_JMPL, FRVBF_SFMT_JMPIL, FRVBF_SFMT_CALL
+ , FRVBF_SFMT_RETT, FRVBF_SFMT_REI, FRVBF_SFMT_TRA, FRVBF_SFMT_TEQ
+ , FRVBF_SFMT_FTNE, FRVBF_SFMT_TIRA, FRVBF_SFMT_TIEQ, FRVBF_SFMT_FTINE
+ , FRVBF_SFMT_BREAK, FRVBF_SFMT_ANDCR, FRVBF_SFMT_NOTCR, FRVBF_SFMT_CKRA
+ , FRVBF_SFMT_CKEQ, FRVBF_SFMT_FCKRA, FRVBF_SFMT_FCKNE, FRVBF_SFMT_CCKRA
+ , FRVBF_SFMT_CCKEQ, FRVBF_SFMT_CFCKRA, FRVBF_SFMT_CFCKNE, FRVBF_SFMT_CJMPL
+ , FRVBF_SFMT_ICI, FRVBF_SFMT_ICEI, FRVBF_SFMT_ICPL, FRVBF_SFMT_ICUL
+ , FRVBF_SFMT_CLRGR, FRVBF_SFMT_CLRFR, FRVBF_SFMT_COMMITGR, FRVBF_SFMT_COMMITFR
+ , FRVBF_SFMT_FITOS, FRVBF_SFMT_FSTOI, FRVBF_SFMT_FITOD, FRVBF_SFMT_FDTOI
+ , FRVBF_SFMT_FDITOS, FRVBF_SFMT_FDSTOI, FRVBF_SFMT_CFITOS, FRVBF_SFMT_CFSTOI
+ , FRVBF_SFMT_NFITOS, FRVBF_SFMT_NFSTOI, FRVBF_SFMT_FMOVS, FRVBF_SFMT_FMOVD
+ , FRVBF_SFMT_FDMOVS, FRVBF_SFMT_CFMOVS, FRVBF_SFMT_NFSQRTS, FRVBF_SFMT_FADDS
+ , FRVBF_SFMT_FADDD, FRVBF_SFMT_CFADDS, FRVBF_SFMT_NFADDS, FRVBF_SFMT_FCMPS
+ , FRVBF_SFMT_FCMPD, FRVBF_SFMT_CFCMPS, FRVBF_SFMT_FDCMPS, FRVBF_SFMT_FMADDS
+ , FRVBF_SFMT_FMADDD, FRVBF_SFMT_FDMADDS, FRVBF_SFMT_CFMADDS, FRVBF_SFMT_NFMADDS
+ , FRVBF_SFMT_FMAS, FRVBF_SFMT_FDMAS, FRVBF_SFMT_CFMAS, FRVBF_SFMT_NFDCMPS
+ , FRVBF_SFMT_MHSETLOS, FRVBF_SFMT_MHSETHIS, FRVBF_SFMT_MHDSETS, FRVBF_SFMT_MHSETLOH
+ , FRVBF_SFMT_MHSETHIH, FRVBF_SFMT_MHDSETH, FRVBF_SFMT_MAND, FRVBF_SFMT_CMAND
+ , FRVBF_SFMT_MNOT, FRVBF_SFMT_CMNOT, FRVBF_SFMT_MROTLI, FRVBF_SFMT_MWCUT
+ , FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT, FRVBF_SFMT_MCUTI, FRVBF_SFMT_MDCUTSSI
+ , FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI, FRVBF_SFMT_MCPLHI, FRVBF_SFMT_MCPLI
+ , FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS, FRVBF_SFMT_MCMPSH, FRVBF_SFMT_MABSHS
+ , FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MADDACCS, FRVBF_SFMT_MDADDACCS
+ , FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS, FRVBF_SFMT_CMMULHS
+ , FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS, FRVBF_SFMT_MMACHU
+ , FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS, FRVBF_SFMT_MQMACHU
+ , FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS, FRVBF_SFMT_CMCPXRS
+ , FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW, FRVBF_SFMT_MEXPDHD
+ , FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH, FRVBF_SFMT_MUNPACKH
+ , FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH, FRVBF_SFMT_MHTOB
+ , FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE, FRVBF_SFMT_MCLRACC_0
+ , FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC, FRVBF_SFMT_MWTACCG
} FRVBF_SFMT_TYPE;
/* Function unit handlers (user written). */
extern int frvbf_model_frv_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int frvbf_model_fr550_u_media_4_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintieven*/, INT /*FRintjeven*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
+extern int frvbf_model_fr550_u_media_4_add_sub_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
+extern int frvbf_model_fr550_u_media_4_add_sub (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
+extern int frvbf_model_fr550_u_media_4_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
+extern int frvbf_model_fr550_u_media_4_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
+extern int frvbf_model_fr550_u_media_4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
+extern int frvbf_model_fr550_u_media_set (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/);
+extern int frvbf_model_fr550_u_media_3_mclracc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int frvbf_model_fr550_u_media_3_wtacc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*ACC40Sk*/);
+extern int frvbf_model_fr550_u_media_3_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintkeven*/);
+extern int frvbf_model_fr550_u_media_3_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*ACC40Si*/, INT /*FRintk*/);
+extern int frvbf_model_fr550_u_media_3_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/);
+extern int frvbf_model_fr550_u_media_dual_expand (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintkeven*/);
+extern int frvbf_model_fr550_u_media_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintieven*/, INT /*FRintjeven*/, INT /*FRintkeven*/);
+extern int frvbf_model_fr550_u_media (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr550_u_float_convert (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRj*/, INT /*FRintj*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRintk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr550_u_commit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRk*/, INT /*FRk*/);
+extern int frvbf_model_fr550_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr550_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr550_u_dcpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr550_u_icpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr550_u_dcf (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr550_u_dci (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr550_u_ici (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr550_u_clrfr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRk*/);
+extern int frvbf_model_fr550_u_clrgr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRk*/);
+extern int frvbf_model_fr550_u_fr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRk*/);
+extern int frvbf_model_fr550_u_swap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/);
+extern int frvbf_model_fr550_u_fr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr550_u_fr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr550_u_gr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
+extern int frvbf_model_fr550_u_gr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
+extern int frvbf_model_fr550_u_set_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRkhi*/, INT /*GRklo*/);
+extern int frvbf_model_fr550_u_gr2spr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*spr*/);
+extern int frvbf_model_fr550_u_spr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*spr*/, INT /*GRj*/);
+extern int frvbf_model_fr550_u_gr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*FRintk*/);
+extern int frvbf_model_fr550_u_fr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/, INT /*GRj*/);
+extern int frvbf_model_fr550_u_float_dual_compare (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FCCi_2*/);
+extern int frvbf_model_fr550_u_float_compare (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FCCi_2*/);
+extern int frvbf_model_fr550_u_float_sqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRj*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr550_u_float_div (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRk*/);
+extern int frvbf_model_fr550_u_float_dual_arith (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr550_u_float_arith (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr550_u_check (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ICCi_3*/, INT /*FCCi_3*/);
+extern int frvbf_model_fr550_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/);
+extern int frvbf_model_fr550_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/);
+extern int frvbf_model_fr550_u_idiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/);
+extern int frvbf_model_fr550_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/);
+extern int frvbf_model_fr550_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/);
+extern int frvbf_model_fr550_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int frvbf_model_fr500_u_commit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRk*/, INT /*FRk*/);
extern int frvbf_model_fr500_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr500_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
diff --git a/sim/frv/frv-sim.h b/sim/frv/frv-sim.h
index 0d690ba..a28df49 100644
--- a/sim/frv/frv-sim.h
+++ b/sim/frv/frv-sim.h
@@ -1,6 +1,6 @@
/* collection of junk waiting time to sort out
Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
- Contributed by Red Hat.
+ Contributed by Red Hat
This file is part of the GNU Simulators.
@@ -104,8 +104,11 @@ extern void frvbf_switch_supervisor_user_context (SIM_CPU *);
extern QI frvbf_set_icc_for_shift_left (SIM_CPU *, SI, SI, QI);
extern QI frvbf_set_icc_for_shift_right (SIM_CPU *, SI, SI, QI);
+/* Insn semantics. */
extern void frvbf_signed_integer_divide (SIM_CPU *, SI, SI, int, int);
extern void frvbf_unsigned_integer_divide (SIM_CPU *, USI, USI, int, int);
+extern SI frvbf_shift_left_arith_saturate (SIM_CPU *, SI, SI);
+extern SI frvbf_iacc_cut (SIM_CPU *, DI, SI);
extern void frvbf_clear_accumulators (SIM_CPU *, SI, int);
@@ -149,6 +152,7 @@ struct _device { int foo; };
/* maintain the address of the start of the previous VLIW insn sequence. */
extern IADDR previous_vliw_pc;
+extern CGEN_ATTR_VALUE_TYPE frv_current_fm_slot;
/* Hardware status. */
#define GET_HSR0() GET_H_SPR (H_SPR_HSR0)
@@ -174,6 +178,9 @@ extern IADDR previous_vliw_pc;
#define GET_IHSR8() GET_H_SPR (H_SPR_IHSR8)
#define GET_IHSR8_NBC(ihsr8) ((ihsr8) & 1)
+#define GET_IHSR8_ICDM(ihsr8) (((ihsr8) >> 1) & 1)
+#define GET_IHSR8_ICWE(ihsr8) (((ihsr8) >> 8) & 7)
+#define GET_IHSR8_DCWE(ihsr8) (((ihsr8) >> 12) & 7)
void frvbf_insn_cache_preload (SIM_CPU *, SI, USI, int);
void frvbf_data_cache_preload (SIM_CPU *, SI, USI, int);
@@ -645,6 +652,9 @@ enum frv_msr_mtt
#define GET_MSR_EMCI(msr) ( \
((msr) >> 24) & 0x1 \
)
+#define GET_MSR_MPEM(msr) ( \
+ ((msr) >> 27) & 0x1 \
+)
#define GET_MSR_SRDAV(msr) ( \
((msr) >> 28) & 0x1 \
)
@@ -677,6 +687,15 @@ struct frv_interrupt_queue_element *
frv_queue_illegal_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
struct frv_interrupt_queue_element *
+frv_queue_privileged_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
+
+struct frv_interrupt_queue_element *
+frv_queue_float_disabled_interrupt (SIM_CPU *);
+
+struct frv_interrupt_queue_element *
+frv_queue_media_disabled_interrupt (SIM_CPU *);
+
+struct frv_interrupt_queue_element *
frv_queue_non_implemented_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
struct frv_interrupt_queue_element *
diff --git a/sim/frv/frv.c b/sim/frv/frv.c
index bd3220d..7f48256 100644
--- a/sim/frv/frv.c
+++ b/sim/frv/frv.c
@@ -113,6 +113,7 @@ check_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
case bfd_mach_frvtomcat:
@@ -140,6 +141,7 @@ check_fr_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
case bfd_mach_frvtomcat:
@@ -431,6 +433,9 @@ frvbf_h_spr_set_handler (SIM_CPU *current_cpu, UINT spr, USI newval)
case H_SPR_SR3:
spr_sr_set_handler (current_cpu, spr, newval);
break;
+ case H_SPR_IHSR8:
+ frv_cache_reconfigure (current_cpu, CPU_INSN_CACHE (current_cpu));
+ break;
default:
CPU (h_spr[spr]) = newval;
break;
@@ -926,9 +931,13 @@ frvbf_clear_accumulators (SIM_CPU *current_cpu, SI acc_ix, int A)
SIM_DESC sd = CPU_STATE (current_cpu);
int acc_num =
(STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) ? 8 :
+ (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) ? 8 :
(STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) ? 4 :
63;
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
+ ps->mclracc_acc = acc_ix;
+ ps->mclracc_A = A;
if (A == 0 || acc_ix != 0) /* Clear 1 accumuator? */
{
/* This instruction is a nop if the referenced accumulator is not
@@ -1027,6 +1036,65 @@ frvbf_media_cut_ss (SIM_CPU *current_cpu, DI acc, SI cut_point)
return frvbf_media_cut (current_cpu, acc, cut_point);
}
+/* Compute the result of int accumulator cut (SCUTSS). */
+SI
+frvbf_iacc_cut (SIM_CPU *current_cpu, DI acc, SI cut_point)
+{
+ /* The cut point is the lower 6 bits (signed) of what we are passed. */
+ cut_point = cut_point << 25 >> 25;
+
+ if (cut_point <= -32)
+ cut_point = -31; /* Special case for full shiftout. */
+
+ /* Negative cuts (cannot saturate). */
+ if (cut_point < 0)
+ return acc >> (32 + -cut_point);
+
+ /* Positive cuts will saturate if significant bits are shifted out. */
+ if (acc != ((acc << cut_point) >> cut_point))
+ if (acc >= 0)
+ return 0x7fffffff;
+ else
+ return 0x80000000;
+
+ /* No saturate, just cut. */
+ return ((acc << cut_point) >> 32);
+}
+
+/* Compute the result of shift-left-arithmetic-with-saturation (SLASS). */
+SI
+frvbf_shift_left_arith_saturate (SIM_CPU *current_cpu, SI arg1, SI arg2)
+{
+ int neg_arg1;
+
+ /* FIXME: what to do with negative shift amt? */
+ if (arg2 <= 0)
+ return arg1;
+
+ if (arg1 == 0)
+ return 0;
+
+ /* Signed shift by 31 or greater saturates by definition. */
+ if (arg2 >= 31)
+ if (arg1 > 0)
+ return (SI) 0x7fffffff;
+ else
+ return (SI) 0x80000000;
+
+ /* OK, arg2 is between 1 and 31. */
+ neg_arg1 = (arg1 < 0);
+ do {
+ arg1 <<= 1;
+ /* Check for sign bit change (saturation). */
+ if (neg_arg1 && (arg1 >= 0))
+ return (SI) 0x80000000;
+ else if (!neg_arg1 && (arg1 < 0))
+ return (SI) 0x7fffffff;
+ } while (--arg2 > 0);
+
+ return arg1;
+}
+
/* Simulate the media custom insns. */
void
frvbf_media_cop (SIM_CPU *current_cpu, int cop_num)
@@ -1051,12 +1119,13 @@ do_media_average (SIM_CPU *current_cpu, HI arg1, HI arg2)
HI result = sum >> 1;
int rounding_value;
- /* On fr400, check the rounding mode. On other machines rounding is always
+ /* On fr400 and fr550, check the rounding mode. On other machines rounding is always
toward negative infinity and the result is already correctly rounded. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
/* Need to check rounding mode. */
case bfd_mach_fr400:
+ case bfd_mach_fr550:
/* Check whether rounding will be required. Rounding will be required
if the sum is an odd number. */
rounding_value = sum & 1;
diff --git a/sim/frv/interrupts.c b/sim/frv/interrupts.c
index 1f5547e..540ee06 100644
--- a/sim/frv/interrupts.c
+++ b/sim/frv/interrupts.c
@@ -235,10 +235,14 @@ frv_queue_illegal_instruction_interrupt (
SIM_CPU *current_cpu, const CGEN_INSN *insn
)
{
- /* The fr400 does not have the fp_exception. */
SIM_DESC sd = CPU_STATE (current_cpu);
- if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400)
+ switch (STATE_ARCHITECTURE (sd)->mach)
{
+ case bfd_mach_fr400:
+ case bfd_mach_fr550:
+ break;
+ default:
+ /* Some machines generate fp_exception for this case. */
if (frv_is_float_insn (insn) || frv_is_media_insn (insn))
{
struct frv_fp_exception_info fp_info = {
@@ -246,21 +250,59 @@ frv_queue_illegal_instruction_interrupt (
};
return frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
}
+ break;
}
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
}
struct frv_interrupt_queue_element *
+frv_queue_privileged_instruction_interrupt (SIM_CPU *current_cpu, const CGEN_INSN *insn)
+{
+ /* The fr550 has no privileged instruction interrupt. It uses
+ illegal_instruction. */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+
+ return frv_queue_program_interrupt (current_cpu, FRV_PRIVILEGED_INSTRUCTION);
+}
+
+struct frv_interrupt_queue_element *
+frv_queue_float_disabled_interrupt (SIM_CPU *current_cpu)
+{
+ /* The fr550 has no fp_disabled interrupt. It uses illegal_instruction. */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+
+ return frv_queue_program_interrupt (current_cpu, FRV_FP_DISABLED);
+}
+
+struct frv_interrupt_queue_element *
+frv_queue_media_disabled_interrupt (SIM_CPU *current_cpu)
+{
+ /* The fr550 has no mp_disabled interrupt. It uses illegal_instruction. */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+
+ return frv_queue_program_interrupt (current_cpu, FRV_MP_DISABLED);
+}
+
+struct frv_interrupt_queue_element *
frv_queue_non_implemented_instruction_interrupt (
SIM_CPU *current_cpu, const CGEN_INSN *insn
)
{
- /* The fr400 does not have the fp_exception, nor does it generate mp_exception
- for this case. */
SIM_DESC sd = CPU_STATE (current_cpu);
- if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400)
+ switch (STATE_ARCHITECTURE (sd)->mach)
{
+ case bfd_mach_fr400:
+ case bfd_mach_fr550:
+ break;
+ default:
+ /* Some machines generate fp_exception or mp_exception for this case. */
if (frv_is_float_insn (insn))
{
struct frv_fp_exception_info fp_info = {
@@ -268,14 +310,13 @@ frv_queue_non_implemented_instruction_interrupt (
};
return frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
}
-
if (frv_is_media_insn (insn))
{
frv_set_mp_exception_registers (current_cpu, MTT_UNIMPLEMENTED_MPOP,
0);
return NULL; /* no interrupt queued at this time. */
}
-
+ break;
}
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
@@ -364,19 +405,19 @@ frv_detect_insn_access_interrupts (SIM_CPU *current_cpu, SCACHE *sc)
if (frv_is_float_insn (insn)
|| (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR_ACCESS)
&& ! GET_H_PSR_EM ()))
- frv_queue_program_interrupt (current_cpu, FRV_FP_DISABLED);
+ frv_queue_float_disabled_interrupt (current_cpu);
}
/* Make sure media support is enabled. */
else if (! GET_H_PSR_EM ())
{
/* Generate mp_disabled if it is a media insn. */
if (frv_is_media_insn (insn) || CGEN_INSN_NUM (insn) == FRV_INSN_MTRAP)
- frv_queue_program_interrupt (current_cpu, FRV_MP_DISABLED);
+ frv_queue_media_disabled_interrupt (current_cpu);
}
/* Check for privileged insns. */
else if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_PRIVILEGED) &&
! GET_H_PSR_S ())
- frv_queue_program_interrupt (current_cpu, FRV_PRIVILEGED_INSTRUCTION);
+ frv_queue_privileged_instruction_interrupt (current_cpu, insn);
#if 0 /* disable for now until we find out how FSR0.QNE gets reset. */
else
{
@@ -552,6 +593,10 @@ esr_for_data_access_exception (
SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
)
{
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ return 8; /* Use ESR8, EPCR8. */
+
if (item->slot == UNIT_I0)
return 8; /* Use ESR8, EPCR8, EAR8, EDR8. */
@@ -593,7 +638,7 @@ clear_exception_status_registers (SIM_CPU *current_cpu)
CLEAR_ESR_VALID (esr);
SET_ESR (i, esr);
}
- for (i = 8; i <= 13; ++i)
+ for (i = 8; i <= 15; ++i)
{
SI esr = GET_ESR (i);
CLEAR_ESR_VALID (esr);
@@ -617,10 +662,11 @@ frv_set_mp_exception_registers (
{
FRV_VLIW *vliw = CPU_VLIW (current_cpu);
int slot = vliw->next_slot - 1;
+ SIM_DESC sd = CPU_STATE (current_cpu);
/* If this insn is in the M2 slot, then set MSR1.OVF and MSR1.SIE,
otherwise set MSR0.OVF and MSR0.SIE. */
- if ((*vliw->current_vliw)[slot] == UNIT_FM1)
+ if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550 && (*vliw->current_vliw)[slot] == UNIT_FM1)
{
SI msr = GET_MSR (1);
OR_MSR_SIE (msr, sie);
@@ -633,8 +679,14 @@ frv_set_mp_exception_registers (
SET_MSR_OVF (msr0);
}
- /* Regardless of the slot, set MSR0.AOVF. */
- SET_MSR_AOVF (msr0);
+ /* Generate the interrupt now if MSR0.MPEM is set on fr550 */
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550 && GET_MSR_MPEM (msr0))
+ frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION);
+ else
+ {
+ /* Regardless of the slot, set MSR0.AOVF. */
+ SET_MSR_AOVF (msr0);
+ }
}
SET_MSR (0, msr0);
@@ -689,6 +741,18 @@ set_fp_exception_registers (
SI fsr0;
IADDR pc;
struct frv_fp_exception_info *fp_info;
+ SIM_DESC sd = CPU_STATE (current_cpu);
+
+ /* No FQ registers on fr550 */
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ /* Update the fsr. */
+ fp_info = & item->u.fp_info;
+ fsr0 = GET_FSR (0);
+ SET_FSR_FTT (fsr0, fp_info->ftt);
+ SET_FSR (0, fsr0);
+ return;
+ }
/* Select an FQ and update it with the exception information. */
fq_index = fq_for_exception (current_cpu, item);
@@ -755,7 +819,9 @@ set_exception_status_registers (
SET_ESR_REC (esr, item->u.rec);
else if (interrupt->kind == FRV_INSTRUCTION_ACCESS_EXCEPTION)
SET_ESR_IAEC (esr, item->u.iaec);
- set_epcr = 1;
+ /* For fr550, don't set epcr for precise interrupts. */
+ if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
+ set_epcr = 1;
}
else
{
@@ -765,14 +831,17 @@ set_exception_status_registers (
set_isr_exception_fields (current_cpu, item);
/* fall thru to set reg_index. */
case FRV_COMMIT_EXCEPTION:
- if (item->slot == UNIT_I0)
+ /* For fr550, always use ESR0. */
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ reg_index = 0;
+ else if (item->slot == UNIT_I0)
reg_index = 0;
else if (item->slot == UNIT_I1)
reg_index = 1;
set_epcr = 1;
break;
case FRV_DATA_STORE_ERROR:
- reg_index = 14; /* Use ESR15, EPCR15. */
+ reg_index = 14; /* Use ESR14. */
break;
case FRV_DATA_ACCESS_ERROR:
reg_index = 15; /* Use ESR15, EPCR15. */
@@ -787,15 +856,29 @@ set_exception_status_registers (
/* Get the appropriate ESR, EPCR, EAR and EDR.
EAR will be set. EDR will not be set if this is a store insn. */
set_ear = 1;
- if (item->u.data_written.length != 0)
- set_edr = 1;
+ /* For fr550, never use EDRx. */
+ if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
+ if (item->u.data_written.length != 0)
+ set_edr = 1;
reg_index = esr_for_data_access_exception (current_cpu, item);
set_epcr = 1;
break;
case FRV_MP_EXCEPTION:
+ /* For fr550, use EPCR2 and ESR2. */
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ reg_index = 2;
+ set_epcr = 1;
+ }
break; /* MSR0-1, FQ0-9 are already set. */
case FRV_FP_EXCEPTION:
set_fp_exception_registers (current_cpu, item);
+ /* For fr550, use EPCR2 and ESR2. */
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ reg_index = 2;
+ set_epcr = 1;
+ }
break;
default:
{
diff --git a/sim/frv/memory.c b/sim/frv/memory.c
index 603f7bb..4dbc652 100644
--- a/sim/frv/memory.c
+++ b/sim/frv/memory.c
@@ -1,6 +1,6 @@
/* frv memory model.
- Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
- Contributed by Red Hat.
+ Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
+ Contributed by Red Hat
This file is part of the GNU simulators.
@@ -56,6 +56,17 @@ fr500_check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
}
static SI
+fr550_check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
+{
+ if ((USI)address >= 0xfe800000 && (USI)address <= 0xfefeffff
+ || (align_mask > 0x3
+ && ((USI)address >= 0xfeff0000 && (USI)address <= 0xfeffffff)))
+ frv_queue_data_access_error_interrupt (current_cpu, address);
+
+ return address;
+}
+
+static SI
check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
{
SIM_DESC sd = CPU_STATE (current_cpu);
@@ -71,6 +82,10 @@ check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
address = fr500_check_data_read_address (current_cpu, address,
align_mask);
break;
+ case bfd_mach_fr550:
+ address = fr550_check_data_read_address (current_cpu, address,
+ align_mask);
+ break;
default:
break;
}
@@ -109,6 +124,25 @@ fr500_check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
}
static SI
+fr550_check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
+{
+ /* No alignment restrictions on fr550 */
+
+ if ((USI)address >= 0xfe000000 && (USI)address <= 0xfe3fffff
+ || (USI)address >= 0xfe408000 && (USI)address <= 0xfe7fffff)
+ frv_queue_data_access_exception_interrupt (current_cpu);
+ else
+ {
+ USI hsr0 = GET_HSR0 ();
+ if (! GET_HSR0_RME (hsr0)
+ && (USI)address >= 0xfe400000 && (USI)address <= 0xfe407fff)
+ frv_queue_data_access_exception_interrupt (current_cpu);
+ }
+
+ return address;
+}
+
+static SI
check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
{
SIM_DESC sd = CPU_STATE (current_cpu);
@@ -124,6 +158,10 @@ check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
address = fr500_check_readwrite_address (current_cpu, address,
align_mask);
break;
+ case bfd_mach_fr550:
+ address = fr550_check_readwrite_address (current_cpu, address,
+ align_mask);
+ break;
default:
break;
}
@@ -175,6 +213,27 @@ fr500_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address,
}
static PCADDR
+fr550_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address,
+ int align_mask)
+{
+ address &= ~align_mask;
+
+ if ((USI)address >= 0xfe800000 && (USI)address <= 0xfeffffff)
+ frv_queue_instruction_access_error_interrupt (current_cpu);
+ else if ((USI)address >= 0xfe008000 && (USI)address <= 0xfe7fffff)
+ frv_queue_instruction_access_exception_interrupt (current_cpu);
+ else
+ {
+ USI hsr0 = GET_HSR0 ();
+ if (! GET_HSR0_RME (hsr0)
+ && (USI)address >= 0xfe000000 && (USI)address <= 0xfe007fff)
+ frv_queue_instruction_access_exception_interrupt (current_cpu);
+ }
+
+ return address;
+}
+
+static PCADDR
check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, int align_mask)
{
SIM_DESC sd = CPU_STATE (current_cpu);
@@ -190,6 +249,10 @@ check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, int align_mask)
address = fr500_check_insn_read_address (current_cpu, address,
align_mask);
break;
+ case bfd_mach_fr550:
+ address = fr550_check_insn_read_address (current_cpu, address,
+ align_mask);
+ break;
default:
break;
}
@@ -262,6 +325,16 @@ frvbf_read_mem_UQI (SIM_CPU *current_cpu, IADDR pc, SI address)
return GETMEMUQI (current_cpu, pc, address);
}
+/* Read a HI which spans two cache lines */
+static HI
+read_mem_unaligned_HI (SIM_CPU *current_cpu, IADDR pc, SI address)
+{
+ HI value = frvbf_read_mem_QI (current_cpu, pc, address);
+ value <<= 8;
+ value |= frvbf_read_mem_UQI (current_cpu, pc, address + 1);
+ return T2H_2 (value);
+}
+
HI
frvbf_read_mem_HI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
@@ -288,6 +361,13 @@ frvbf_read_mem_HI (SIM_CPU *current_cpu, IADDR pc, SI address)
if (GET_HSR0_DCE (hsr0))
{
int cycles;
+ /* Handle access which crosses cache line boundary */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ if (DATA_CROSSES_CACHE_LINE (cache, address, 2))
+ return read_mem_unaligned_HI (current_cpu, pc, address);
+ }
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, HI, 2);
@@ -322,6 +402,13 @@ frvbf_read_mem_UHI (SIM_CPU *current_cpu, IADDR pc, SI address)
if (GET_HSR0_DCE (hsr0))
{
int cycles;
+ /* Handle access which crosses cache line boundary */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ if (DATA_CROSSES_CACHE_LINE (cache, address, 2))
+ return read_mem_unaligned_HI (current_cpu, pc, address);
+ }
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, UHI, 2);
@@ -330,6 +417,44 @@ frvbf_read_mem_UHI (SIM_CPU *current_cpu, IADDR pc, SI address)
return GETMEMUHI (current_cpu, pc, address);
}
+/* Read a SI which spans two cache lines */
+static SI
+read_mem_unaligned_SI (SIM_CPU *current_cpu, IADDR pc, SI address)
+{
+ FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+ unsigned hi_len = cache->line_size - (address & (cache->line_size - 1));
+ char valarray[4];
+ SI SIvalue;
+ HI HIvalue;
+
+ switch (hi_len)
+ {
+ case 1:
+ valarray[0] = frvbf_read_mem_QI (current_cpu, pc, address);
+ SIvalue = frvbf_read_mem_SI (current_cpu, pc, address + 1);
+ SIvalue = H2T_4 (SIvalue);
+ memcpy (valarray + 1, (char*)&SIvalue, 3);
+ break;
+ case 2:
+ HIvalue = frvbf_read_mem_HI (current_cpu, pc, address);
+ HIvalue = H2T_2 (HIvalue);
+ memcpy (valarray, (char*)&HIvalue, 2);
+ HIvalue = frvbf_read_mem_HI (current_cpu, pc, address + 2);
+ HIvalue = H2T_2 (HIvalue);
+ memcpy (valarray + 2, (char*)&HIvalue, 2);
+ break;
+ case 3:
+ SIvalue = frvbf_read_mem_SI (current_cpu, pc, address - 1);
+ SIvalue = H2T_4 (SIvalue);
+ memcpy (valarray, (char*)&SIvalue, 3);
+ valarray[3] = frvbf_read_mem_QI (current_cpu, pc, address + 3);
+ break;
+ default:
+ abort (); /* can't happen */
+ }
+ return T2H_4 (*(SI*)valarray);
+}
+
SI
frvbf_read_mem_SI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
@@ -355,6 +480,13 @@ frvbf_read_mem_SI (SIM_CPU *current_cpu, IADDR pc, SI address)
if (GET_HSR0_DCE (hsr0))
{
int cycles;
+ /* Handle access which crosses cache line boundary */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ if (DATA_CROSSES_CACHE_LINE (cache, address, 4))
+ return read_mem_unaligned_SI (current_cpu, pc, address);
+ }
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, SI, 4);
@@ -369,6 +501,79 @@ frvbf_read_mem_WI (SIM_CPU *current_cpu, IADDR pc, SI address)
return frvbf_read_mem_SI (current_cpu, pc, address);
}
+/* Read a SI which spans two cache lines */
+static DI
+read_mem_unaligned_DI (SIM_CPU *current_cpu, IADDR pc, SI address)
+{
+ FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+ unsigned hi_len = cache->line_size - (address & (cache->line_size - 1));
+ DI value, value1;
+
+ switch (hi_len)
+ {
+ case 1:
+ value = frvbf_read_mem_QI (current_cpu, pc, address);
+ value <<= 56;
+ value1 = frvbf_read_mem_DI (current_cpu, pc, address + 1);
+ value1 = H2T_8 (value1);
+ value |= value1 & ((DI)0x00ffffff << 32);
+ value |= value1 & 0xffffffffu;
+ break;
+ case 2:
+ value = frvbf_read_mem_HI (current_cpu, pc, address);
+ value = H2T_2 (value);
+ value <<= 48;
+ value1 = frvbf_read_mem_DI (current_cpu, pc, address + 2);
+ value1 = H2T_8 (value1);
+ value |= value1 & ((DI)0x0000ffff << 32);
+ value |= value1 & 0xffffffffu;
+ break;
+ case 3:
+ value = frvbf_read_mem_SI (current_cpu, pc, address - 1);
+ value = H2T_4 (value);
+ value <<= 40;
+ value1 = frvbf_read_mem_DI (current_cpu, pc, address + 3);
+ value1 = H2T_8 (value1);
+ value |= value1 & ((DI)0x000000ff << 32);
+ value |= value1 & 0xffffffffu;
+ break;
+ case 4:
+ value = frvbf_read_mem_SI (current_cpu, pc, address);
+ value = H2T_4 (value);
+ value <<= 32;
+ value1 = frvbf_read_mem_SI (current_cpu, pc, address + 4);
+ value1 = H2T_4 (value1);
+ value |= value1 & 0xffffffffu;
+ break;
+ case 5:
+ value = frvbf_read_mem_DI (current_cpu, pc, address - 3);
+ value = H2T_8 (value);
+ value <<= 24;
+ value1 = frvbf_read_mem_SI (current_cpu, pc, address + 5);
+ value1 = H2T_4 (value1);
+ value |= value1 & 0x00ffffff;
+ break;
+ case 6:
+ value = frvbf_read_mem_DI (current_cpu, pc, address - 2);
+ value = H2T_8 (value);
+ value <<= 16;
+ value1 = frvbf_read_mem_HI (current_cpu, pc, address + 6);
+ value1 = H2T_2 (value1);
+ value |= value1 & 0x0000ffff;
+ break;
+ case 7:
+ value = frvbf_read_mem_DI (current_cpu, pc, address - 1);
+ value = H2T_8 (value);
+ value <<= 8;
+ value1 = frvbf_read_mem_QI (current_cpu, pc, address + 7);
+ value |= value1 & 0x000000ff;
+ break;
+ default:
+ abort (); /* can't happen */
+ }
+ return T2H_8 (value);
+}
+
DI
frvbf_read_mem_DI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
@@ -394,6 +599,13 @@ frvbf_read_mem_DI (SIM_CPU *current_cpu, IADDR pc, SI address)
if (GET_HSR0_DCE (hsr0))
{
int cycles;
+ /* Handle access which crosses cache line boundary */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ if (DATA_CROSSES_CACHE_LINE (cache, address, 8))
+ return read_mem_unaligned_DI (current_cpu, pc, address);
+ }
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, DI, 8);
@@ -427,6 +639,13 @@ frvbf_read_mem_DF (SIM_CPU *current_cpu, IADDR pc, SI address)
if (GET_HSR0_DCE (hsr0))
{
int cycles;
+ /* Handle access which crosses cache line boundary */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ if (DATA_CROSSES_CACHE_LINE (cache, address, 8))
+ return read_mem_unaligned_DI (current_cpu, pc, address);
+ }
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, DF, 8);
@@ -499,6 +718,17 @@ fr500_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
}
static SI
+fr550_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
+{
+ if ((USI)address >= 0xfe800000 && (USI)address <= 0xfefeffff
+ || (align_mask > 0x3
+ && ((USI)address >= 0xfeff0000 && (USI)address <= 0xfeffffff)))
+ frv_queue_program_interrupt (current_cpu, FRV_DATA_STORE_ERROR);
+
+ return address;
+}
+
+static SI
check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
{
SIM_DESC sd = CPU_STATE (current_cpu);
@@ -512,6 +742,9 @@ check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
case bfd_mach_frv:
address = fr500_check_write_address (current_cpu, address, align_mask);
break;
+ case bfd_mach_fr550:
+ address = fr550_check_write_address (current_cpu, address, align_mask);
+ break;
default:
break;
}
@@ -618,6 +851,16 @@ frvbf_mem_set_QI (SIM_CPU *current_cpu, IADDR pc, SI address, QI value)
frv_cache_write (cache, address, (char *)&value, sizeof (value));
}
+/* Write a HI which spans two cache lines */
+static void
+mem_set_unaligned_HI (SIM_CPU *current_cpu, IADDR pc, SI address, HI value)
+{
+ FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+ /* value is already in target byte order */
+ frv_cache_write (cache, address, (char *)&value, 1);
+ frv_cache_write (cache, address + 1, ((char *)&value + 1), 1);
+}
+
void
frvbf_mem_set_HI (SIM_CPU *current_cpu, IADDR pc, SI address, HI value)
{
@@ -638,7 +881,30 @@ frvbf_mem_set_HI (SIM_CPU *current_cpu, IADDR pc, SI address, HI value)
(char *)&value, sizeof (value));
}
else
- frv_cache_write (cache, address, (char *)&value, sizeof (value));
+ {
+ /* Handle access which crosses cache line boundary */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ if (DATA_CROSSES_CACHE_LINE (cache, address, 2))
+ {
+ mem_set_unaligned_HI (current_cpu, pc, address, value);
+ return;
+ }
+ }
+ frv_cache_write (cache, address, (char *)&value, sizeof (value));
+ }
+}
+
+/* Write a SI which spans two cache lines */
+static void
+mem_set_unaligned_SI (SIM_CPU *current_cpu, IADDR pc, SI address, SI value)
+{
+ FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+ unsigned hi_len = cache->line_size - (address & (cache->line_size - 1));
+ /* value is already in target byte order */
+ frv_cache_write (cache, address, (char *)&value, hi_len);
+ frv_cache_write (cache, address + hi_len, (char *)&value + hi_len, 4 - hi_len);
}
void
@@ -661,7 +927,30 @@ frvbf_mem_set_SI (SIM_CPU *current_cpu, IADDR pc, SI address, SI value)
(char *)&value, sizeof (value));
}
else
- frv_cache_write (cache, address, (char *)&value, sizeof (value));
+ {
+ /* Handle access which crosses cache line boundary */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ if (DATA_CROSSES_CACHE_LINE (cache, address, 4))
+ {
+ mem_set_unaligned_SI (current_cpu, pc, address, value);
+ return;
+ }
+ }
+ frv_cache_write (cache, address, (char *)&value, sizeof (value));
+ }
+}
+
+/* Write a DI which spans two cache lines */
+static void
+mem_set_unaligned_DI (SIM_CPU *current_cpu, IADDR pc, SI address, DI value)
+{
+ FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+ unsigned hi_len = cache->line_size - (address & (cache->line_size - 1));
+ /* value is already in target byte order */
+ frv_cache_write (cache, address, (char *)&value, hi_len);
+ frv_cache_write (cache, address + hi_len, (char *)&value + hi_len, 8 - hi_len);
}
void
@@ -684,7 +973,19 @@ frvbf_mem_set_DI (SIM_CPU *current_cpu, IADDR pc, SI address, DI value)
(char *)&value, sizeof (value));
}
else
- frv_cache_write (cache, address, (char *)&value, sizeof (value));
+ {
+ /* Handle access which crosses cache line boundary */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ if (DATA_CROSSES_CACHE_LINE (cache, address, 8))
+ {
+ mem_set_unaligned_DI (current_cpu, pc, address, value);
+ return;
+ }
+ }
+ frv_cache_write (cache, address, (char *)&value, sizeof (value));
+ }
}
void
@@ -707,7 +1008,19 @@ frvbf_mem_set_DF (SIM_CPU *current_cpu, IADDR pc, SI address, DF value)
(char *)&value, sizeof (value));
}
else
- frv_cache_write (cache, address, (char *)&value, sizeof (value));
+ {
+ /* Handle access which crosses cache line boundary */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ if (DATA_CROSSES_CACHE_LINE (cache, address, 8))
+ {
+ mem_set_unaligned_DI (current_cpu, pc, address, value);
+ return;
+ }
+ }
+ frv_cache_write (cache, address, (char *)&value, sizeof (value));
+ }
}
void
diff --git a/sim/frv/mloop.in b/sim/frv/mloop.in
index 2d1726d..073d81d 100644
--- a/sim/frv/mloop.in
+++ b/sim/frv/mloop.in
@@ -1,5 +1,5 @@
# Simulator main loop for frv. -*- C -*-
-# Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+# Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
# Contributed by Red Hat.
#
# This file is part of the GNU Simulators.
@@ -395,6 +395,7 @@ static void
break;
case bfd_mach_frvtomcat:
case bfd_mach_fr500:
+ case bfd_mach_fr550:
case bfd_mach_frv:
simulate_dual_insn_prefetch (current_cpu, vpc, 16);
break;
@@ -454,6 +455,7 @@ cat <<EOF
int first_insn_p = 1;
int last_insn_p = 0;
int ninsns;
+ CGEN_ATTR_VALUE_TYPE slot;
/* If the timer is enabled, then enable model profiling. This is because
the timer needs accurate cycles counts to work properly. */
@@ -465,6 +467,7 @@ cat <<EOF
vliw = CPU_VLIW (current_cpu);
frv_vliw_reset (vliw, STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach,
CPU_ELF_FLAGS (current_cpu));
+ frv_current_fm_slot = UNIT_NIL;
for (ninsns = 0; ! last_insn_p && ninsns < FRV_VLIW_SIZE; ++ninsns)
{
@@ -484,6 +487,9 @@ cat <<EOF
if (! error)
frv_vliw_setup_insn (current_cpu, insn);
frv_detect_insn_access_interrupts (current_cpu, sc);
+ slot = (*vliw->current_vliw)[vliw->next_slot - 1];
+ if (slot >= UNIT_FM0 && slot <= UNIT_FM3)
+ frv_current_fm_slot = slot;
vpc = execute (current_cpu, sc, FAST_P);
diff --git a/sim/frv/model.c b/sim/frv/model.c
index cca2f22..864c180 100644
--- a/sim/frv/model.c
+++ b/sim/frv/model.c
@@ -117,7 +117,7 @@ model_frv_xor (SIM_CPU *current_cpu, void *sem_arg)
static int
model_frv_not (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_addcc.f
+#define FLD(f) abuf->fields.sfmt_scutss.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -227,6 +227,54 @@ model_frv_umul (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_frv_smu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_frv_smass (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_frv_smsss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_frv_sll (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addcc.f
@@ -275,6 +323,38 @@ model_frv_sra (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_frv_slass (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_frv_scutss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_scutss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_frv_scan (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addcc.f
@@ -867,6 +947,38 @@ model_frv_subxcc (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_frv_addss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_frv_subss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_frv_addi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_swapi.f
@@ -11859,6 +11971,16942 @@ model_frv_fnop (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_fr550_add (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_not (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_scutss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nsdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_udiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nudiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_smul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_umul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_smu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_smass (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_smsss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_srl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_slass (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_scutss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_scutss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_scan (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cadd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csmul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cudiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csrl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cscan (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_addcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_subcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_andcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_orcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_xorcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sllcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_srlcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_smulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_umulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_caddcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csubcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csmulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_csmulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_candcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_corcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cxorcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csllcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csrlcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_addx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_subx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_addxcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_subxcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_addss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_subss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_addi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_subi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_andi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_xori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sdivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nsdivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_udivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nudivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_smuli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRdoublek = FLD (out_GRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_umuli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRdoublek = FLD (out_GRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_slli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_srli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_srai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_scani (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_addicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_subicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_andicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_oricc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_xoricc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_smulicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRdoublek = FLD (out_GRdoublek);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_umulicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRdoublek = FLD (out_GRdoublek);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sllicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_srlicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sraicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_addxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_subxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_addxicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_subxicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmpb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmpba (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_setlo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlo.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_GRkhi = -1;
+ INT out_GRklo = -1;
+ out_GRklo = FLD (out_GRklo);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sethi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_sethi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_GRkhi = -1;
+ INT out_GRklo = -1;
+ out_GRkhi = FLD (out_GRkhi);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_setlos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_lduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nlduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_lddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRdoublek = FLD (out_FRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_lddc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nlddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRdoublek = FLD (out_FRdoublek);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldqc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_lduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nlduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_lddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nlddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_lddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRdoublek = FLD (out_FRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_lddcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nlddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRdoublek = FLD (out_FRdoublek);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldqcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldsbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldshi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldubi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_lduhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldhfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldsbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldubi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldshi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nlduhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldhfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_lddi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_lddfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_FRdoublek = FLD (out_FRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nlddi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nlddfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_FRdoublek = FLD (out_FRdoublek);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ldqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nldqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_st (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_rstb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_rsth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_rst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_rstbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_rsthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_rstf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_std (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRdoublek = FLD (in_GRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRdoublek = FLD (in_FRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stdc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_rstd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_rstdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stqc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_rstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_rstqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sthu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sthfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stdu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRdoublek = FLD (in_GRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stdfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRdoublek = FLD (in_FRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stdcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stqcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_clduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_clddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRdoublek = FLD (out_FRdoublek);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_clduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_clddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 7)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_clddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRdoublek = FLD (out_FRdoublek);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cstb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cstbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cstf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cstd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRdoublek = FLD (in_GRdoublek);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cstdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRdoublek = FLD (in_FRdoublek);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cstbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csthu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cstu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cstbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_csthfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cstfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cstdu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRdoublek = FLD (in_GRdoublek);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cstdfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRdoublek = FLD (in_FRdoublek);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sthi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_sthfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stdi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRdoublek = FLD (in_GRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stdfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_FRdoublek = FLD (in_FRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_stqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_swap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_swapi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cswap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_movgf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_movfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintk = -1;
+ INT out_GRj = -1;
+ in_FRintk = FLD (in_FRintk);
+ out_GRj = FLD (out_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_movgfd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_movfgd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintk = -1;
+ INT out_GRj = -1;
+ in_FRintk = FLD (in_FRintk);
+ out_GRj = FLD (out_GRj);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_movgfq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgfq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_movfgq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movfgq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmovgf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmovfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintk = -1;
+ INT out_GRj = -1;
+ in_FRintk = FLD (in_FRintk);
+ out_GRj = FLD (out_GRj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmovgfd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmovfgd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintk = -1;
+ INT out_GRj = -1;
+ in_FRintk = FLD (in_FRintk);
+ out_GRj = FLD (out_GRj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_movgs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRj = -1;
+ INT out_spr = -1;
+ in_GRj = FLD (in_GRj);
+ out_spr = FLD (out_spr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_gr2spr (current_cpu, idesc, 0, referenced, in_GRj, out_spr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_movsg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movsg.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_spr = -1;
+ INT out_GRj = -1;
+ in_spr = FLD (in_spr);
+ out_GRj = FLD (out_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_spr2gr (current_cpu, idesc, 0, referenced, in_spr, out_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_beq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_blt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fblg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fblt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bctrlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_beqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_blelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_blslr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bhilr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bnclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bnlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bplr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bnvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbeqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fblglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbuelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbullr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbugelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbuglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fblelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbulelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbulr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fbolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bcralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bcnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bceqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bcnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bclelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bcgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bcltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bcgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bclslr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bchilr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bcclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bcnclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bcnlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bcplr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bcvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bcnvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcbralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcbnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcbnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcblglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcbuelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcbullr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcbgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcbltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcbugelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcbuglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcblelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcbulelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcbulr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcbolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_jmpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_calll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_jmpil (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ referenced |= 1 << 0;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_callil (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_call (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_call.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_rett (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rett.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_rei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_teq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tlt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_thi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fteq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftlg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftlt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fto (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tira (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tino (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tieq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tine (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tile (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tigt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tilt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tige (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tils (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tihi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tic (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tinc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tin (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tip (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tinv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftira (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftino (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftine (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftieq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftilg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftiue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftiul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftige (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftilt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftiuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftiug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftile (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftigt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftiule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ftio (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_break (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_break.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mtrap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_andcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_orcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_xorcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nandcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_norcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_andncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_orncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nandncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_norncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_notcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ckls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ckhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ckc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cknc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ckn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ckp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ckv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cknv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcklg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fckue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fckul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fckuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fckug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fckule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcku (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcko (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ccklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cckls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cckhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cckc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ccknc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cckn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cckp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cckv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ccknv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfcklg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfckue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfckul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfcklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfckuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfckug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfckule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfcku (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfcko (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cjmpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ccalll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_ici (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_dci (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_icei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_dcei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_dcf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_dcef (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_witlb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_wdtlb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_itlbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_dtlbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_icpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_icpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_dcpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_dcpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_icul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_icul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_dcul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_dcul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_bar (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_membar (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cop1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cop2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_clrgr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRk = -1;
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_clrgr (current_cpu, idesc, 0, referenced, in_GRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_clrfr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRk = -1;
+ in_FRk = FLD (in_FRk);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_clrfr (current_cpu, idesc, 0, referenced, in_FRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_clrga (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRk = -1;
+ cycles += frvbf_model_fr550_u_clrgr (current_cpu, idesc, 0, referenced, in_GRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_clrfa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRk = -1;
+ cycles += frvbf_model_fr550_u_clrfr (current_cpu, idesc, 0, referenced, in_FRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_commitgr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRk = -1;
+ INT in_FRk = -1;
+ cycles += frvbf_model_fr550_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_commitfr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRk = -1;
+ INT in_FRk = -1;
+ cycles += frvbf_model_fr550_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_commitga (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRk = -1;
+ INT in_FRk = -1;
+ cycles += frvbf_model_fr550_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_commitfa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRk = -1;
+ INT in_FRk = -1;
+ cycles += frvbf_model_fr550_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRj = -1;
+ INT in_FRintj = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_FRintj = FLD (in_FRintj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRj = -1;
+ INT in_FRintj = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_FRj = FLD (in_FRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fitod (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fitod.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRj = -1;
+ INT in_FRintj = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_FRintj = FLD (in_FRintj);
+ out_FRdoublek = FLD (out_FRdoublek);
+ referenced |= 1 << 1;
+ referenced |= 1 << 5;
+ cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdtoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdtoi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRj = -1;
+ INT in_FRintj = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_FRdoublej = FLD (in_FRdoublej);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 2;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fditos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfditos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfdstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfitos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRj = -1;
+ INT in_FRintj = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_FRintj = FLD (in_FRintj);
+ out_FRk = FLD (out_FRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfstoi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRj = -1;
+ INT in_FRintj = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_FRj = FLD (in_FRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRj = -1;
+ INT in_FRintj = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_FRintj = FLD (in_FRintj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRj = -1;
+ INT in_FRintj = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_FRj = FLD (in_FRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_convert (current_cpu, idesc, 0, referenced, in_FRj, in_FRintj, in_FRdoublej, out_FRk, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fmovd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT out_FRk = -1;
+ cycles += frvbf_model_fr550_u_fr2fr (current_cpu, idesc, 0, referenced, in_FRi, out_FRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT out_FRk = -1;
+ out_FRk = FLD (out_FRk);
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_fr2fr (current_cpu, idesc, 0, referenced, in_FRi, out_FRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fnegd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRdoublej = FLD (in_FRdoublej);
+ out_FRdoublek = FLD (out_FRdoublek);
+ referenced |= 1 << 3;
+ referenced |= 1 << 5;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fabsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRdoublej = FLD (in_FRdoublej);
+ out_FRdoublek = FLD (out_FRdoublek);
+ referenced |= 1 << 3;
+ referenced |= 1 << 5;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRj = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_float_sqrt (current_cpu, idesc, 0, referenced, in_FRj, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fsqrtd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRj = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_float_sqrt (current_cpu, idesc, 0, referenced, in_FRj, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRj = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_float_sqrt (current_cpu, idesc, 0, referenced, in_FRj, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT out_FRk = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_float_div (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_faddd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fsubd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fmuld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdivd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT out_FRk = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_float_div (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT out_FRk = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_float_div (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FCCi_2 = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FCCi_2 = FLD (out_FCCi_2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fcmpd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcmpd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FCCi_2 = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FCCi_2 = FLD (out_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT out_FCCi_2 = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FCCi_2 = FLD (out_FCCi_2);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_float_dual_compare (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fmaddd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fmsubd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfdmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfdmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfdmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cfmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fmad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fmsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fddivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdsads (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fdmulcs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfdadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfdsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfdmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfddivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfdsads (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRi = -1;
+ INT in_FRj = -1;
+ INT in_FRdoublei = -1;
+ INT in_FRdoublej = -1;
+ INT out_FRk = -1;
+ INT out_FRdoublek = -1;
+ in_FRi = FLD (in_FRi);
+ in_FRj = FLD (in_FRj);
+ out_FRk = FLD (out_FRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr550_u_float_dual_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_nfdcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mhsetlos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetlos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRklo);
+ cycles += frvbf_model_fr550_u_media_set (current_cpu, idesc, 0, referenced, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mhsethis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRkhi);
+ cycles += frvbf_model_fr550_u_media_set (current_cpu, idesc, 0, referenced, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mhdsets (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdsets.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_media_set (current_cpu, idesc, 0, referenced, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mhsetloh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetloh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRklo);
+ cycles += frvbf_model_fr550_u_media_set (current_cpu, idesc, 0, referenced, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mhsethih (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethih.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRkhi);
+ cycles += frvbf_model_fr550_u_media_set (current_cpu, idesc, 0, referenced, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mhdseth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdseth.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_media_set (current_cpu, idesc, 0, referenced, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mrotli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mrotri (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mwcut (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mwcuti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mcut (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintj = -1;
+ INT in_ACC40Si = -1;
+ INT out_FRintk = -1;
+ in_FRintj = FLD (in_FRintj);
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_3_acc (current_cpu, idesc, 0, referenced, in_FRintj, in_ACC40Si, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mcuti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintj = -1;
+ INT in_ACC40Si = -1;
+ INT out_FRintk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_3_acc (current_cpu, idesc, 0, referenced, in_FRintj, in_ACC40Si, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mcutss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintj = -1;
+ INT in_ACC40Si = -1;
+ INT out_FRintk = -1;
+ in_FRintj = FLD (in_FRintj);
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_3_acc (current_cpu, idesc, 0, referenced, in_FRintj, in_ACC40Si, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mcutssi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintj = -1;
+ INT in_ACC40Si = -1;
+ INT out_FRintk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_3_acc (current_cpu, idesc, 0, referenced, in_FRintj, in_ACC40Si, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mdcutssi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdcutssi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT out_FRintkeven = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_3_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_maveh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_msllhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_msrlhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_msrahi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mdrotli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdrotli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_FRintkeven = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mcplhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcplhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mcpli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_msaths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqsaths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_FRintkeven = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 14)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_msathu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mcmpsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mcmpuh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mabshs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mabshs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_maddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_maddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_msubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_msubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_FRintkeven = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 14)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_FRintkeven = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 14)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_FRintkeven = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 14)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_FRintkeven = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 14)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_FRintkeven = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 16)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_FRintkeven = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 16)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_FRintkeven = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 16)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_FRintkeven = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 16)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT out_ACC40Sk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_4_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_msubaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT out_ACC40Sk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_4_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT out_ACC40Sk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_4_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT out_ACC40Sk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_4_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_masaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT out_ACC40Sk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_4_add_sub (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mdasaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT out_ACC40Sk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_4_add_sub_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 15)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 15)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Uk = FLD (out_ACC40Uk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mmrdhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mmrdhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Uk = FLD (out_ACC40Uk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Uk = FLD (out_ACC40Uk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Uk = FLD (out_ACC40Uk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 17)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmqmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 19)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmqmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Uk = FLD (out_ACC40Uk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 19)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqxmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintkeven = -1;
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintkeven = -1;
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 8)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ cycles += frvbf_model_fr550_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mdpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdpackh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintieven = -1;
+ INT in_FRintjeven = -1;
+ INT out_FRintkeven = -1;
+ in_FRintieven = FLD (in_FRintieven);
+ in_FRintjeven = FLD (in_FRintjeven);
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 12)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_quad (current_cpu, idesc, 0, referenced, in_FRintieven, in_FRintjeven, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_munpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_munpackh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintkeven = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintkeven = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 7)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mdunpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdunpackh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mbtoh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintkeven = -1;
+ out_FRintkeven = FLD (out_FRintkeven);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmbtoh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintkeven = -1;
+ out_FRintkeven = FLD (out_FRintkeven);
+ in_FRinti = FLD (in_FRintj);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintkeven);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mhtob (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRintk);
+ in_FRinti = FLD (in_FRintjeven);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmhtob (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRintk);
+ in_FRinti = FLD (in_FRintjeven);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mbtohe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_cmbtohe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mnop (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_media_3_mclracc (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_media_3_mclracc (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mrdacc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintj = -1;
+ INT in_ACC40Si = -1;
+ INT out_FRintk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_3_acc (current_cpu, idesc, 0, referenced, in_FRintj, in_ACC40Si, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mrdaccg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mrdaccg.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintj = -1;
+ INT in_ACC40Si = -1;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRintk);
+ in_ACC40Si = FLD (in_ACCGi);
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_3_acc (current_cpu, idesc, 0, referenced, in_FRintj, in_ACC40Si, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mwtacc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_ACC40Sk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_ACC40Sk = FLD (in_ACC40Sk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_3_wtacc (current_cpu, idesc, 0, referenced, in_FRinti, in_ACC40Sk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mwtaccg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwtaccg.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_ACC40Sk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_ACC40Sk = FLD (in_ACCGk);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr550_u_media_3_wtacc (current_cpu, idesc, 0, referenced, in_FRinti, in_ACC40Sk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mcop1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mcop2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_fnop (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_fr500_add (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addcc.f
@@ -11991,7 +29039,7 @@ model_fr500_xor (SIM_CPU *current_cpu, void *sem_arg)
static int
model_fr500_not (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_addcc.f
+#define FLD(f) abuf->fields.sfmt_scutss.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -12169,6 +29217,54 @@ model_fr500_umul (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_fr500_smu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_smass (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_smsss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_fr500_sll (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addcc.f
@@ -12247,6 +29343,38 @@ model_fr500_sra (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_fr500_slass (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_scutss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_scutss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_fr500_scan (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addcc.f
@@ -13231,6 +30359,38 @@ model_fr500_subxcc (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_fr500_addss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_subss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_fr500_addi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_swapi.f
@@ -28411,19 +45571,15 @@ model_fr500_mcpxrs (SIM_CPU *current_cpu, void *sem_arg)
int UNUSED insn_referenced = abuf->written;
INT in_FRinti = -1;
INT in_FRintj = -1;
- INT in_ACC40Si = -1;
- INT in_ACCGi = -1;
- INT out_FRintk = -1;
INT out_ACC40Sk = -1;
INT out_ACC40Uk = -1;
- INT out_ACCGk = -1;
in_FRinti = FLD (in_FRinti);
in_FRintj = FLD (in_FRintj);
out_ACC40Sk = FLD (out_ACC40Sk);
- referenced |= 1 << 0;
- referenced |= 1 << 1;
- if (insn_referenced & (1 << 8)) referenced |= 1 << 5;
- cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
@@ -28441,19 +45597,15 @@ model_fr500_mcpxru (SIM_CPU *current_cpu, void *sem_arg)
int UNUSED insn_referenced = abuf->written;
INT in_FRinti = -1;
INT in_FRintj = -1;
- INT in_ACC40Si = -1;
- INT in_ACCGi = -1;
- INT out_FRintk = -1;
INT out_ACC40Sk = -1;
INT out_ACC40Uk = -1;
- INT out_ACCGk = -1;
in_FRinti = FLD (in_FRinti);
in_FRintj = FLD (in_FRintj);
out_ACC40Sk = FLD (out_ACC40Sk);
- referenced |= 1 << 0;
- referenced |= 1 << 1;
- if (insn_referenced & (1 << 8)) referenced |= 1 << 5;
- cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
@@ -28476,9 +45628,9 @@ model_fr500_mcpxis (SIM_CPU *current_cpu, void *sem_arg)
in_FRinti = FLD (in_FRinti);
in_FRintj = FLD (in_FRintj);
out_ACC40Sk = FLD (out_ACC40Sk);
- referenced |= 1 << 0;
- referenced |= 1 << 1;
- if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
@@ -28502,9 +45654,9 @@ model_fr500_mcpxiu (SIM_CPU *current_cpu, void *sem_arg)
in_FRinti = FLD (in_FRinti);
in_FRintj = FLD (in_FRintj);
out_ACC40Sk = FLD (out_ACC40Sk);
- referenced |= 1 << 0;
- referenced |= 1 << 1;
- if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
@@ -28523,19 +45675,15 @@ model_fr500_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg)
int UNUSED insn_referenced = abuf->written;
INT in_FRinti = -1;
INT in_FRintj = -1;
- INT in_ACC40Si = -1;
- INT in_ACCGi = -1;
- INT out_FRintk = -1;
INT out_ACC40Sk = -1;
INT out_ACC40Uk = -1;
- INT out_ACCGk = -1;
in_FRinti = FLD (in_FRinti);
in_FRintj = FLD (in_FRintj);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 10)) referenced |= 1 << 5;
- cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
@@ -28553,19 +45701,15 @@ model_fr500_cmcpxru (SIM_CPU *current_cpu, void *sem_arg)
int UNUSED insn_referenced = abuf->written;
INT in_FRinti = -1;
INT in_FRintj = -1;
- INT in_ACC40Si = -1;
- INT in_ACCGi = -1;
- INT out_FRintk = -1;
INT out_ACC40Sk = -1;
INT out_ACC40Uk = -1;
- INT out_ACCGk = -1;
in_FRinti = FLD (in_FRinti);
in_FRintj = FLD (in_FRintj);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 10)) referenced |= 1 << 5;
- cycles += frvbf_model_fr500_u_media (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, in_ACC40Si, in_ACCGi, out_FRintk, out_ACC40Sk, out_ACC40Uk, out_ACCGk);
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
@@ -28590,7 +45734,7 @@ model_fr500_cmcpxis (SIM_CPU *current_cpu, void *sem_arg)
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 10)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
@@ -28616,7 +45760,7 @@ model_fr500_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg)
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 10)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
cycles += frvbf_model_fr500_u_media_dual_mul (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
@@ -29324,7 +46468,7 @@ model_tomcat_xor (SIM_CPU *current_cpu, void *sem_arg)
static int
model_tomcat_not (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_addcc.f
+#define FLD(f) abuf->fields.sfmt_scutss.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -29434,6 +46578,54 @@ model_tomcat_umul (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_tomcat_smu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_smass (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_smsss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_tomcat_sll (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addcc.f
@@ -29482,6 +46674,38 @@ model_tomcat_sra (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_tomcat_slass (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_scutss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_scutss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_tomcat_scan (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addcc.f
@@ -30074,6 +47298,38 @@ model_tomcat_subxcc (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_tomcat_addss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_subss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_tomcat_addi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_swapi.f
@@ -41198,7 +58454,7 @@ model_fr400_xor (SIM_CPU *current_cpu, void *sem_arg)
static int
model_fr400_not (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_addcc.f
+#define FLD(f) abuf->fields.sfmt_scutss.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -41376,6 +58632,78 @@ model_fr400_umul (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_fr400_smu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_smass (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_smsss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_fr400_sll (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addcc.f
@@ -41454,6 +58782,38 @@ model_fr400_sra (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_fr400_slass (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_scutss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_scutss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_fr400_scan (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addcc.f
@@ -42438,6 +59798,58 @@ model_fr400_subxcc (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_fr400_addss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_subss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_fr400_addi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_swapi.f
@@ -55515,7 +72927,7 @@ model_fr400_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
in_ACC40Si = FLD (in_ACC40Si);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
cycles += frvbf_model_fr400_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
}
return cycles;
@@ -55537,7 +72949,7 @@ model_fr400_msubaccs (SIM_CPU *current_cpu, void *sem_arg)
in_ACC40Si = FLD (in_ACC40Si);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
cycles += frvbf_model_fr400_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
}
return cycles;
@@ -56273,9 +73685,9 @@ model_fr400_mcpxrs (SIM_CPU *current_cpu, void *sem_arg)
in_FRinti = FLD (in_FRinti);
in_FRintj = FLD (in_FRintj);
out_ACC40Sk = FLD (out_ACC40Sk);
- referenced |= 1 << 0;
- referenced |= 1 << 1;
- if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
@@ -56299,9 +73711,9 @@ model_fr400_mcpxru (SIM_CPU *current_cpu, void *sem_arg)
in_FRinti = FLD (in_FRinti);
in_FRintj = FLD (in_FRintj);
out_ACC40Sk = FLD (out_ACC40Sk);
- referenced |= 1 << 0;
- referenced |= 1 << 1;
- if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
@@ -56325,9 +73737,9 @@ model_fr400_mcpxis (SIM_CPU *current_cpu, void *sem_arg)
in_FRinti = FLD (in_FRinti);
in_FRintj = FLD (in_FRintj);
out_ACC40Sk = FLD (out_ACC40Sk);
- referenced |= 1 << 0;
- referenced |= 1 << 1;
- if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
@@ -56351,9 +73763,9 @@ model_fr400_mcpxiu (SIM_CPU *current_cpu, void *sem_arg)
in_FRinti = FLD (in_FRinti);
in_FRintj = FLD (in_FRintj);
out_ACC40Sk = FLD (out_ACC40Sk);
- referenced |= 1 << 0;
- referenced |= 1 << 1;
- if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
@@ -56379,7 +73791,7 @@ model_fr400_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg)
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 10)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
@@ -56405,7 +73817,7 @@ model_fr400_cmcpxru (SIM_CPU *current_cpu, void *sem_arg)
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 10)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
@@ -56431,7 +73843,7 @@ model_fr400_cmcpxis (SIM_CPU *current_cpu, void *sem_arg)
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 10)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
@@ -56457,7 +73869,7 @@ model_fr400_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg)
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 10)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
@@ -57107,7 +74519,7 @@ model_simple_xor (SIM_CPU *current_cpu, void *sem_arg)
static int
model_simple_not (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_addcc.f
+#define FLD(f) abuf->fields.sfmt_scutss.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -57217,6 +74629,54 @@ model_simple_umul (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_simple_smu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_simple_smass (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_simple_smsss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_simple_sll (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addcc.f
@@ -57265,6 +74725,38 @@ model_simple_sra (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_simple_slass (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_simple_scutss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_scutss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_simple_scan (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addcc.f
@@ -57857,6 +75349,38 @@ model_simple_subxcc (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_simple_addss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_simple_subss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_simple_addi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_swapi.f
@@ -68872,9 +86396,14 @@ static const INSN_TIMING frv_timing[] = {
{ FRVBF_INSN_NUDIV, model_frv_nudiv, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SMUL, model_frv_smul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_UMUL, model_frv_umul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMU, model_frv_smu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMASS, model_frv_smass, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMSSS, model_frv_smsss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SLL, model_frv_sll, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SRL, model_frv_srl, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SRA, model_frv_sra, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SLASS, model_frv_slass, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SCUTSS, model_frv_scutss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SCAN, model_frv_scan, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CADD, model_frv_cadd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CSUB, model_frv_csub, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
@@ -68912,6 +86441,8 @@ static const INSN_TIMING frv_timing[] = {
{ FRVBF_INSN_SUBX, model_frv_subx, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_ADDXCC, model_frv_addxcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SUBXCC, model_frv_subxcc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ADDSS, model_frv_addss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SUBSS, model_frv_subss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_ADDI, model_frv_addi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SUBI, model_frv_subi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_ANDI, model_frv_andi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
@@ -69601,6 +87132,763 @@ static const INSN_TIMING frv_timing[] = {
{ FRVBF_INSN_FNOP, model_frv_fnop, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
};
+/* Model timing data for `fr550'. */
+
+static const INSN_TIMING fr550_timing[] = {
+ { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ADD, model_fr550_add, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUB, model_fr550_sub, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_AND, model_fr550_and, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_OR, model_fr550_or, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_XOR, model_fr550_xor, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_NOT, model_fr550_not, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SDIV, model_fr550_sdiv, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_NSDIV, model_fr550_nsdiv, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_UDIV, model_fr550_udiv, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_NUDIV, model_fr550_nudiv, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_SMUL, model_fr550_smul, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_UMUL, model_fr550_umul, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_SMU, model_fr550_smu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMASS, model_fr550_smass, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMSSS, model_fr550_smsss, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SLL, model_fr550_sll, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRL, model_fr550_srl, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRA, model_fr550_sra, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SLASS, model_fr550_slass, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SCUTSS, model_fr550_scutss, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SCAN, model_fr550_scan, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CADD, model_fr550_cadd, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSUB, model_fr550_csub, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CAND, model_fr550_cand, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_COR, model_fr550_cor, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CXOR, model_fr550_cxor, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CNOT, model_fr550_cnot, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSMUL, model_fr550_csmul, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_CSDIV, model_fr550_csdiv, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_CUDIV, model_fr550_cudiv, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_CSLL, model_fr550_csll, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSRL, model_fr550_csrl, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSRA, model_fr550_csra, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSCAN, model_fr550_cscan, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDCC, model_fr550_addcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBCC, model_fr550_subcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ANDCC, model_fr550_andcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ORCC, model_fr550_orcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_XORCC, model_fr550_xorcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SLLCC, model_fr550_sllcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRLCC, model_fr550_srlcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRACC, model_fr550_sracc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SMULCC, model_fr550_smulcc, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_UMULCC, model_fr550_umulcc, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_CADDCC, model_fr550_caddcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSUBCC, model_fr550_csubcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSMULCC, model_fr550_csmulcc, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_CANDCC, model_fr550_candcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CORCC, model_fr550_corcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CXORCC, model_fr550_cxorcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSLLCC, model_fr550_csllcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSRLCC, model_fr550_csrlcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSRACC, model_fr550_csracc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDX, model_fr550_addx, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBX, model_fr550_subx, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDXCC, model_fr550_addxcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBXCC, model_fr550_subxcc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDSS, model_fr550_addss, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SUBSS, model_fr550_subss, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ADDI, model_fr550_addi, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBI, model_fr550_subi, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ANDI, model_fr550_andi, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ORI, model_fr550_ori, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_XORI, model_fr550_xori, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SDIVI, model_fr550_sdivi, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_NSDIVI, model_fr550_nsdivi, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_UDIVI, model_fr550_udivi, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_NUDIVI, model_fr550_nudivi, { { (int) UNIT_FR550_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_SMULI, model_fr550_smuli, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_UMULI, model_fr550_umuli, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_SLLI, model_fr550_slli, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRLI, model_fr550_srli, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRAI, model_fr550_srai, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SCANI, model_fr550_scani, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDICC, model_fr550_addicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBICC, model_fr550_subicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ANDICC, model_fr550_andicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ORICC, model_fr550_oricc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_XORICC, model_fr550_xoricc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SMULICC, model_fr550_smulicc, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_UMULICC, model_fr550_umulicc, { { (int) UNIT_FR550_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_SLLICC, model_fr550_sllicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRLICC, model_fr550_srlicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRAICC, model_fr550_sraicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDXI, model_fr550_addxi, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBXI, model_fr550_subxi, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDXICC, model_fr550_addxicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBXICC, model_fr550_subxicc, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CMPB, model_fr550_cmpb, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CMPBA, model_fr550_cmpba, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SETLO, model_fr550_setlo, { { (int) UNIT_FR550_U_SET_HILO, 1, 1 } } },
+ { FRVBF_INSN_SETHI, model_fr550_sethi, { { (int) UNIT_FR550_U_SET_HILO, 1, 1 } } },
+ { FRVBF_INSN_SETLOS, model_fr550_setlos, { { (int) UNIT_FR550_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_LDSB, model_fr550_ldsb, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDUB, model_fr550_ldub, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDSH, model_fr550_ldsh, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDUH, model_fr550_lduh, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LD, model_fr550_ld, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDBF, model_fr550_ldbf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDHF, model_fr550_ldhf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDF, model_fr550_ldf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDC, model_fr550_ldc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDSB, model_fr550_nldsb, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDUB, model_fr550_nldub, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDSH, model_fr550_nldsh, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDUH, model_fr550_nlduh, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLD, model_fr550_nld, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDBF, model_fr550_nldbf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDHF, model_fr550_nldhf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDF, model_fr550_nldf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDD, model_fr550_ldd, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDDF, model_fr550_lddf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDDC, model_fr550_lddc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDD, model_fr550_nldd, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDDF, model_fr550_nlddf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDQ, model_fr550_ldq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDQF, model_fr550_ldqf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDQC, model_fr550_ldqc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDQ, model_fr550_nldq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDQF, model_fr550_nldqf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDSBU, model_fr550_ldsbu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDUBU, model_fr550_ldubu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDSHU, model_fr550_ldshu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDUHU, model_fr550_lduhu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDU, model_fr550_ldu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDSBU, model_fr550_nldsbu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDUBU, model_fr550_nldubu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDSHU, model_fr550_nldshu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDUHU, model_fr550_nlduhu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDU, model_fr550_nldu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDBFU, model_fr550_ldbfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDHFU, model_fr550_ldhfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDFU, model_fr550_ldfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDCU, model_fr550_ldcu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDBFU, model_fr550_nldbfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDHFU, model_fr550_nldhfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDFU, model_fr550_nldfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDDU, model_fr550_lddu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDDU, model_fr550_nlddu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDDFU, model_fr550_lddfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDDCU, model_fr550_lddcu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDDFU, model_fr550_nlddfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDQU, model_fr550_ldqu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDQU, model_fr550_nldqu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDQFU, model_fr550_ldqfu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDQCU, model_fr550_ldqcu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDQFU, model_fr550_nldqfu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDSBI, model_fr550_ldsbi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDSHI, model_fr550_ldshi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDI, model_fr550_ldi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDUBI, model_fr550_ldubi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDUHI, model_fr550_lduhi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDBFI, model_fr550_ldbfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDHFI, model_fr550_ldhfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDFI, model_fr550_ldfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDSBI, model_fr550_nldsbi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDUBI, model_fr550_nldubi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDSHI, model_fr550_nldshi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDUHI, model_fr550_nlduhi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDI, model_fr550_nldi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDBFI, model_fr550_nldbfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDHFI, model_fr550_nldhfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDFI, model_fr550_nldfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDDI, model_fr550_lddi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDDFI, model_fr550_lddfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDDI, model_fr550_nlddi, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDDFI, model_fr550_nlddfi, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDQI, model_fr550_ldqi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDQFI, model_fr550_ldqfi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDQFI, model_fr550_nldqfi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STB, model_fr550_stb, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STH, model_fr550_sth, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_ST, model_fr550_st, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STBF, model_fr550_stbf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STHF, model_fr550_sthf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STF, model_fr550_stf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STC, model_fr550_stc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_RSTB, model_fr550_rstb, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_RSTH, model_fr550_rsth, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_RST, model_fr550_rst, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_RSTBF, model_fr550_rstbf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_RSTHF, model_fr550_rsthf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_RSTF, model_fr550_rstf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STD, model_fr550_std, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STDF, model_fr550_stdf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STDC, model_fr550_stdc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_RSTD, model_fr550_rstd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_RSTDF, model_fr550_rstdf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STQ, model_fr550_stq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STQF, model_fr550_stqf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STQC, model_fr550_stqc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_RSTQ, model_fr550_rstq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_RSTQF, model_fr550_rstqf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STBU, model_fr550_stbu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STHU, model_fr550_sthu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STU, model_fr550_stu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STBFU, model_fr550_stbfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STHFU, model_fr550_sthfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STFU, model_fr550_stfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STCU, model_fr550_stcu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STDU, model_fr550_stdu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STDFU, model_fr550_stdfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STDCU, model_fr550_stdcu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STQU, model_fr550_stqu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STQFU, model_fr550_stqfu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STQCU, model_fr550_stqcu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CLDSB, model_fr550_cldsb, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDUB, model_fr550_cldub, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDSH, model_fr550_cldsh, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDUH, model_fr550_clduh, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLD, model_fr550_cld, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDBF, model_fr550_cldbf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDHF, model_fr550_cldhf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDF, model_fr550_cldf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDD, model_fr550_cldd, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDDF, model_fr550_clddf, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDQ, model_fr550_cldq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CLDSBU, model_fr550_cldsbu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDUBU, model_fr550_cldubu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDSHU, model_fr550_cldshu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDUHU, model_fr550_clduhu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDU, model_fr550_cldu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDBFU, model_fr550_cldbfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDHFU, model_fr550_cldhfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDFU, model_fr550_cldfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDDU, model_fr550_clddu, { { (int) UNIT_FR550_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDDFU, model_fr550_clddfu, { { (int) UNIT_FR550_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDQU, model_fr550_cldqu, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CSTB, model_fr550_cstb, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTH, model_fr550_csth, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CST, model_fr550_cst, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTBF, model_fr550_cstbf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTHF, model_fr550_csthf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTF, model_fr550_cstf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTD, model_fr550_cstd, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTDF, model_fr550_cstdf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTQ, model_fr550_cstq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CSTBU, model_fr550_cstbu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTHU, model_fr550_csthu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTU, model_fr550_cstu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTBFU, model_fr550_cstbfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTHFU, model_fr550_csthfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTFU, model_fr550_cstfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTDU, model_fr550_cstdu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTDFU, model_fr550_cstdfu, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STBI, model_fr550_stbi, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STHI, model_fr550_sthi, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STI, model_fr550_sti, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STBFI, model_fr550_stbfi, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STHFI, model_fr550_sthfi, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STFI, model_fr550_stfi, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STDI, model_fr550_stdi, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STDFI, model_fr550_stdfi, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STQI, model_fr550_stqi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STQFI, model_fr550_stqfi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SWAP, model_fr550_swap, { { (int) UNIT_FR550_U_SWAP, 1, 1 } } },
+ { FRVBF_INSN_SWAPI, model_fr550_swapi, { { (int) UNIT_FR550_U_SWAP, 1, 1 } } },
+ { FRVBF_INSN_CSWAP, model_fr550_cswap, { { (int) UNIT_FR550_U_SWAP, 1, 1 } } },
+ { FRVBF_INSN_MOVGF, model_fr550_movgf, { { (int) UNIT_FR550_U_GR2FR, 1, 1 } } },
+ { FRVBF_INSN_MOVFG, model_fr550_movfg, { { (int) UNIT_FR550_U_FR2GR, 1, 1 } } },
+ { FRVBF_INSN_MOVGFD, model_fr550_movgfd, { { (int) UNIT_FR550_U_GR2FR, 1, 1 } } },
+ { FRVBF_INSN_MOVFGD, model_fr550_movfgd, { { (int) UNIT_FR550_U_FR2GR, 1, 1 } } },
+ { FRVBF_INSN_MOVGFQ, model_fr550_movgfq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MOVFGQ, model_fr550_movfgq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CMOVGF, model_fr550_cmovgf, { { (int) UNIT_FR550_U_GR2FR, 1, 1 } } },
+ { FRVBF_INSN_CMOVFG, model_fr550_cmovfg, { { (int) UNIT_FR550_U_FR2GR, 1, 1 } } },
+ { FRVBF_INSN_CMOVGFD, model_fr550_cmovgfd, { { (int) UNIT_FR550_U_GR2FR, 1, 1 } } },
+ { FRVBF_INSN_CMOVFGD, model_fr550_cmovfgd, { { (int) UNIT_FR550_U_FR2GR, 1, 1 } } },
+ { FRVBF_INSN_MOVGS, model_fr550_movgs, { { (int) UNIT_FR550_U_GR2SPR, 1, 1 } } },
+ { FRVBF_INSN_MOVSG, model_fr550_movsg, { { (int) UNIT_FR550_U_SPR2GR, 1, 1 } } },
+ { FRVBF_INSN_BRA, model_fr550_bra, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNO, model_fr550_bno, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BEQ, model_fr550_beq, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNE, model_fr550_bne, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BLE, model_fr550_ble, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BGT, model_fr550_bgt, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BLT, model_fr550_blt, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BGE, model_fr550_bge, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BLS, model_fr550_bls, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BHI, model_fr550_bhi, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BC, model_fr550_bc, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNC, model_fr550_bnc, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BN, model_fr550_bn, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BP, model_fr550_bp, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BV, model_fr550_bv, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNV, model_fr550_bnv, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBRA, model_fr550_fbra, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBNO, model_fr550_fbno, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBNE, model_fr550_fbne, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBEQ, model_fr550_fbeq, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBLG, model_fr550_fblg, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBUE, model_fr550_fbue, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBUL, model_fr550_fbul, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBGE, model_fr550_fbge, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBLT, model_fr550_fblt, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBUGE, model_fr550_fbuge, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBUG, model_fr550_fbug, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBLE, model_fr550_fble, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBGT, model_fr550_fbgt, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBULE, model_fr550_fbule, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBU, model_fr550_fbu, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBO, model_fr550_fbo, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCTRLR, model_fr550_bctrlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BRALR, model_fr550_bralr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNOLR, model_fr550_bnolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BEQLR, model_fr550_beqlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNELR, model_fr550_bnelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BLELR, model_fr550_blelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BGTLR, model_fr550_bgtlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BLTLR, model_fr550_bltlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BGELR, model_fr550_bgelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BLSLR, model_fr550_blslr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BHILR, model_fr550_bhilr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCLR, model_fr550_bclr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNCLR, model_fr550_bnclr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNLR, model_fr550_bnlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BPLR, model_fr550_bplr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BVLR, model_fr550_bvlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNVLR, model_fr550_bnvlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBRALR, model_fr550_fbralr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBNOLR, model_fr550_fbnolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBEQLR, model_fr550_fbeqlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBNELR, model_fr550_fbnelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBLGLR, model_fr550_fblglr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBUELR, model_fr550_fbuelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBULLR, model_fr550_fbullr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBGELR, model_fr550_fbgelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBLTLR, model_fr550_fbltlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBUGELR, model_fr550_fbugelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBUGLR, model_fr550_fbuglr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBLELR, model_fr550_fblelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBGTLR, model_fr550_fbgtlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBULELR, model_fr550_fbulelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBULR, model_fr550_fbulr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBOLR, model_fr550_fbolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCRALR, model_fr550_bcralr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCNOLR, model_fr550_bcnolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCEQLR, model_fr550_bceqlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCNELR, model_fr550_bcnelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCLELR, model_fr550_bclelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCGTLR, model_fr550_bcgtlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCLTLR, model_fr550_bcltlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCGELR, model_fr550_bcgelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCLSLR, model_fr550_bclslr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCHILR, model_fr550_bchilr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCCLR, model_fr550_bcclr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCNCLR, model_fr550_bcnclr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCNLR, model_fr550_bcnlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCPLR, model_fr550_bcplr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCVLR, model_fr550_bcvlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCNVLR, model_fr550_bcnvlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBRALR, model_fr550_fcbralr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBNOLR, model_fr550_fcbnolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBEQLR, model_fr550_fcbeqlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBNELR, model_fr550_fcbnelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBLGLR, model_fr550_fcblglr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBUELR, model_fr550_fcbuelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBULLR, model_fr550_fcbullr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBGELR, model_fr550_fcbgelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBLTLR, model_fr550_fcbltlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBUGELR, model_fr550_fcbugelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBUGLR, model_fr550_fcbuglr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBLELR, model_fr550_fcblelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBGTLR, model_fr550_fcbgtlr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBULELR, model_fr550_fcbulelr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBULR, model_fr550_fcbulr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBOLR, model_fr550_fcbolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_JMPL, model_fr550_jmpl, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_CALLL, model_fr550_calll, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_JMPIL, model_fr550_jmpil, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_CALLIL, model_fr550_callil, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CALL, model_fr550_call, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_RETT, model_fr550_rett, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_REI, model_fr550_rei, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_TRA, model_fr550_tra, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TNO, model_fr550_tno, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TEQ, model_fr550_teq, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TNE, model_fr550_tne, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TLE, model_fr550_tle, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TGT, model_fr550_tgt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TLT, model_fr550_tlt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TGE, model_fr550_tge, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TLS, model_fr550_tls, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_THI, model_fr550_thi, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TC, model_fr550_tc, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TNC, model_fr550_tnc, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TN, model_fr550_tn, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TP, model_fr550_tp, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TV, model_fr550_tv, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TNV, model_fr550_tnv, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTRA, model_fr550_ftra, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTNO, model_fr550_ftno, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTNE, model_fr550_ftne, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTEQ, model_fr550_fteq, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTLG, model_fr550_ftlg, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTUE, model_fr550_ftue, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTUL, model_fr550_ftul, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTGE, model_fr550_ftge, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTLT, model_fr550_ftlt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTUGE, model_fr550_ftuge, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTUG, model_fr550_ftug, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTLE, model_fr550_ftle, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTGT, model_fr550_ftgt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTULE, model_fr550_ftule, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTU, model_fr550_ftu, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTO, model_fr550_fto, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIRA, model_fr550_tira, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TINO, model_fr550_tino, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIEQ, model_fr550_tieq, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TINE, model_fr550_tine, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TILE, model_fr550_tile, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIGT, model_fr550_tigt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TILT, model_fr550_tilt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIGE, model_fr550_tige, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TILS, model_fr550_tils, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIHI, model_fr550_tihi, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIC, model_fr550_tic, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TINC, model_fr550_tinc, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIN, model_fr550_tin, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIP, model_fr550_tip, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIV, model_fr550_tiv, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TINV, model_fr550_tinv, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIRA, model_fr550_ftira, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTINO, model_fr550_ftino, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTINE, model_fr550_ftine, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIEQ, model_fr550_ftieq, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTILG, model_fr550_ftilg, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIUE, model_fr550_ftiue, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIUL, model_fr550_ftiul, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIGE, model_fr550_ftige, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTILT, model_fr550_ftilt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIUGE, model_fr550_ftiuge, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIUG, model_fr550_ftiug, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTILE, model_fr550_ftile, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIGT, model_fr550_ftigt, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIULE, model_fr550_ftiule, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIU, model_fr550_ftiu, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIO, model_fr550_ftio, { { (int) UNIT_FR550_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_BREAK, model_fr550_break, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MTRAP, model_fr550_mtrap, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ANDCR, model_fr550_andcr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ORCR, model_fr550_orcr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_XORCR, model_fr550_xorcr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NANDCR, model_fr550_nandcr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NORCR, model_fr550_norcr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ANDNCR, model_fr550_andncr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ORNCR, model_fr550_orncr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NANDNCR, model_fr550_nandncr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NORNCR, model_fr550_norncr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NOTCR, model_fr550_notcr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CKRA, model_fr550_ckra, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKNO, model_fr550_ckno, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKEQ, model_fr550_ckeq, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKNE, model_fr550_ckne, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKLE, model_fr550_ckle, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKGT, model_fr550_ckgt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKLT, model_fr550_cklt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKGE, model_fr550_ckge, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKLS, model_fr550_ckls, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKHI, model_fr550_ckhi, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKC, model_fr550_ckc, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKNC, model_fr550_cknc, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKN, model_fr550_ckn, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKP, model_fr550_ckp, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKV, model_fr550_ckv, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKNV, model_fr550_cknv, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKRA, model_fr550_fckra, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKNO, model_fr550_fckno, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKNE, model_fr550_fckne, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKEQ, model_fr550_fckeq, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKLG, model_fr550_fcklg, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKUE, model_fr550_fckue, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKUL, model_fr550_fckul, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKGE, model_fr550_fckge, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKLT, model_fr550_fcklt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKUGE, model_fr550_fckuge, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKUG, model_fr550_fckug, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKLE, model_fr550_fckle, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKGT, model_fr550_fckgt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKULE, model_fr550_fckule, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKU, model_fr550_fcku, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKO, model_fr550_fcko, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKRA, model_fr550_cckra, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKNO, model_fr550_cckno, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKEQ, model_fr550_cckeq, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKNE, model_fr550_cckne, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKLE, model_fr550_cckle, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKGT, model_fr550_cckgt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKLT, model_fr550_ccklt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKGE, model_fr550_cckge, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKLS, model_fr550_cckls, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKHI, model_fr550_cckhi, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKC, model_fr550_cckc, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKNC, model_fr550_ccknc, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKN, model_fr550_cckn, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKP, model_fr550_cckp, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKV, model_fr550_cckv, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKNV, model_fr550_ccknv, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKRA, model_fr550_cfckra, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKNO, model_fr550_cfckno, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKNE, model_fr550_cfckne, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKEQ, model_fr550_cfckeq, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKLG, model_fr550_cfcklg, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKUE, model_fr550_cfckue, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKUL, model_fr550_cfckul, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKGE, model_fr550_cfckge, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKLT, model_fr550_cfcklt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKUGE, model_fr550_cfckuge, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKUG, model_fr550_cfckug, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKLE, model_fr550_cfckle, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKGT, model_fr550_cfckgt, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKULE, model_fr550_cfckule, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKU, model_fr550_cfcku, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKO, model_fr550_cfcko, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CJMPL, model_fr550_cjmpl, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_CCALLL, model_fr550_ccalll, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ICI, model_fr550_ici, { { (int) UNIT_FR550_U_ICI, 1, 1 } } },
+ { FRVBF_INSN_DCI, model_fr550_dci, { { (int) UNIT_FR550_U_DCI, 1, 1 } } },
+ { FRVBF_INSN_ICEI, model_fr550_icei, { { (int) UNIT_FR550_U_ICI, 1, 1 } } },
+ { FRVBF_INSN_DCEI, model_fr550_dcei, { { (int) UNIT_FR550_U_DCI, 1, 1 } } },
+ { FRVBF_INSN_DCF, model_fr550_dcf, { { (int) UNIT_FR550_U_DCF, 1, 1 } } },
+ { FRVBF_INSN_DCEF, model_fr550_dcef, { { (int) UNIT_FR550_U_DCF, 1, 1 } } },
+ { FRVBF_INSN_WITLB, model_fr550_witlb, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_WDTLB, model_fr550_wdtlb, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ITLBI, model_fr550_itlbi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_DTLBI, model_fr550_dtlbi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ICPL, model_fr550_icpl, { { (int) UNIT_FR550_U_ICPL, 1, 1 } } },
+ { FRVBF_INSN_DCPL, model_fr550_dcpl, { { (int) UNIT_FR550_U_DCPL, 1, 1 } } },
+ { FRVBF_INSN_ICUL, model_fr550_icul, { { (int) UNIT_FR550_U_ICUL, 1, 1 } } },
+ { FRVBF_INSN_DCUL, model_fr550_dcul, { { (int) UNIT_FR550_U_DCUL, 1, 1 } } },
+ { FRVBF_INSN_BAR, model_fr550_bar, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MEMBAR, model_fr550_membar, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_COP1, model_fr550_cop1, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_COP2, model_fr550_cop2, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CLRGR, model_fr550_clrgr, { { (int) UNIT_FR550_U_CLRGR, 1, 1 } } },
+ { FRVBF_INSN_CLRFR, model_fr550_clrfr, { { (int) UNIT_FR550_U_CLRFR, 1, 1 } } },
+ { FRVBF_INSN_CLRGA, model_fr550_clrga, { { (int) UNIT_FR550_U_CLRGR, 1, 1 } } },
+ { FRVBF_INSN_CLRFA, model_fr550_clrfa, { { (int) UNIT_FR550_U_CLRFR, 1, 1 } } },
+ { FRVBF_INSN_COMMITGR, model_fr550_commitgr, { { (int) UNIT_FR550_U_COMMIT, 1, 1 } } },
+ { FRVBF_INSN_COMMITFR, model_fr550_commitfr, { { (int) UNIT_FR550_U_COMMIT, 1, 1 } } },
+ { FRVBF_INSN_COMMITGA, model_fr550_commitga, { { (int) UNIT_FR550_U_COMMIT, 1, 1 } } },
+ { FRVBF_INSN_COMMITFA, model_fr550_commitfa, { { (int) UNIT_FR550_U_COMMIT, 1, 1 } } },
+ { FRVBF_INSN_FITOS, model_fr550_fitos, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } },
+ { FRVBF_INSN_FSTOI, model_fr550_fstoi, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } },
+ { FRVBF_INSN_FITOD, model_fr550_fitod, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } },
+ { FRVBF_INSN_FDTOI, model_fr550_fdtoi, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } },
+ { FRVBF_INSN_FDITOS, model_fr550_fditos, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDSTOI, model_fr550_fdstoi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDITOS, model_fr550_nfditos, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDSTOI, model_fr550_nfdstoi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFITOS, model_fr550_cfitos, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } },
+ { FRVBF_INSN_CFSTOI, model_fr550_cfstoi, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } },
+ { FRVBF_INSN_NFITOS, model_fr550_nfitos, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } },
+ { FRVBF_INSN_NFSTOI, model_fr550_nfstoi, { { (int) UNIT_FR550_U_FLOAT_CONVERT, 1, 1 } } },
+ { FRVBF_INSN_FMOVS, model_fr550_fmovs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMOVD, model_fr550_fmovd, { { (int) UNIT_FR550_U_FR2FR, 1, 1 } } },
+ { FRVBF_INSN_FDMOVS, model_fr550_fdmovs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFMOVS, model_fr550_cfmovs, { { (int) UNIT_FR550_U_FR2FR, 1, 1 } } },
+ { FRVBF_INSN_FNEGS, model_fr550_fnegs, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_FNEGD, model_fr550_fnegd, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_FDNEGS, model_fr550_fdnegs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFNEGS, model_fr550_cfnegs, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_FABSS, model_fr550_fabss, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_FABSD, model_fr550_fabsd, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_FDABSS, model_fr550_fdabss, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFABSS, model_fr550_cfabss, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_FSQRTS, model_fr550_fsqrts, { { (int) UNIT_FR550_U_FLOAT_SQRT, 1, 1 } } },
+ { FRVBF_INSN_FDSQRTS, model_fr550_fdsqrts, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDSQRTS, model_fr550_nfdsqrts, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FSQRTD, model_fr550_fsqrtd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFSQRTS, model_fr550_cfsqrts, { { (int) UNIT_FR550_U_FLOAT_SQRT, 1, 1 } } },
+ { FRVBF_INSN_NFSQRTS, model_fr550_nfsqrts, { { (int) UNIT_FR550_U_FLOAT_SQRT, 1, 1 } } },
+ { FRVBF_INSN_FADDS, model_fr550_fadds, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_FSUBS, model_fr550_fsubs, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_FMULS, model_fr550_fmuls, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_FDIVS, model_fr550_fdivs, { { (int) UNIT_FR550_U_FLOAT_DIV, 1, 1 } } },
+ { FRVBF_INSN_FADDD, model_fr550_faddd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FSUBD, model_fr550_fsubd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMULD, model_fr550_fmuld, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDIVD, model_fr550_fdivd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFADDS, model_fr550_cfadds, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_CFSUBS, model_fr550_cfsubs, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_CFMULS, model_fr550_cfmuls, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_CFDIVS, model_fr550_cfdivs, { { (int) UNIT_FR550_U_FLOAT_DIV, 1, 1 } } },
+ { FRVBF_INSN_NFADDS, model_fr550_nfadds, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_NFSUBS, model_fr550_nfsubs, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_NFMULS, model_fr550_nfmuls, { { (int) UNIT_FR550_U_FLOAT_ARITH, 1, 1 } } },
+ { FRVBF_INSN_NFDIVS, model_fr550_nfdivs, { { (int) UNIT_FR550_U_FLOAT_DIV, 1, 1 } } },
+ { FRVBF_INSN_FCMPS, model_fr550_fcmps, { { (int) UNIT_FR550_U_FLOAT_COMPARE, 1, 1 } } },
+ { FRVBF_INSN_FCMPD, model_fr550_fcmpd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFCMPS, model_fr550_cfcmps, { { (int) UNIT_FR550_U_FLOAT_COMPARE, 1, 1 } } },
+ { FRVBF_INSN_FDCMPS, model_fr550_fdcmps, { { (int) UNIT_FR550_U_FLOAT_DUAL_COMPARE, 1, 3 } } },
+ { FRVBF_INSN_FMADDS, model_fr550_fmadds, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMSUBS, model_fr550_fmsubs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMADDD, model_fr550_fmaddd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMSUBD, model_fr550_fmsubd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDMADDS, model_fr550_fdmadds, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDMADDS, model_fr550_nfdmadds, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFMADDS, model_fr550_cfmadds, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFMSUBS, model_fr550_cfmsubs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFMADDS, model_fr550_nfmadds, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFMSUBS, model_fr550_nfmsubs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMAS, model_fr550_fmas, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_FMSS, model_fr550_fmss, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_FDMAS, model_fr550_fdmas, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDMSS, model_fr550_fdmss, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDMAS, model_fr550_nfdmas, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDMSS, model_fr550_nfdmss, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFMAS, model_fr550_cfmas, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_CFMSS, model_fr550_cfmss, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_FMAD, model_fr550_fmad, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMSD, model_fr550_fmsd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFMAS, model_fr550_nfmas, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_NFMSS, model_fr550_nfmss, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_FDADDS, model_fr550_fdadds, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_FDSUBS, model_fr550_fdsubs, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_FDMULS, model_fr550_fdmuls, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_FDDIVS, model_fr550_fddivs, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_FDSADS, model_fr550_fdsads, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_FDMULCS, model_fr550_fdmulcs, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_NFDMULCS, model_fr550_nfdmulcs, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_NFDADDS, model_fr550_nfdadds, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_NFDSUBS, model_fr550_nfdsubs, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_NFDMULS, model_fr550_nfdmuls, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_NFDDIVS, model_fr550_nfddivs, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_NFDSADS, model_fr550_nfdsads, { { (int) UNIT_FR550_U_FLOAT_DUAL_ARITH, 1, 3 } } },
+ { FRVBF_INSN_NFDCMPS, model_fr550_nfdcmps, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MHSETLOS, model_fr550_mhsetlos, { { (int) UNIT_FR550_U_MEDIA_SET, 1, 1 } } },
+ { FRVBF_INSN_MHSETHIS, model_fr550_mhsethis, { { (int) UNIT_FR550_U_MEDIA_SET, 1, 1 } } },
+ { FRVBF_INSN_MHDSETS, model_fr550_mhdsets, { { (int) UNIT_FR550_U_MEDIA_SET, 1, 1 } } },
+ { FRVBF_INSN_MHSETLOH, model_fr550_mhsetloh, { { (int) UNIT_FR550_U_MEDIA_SET, 1, 1 } } },
+ { FRVBF_INSN_MHSETHIH, model_fr550_mhsethih, { { (int) UNIT_FR550_U_MEDIA_SET, 1, 1 } } },
+ { FRVBF_INSN_MHDSETH, model_fr550_mhdseth, { { (int) UNIT_FR550_U_MEDIA_SET, 1, 1 } } },
+ { FRVBF_INSN_MAND, model_fr550_mand, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MOR, model_fr550_mor, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MXOR, model_fr550_mxor, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_CMAND, model_fr550_cmand, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_CMOR, model_fr550_cmor, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_CMXOR, model_fr550_cmxor, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MNOT, model_fr550_mnot, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_CMNOT, model_fr550_cmnot, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MROTLI, model_fr550_mrotli, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MROTRI, model_fr550_mrotri, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MWCUT, model_fr550_mwcut, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MWCUTI, model_fr550_mwcuti, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MCUT, model_fr550_mcut, { { (int) UNIT_FR550_U_MEDIA_3_ACC, 1, 1 } } },
+ { FRVBF_INSN_MCUTI, model_fr550_mcuti, { { (int) UNIT_FR550_U_MEDIA_3_ACC, 1, 1 } } },
+ { FRVBF_INSN_MCUTSS, model_fr550_mcutss, { { (int) UNIT_FR550_U_MEDIA_3_ACC, 1, 1 } } },
+ { FRVBF_INSN_MCUTSSI, model_fr550_mcutssi, { { (int) UNIT_FR550_U_MEDIA_3_ACC, 1, 1 } } },
+ { FRVBF_INSN_MDCUTSSI, model_fr550_mdcutssi, { { (int) UNIT_FR550_U_MEDIA_3_ACC_DUAL, 1, 1 } } },
+ { FRVBF_INSN_MAVEH, model_fr550_maveh, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MSLLHI, model_fr550_msllhi, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MSRLHI, model_fr550_msrlhi, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MSRAHI, model_fr550_msrahi, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MDROTLI, model_fr550_mdrotli, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MCPLHI, model_fr550_mcplhi, { { (int) UNIT_FR550_U_MEDIA_3_DUAL, 1, 1 } } },
+ { FRVBF_INSN_MCPLI, model_fr550_mcpli, { { (int) UNIT_FR550_U_MEDIA_3_DUAL, 1, 1 } } },
+ { FRVBF_INSN_MSATHS, model_fr550_msaths, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MQSATHS, model_fr550_mqsaths, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MSATHU, model_fr550_msathu, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MCMPSH, model_fr550_mcmpsh, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MCMPUH, model_fr550_mcmpuh, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MABSHS, model_fr550_mabshs, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MADDHSS, model_fr550_maddhss, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MADDHUS, model_fr550_maddhus, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MSUBHSS, model_fr550_msubhss, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MSUBHUS, model_fr550_msubhus, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_CMADDHSS, model_fr550_cmaddhss, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_CMADDHUS, model_fr550_cmaddhus, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_CMSUBHSS, model_fr550_cmsubhss, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_CMSUBHUS, model_fr550_cmsubhus, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MQADDHSS, model_fr550_mqaddhss, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQADDHUS, model_fr550_mqaddhus, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQSUBHSS, model_fr550_mqsubhss, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQSUBHUS, model_fr550_mqsubhus, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQADDHSS, model_fr550_cmqaddhss, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQADDHUS, model_fr550_cmqaddhus, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQSUBHSS, model_fr550_cmqsubhss, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQSUBHUS, model_fr550_cmqsubhus, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MADDACCS, model_fr550_maddaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC, 1, 1 } } },
+ { FRVBF_INSN_MSUBACCS, model_fr550_msubaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC, 1, 1 } } },
+ { FRVBF_INSN_MDADDACCS, model_fr550_mdaddaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC_DUAL, 1, 1 } } },
+ { FRVBF_INSN_MDSUBACCS, model_fr550_mdsubaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC_DUAL, 1, 1 } } },
+ { FRVBF_INSN_MASACCS, model_fr550_masaccs, { { (int) UNIT_FR550_U_MEDIA_4_ADD_SUB, 1, 1 } } },
+ { FRVBF_INSN_MDASACCS, model_fr550_mdasaccs, { { (int) UNIT_FR550_U_MEDIA_4_ADD_SUB_DUAL, 1, 1 } } },
+ { FRVBF_INSN_MMULHS, model_fr550_mmulhs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MMULHU, model_fr550_mmulhu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MMULXHS, model_fr550_mmulxhs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MMULXHU, model_fr550_mmulxhu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_CMMULHS, model_fr550_cmmulhs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_CMMULHU, model_fr550_cmmulhu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MQMULHS, model_fr550_mqmulhs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQMULHU, model_fr550_mqmulhu, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQMULXHS, model_fr550_mqmulxhs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQMULXHU, model_fr550_mqmulxhu, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQMULHS, model_fr550_cmqmulhs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQMULHU, model_fr550_cmqmulhu, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MMACHS, model_fr550_mmachs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MMACHU, model_fr550_mmachu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MMRDHS, model_fr550_mmrdhs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MMRDHU, model_fr550_mmrdhu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_CMMACHS, model_fr550_cmmachs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_CMMACHU, model_fr550_cmmachu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MQMACHS, model_fr550_mqmachs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQMACHU, model_fr550_mqmachu, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQMACHS, model_fr550_cmqmachs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQMACHU, model_fr550_cmqmachu, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQXMACHS, model_fr550_mqxmachs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQXMACXHS, model_fr550_mqxmacxhs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQMACXHS, model_fr550_mqmacxhs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MCPXRS, model_fr550_mcpxrs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MCPXRU, model_fr550_mcpxru, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MCPXIS, model_fr550_mcpxis, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MCPXIU, model_fr550_mcpxiu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_CMCPXRS, model_fr550_cmcpxrs, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_CMCPXRU, model_fr550_cmcpxru, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_CMCPXIS, model_fr550_cmcpxis, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_CMCPXIU, model_fr550_cmcpxiu, { { (int) UNIT_FR550_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MQCPXRS, model_fr550_mqcpxrs, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQCPXRU, model_fr550_mqcpxru, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQCPXIS, model_fr550_mqcpxis, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQCPXIU, model_fr550_mqcpxiu, { { (int) UNIT_FR550_U_MEDIA_4_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MEXPDHW, model_fr550_mexpdhw, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_CMEXPDHW, model_fr550_cmexpdhw, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MEXPDHD, model_fr550_mexpdhd, { { (int) UNIT_FR550_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+ { FRVBF_INSN_CMEXPDHD, model_fr550_cmexpdhd, { { (int) UNIT_FR550_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+ { FRVBF_INSN_MPACKH, model_fr550_mpackh, { { (int) UNIT_FR550_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MDPACKH, model_fr550_mdpackh, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MUNPACKH, model_fr550_munpackh, { { (int) UNIT_FR550_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+ { FRVBF_INSN_MDUNPACKH, model_fr550_mdunpackh, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MBTOH, model_fr550_mbtoh, { { (int) UNIT_FR550_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+ { FRVBF_INSN_CMBTOH, model_fr550_cmbtoh, { { (int) UNIT_FR550_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+ { FRVBF_INSN_MHTOB, model_fr550_mhtob, { { (int) UNIT_FR550_U_MEDIA_3_DUAL, 1, 1 } } },
+ { FRVBF_INSN_CMHTOB, model_fr550_cmhtob, { { (int) UNIT_FR550_U_MEDIA_3_DUAL, 1, 1 } } },
+ { FRVBF_INSN_MBTOHE, model_fr550_mbtohe, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CMBTOHE, model_fr550_cmbtohe, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MNOP, model_fr550_mnop, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MCLRACC_0, model_fr550_mclracc_0, { { (int) UNIT_FR550_U_MEDIA_3_MCLRACC, 1, 1 } } },
+ { FRVBF_INSN_MCLRACC_1, model_fr550_mclracc_1, { { (int) UNIT_FR550_U_MEDIA_3_MCLRACC, 1, 1 } } },
+ { FRVBF_INSN_MRDACC, model_fr550_mrdacc, { { (int) UNIT_FR550_U_MEDIA_3_ACC, 1, 1 } } },
+ { FRVBF_INSN_MRDACCG, model_fr550_mrdaccg, { { (int) UNIT_FR550_U_MEDIA_3_ACC, 1, 1 } } },
+ { FRVBF_INSN_MWTACC, model_fr550_mwtacc, { { (int) UNIT_FR550_U_MEDIA_3_WTACC, 1, 1 } } },
+ { FRVBF_INSN_MWTACCG, model_fr550_mwtaccg, { { (int) UNIT_FR550_U_MEDIA_3_WTACC, 1, 1 } } },
+ { FRVBF_INSN_MCOP1, model_fr550_mcop1, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MCOP2, model_fr550_mcop2, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FNOP, model_fr550_fnop, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+};
+
/* Model timing data for `fr500'. */
static const INSN_TIMING fr500_timing[] = {
@@ -69622,9 +87910,14 @@ static const INSN_TIMING fr500_timing[] = {
{ FRVBF_INSN_NUDIV, model_fr500_nudiv, { { (int) UNIT_FR500_U_IDIV, 1, 1 } } },
{ FRVBF_INSN_SMUL, model_fr500_smul, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } },
{ FRVBF_INSN_UMUL, model_fr500_umul, { { (int) UNIT_FR500_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_SMU, model_fr500_smu, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMASS, model_fr500_smass, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMSSS, model_fr500_smsss, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SLL, model_fr500_sll, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_SRL, model_fr500_srl, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_SRA, model_fr500_sra, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SLASS, model_fr500_slass, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SCUTSS, model_fr500_scutss, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SCAN, model_fr500_scan, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_CADD, model_fr500_cadd, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_CSUB, model_fr500_csub, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
@@ -69662,6 +87955,8 @@ static const INSN_TIMING fr500_timing[] = {
{ FRVBF_INSN_SUBX, model_fr500_subx, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_ADDXCC, model_fr500_addxcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_SUBXCC, model_fr500_subxcc, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDSS, model_fr500_addss, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SUBSS, model_fr500_subss, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_ADDI, model_fr500_addi, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_SUBI, model_fr500_subi, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_ANDI, model_fr500_andi, { { (int) UNIT_FR500_U_INTEGER, 1, 1 } } },
@@ -70313,12 +88608,12 @@ static const INSN_TIMING fr500_timing[] = {
{ FRVBF_INSN_MQXMACHS, model_fr500_mqxmachs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MQXMACXHS, model_fr500_mqxmacxhs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MQMACXHS, model_fr500_mqmacxhs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
- { FRVBF_INSN_MCPXRS, model_fr500_mcpxrs, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
- { FRVBF_INSN_MCPXRU, model_fr500_mcpxru, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_MCPXRS, model_fr500_mcpxrs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+ { FRVBF_INSN_MCPXRU, model_fr500_mcpxru, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
{ FRVBF_INSN_MCPXIS, model_fr500_mcpxis, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
{ FRVBF_INSN_MCPXIU, model_fr500_mcpxiu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
- { FRVBF_INSN_CMCPXRS, model_fr500_cmcpxrs, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
- { FRVBF_INSN_CMCPXRU, model_fr500_cmcpxru, { { (int) UNIT_FR500_U_MEDIA, 1, 1 } } },
+ { FRVBF_INSN_CMCPXRS, model_fr500_cmcpxrs, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
+ { FRVBF_INSN_CMCPXRU, model_fr500_cmcpxru, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
{ FRVBF_INSN_CMCPXIS, model_fr500_cmcpxis, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
{ FRVBF_INSN_CMCPXIU, model_fr500_cmcpxiu, { { (int) UNIT_FR500_U_MEDIA_DUAL_MUL, 1, 1 } } },
{ FRVBF_INSN_MQCPXRS, model_fr500_mqcpxrs, { { (int) UNIT_FR500_U_MEDIA_QUAD_COMPLEX, 1, 1 } } },
@@ -70372,9 +88667,14 @@ static const INSN_TIMING tomcat_timing[] = {
{ FRVBF_INSN_NUDIV, model_tomcat_nudiv, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SMUL, model_tomcat_smul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_UMUL, model_tomcat_umul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMU, model_tomcat_smu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMASS, model_tomcat_smass, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMSSS, model_tomcat_smsss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SLL, model_tomcat_sll, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SRL, model_tomcat_srl, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SRA, model_tomcat_sra, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SLASS, model_tomcat_slass, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SCUTSS, model_tomcat_scutss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SCAN, model_tomcat_scan, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CADD, model_tomcat_cadd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CSUB, model_tomcat_csub, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
@@ -70412,6 +88712,8 @@ static const INSN_TIMING tomcat_timing[] = {
{ FRVBF_INSN_SUBX, model_tomcat_subx, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_ADDXCC, model_tomcat_addxcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SUBXCC, model_tomcat_subxcc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ADDSS, model_tomcat_addss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SUBSS, model_tomcat_subss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_ADDI, model_tomcat_addi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SUBI, model_tomcat_subi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_ANDI, model_tomcat_andi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
@@ -71122,9 +89424,14 @@ static const INSN_TIMING fr400_timing[] = {
{ FRVBF_INSN_NUDIV, model_fr400_nudiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
{ FRVBF_INSN_SMUL, model_fr400_smul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
{ FRVBF_INSN_UMUL, model_fr400_umul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_SMU, model_fr400_smu, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SMASS, model_fr400_smass, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SMSSS, model_fr400_smsss, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_SLL, model_fr400_sll, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_SRL, model_fr400_srl, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_SRA, model_fr400_sra, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SLASS, model_fr400_slass, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SCUTSS, model_fr400_scutss, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SCAN, model_fr400_scan, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_CADD, model_fr400_cadd, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_CSUB, model_fr400_csub, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
@@ -71162,6 +89469,8 @@ static const INSN_TIMING fr400_timing[] = {
{ FRVBF_INSN_SUBX, model_fr400_subx, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_ADDXCC, model_fr400_addxcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_SUBXCC, model_fr400_subxcc, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDSS, model_fr400_addss, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBSS, model_fr400_subss, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_ADDI, model_fr400_addi, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_SUBI, model_fr400_subi, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
{ FRVBF_INSN_ANDI, model_fr400_andi, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
@@ -71872,9 +90181,14 @@ static const INSN_TIMING simple_timing[] = {
{ FRVBF_INSN_NUDIV, model_simple_nudiv, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SMUL, model_simple_smul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_UMUL, model_simple_umul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMU, model_simple_smu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMASS, model_simple_smass, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMSSS, model_simple_smsss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SLL, model_simple_sll, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SRL, model_simple_srl, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SRA, model_simple_sra, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SLASS, model_simple_slass, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SCUTSS, model_simple_scutss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SCAN, model_simple_scan, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CADD, model_simple_cadd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CSUB, model_simple_csub, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
@@ -71912,6 +90226,8 @@ static const INSN_TIMING simple_timing[] = {
{ FRVBF_INSN_SUBX, model_simple_subx, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_ADDXCC, model_simple_addxcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SUBXCC, model_simple_subxcc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ADDSS, model_simple_addss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SUBSS, model_simple_subss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_ADDI, model_simple_addi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_SUBI, model_simple_subi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_ANDI, model_simple_andi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
@@ -72610,6 +90926,12 @@ frv_model_init (SIM_CPU *cpu)
}
static void
+fr550_model_init (SIM_CPU *cpu)
+{
+ CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_FR550_DATA));
+}
+
+static void
fr500_model_init (SIM_CPU *cpu)
{
CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_FR500_DATA));
@@ -72645,6 +90967,12 @@ static const MODEL frv_models[] =
{ 0 }
};
+static const MODEL fr550_models[] =
+{
+ { "fr550", & fr550_mach, MODEL_FR550, TIMING_DATA (& fr550_timing[0]), fr550_model_init },
+ { 0 }
+};
+
static const MODEL fr500_models[] =
{
{ "fr500", & fr500_mach, MODEL_FR500, TIMING_DATA (& fr500_timing[0]), fr500_model_init },
@@ -72722,6 +91050,32 @@ const MACH frv_mach =
};
static void
+fr550_init_cpu (SIM_CPU *cpu)
+{
+ CPU_REG_FETCH (cpu) = frvbf_fetch_register;
+ CPU_REG_STORE (cpu) = frvbf_store_register;
+ CPU_PC_FETCH (cpu) = frvbf_h_pc_get;
+ CPU_PC_STORE (cpu) = frvbf_h_pc_set;
+ CPU_GET_IDATA (cpu) = frvbf_get_idata;
+ CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX;
+ CPU_INSN_NAME (cpu) = cgen_insn_name;
+ CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full;
+#if WITH_FAST
+ CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast;
+#else
+ CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full;
+#endif
+}
+
+const MACH fr550_mach =
+{
+ "fr550", "fr550", MACH_FR550,
+ 32, 32, & fr550_models[0], & frvbf_imp_properties,
+ fr550_init_cpu,
+ frvbf_prepare_run
+};
+
+static void
fr500_init_cpu (SIM_CPU *cpu)
{
CPU_REG_FETCH (cpu) = frvbf_fetch_register;
diff --git a/sim/frv/pipeline.c b/sim/frv/pipeline.c
index 90d55c7..291a5dc 100644
--- a/sim/frv/pipeline.c
+++ b/sim/frv/pipeline.c
@@ -1,5 +1,5 @@
/* frv vliw model.
- Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
+ Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU simulators.
diff --git a/sim/frv/profile-fr550.c b/sim/frv/profile-fr550.c
new file mode 100644
index 0000000..c92cf97
--- /dev/null
+++ b/sim/frv/profile-fr550.c
@@ -0,0 +1,2664 @@
+/* frv simulator fr550 dependent profiling code.
+
+ Copyright (C) 2003 Free Software Foundation, Inc.
+ Contributed by Red Hat
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+#define WANT_CPU
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "bfd.h"
+
+#if WITH_PROFILE_MODEL_P
+
+#include "profile.h"
+#include "profile-fr550.h"
+
+/* Initialize cycle counting for an insn.
+ FIRST_P is non-zero if this is the first insn in a set of parallel
+ insns. */
+void
+fr550_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+ if (first_p)
+ {
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ d->cur_fr_load = d->prev_fr_load;
+ d->cur_fr_complex_1 = d->prev_fr_complex_1;
+ d->cur_fr_complex_2 = d->prev_fr_complex_2;
+ d->cur_ccr_complex = d->prev_ccr_complex;
+ d->cur_acc_mmac = d->prev_acc_mmac;
+ }
+}
+
+/* Record the cycles computed for an insn.
+ LAST_P is non-zero if this is the last insn in a set of parallel insns,
+ and we update the total cycle count.
+ CYCLES is the cycle count of the insn. */
+void
+fr550_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
+{
+ if (last_p)
+ {
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ d->prev_fr_load = d->cur_fr_load;
+ d->prev_fr_complex_1 = d->cur_fr_complex_1;
+ d->prev_fr_complex_2 = d->cur_fr_complex_2;
+ d->prev_ccr_complex = d->cur_ccr_complex;
+ d->prev_acc_mmac = d->cur_acc_mmac;
+ }
+}
+
+static void fr550_reset_fr_flags (SIM_CPU *cpu, INT fr);
+static void fr550_reset_ccr_flags (SIM_CPU *cpu, INT ccr);
+static void fr550_reset_acc_flags (SIM_CPU *cpu, INT acc);
+
+static void
+set_use_is_fr_load (SIM_CPU *cpu, INT fr)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ fr550_reset_fr_flags (cpu, (fr));
+ d->cur_fr_load |= (((DI)1) << (fr));
+}
+
+static void
+set_use_not_fr_load (SIM_CPU *cpu, INT fr)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ d->cur_fr_load &= ~(((DI)1) << (fr));
+}
+
+static int
+use_is_fr_load (SIM_CPU *cpu, INT fr)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ return d->prev_fr_load & (((DI)1) << (fr));
+}
+
+static void
+set_use_is_fr_complex_1 (SIM_CPU *cpu, INT fr)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ fr550_reset_fr_flags (cpu, (fr));
+ d->cur_fr_complex_1 |= (((DI)1) << (fr));
+}
+
+static void
+set_use_not_fr_complex_1 (SIM_CPU *cpu, INT fr)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ d->cur_fr_complex_1 &= ~(((DI)1) << (fr));
+}
+
+static int
+use_is_fr_complex_1 (SIM_CPU *cpu, INT fr)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ return d->prev_fr_complex_1 & (((DI)1) << (fr));
+}
+
+static void
+set_use_is_fr_complex_2 (SIM_CPU *cpu, INT fr)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ fr550_reset_fr_flags (cpu, (fr));
+ d->cur_fr_complex_2 |= (((DI)1) << (fr));
+}
+
+static void
+set_use_not_fr_complex_2 (SIM_CPU *cpu, INT fr)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ d->cur_fr_complex_2 &= ~(((DI)1) << (fr));
+}
+
+static int
+use_is_fr_complex_2 (SIM_CPU *cpu, INT fr)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ return d->prev_fr_complex_2 & (((DI)1) << (fr));
+}
+
+static void
+set_use_is_ccr_complex (SIM_CPU *cpu, INT ccr)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ fr550_reset_ccr_flags (cpu, (ccr));
+ d->cur_ccr_complex |= (((SI)1) << (ccr));
+}
+
+static void
+set_use_not_ccr_complex (SIM_CPU *cpu, INT ccr)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ d->cur_ccr_complex &= ~(((SI)1) << (ccr));
+}
+
+static int
+use_is_ccr_complex (SIM_CPU *cpu, INT ccr)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ return d->prev_ccr_complex & (((SI)1) << (ccr));
+}
+
+static void
+set_use_is_acc_mmac (SIM_CPU *cpu, INT acc)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ fr550_reset_acc_flags (cpu, (acc));
+ d->cur_acc_mmac |= (((DI)1) << (acc));
+}
+
+static void
+set_use_not_acc_mmac (SIM_CPU *cpu, INT acc)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ d->cur_acc_mmac &= ~(((DI)1) << (acc));
+}
+
+static int
+use_is_acc_mmac (SIM_CPU *cpu, INT acc)
+{
+ MODEL_FR550_DATA *d = CPU_MODEL_DATA (cpu);
+ return d->prev_acc_mmac & (((DI)1) << (acc));
+}
+
+static void
+fr550_reset_fr_flags (SIM_CPU *cpu, INT fr)
+{
+ set_use_not_fr_load (cpu, fr);
+ set_use_not_fr_complex_1 (cpu, fr);
+ set_use_not_fr_complex_2 (cpu, fr);
+}
+
+static void
+fr550_reset_ccr_flags (SIM_CPU *cpu, INT ccr)
+{
+ set_use_not_ccr_complex (cpu, ccr);
+}
+
+static void
+fr550_reset_acc_flags (SIM_CPU *cpu, INT acc)
+{
+ set_use_not_acc_mmac (cpu, acc);
+}
+
+/* Detect overlap between two register ranges. Works if one of the registers
+ is -1 with width 1 (i.e. undefined), but not both. */
+#define REG_OVERLAP(r1, w1, r2, w2) ( \
+ (r1) + (w1) - 1 >= (r2) && (r2) + (w2) - 1 >= (r1) \
+)
+
+/* Latency of floating point registers may be less than recorded when followed
+ by another floating point insn. */
+static void
+adjust_float_register_busy (SIM_CPU *cpu,
+ INT in_FRi, int iwidth,
+ INT in_FRj, int jwidth,
+ INT out_FRk, int kwidth)
+{
+ int i;
+ /* The latency of FRk may be less than previously recorded.
+ See Table 14-15 in the LSI. */
+ if (in_FRi >= 0)
+ {
+ for (i = 0; i < iwidth; ++i)
+ {
+ if (! REG_OVERLAP (in_FRi + i, 1, out_FRk, kwidth))
+ if (use_is_fr_load (cpu, in_FRi + i))
+ decrease_FR_busy (cpu, in_FRi + i, 1);
+ else
+ enforce_full_fr_latency (cpu, in_FRi + i);
+ }
+ }
+
+ if (in_FRj >= 0)
+ {
+ for (i = 0; i < jwidth; ++i)
+ {
+ if (! REG_OVERLAP (in_FRj + i, 1, in_FRi, iwidth)
+ && ! REG_OVERLAP (in_FRj + i, 1, out_FRk, kwidth))
+ if (use_is_fr_load (cpu, in_FRj + i))
+ decrease_FR_busy (cpu, in_FRj + i, 1);
+ else
+ enforce_full_fr_latency (cpu, in_FRj + i);
+ }
+ }
+
+ if (out_FRk >= 0)
+ {
+ for (i = 0; i < kwidth; ++i)
+ {
+ if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth)
+ && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth))
+ {
+ if (use_is_fr_complex_1 (cpu, out_FRk + i))
+ decrease_FR_busy (cpu, out_FRk + i, 1);
+ else if (use_is_fr_complex_2 (cpu, out_FRk + i))
+ decrease_FR_busy (cpu, out_FRk + i, 2);
+ else
+ enforce_full_fr_latency (cpu, out_FRk + i);
+ }
+ }
+ }
+}
+
+static void
+restore_float_register_busy (SIM_CPU *cpu,
+ INT in_FRi, int iwidth,
+ INT in_FRj, int jwidth,
+ INT out_FRk, int kwidth)
+{
+ int i;
+ /* The latency of FRk may be less than previously recorded.
+ See Table 14-15 in the LSI. */
+ if (in_FRi >= 0)
+ {
+ for (i = 0; i < iwidth; ++i)
+ {
+ if (! REG_OVERLAP (in_FRi + i, 1, out_FRk, kwidth))
+ if (use_is_fr_load (cpu, in_FRi + i))
+ increase_FR_busy (cpu, in_FRi + i, 1);
+ }
+ }
+
+ if (in_FRj >= 0)
+ {
+ for (i = 0; i < jwidth; ++i)
+ {
+ if (! REG_OVERLAP (in_FRj + i, 1, in_FRi, iwidth)
+ && ! REG_OVERLAP (in_FRj + i, 1, out_FRk, kwidth))
+ if (use_is_fr_load (cpu, in_FRj + i))
+ increase_FR_busy (cpu, in_FRj + i, 1);
+ }
+ }
+
+ if (out_FRk >= 0)
+ {
+ for (i = 0; i < kwidth; ++i)
+ {
+ if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth)
+ && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth))
+ {
+ if (use_is_fr_complex_1 (cpu, out_FRk + i))
+ increase_FR_busy (cpu, out_FRk + i, 1);
+ else if (use_is_fr_complex_2 (cpu, out_FRk + i))
+ increase_FR_busy (cpu, out_FRk + i, 2);
+ }
+ }
+ }
+}
+
+/* Latency of floating point registers may be less than recorded when used in a
+ media insns and followed by another media insn. */
+static void
+adjust_float_register_busy_for_media (SIM_CPU *cpu,
+ INT in_FRi, int iwidth,
+ INT in_FRj, int jwidth,
+ INT out_FRk, int kwidth)
+{
+ int i;
+ /* The latency of FRk may be less than previously recorded.
+ See Table 14-15 in the LSI. */
+ if (out_FRk >= 0)
+ {
+ for (i = 0; i < kwidth; ++i)
+ {
+ if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth)
+ && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth))
+ {
+ if (use_is_fr_complex_1 (cpu, out_FRk + i))
+ decrease_FR_busy (cpu, out_FRk + i, 1);
+ else
+ enforce_full_fr_latency (cpu, out_FRk + i);
+ }
+ }
+ }
+}
+
+static void
+restore_float_register_busy_for_media (SIM_CPU *cpu,
+ INT in_FRi, int iwidth,
+ INT in_FRj, int jwidth,
+ INT out_FRk, int kwidth)
+{
+ int i;
+ if (out_FRk >= 0)
+ {
+ for (i = 0; i < kwidth; ++i)
+ {
+ if (! REG_OVERLAP (out_FRk + i, 1, in_FRi, iwidth)
+ && ! REG_OVERLAP (out_FRk + i, 1, in_FRj, jwidth))
+ {
+ if (use_is_fr_complex_1 (cpu, out_FRk + i))
+ increase_FR_busy (cpu, out_FRk + i, 1);
+ }
+ }
+ }
+}
+
+/* Latency of accumulator registers may be less than recorded when used in a
+ media insns and followed by another media insn. */
+static void
+adjust_acc_busy_for_mmac (SIM_CPU *cpu,
+ INT in_ACC, int inwidth,
+ INT out_ACC, int outwidth)
+{
+ int i;
+ /* The latency of an accumulator may be less than previously recorded.
+ See Table 14-15 in the LSI. */
+ if (in_ACC >= 0)
+ {
+ for (i = 0; i < inwidth; ++i)
+ {
+ if (use_is_acc_mmac (cpu, in_ACC + i))
+ decrease_ACC_busy (cpu, in_ACC + i, 1);
+ else
+ enforce_full_acc_latency (cpu, in_ACC + i);
+ }
+ }
+ if (out_ACC >= 0)
+ {
+ for (i = 0; i < outwidth; ++i)
+ {
+ if (! REG_OVERLAP (out_ACC + i, 1, in_ACC, inwidth))
+ {
+ if (use_is_acc_mmac (cpu, out_ACC + i))
+ decrease_ACC_busy (cpu, out_ACC + i, 1);
+ else
+ enforce_full_acc_latency (cpu, out_ACC + i);
+ }
+ }
+ }
+}
+
+static void
+restore_acc_busy_for_mmac (SIM_CPU *cpu,
+ INT in_ACC, int inwidth,
+ INT out_ACC, int outwidth)
+{
+ int i;
+ if (in_ACC >= 0)
+ {
+ for (i = 0; i < inwidth; ++i)
+ {
+ if (use_is_acc_mmac (cpu, in_ACC + i))
+ increase_ACC_busy (cpu, in_ACC + i, 1);
+ }
+ }
+ if (out_ACC >= 0)
+ {
+ for (i = 0; i < outwidth; ++i)
+ {
+ if (! REG_OVERLAP (out_ACC + i, 1, in_ACC, inwidth))
+ {
+ if (use_is_acc_mmac (cpu, out_ACC + i))
+ increase_ACC_busy (cpu, out_ACC + i, 1);
+ }
+ }
+ }
+}
+
+int
+frvbf_model_fr550_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced)
+{
+ return idesc->timing->units[unit_num].done;
+}
+
+int
+frvbf_model_fr550_u_integer (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj, INT out_GRk,
+ INT out_ICCi_1)
+{
+ int cycles;
+
+ /* icc0-icc4 are the upper 4 fields of the CCR. */
+ if (out_ICCi_1 >= 0)
+ out_ICCi_1 += 4;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ vliw_wait_for_GR (cpu, out_GRk);
+ vliw_wait_for_CCR (cpu, out_ICCi_1);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ load_wait_for_GR (cpu, out_GRk);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ fr550_reset_ccr_flags (cpu, out_ICCi_1);
+
+ /* GRk is available immediately to the next VLIW insn as is ICCi_1. */
+ cycles = idesc->timing->units[unit_num].done;
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_imul (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
+{
+ int cycles;
+ /* icc0-icc4 are the upper 4 fields of the CCR. */
+ if (out_ICCi_1 >= 0)
+ out_ICCi_1 += 4;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ vliw_wait_for_GRdouble (cpu, out_GRk);
+ vliw_wait_for_CCR (cpu, out_ICCi_1);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ load_wait_for_GRdouble (cpu, out_GRk);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ /* GRk has a latency of 1 cycles. */
+ cycles = idesc->timing->units[unit_num].done;
+ update_GRdouble_latency (cpu, out_GRk, cycles + 1);
+
+ /* ICCi_1 has a latency of 1 cycle. */
+ update_CCR_latency (cpu, out_ICCi_1, cycles + 1);
+
+ fr550_reset_ccr_flags (cpu, out_ICCi_1);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
+{
+ int cycles;
+ FRV_VLIW *vliw;
+ int slot;
+
+ /* icc0-icc4 are the upper 4 fields of the CCR. */
+ if (out_ICCi_1 >= 0)
+ out_ICCi_1 += 4;
+
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_I0;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ vliw_wait_for_GR (cpu, out_GRk);
+ vliw_wait_for_CCR (cpu, out_ICCi_1);
+ vliw_wait_for_idiv_resource (cpu, slot);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ load_wait_for_GR (cpu, out_GRk);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ /* GRk has a latency of 18 cycles! */
+ cycles = idesc->timing->units[unit_num].done;
+ update_GR_latency (cpu, out_GRk, cycles + 18);
+
+ /* ICCi_1 has a latency of 18 cycles. */
+ update_CCR_latency (cpu, out_ICCi_1, cycles + 18);
+
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ /* GNER has a latency of 18 cycles. */
+ update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 18);
+ }
+
+ /* the idiv resource has a latency of 18 cycles! */
+ update_idiv_resource_latency (cpu, slot, cycles + 18);
+
+ fr550_reset_ccr_flags (cpu, out_ICCi_1);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_branch (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj,
+ INT in_ICCi_2, INT in_FCCi_2)
+{
+ int cycles;
+ FRV_PROFILE_STATE *ps;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* icc0-icc4 are the upper 4 fields of the CCR. */
+ if (in_ICCi_2 >= 0)
+ in_ICCi_2 += 4;
+
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ vliw_wait_for_CCR (cpu, in_ICCi_2);
+ vliw_wait_for_CCR (cpu, in_FCCi_2);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ /* When counting branches taken or not taken, don't consider branches after
+ the first taken branch in a vliw insn. */
+ ps = CPU_PROFILE_STATE (cpu);
+ if (! ps->vliw_branch_taken)
+ {
+ /* (1 << 4): The pc is the 5th element in inputs, outputs.
+ ??? can be cleaned up */
+ PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
+ int taken = (referenced & (1 << 4)) != 0;
+ if (taken)
+ {
+ ++PROFILE_MODEL_TAKEN_COUNT (p);
+ ps->vliw_branch_taken = 1;
+ }
+ else
+ ++PROFILE_MODEL_UNTAKEN_COUNT (p);
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_trap (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj,
+ INT in_ICCi_2, INT in_FCCi_2)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* icc0-icc4 are the upper 4 fields of the CCR. */
+ if (in_ICCi_2 >= 0)
+ in_ICCi_2 += 4;
+
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ vliw_wait_for_CCR (cpu, in_ICCi_2);
+ vliw_wait_for_CCR (cpu, in_FCCi_2);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_check (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_ICCi_3, INT in_FCCi_3)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced,
+ in_ICCi_3, in_FCCi_3);
+}
+
+int
+frvbf_model_fr550_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT out_GRkhi, INT out_GRklo)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a GR
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, out_GRkhi);
+ vliw_wait_for_GR (cpu, out_GRklo);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, out_GRkhi);
+ load_wait_for_GR (cpu, out_GRklo);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ /* GRk is available immediately to the next VLIW insn. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj,
+ INT out_GRk, INT out_GRdoublek)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ vliw_wait_for_GR (cpu, out_GRk);
+ vliw_wait_for_GRdouble (cpu, out_GRdoublek);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ load_wait_for_GR (cpu, out_GRk);
+ load_wait_for_GRdouble (cpu, out_GRdoublek);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* The latency of GRk for a load will depend on how long it takes to retrieve
+ the the data from the cache or memory. */
+ update_GR_latency_for_load (cpu, out_GRk, cycles);
+ update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles);
+
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ /* GNER has a latency of 2 cycles. */
+ update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2);
+ update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2);
+ }
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj,
+ INT in_GRk, INT in_GRdoublek)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ vliw_wait_for_GR (cpu, in_GRk);
+ vliw_wait_for_GRdouble (cpu, in_GRdoublek);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ load_wait_for_GR (cpu, in_GRk);
+ load_wait_for_GRdouble (cpu, in_GRdoublek);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ /* The target register is available immediately. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj,
+ INT out_FRk, INT out_FRdoublek)
+{
+ int cycles;
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet.
+ The latency of the registers may be less than previously recorded,
+ depending on how they were used previously.
+ See Table 13-8 in the LSI. */
+ adjust_float_register_busy (cpu, -1, 1, -1, 1, out_FRk, 1);
+ adjust_float_register_busy (cpu, -1, 1, -1, 1, out_FRdoublek, 2);
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ vliw_wait_for_FR (cpu, out_FRk);
+ vliw_wait_for_FRdouble (cpu, out_FRdoublek);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
+ vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
+ }
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ load_wait_for_FR (cpu, out_FRk);
+ load_wait_for_FRdouble (cpu, out_FRdoublek);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* The latency of FRk for a load will depend on how long it takes to retrieve
+ the the data from the cache or memory. */
+ update_FR_latency_for_load (cpu, out_FRk, cycles);
+ update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles);
+
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ /* FNER has a latency of 3 cycles. */
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), cycles + 3);
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), cycles + 3);
+ }
+
+ if (out_FRk >= 0)
+ set_use_is_fr_load (cpu, out_FRk);
+ if (out_FRdoublek >= 0)
+ {
+ set_use_is_fr_load (cpu, out_FRdoublek);
+ set_use_is_fr_load (cpu, out_FRdoublek + 1);
+ }
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj,
+ INT in_FRk, INT in_FRdoublek)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ adjust_float_register_busy (cpu, in_FRk, 1, -1, 1, -1, 1);
+ adjust_float_register_busy (cpu, in_FRdoublek, 2, -1, 1, -1, 1);
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ vliw_wait_for_FR (cpu, in_FRk);
+ vliw_wait_for_FRdouble (cpu, in_FRdoublek);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ load_wait_for_FR (cpu, in_FRk);
+ load_wait_for_FRdouble (cpu, in_FRdoublek);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ /* The target register is available immediately. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_ici (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+ request_cache_invalidate (cpu, CPU_INSN_CACHE (cpu), cycles);
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_dci (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+ request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+ request_cache_flush (cpu, CPU_DATA_CACHE (cpu), cycles);
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+ request_cache_preload (cpu, CPU_INSN_CACHE (cpu), cycles);
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+ request_cache_preload (cpu, CPU_DATA_CACHE (cpu), cycles);
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_icul (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+ request_cache_unlock (cpu, CPU_INSN_CACHE (cpu), cycles);
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+ request_cache_unlock (cpu, CPU_DATA_CACHE (cpu), cycles);
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_float_arith (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj,
+ INT in_FRdoublei, INT in_FRdoublej,
+ INT out_FRk, INT out_FRdoublek)
+{
+ int cycles;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ adjust_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1);
+ adjust_float_register_busy (cpu, in_FRdoublei, 2, in_FRdoublej, 2, out_FRdoublek, 2);
+ ps = CPU_PROFILE_STATE (cpu);
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_float (cpu, slot);
+ post_wait_for_FR (cpu, in_FRi);
+ post_wait_for_FR (cpu, in_FRj);
+ post_wait_for_FR (cpu, out_FRk);
+ post_wait_for_FRdouble (cpu, in_FRdoublei);
+ post_wait_for_FRdouble (cpu, in_FRdoublej);
+ post_wait_for_FRdouble (cpu, out_FRdoublek);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
+ }
+ restore_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1);
+ restore_float_register_busy (cpu, in_FRdoublei, 2, in_FRdoublej, 2, out_FRdoublek, 2);
+
+ /* The latency of FRk will be at least the latency of the other inputs. */
+ update_FR_latency (cpu, out_FRk, ps->post_wait);
+ update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
+
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait);
+ }
+
+ /* Once initiated, post-processing will take 2 cycles. */
+ update_FR_ptime (cpu, out_FRk, 2);
+ update_FRdouble_ptime (cpu, out_FRdoublek, 2);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 2);
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 2);
+ }
+
+ /* Mark this use of the register as a floating point op. */
+ if (out_FRk >= 0)
+ set_use_is_fr_complex_2 (cpu, out_FRk);
+ if (out_FRdoublek >= 0)
+ {
+ set_use_is_fr_complex_2 (cpu, out_FRdoublek);
+ if (out_FRdoublek < 63)
+ set_use_is_fr_complex_2 (cpu, out_FRdoublek + 1);
+ }
+
+ /* the media point unit resource has a latency of 4 cycles */
+ update_media_resource_latency (cpu, slot, cycles + 4);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_float_dual_arith (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj,
+ INT in_FRdoublei, INT in_FRdoublej,
+ INT out_FRk, INT out_FRdoublek)
+{
+ int cycles;
+ INT dual_FRi;
+ INT dual_FRj;
+ INT dual_FRk;
+ INT dual_FRdoublei;
+ INT dual_FRdoublej;
+ INT dual_FRdoublek;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ dual_FRi = DUAL_REG (in_FRi);
+ dual_FRj = DUAL_REG (in_FRj);
+ dual_FRk = DUAL_REG (out_FRk);
+ dual_FRdoublei = DUAL_DOUBLE (in_FRdoublei);
+ dual_FRdoublej = DUAL_DOUBLE (in_FRdoublej);
+ dual_FRdoublek = DUAL_DOUBLE (out_FRdoublek);
+
+ adjust_float_register_busy (cpu, in_FRi, 2, in_FRj, 2, out_FRk, 2);
+ adjust_float_register_busy (cpu, in_FRdoublei, 4, in_FRdoublej, 4, out_FRdoublek, 4);
+ ps = CPU_PROFILE_STATE (cpu);
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_float (cpu, slot);
+ post_wait_for_FR (cpu, in_FRi);
+ post_wait_for_FR (cpu, in_FRj);
+ post_wait_for_FR (cpu, out_FRk);
+ post_wait_for_FR (cpu, dual_FRi);
+ post_wait_for_FR (cpu, dual_FRj);
+ post_wait_for_FR (cpu, dual_FRk);
+ post_wait_for_FRdouble (cpu, in_FRdoublei);
+ post_wait_for_FRdouble (cpu, in_FRdoublej);
+ post_wait_for_FRdouble (cpu, out_FRdoublek);
+ post_wait_for_FRdouble (cpu, dual_FRdoublei);
+ post_wait_for_FRdouble (cpu, dual_FRdoublej);
+ post_wait_for_FRdouble (cpu, dual_FRdoublek);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
+ post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRk));
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
+ post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRdoublek));
+ }
+ restore_float_register_busy (cpu, in_FRi, 2, in_FRj, 2, out_FRk, 2);
+ restore_float_register_busy (cpu, in_FRdoublei, 4, in_FRdoublej, 4, out_FRdoublek, 4);
+
+ /* The latency of FRk will be at least the latency of the other inputs. */
+ update_FR_latency (cpu, out_FRk, ps->post_wait);
+ update_FR_latency (cpu, dual_FRk, ps->post_wait);
+ update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
+ update_FRdouble_latency (cpu, dual_FRdoublek, ps->post_wait);
+
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
+ update_SPR_latency (cpu, FNER_FOR_FR (dual_FRk), ps->post_wait);
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait);
+ update_SPR_latency (cpu, FNER_FOR_FR (dual_FRdoublek), ps->post_wait);
+ }
+
+ /* Once initiated, post-processing will take 3 cycles. */
+ update_FR_ptime (cpu, out_FRk, 3);
+ update_FR_ptime (cpu, dual_FRk, 3);
+ update_FRdouble_ptime (cpu, out_FRdoublek, 3);
+ update_FRdouble_ptime (cpu, dual_FRdoublek, 3);
+
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3);
+ update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRk), 3);
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3);
+ update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRdoublek), 3);
+ }
+
+ /* Mark this use of the register as a floating point op. */
+ if (out_FRk >= 0)
+ fr550_reset_fr_flags (cpu, out_FRk);
+ if (dual_FRk >= 0)
+ fr550_reset_fr_flags (cpu, dual_FRk);
+ if (out_FRdoublek >= 0)
+ {
+ fr550_reset_fr_flags (cpu, out_FRdoublek);
+ if (out_FRdoublek < 63)
+ fr550_reset_fr_flags (cpu, out_FRdoublek + 1);
+ }
+ if (dual_FRdoublek >= 0)
+ {
+ fr550_reset_fr_flags (cpu, dual_FRdoublek);
+ if (dual_FRdoublek < 63)
+ fr550_reset_fr_flags (cpu, dual_FRdoublek + 1);
+ }
+
+ /* the media point unit resource has a latency of 5 cycles */
+ update_media_resource_latency (cpu, slot, cycles + 5);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_float_div (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj, INT out_FRk)
+{
+ int cycles;
+ FRV_VLIW *vliw;
+ int slot;
+ FRV_PROFILE_STATE *ps;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ adjust_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1);
+ ps = CPU_PROFILE_STATE (cpu);
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_float (cpu, slot);
+ post_wait_for_fdiv (cpu, slot);
+ post_wait_for_FR (cpu, in_FRi);
+ post_wait_for_FR (cpu, in_FRj);
+ post_wait_for_FR (cpu, out_FRk);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
+ restore_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1);
+
+ /* The latency of FRk will be at least the latency of the other inputs. */
+ /* Once initiated, post-processing will take 9 cycles. */
+ update_FR_latency (cpu, out_FRk, ps->post_wait);
+ update_FR_ptime (cpu, out_FRk, 9);
+
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ /* FNER has a latency of 9 cycles. */
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 9);
+ }
+
+ /* The latency of the fdiv unit will be at least the latency of the other
+ inputs. Once initiated, post-processing will take 9 cycles. */
+ update_fdiv_resource_latency (cpu, slot, ps->post_wait + 9);
+
+ /* the media point unit resource has a latency of 11 cycles */
+ update_media_resource_latency (cpu, slot, cycles + 11);
+
+ fr550_reset_fr_flags (cpu, out_FRk);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_float_sqrt (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRj, INT in_FRdoublej,
+ INT out_FRk, INT out_FRdoublek)
+{
+ int cycles;
+ FRV_VLIW *vliw;
+ int slot;
+ FRV_PROFILE_STATE *ps;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ adjust_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1);
+ adjust_float_register_busy (cpu, -1, 1, in_FRdoublej, 2, out_FRdoublek, 2);
+ ps = CPU_PROFILE_STATE (cpu);
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_float (cpu, slot);
+ post_wait_for_fsqrt (cpu, slot);
+ post_wait_for_FR (cpu, in_FRj);
+ post_wait_for_FR (cpu, out_FRk);
+ post_wait_for_FRdouble (cpu, in_FRdoublej);
+ post_wait_for_FRdouble (cpu, out_FRdoublek);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
+ }
+ restore_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1);
+ restore_float_register_busy (cpu, -1, 1, in_FRdoublej, 2, out_FRdoublek, 2);
+
+ /* The latency of FRk will be at least the latency of the other inputs. */
+ update_FR_latency (cpu, out_FRk, ps->post_wait);
+ update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
+
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ /* FNER has a latency of 14 cycles. */
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait);
+ }
+
+ /* Once initiated, post-processing will take 14 cycles. */
+ update_FR_ptime (cpu, out_FRk, 14);
+ update_FRdouble_ptime (cpu, out_FRdoublek, 14);
+
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ /* FNER has a latency of 14 cycles. */
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 14);
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 14);
+ }
+
+ /* The latency of the sqrt unit will be the latency of the other
+ inputs plus 14 cycles. */
+ update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14);
+
+ fr550_reset_fr_flags (cpu, out_FRk);
+ if (out_FRdoublek != -1)
+ {
+ fr550_reset_fr_flags (cpu, out_FRdoublek);
+ fr550_reset_fr_flags (cpu, out_FRdoublek + 1);
+ }
+
+ /* the media point unit resource has a latency of 16 cycles */
+ update_media_resource_latency (cpu, slot, cycles + 16);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_float_compare (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj,
+ INT in_FRdoublei, INT in_FRdoublej,
+ INT out_FCCi_2)
+{
+ int cycles;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ adjust_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, -1, 1);
+ adjust_float_register_busy (cpu, in_FRdoublei, 2, in_FRdoublej, 2, -1, 1);
+ ps = CPU_PROFILE_STATE (cpu);
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_float (cpu, slot);
+ post_wait_for_FR (cpu, in_FRi);
+ post_wait_for_FR (cpu, in_FRj);
+ post_wait_for_FRdouble (cpu, in_FRdoublei);
+ post_wait_for_FRdouble (cpu, in_FRdoublej);
+ post_wait_for_CCR (cpu, out_FCCi_2);
+ restore_float_register_busy (cpu, in_FRi, 1, in_FRj, 1, -1, 1);
+ restore_float_register_busy (cpu, in_FRdoublei, 2, in_FRdoublej, 2, -1, 1);
+
+ /* The latency of FCCi_2 will be the latency of the other inputs plus 2
+ cycles. */
+ update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 2);
+
+ /* the media point unit resource has a latency of 4 cycles */
+ update_media_resource_latency (cpu, slot, cycles + 4);
+
+ set_use_is_ccr_complex (cpu, out_FCCi_2);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_float_dual_compare (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj,
+ INT out_FCCi_2)
+{
+ int cycles;
+ INT dual_FRi;
+ INT dual_FRj;
+ INT dual_FCCi_2;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ ps = CPU_PROFILE_STATE (cpu);
+ ps->post_wait = cycles;
+ dual_FRi = DUAL_REG (in_FRi);
+ dual_FRj = DUAL_REG (in_FRj);
+ dual_FCCi_2 = out_FCCi_2 + 1;
+ adjust_float_register_busy (cpu, in_FRi, 2, in_FRj, 2, -1, 1);
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_float (cpu, slot);
+ post_wait_for_FR (cpu, in_FRi);
+ post_wait_for_FR (cpu, in_FRj);
+ post_wait_for_FR (cpu, dual_FRi);
+ post_wait_for_FR (cpu, dual_FRj);
+ post_wait_for_CCR (cpu, out_FCCi_2);
+ post_wait_for_CCR (cpu, dual_FCCi_2);
+ restore_float_register_busy (cpu, in_FRi, 2, in_FRj, 2, -1, 1);
+
+ /* The latency of FCCi_2 will be the latency of the other inputs plus 3
+ cycles. */
+ update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3);
+ update_CCR_latency (cpu, dual_FCCi_2, ps->post_wait + 3);
+
+ set_use_is_ccr_complex (cpu, out_FCCi_2);
+ if (dual_FCCi_2 >= 0)
+ set_use_is_ccr_complex (cpu, dual_FCCi_2);
+
+ /* the media point unit resource has a latency of 5 cycles */
+ update_media_resource_latency (cpu, slot, cycles + 5);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_float_convert (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRj, INT in_FRintj, INT in_FRdoublej,
+ INT out_FRk, INT out_FRintk,
+ INT out_FRdoublek)
+{
+ int cycles;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ ps = CPU_PROFILE_STATE (cpu);
+ ps->post_wait = cycles;
+ adjust_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1);
+ adjust_float_register_busy (cpu, -1, 1, in_FRintj, 1, out_FRintk, 1);
+ adjust_float_register_busy (cpu, -1, 1, in_FRdoublej, 2, out_FRdoublek, 2);
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_float (cpu, slot);
+ post_wait_for_FR (cpu, in_FRj);
+ post_wait_for_FR (cpu, in_FRintj);
+ post_wait_for_FRdouble (cpu, in_FRdoublej);
+ post_wait_for_FR (cpu, out_FRk);
+ post_wait_for_FR (cpu, out_FRintk);
+ post_wait_for_FRdouble (cpu, out_FRdoublek);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRintk));
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
+ }
+ restore_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1);
+ restore_float_register_busy (cpu, -1, 1, in_FRintj, 1, out_FRintk, 1);
+ restore_float_register_busy (cpu, -1, 1, in_FRdoublej, 2, out_FRdoublek, 2);
+
+ /* The latency of FRk will be at least the latency of the other inputs. */
+ update_FR_latency (cpu, out_FRk, ps->post_wait);
+ update_FR_latency (cpu, out_FRintk, ps->post_wait);
+ update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
+
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRintk), ps->post_wait);
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait);
+ }
+
+ /* Once initiated, post-processing will take 2 cycles. */
+ update_FR_ptime (cpu, out_FRk, 2);
+ update_FR_ptime (cpu, out_FRintk, 2);
+ update_FRdouble_ptime (cpu, out_FRdoublek, 2);
+
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 2);
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRintk), 2);
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 2);
+ }
+
+ /* Mark this use of the register as a floating point op. */
+ if (out_FRk >= 0)
+ set_use_is_fr_complex_2 (cpu, out_FRk);
+ if (out_FRintk >= 0)
+ set_use_is_fr_complex_2 (cpu, out_FRintk);
+ if (out_FRdoublek >= 0)
+ {
+ set_use_is_fr_complex_2 (cpu, out_FRdoublek);
+ set_use_is_fr_complex_2 (cpu, out_FRdoublek + 1);
+ }
+
+ /* the media point unit resource has a latency of 4 cycles */
+ update_media_resource_latency (cpu, slot, cycles + 4);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_spr, INT out_GRj)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced,
+ in_spr, out_GRj);
+}
+
+int
+frvbf_model_fr550_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRj, INT out_spr)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRj);
+ vliw_wait_for_SPR (cpu, out_spr);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRj);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+
+#if 0
+ /* The latency of spr is ? cycles. */
+ update_SPR_latency (cpu, out_spr, cycles + ?);
+#endif
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRj, INT out_FRk)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet.
+ The latency of the registers may be less than previously recorded,
+ depending on how they were used previously.
+ See Table 14-15 in the LSI. */
+ adjust_float_register_busy (cpu, -1, 1, -1, 1, out_FRk, 1);
+ vliw_wait_for_GR (cpu, in_GRj);
+ vliw_wait_for_FR (cpu, out_FRk);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRj);
+ load_wait_for_FR (cpu, out_FRk);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ /* The latency of FRk is 1 cycles. */
+ cycles = idesc->timing->units[unit_num].done;
+ update_FR_latency (cpu, out_FRk, cycles + 1);
+
+ set_use_is_fr_complex_1 (cpu, out_FRk);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_swap (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj, INT out_GRk)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet. */
+ vliw_wait_for_GR (cpu, in_GRi);
+ vliw_wait_for_GR (cpu, in_GRj);
+ vliw_wait_for_GR (cpu, out_GRk);
+ handle_resource_wait (cpu);
+ load_wait_for_GR (cpu, in_GRi);
+ load_wait_for_GR (cpu, in_GRj);
+ load_wait_for_GR (cpu, out_GRk);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* The latency of GRk will depend on how long it takes to swap
+ the the data from the cache or memory. */
+ update_GR_latency_for_swap (cpu, out_GRk, cycles);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_fr2fr (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRj, INT out_FRk)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet.
+ The latency of the registers may be less than previously recorded,
+ depending on how they were used previously.
+ See Table 14-15 in the LSI. */
+ adjust_float_register_busy (cpu, -1, 1, in_FRj, 1, out_FRk, 1);
+ vliw_wait_for_FR (cpu, in_FRj);
+ vliw_wait_for_FR (cpu, out_FRk);
+ handle_resource_wait (cpu);
+ load_wait_for_FR (cpu, in_FRj);
+ load_wait_for_FR (cpu, out_FRk);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ /* The latency of FRj is 2 cycles. */
+ cycles = idesc->timing->units[unit_num].done;
+ update_FR_latency (cpu, out_FRk, cycles + 2);
+
+ set_use_is_fr_complex_2 (cpu, out_FRk);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRk, INT out_GRj)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* The entire VLIW insn must wait if there is a dependency on a register
+ which is not ready yet.
+ The latency of the registers may be less than previously recorded,
+ depending on how they were used previously.
+ See Table 14-15 in the LSI. */
+ adjust_float_register_busy (cpu, in_FRk, 1, -1, 1, -1, 1);
+ vliw_wait_for_FR (cpu, in_FRk);
+ vliw_wait_for_GR (cpu, out_GRj);
+ handle_resource_wait (cpu);
+ load_wait_for_FR (cpu, in_FRk);
+ load_wait_for_GR (cpu, out_GRj);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ /* The latency of GRj is 1 cycle. */
+ cycles = idesc->timing->units[unit_num].done;
+ update_GR_latency (cpu, out_GRj, cycles + 1);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_clrgr (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRk)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_clrgr (cpu, idesc, unit_num, referenced, in_GRk);
+}
+
+int
+frvbf_model_fr550_u_clrfr (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRk)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_clrfr (cpu, idesc, unit_num, referenced, in_FRk);
+}
+
+int
+frvbf_model_fr550_u_commit (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRk, INT in_FRk)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_commit (cpu, idesc, unit_num, referenced,
+ in_GRk, in_FRk);
+}
+
+int
+frvbf_model_fr550_u_media (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj, INT out_FRk)
+{
+ int cycles;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* If the previous use of the registers was a media op,
+ then their latency may be less than previously recorded.
+ See Table 14-15 in the LSI. */
+ adjust_float_register_busy_for_media (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1);
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ ps = CPU_PROFILE_STATE (cpu);
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+ post_wait_for_FR (cpu, in_FRi);
+ post_wait_for_FR (cpu, in_FRj);
+ post_wait_for_FR (cpu, out_FRk);
+
+ /* Restore the busy cycles of the registers we used. */
+ restore_float_register_busy_for_media (cpu, in_FRi, 1, in_FRj, 1, out_FRk, 1);
+
+ /* The latency of tht output register will be at least the latency of the
+ other inputs. Once initiated, post-processing will take 1 cycle. */
+ if (out_FRk >= 0)
+ {
+ update_FR_latency (cpu, out_FRk, ps->post_wait);
+ update_FR_ptime (cpu, out_FRk, 1);
+ /* Mark this use of the register as a media op. */
+ set_use_is_fr_complex_1 (cpu, out_FRk);
+ }
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_media_quad (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj,
+ INT out_FRk)
+{
+ int cycles;
+ INT dual_FRi;
+ INT dual_FRj;
+ INT dual_FRk;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ dual_FRi = DUAL_REG (in_FRi);
+ dual_FRj = DUAL_REG (in_FRj);
+ dual_FRk = DUAL_REG (out_FRk);
+
+ /* The latency of the registers may be less than previously recorded,
+ depending on how they were used previously.
+ See Table 14-15 in the LSI. */
+ adjust_float_register_busy_for_media (cpu, in_FRi, 2, in_FRj, 2, out_FRk, 2);
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ ps = CPU_PROFILE_STATE (cpu);
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+ post_wait_for_FR (cpu, in_FRi);
+ post_wait_for_FR (cpu, dual_FRi);
+ post_wait_for_FR (cpu, in_FRj);
+ post_wait_for_FR (cpu, dual_FRj);
+ post_wait_for_FR (cpu, out_FRk);
+ post_wait_for_FR (cpu, dual_FRk);
+
+ /* Restore the busy cycles of the registers we used. */
+ restore_float_register_busy_for_media (cpu, in_FRi, 2, in_FRj, 2, out_FRk, 2);
+
+ /* The latency of the output register will be at least the latency of the
+ other inputs. Once initiated, post-processing take 1 cycle. */
+ update_FR_latency (cpu, out_FRk, ps->post_wait);
+ update_FR_ptime (cpu, out_FRk, 1);
+ set_use_is_fr_complex_1 (cpu, out_FRk);
+
+ if (dual_FRk >= 0)
+ {
+ update_FR_latency (cpu, dual_FRk, ps->post_wait);
+ update_FR_ptime (cpu, dual_FRk, 1);
+ set_use_is_fr_complex_1 (cpu, dual_FRk);
+ }
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT out_FRk)
+{
+ int cycles;
+ INT dual_FRk;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* If the previous use of the registers was a media op,
+ then their latency will be less than previously recorded.
+ See Table 14-15 in the LSI. */
+ dual_FRk = DUAL_REG (out_FRk);
+ adjust_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, out_FRk, 2);
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ ps = CPU_PROFILE_STATE (cpu);
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+ post_wait_for_FR (cpu, in_FRi);
+ post_wait_for_FR (cpu, out_FRk);
+ post_wait_for_FR (cpu, dual_FRk);
+
+ /* Restore the busy cycles of the registers we used. */
+ restore_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, out_FRk, 2);
+
+ /* The latency of the output register will be at least the latency of the
+ other inputs. Once initiated, post-processing will take 1 cycle. */
+ update_FR_latency (cpu, out_FRk, ps->post_wait);
+ update_FR_ptime (cpu, out_FRk, 1);
+ set_use_is_fr_complex_1 (cpu, out_FRk);
+
+ if (dual_FRk >= 0)
+ {
+ update_FR_latency (cpu, dual_FRk, ps->post_wait);
+ update_FR_ptime (cpu, dual_FRk, 1);
+ set_use_is_fr_complex_1 (cpu, dual_FRk);
+ }
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT out_FRk)
+{
+ int cycles;
+ INT dual_FRi;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ dual_FRi = DUAL_REG (in_FRi);
+
+ /* The latency of the registers may be less than previously recorded,
+ depending on how they were used previously.
+ See Table 14-15 in the LSI. */
+ adjust_float_register_busy_for_media (cpu, in_FRi, 2, -1, 1, out_FRk, 1);
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ ps = CPU_PROFILE_STATE (cpu);
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+ post_wait_for_FR (cpu, in_FRi);
+ post_wait_for_FR (cpu, dual_FRi);
+ post_wait_for_FR (cpu, out_FRk);
+
+ /* Restore the busy cycles of the registers we used. */
+ restore_float_register_busy_for_media (cpu, in_FRi, 2, -1, 1, out_FRk, 1);
+
+ /* The latency of the output register will be at least the latency of the
+ other inputs. Once initiated, post-processing takes 1 cycle. */
+ update_FR_latency (cpu, out_FRk, ps->post_wait);
+ update_FR_ptime (cpu, out_FRk, 1);
+
+ set_use_is_fr_complex_1 (cpu, out_FRk);
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_media_3_acc (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRj, INT in_ACC40Si,
+ INT out_FRk)
+{
+ int cycles;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* If the previous use of the registers was a media op,
+ then their latency will be less than previously recorded.
+ See Table 14-15 in the LSI. */
+ adjust_float_register_busy_for_media (cpu, -1, 1, in_FRj, 1, out_FRk, 1);
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ ps = CPU_PROFILE_STATE (cpu);
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+ post_wait_for_FR (cpu, in_FRj);
+ post_wait_for_FR (cpu, out_FRk);
+ post_wait_for_ACC (cpu, in_ACC40Si);
+
+ /* Restore the busy cycles of the registers we used. */
+ restore_float_register_busy_for_media (cpu, -1, 1, in_FRj, 1, out_FRk, 1);
+
+ /* The latency of tht output register will be at least the latency of the
+ other inputs. Once initiated, post-processing will take 1 cycle. */
+ update_FR_latency (cpu, out_FRk, ps->post_wait);
+ update_FR_ptime (cpu, out_FRk, 1);
+
+ set_use_is_fr_complex_1 (cpu, out_FRk);
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_media_3_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_ACC40Si, INT out_FRk)
+{
+ int cycles;
+ FRV_PROFILE_STATE *ps;
+ INT ACC40Si_1;
+ INT dual_FRk;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ ACC40Si_1 = DUAL_REG (in_ACC40Si);
+ dual_FRk = DUAL_REG (out_FRk);
+
+ /* If the previous use of the registers was a media op,
+ then their latency will be less than previously recorded.
+ See Table 14-15 in the LSI. */
+ adjust_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 2);
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ ps = CPU_PROFILE_STATE (cpu);
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+ post_wait_for_ACC (cpu, in_ACC40Si);
+ post_wait_for_ACC (cpu, ACC40Si_1);
+ post_wait_for_FR (cpu, out_FRk);
+ post_wait_for_FR (cpu, dual_FRk);
+
+ /* Restore the busy cycles of the registers we used. */
+ restore_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 2);
+
+ /* The latency of the output register will be at least the latency of the
+ other inputs. Once initiated, post-processing will take 1 cycle. */
+ update_FR_latency (cpu, out_FRk, ps->post_wait);
+ update_FR_ptime (cpu, out_FRk, 1);
+ set_use_is_fr_complex_1 (cpu, out_FRk);
+ if (dual_FRk >= 0)
+ {
+ update_FR_latency (cpu, dual_FRk, ps->post_wait);
+ update_FR_ptime (cpu, dual_FRk, 1);
+ set_use_is_fr_complex_1 (cpu, dual_FRk);
+ }
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_media_3_wtacc (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT out_ACC40Sk)
+{
+ int cycles;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ ps = CPU_PROFILE_STATE (cpu);
+
+ /* The latency of the registers may be less than previously recorded,
+ depending on how they were used previously.
+ See Table 14-15 in the LSI. */
+ adjust_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, -1, 1);
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+ post_wait_for_FR (cpu, in_FRi);
+ post_wait_for_ACC (cpu, out_ACC40Sk);
+
+ /* Restore the busy cycles of the registers we used. */
+ restore_float_register_busy_for_media (cpu, in_FRi, 1, -1, 1, -1, 1);
+
+ /* The latency of the output register will be at least the latency of the
+ other inputs. Once initiated, post-processing will take 1 cycle. */
+ update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait);
+ update_ACC_ptime (cpu, out_ACC40Sk, 1);
+ set_use_is_acc_mmac (cpu, out_ACC40Sk);
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_media_3_mclracc (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced)
+{
+ int cycles;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+ int i;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ ps = CPU_PROFILE_STATE (cpu);
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+
+ /* If A was 1 and the accumulator was ACC0, then we must check all
+ accumulators. Otherwise just wait for the specified accumulator. */
+ if (ps->mclracc_A && ps->mclracc_acc == 0)
+ {
+ for (i = 0; i < 8; ++i)
+ post_wait_for_ACC (cpu, i);
+ }
+ else
+ post_wait_for_ACC (cpu, ps->mclracc_acc);
+
+ /* The latency of the output registers will be at least the latency of the
+ other inputs. Once initiated, post-processing will take 1 cycle. */
+ if (ps->mclracc_A && ps->mclracc_acc == 0)
+ {
+ for (i = 0; i < 8; ++i)
+ {
+ update_ACC_latency (cpu, i, ps->post_wait);
+ update_ACC_ptime (cpu, i, 1);
+ set_use_is_acc_mmac (cpu, i);
+ }
+ }
+ else
+ {
+ update_ACC_latency (cpu, ps->mclracc_acc, ps->post_wait);
+ update_ACC_ptime (cpu, ps->mclracc_acc, 1);
+ set_use_is_acc_mmac (cpu, ps->mclracc_acc);
+ }
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_media_set (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT out_FRk)
+{
+ int cycles;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* If the previous use of the registers was a media op,
+ then their latency will be less than previously recorded.
+ See Table 14-15 in the LSI. */
+ adjust_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 1);
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ ps = CPU_PROFILE_STATE (cpu);
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+ post_wait_for_FR (cpu, out_FRk);
+
+ /* Restore the busy cycles of the registers we used. */
+ restore_float_register_busy_for_media (cpu, -1, 1, -1, 1, out_FRk, 1);
+
+ /* The latency of the output register will be at least the latency of the
+ other inputs. Once initiated, post-processing takes 1 cycle. */
+ update_FR_latency (cpu, out_FRk, ps->post_wait);
+ update_FR_ptime (cpu, out_FRk, 1);
+ fr550_reset_acc_flags (cpu, out_FRk);
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_media_4 (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj,
+ INT out_ACC40Sk, INT out_ACC40Uk)
+{
+ int cycles;
+ INT dual_ACC40Sk;
+ INT dual_ACC40Uk;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ ps = CPU_PROFILE_STATE (cpu);
+ dual_ACC40Sk = DUAL_REG (out_ACC40Sk);
+ dual_ACC40Uk = DUAL_REG (out_ACC40Uk);
+
+ /* The latency of the registers may be less than previously recorded,
+ depending on how they were used previously.
+ See Table 14-15 in the LSI. */
+ adjust_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Sk, 2);
+ adjust_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Uk, 2);
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+ post_wait_for_FR (cpu, in_FRi);
+ post_wait_for_FR (cpu, in_FRj);
+ post_wait_for_ACC (cpu, out_ACC40Sk);
+ post_wait_for_ACC (cpu, dual_ACC40Sk);
+ post_wait_for_ACC (cpu, out_ACC40Uk);
+ post_wait_for_ACC (cpu, dual_ACC40Uk);
+
+ /* Restore the busy cycles of the registers we used. */
+ restore_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Sk, 2);
+ restore_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Uk, 2);
+
+ /* The latency of the output register will be at least the latency of the
+ other inputs. Once initiated, post-processing will take 1 cycles. */
+ if (out_ACC40Sk >= 0)
+ {
+ update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+ set_use_is_acc_mmac (cpu, out_ACC40Sk);
+ }
+ if (dual_ACC40Sk >= 0)
+ {
+ update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1);
+ set_use_is_acc_mmac (cpu, dual_ACC40Sk);
+ }
+ if (out_ACC40Uk >= 0)
+ {
+ update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
+ set_use_is_acc_mmac (cpu, out_ACC40Uk);
+ }
+ if (dual_ACC40Uk >= 0)
+ {
+ update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1);
+ set_use_is_acc_mmac (cpu, dual_ACC40Uk);
+ }
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_media_4_acc (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_ACC40Si, INT out_ACC40Sk)
+{
+ int cycles;
+ INT ACC40Si_1;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ ACC40Si_1 = DUAL_REG (in_ACC40Si);
+
+ ps = CPU_PROFILE_STATE (cpu);
+ /* The latency of the registers may be less than previously recorded,
+ depending on how they were used previously.
+ See Table 14-15 in the LSI. */
+ adjust_acc_busy_for_mmac (cpu, in_ACC40Si, 2, out_ACC40Sk, 1);
+
+ /* The post processing must wait if there is a dependency on a register
+ which is not ready yet. */
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+ post_wait_for_ACC (cpu, in_ACC40Si);
+ post_wait_for_ACC (cpu, ACC40Si_1);
+ post_wait_for_ACC (cpu, out_ACC40Sk);
+
+ /* Restore the busy cycles of the registers we used. */
+ restore_acc_busy_for_mmac (cpu, in_ACC40Si, 2, out_ACC40Sk, 1);
+
+ /* The latency of the output register will be at least the latency of the
+ other inputs. Once initiated, post-processing will take 1 cycle. */
+ update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+ set_use_is_acc_mmac (cpu, out_ACC40Sk);
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_ACC40Si, INT out_ACC40Sk)
+{
+ int cycles;
+ INT ACC40Si_1;
+ INT ACC40Si_2;
+ INT ACC40Si_3;
+ INT ACC40Sk_1;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ ACC40Si_1 = DUAL_REG (in_ACC40Si);
+ ACC40Si_2 = DUAL_REG (ACC40Si_1);
+ ACC40Si_3 = DUAL_REG (ACC40Si_2);
+ ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
+
+ ps = CPU_PROFILE_STATE (cpu);
+ /* The latency of the registers may be less than previously recorded,
+ depending on how they were used previously.
+ See Table 14-15 in the LSI. */
+ adjust_acc_busy_for_mmac (cpu, in_ACC40Si, 4, out_ACC40Sk, 2);
+
+ /* The post processing must wait if there is a dependency on a register
+ which is not ready yet. */
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+ post_wait_for_ACC (cpu, in_ACC40Si);
+ post_wait_for_ACC (cpu, ACC40Si_1);
+ post_wait_for_ACC (cpu, ACC40Si_2);
+ post_wait_for_ACC (cpu, ACC40Si_3);
+ post_wait_for_ACC (cpu, out_ACC40Sk);
+ post_wait_for_ACC (cpu, ACC40Sk_1);
+
+ /* Restore the busy cycles of the registers we used. */
+ restore_acc_busy_for_mmac (cpu, in_ACC40Si, 4, out_ACC40Sk, 2);
+
+ /* The latency of the output register will be at least the latency of the
+ other inputs. Once initiated, post-processing will take 1 cycle. */
+ update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+ set_use_is_acc_mmac (cpu, out_ACC40Sk);
+ if (ACC40Sk_1 >= 0)
+ {
+ update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
+ set_use_is_acc_mmac (cpu, ACC40Sk_1);
+ }
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_media_4_add_sub (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_ACC40Si, INT out_ACC40Sk)
+{
+ int cycles;
+ INT ACC40Si_1;
+ INT ACC40Sk_1;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ ACC40Si_1 = DUAL_REG (in_ACC40Si);
+ ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
+
+ ps = CPU_PROFILE_STATE (cpu);
+ /* The latency of the registers may be less than previously recorded,
+ depending on how they were used previously.
+ See Table 14-15 in the LSI. */
+ adjust_acc_busy_for_mmac (cpu, in_ACC40Si, 2, out_ACC40Sk, 2);
+
+ /* The post processing must wait if there is a dependency on a register
+ which is not ready yet. */
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+ post_wait_for_ACC (cpu, in_ACC40Si);
+ post_wait_for_ACC (cpu, ACC40Si_1);
+ post_wait_for_ACC (cpu, out_ACC40Sk);
+ post_wait_for_ACC (cpu, ACC40Sk_1);
+
+ /* Restore the busy cycles of the registers we used. */
+ restore_acc_busy_for_mmac (cpu, in_ACC40Si, 2, out_ACC40Sk, 2);
+
+ /* The latency of the output register will be at least the latency of the
+ other inputs. Once initiated, post-processing will take 1 cycle. */
+ update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+ set_use_is_acc_mmac (cpu, out_ACC40Sk);
+ if (ACC40Sk_1 >= 0)
+ {
+ update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
+ set_use_is_acc_mmac (cpu, ACC40Sk_1);
+ }
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_media_4_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_ACC40Si, INT out_ACC40Sk)
+{
+ int cycles;
+ INT ACC40Si_1;
+ INT ACC40Si_2;
+ INT ACC40Si_3;
+ INT ACC40Sk_1;
+ INT ACC40Sk_2;
+ INT ACC40Sk_3;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ ACC40Si_1 = DUAL_REG (in_ACC40Si);
+ ACC40Si_2 = DUAL_REG (ACC40Si_1);
+ ACC40Si_3 = DUAL_REG (ACC40Si_2);
+ ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
+ ACC40Sk_2 = DUAL_REG (ACC40Sk_1);
+ ACC40Sk_3 = DUAL_REG (ACC40Sk_2);
+
+ ps = CPU_PROFILE_STATE (cpu);
+ /* The latency of the registers may be less than previously recorded,
+ depending on how they were used previously.
+ See Table 14-15 in the LSI. */
+ adjust_acc_busy_for_mmac (cpu, in_ACC40Si, 4, out_ACC40Sk, 4);
+
+ /* The post processing must wait if there is a dependency on a register
+ which is not ready yet. */
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+ post_wait_for_ACC (cpu, in_ACC40Si);
+ post_wait_for_ACC (cpu, ACC40Si_1);
+ post_wait_for_ACC (cpu, ACC40Si_2);
+ post_wait_for_ACC (cpu, ACC40Si_3);
+ post_wait_for_ACC (cpu, out_ACC40Sk);
+ post_wait_for_ACC (cpu, ACC40Sk_1);
+ post_wait_for_ACC (cpu, ACC40Sk_2);
+ post_wait_for_ACC (cpu, ACC40Sk_3);
+
+ /* Restore the busy cycles of the registers we used. */
+ restore_acc_busy_for_mmac (cpu, in_ACC40Si, 4, out_ACC40Sk, 4);
+
+ /* The latency of the output register will be at least the latency of the
+ other inputs. Once initiated, post-processing will take 1 cycle. */
+ update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+ set_use_is_acc_mmac (cpu, out_ACC40Sk);
+ if (ACC40Sk_1 >= 0)
+ {
+ update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
+ set_use_is_acc_mmac (cpu, ACC40Sk_1);
+ }
+ if (ACC40Sk_2 >= 0)
+ {
+ update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1);
+ set_use_is_acc_mmac (cpu, ACC40Sk_2);
+ }
+ if (ACC40Sk_3 >= 0)
+ {
+ update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1);
+ set_use_is_acc_mmac (cpu, ACC40Sk_3);
+ }
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr550_u_media_4_quad (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj,
+ INT out_ACC40Sk, INT out_ACC40Uk)
+{
+ int cycles;
+ INT dual_FRi;
+ INT dual_FRj;
+ INT ACC40Sk_1;
+ INT ACC40Sk_2;
+ INT ACC40Sk_3;
+ INT ACC40Uk_1;
+ INT ACC40Uk_2;
+ INT ACC40Uk_3;
+ FRV_PROFILE_STATE *ps;
+ FRV_VLIW *vliw;
+ int slot;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ dual_FRi = DUAL_REG (in_FRi);
+ dual_FRj = DUAL_REG (in_FRj);
+ ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
+ ACC40Sk_2 = DUAL_REG (ACC40Sk_1);
+ ACC40Sk_3 = DUAL_REG (ACC40Sk_2);
+ ACC40Uk_1 = DUAL_REG (out_ACC40Uk);
+ ACC40Uk_2 = DUAL_REG (ACC40Uk_1);
+ ACC40Uk_3 = DUAL_REG (ACC40Uk_2);
+
+ ps = CPU_PROFILE_STATE (cpu);
+ /* The latency of the registers may be less than previously recorded,
+ depending on how they were used previously.
+ See Table 14-15 in the LSI. */
+ adjust_float_register_busy_for_media (cpu, in_FRi, 2, in_FRj, 2, -1, 1);
+ adjust_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Sk, 4);
+ adjust_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Uk, 4);
+
+ /* The post processing must wait if there is a dependency on a FR
+ which is not ready yet. */
+ ps->post_wait = cycles;
+ vliw = CPU_VLIW (cpu);
+ slot = vliw->next_slot - 1;
+ slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
+ post_wait_for_media (cpu, slot);
+ post_wait_for_FR (cpu, in_FRi);
+ post_wait_for_FR (cpu, dual_FRi);
+ post_wait_for_FR (cpu, in_FRj);
+ post_wait_for_FR (cpu, dual_FRj);
+ post_wait_for_ACC (cpu, out_ACC40Sk);
+ post_wait_for_ACC (cpu, ACC40Sk_1);
+ post_wait_for_ACC (cpu, ACC40Sk_2);
+ post_wait_for_ACC (cpu, ACC40Sk_3);
+ post_wait_for_ACC (cpu, out_ACC40Uk);
+ post_wait_for_ACC (cpu, ACC40Uk_1);
+ post_wait_for_ACC (cpu, ACC40Uk_2);
+ post_wait_for_ACC (cpu, ACC40Uk_3);
+
+ /* Restore the busy cycles of the registers we used. */
+ restore_float_register_busy_for_media (cpu, in_FRi, 2, in_FRj, 2, -1, 1);
+ restore_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Sk, 4);
+ restore_acc_busy_for_mmac (cpu, -1, 1, out_ACC40Uk, 4);
+
+ /* The latency of the output register will be at least the latency of the
+ other inputs. Once initiated, post-processing will take 1 cycle. */
+ if (out_ACC40Sk >= 0)
+ {
+ update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
+
+ set_use_is_acc_mmac (cpu, out_ACC40Sk);
+ if (ACC40Sk_1 >= 0)
+ {
+ update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
+
+ set_use_is_acc_mmac (cpu, ACC40Sk_1);
+ }
+ if (ACC40Sk_2 >= 0)
+ {
+ update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1);
+
+ set_use_is_acc_mmac (cpu, ACC40Sk_2);
+ }
+ if (ACC40Sk_3 >= 0)
+ {
+ update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1);
+
+ set_use_is_acc_mmac (cpu, ACC40Sk_3);
+ }
+ }
+ else if (out_ACC40Uk >= 0)
+ {
+ update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
+
+ set_use_is_acc_mmac (cpu, out_ACC40Uk);
+ if (ACC40Uk_1 >= 0)
+ {
+ update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1);
+
+ set_use_is_acc_mmac (cpu, ACC40Uk_1);
+ }
+ if (ACC40Uk_2 >= 0)
+ {
+ update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1);
+
+ set_use_is_acc_mmac (cpu, ACC40Uk_2);
+ }
+ if (ACC40Uk_3 >= 0)
+ {
+ update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1);
+
+ set_use_is_acc_mmac (cpu, ACC40Uk_3);
+ }
+ }
+
+ /* the floating point unit resource has a latency of 3 cycles */
+ update_float_resource_latency (cpu, slot, cycles + 3);
+
+ return cycles;
+}
+
+#endif /* WITH_PROFILE_MODEL_P */
diff --git a/sim/frv/profile-fr550.h b/sim/frv/profile-fr550.h
new file mode 100644
index 0000000..0a1659b
--- /dev/null
+++ b/sim/frv/profile-fr550.h
@@ -0,0 +1,27 @@
+/* Profiling definitions for the fr550 model of the FRV simulator
+ Copyright (C) 2003 Free Software Foundation, Inc.
+ Contributed by Red Hat.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef PROFILE_FR550_H
+#define PROFILE_FR550_H
+
+void fr550_model_insn_before (SIM_CPU *, int);
+void fr550_model_insn_after (SIM_CPU *, int, int);
+
+#endif /* PROFILE_FR550_H */
diff --git a/sim/frv/profile.c b/sim/frv/profile.c
index 2eadef4..3a3d1aa 100644
--- a/sim/frv/profile.c
+++ b/sim/frv/profile.c
@@ -31,6 +31,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "profile.h"
#include "profile-fr400.h"
#include "profile-fr500.h"
+#include "profile-fr550.h"
static void
reset_gr_flags (SIM_CPU *cpu, INT gr)
@@ -677,6 +678,8 @@ update_latencies (SIM_CPU *cpu, int cycles)
int *fdiv;
int *fsqrt;
int *idiv;
+ int *flt;
+ int *media;
int *ccr;
int *gr = ps->gr_busy;
int *fr = ps->fr_busy;
@@ -758,6 +761,16 @@ update_latencies (SIM_CPU *cpu, int cycles)
++fdiv;
++fsqrt;
}
+ /* Float and media units can occur in 4 slots on some machines. */
+ flt = ps->float_busy;
+ media = ps->media_busy;
+ for (i = 0; i < 4; ++i)
+ {
+ *flt = (*flt <= cycles) ? 0 : (*flt - cycles);
+ *media = (*media <= cycles) ? 0 : (*media - cycles);
+ ++flt;
+ ++media;
+ }
}
/* Print information about the wait for the given number of cycles. */
@@ -918,6 +931,9 @@ frvbf_model_insn_before (SIM_CPU *cpu, int first_p)
case bfd_mach_fr500:
fr500_model_insn_before (cpu, first_p);
break;
+ case bfd_mach_fr550:
+ fr550_model_insn_before (cpu, first_p);
+ break;
default:
break;
}
@@ -981,6 +997,9 @@ frvbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
case bfd_mach_fr500:
fr500_model_insn_after (cpu, last_p, cycles);
break;
+ case bfd_mach_fr550:
+ fr550_model_insn_after (cpu, last_p, cycles);
+ break;
default:
break;
}
@@ -1242,7 +1261,6 @@ decrease_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles)
}
}
-/* start-sanitize-frv */
void
increase_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles)
{
@@ -1261,7 +1279,6 @@ enforce_full_acc_latency (SIM_CPU *cpu, INT in_ACC)
ps->acc_busy_adjust [in_ACC] = -1;
}
-/* end-sanitize-frv */
void
decrease_FR_busy (SIM_CPU *cpu, INT out_FR, int cycles)
{
@@ -1360,6 +1377,27 @@ update_fsqrt_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
r[in_resource] = cycles;
}
+/* Set the latency of the given resource to the given number of cycles. */
+void
+update_float_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
+{
+ /* operate directly on the busy cycles since each resource can only
+ be used once in a VLIW insn. */
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ int *r = ps->float_busy;
+ r[in_resource] = cycles;
+}
+
+void
+update_media_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
+{
+ /* operate directly on the busy cycles since each resource can only
+ be used once in a VLIW insn. */
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ int *r = ps->media_busy;
+ r[in_resource] = cycles;
+}
+
/* Set the branch penalty to the given number of cycles. */
void
update_branch_penalty (SIM_CPU *cpu, int cycles)
@@ -1572,6 +1610,46 @@ vliw_wait_for_fsqrt_resource (SIM_CPU *cpu, INT in_resource)
}
}
+/* Check the availability of the given float unit resource and update
+ the number of cycles the current VLIW insn must wait until it is available.
+*/
+void
+vliw_wait_for_float_resource (SIM_CPU *cpu, INT in_resource)
+{
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ int *r = ps->float_busy;
+ /* If the latency of the resource is greater than the current wait
+ then update the current wait. */
+ if (r[in_resource] > ps->vliw_wait)
+ {
+ if (TRACE_INSN_P (cpu))
+ {
+ sprintf (hazard_name, "Resource hazard for floating point unit in slot F%d:", in_resource);
+ }
+ ps->vliw_wait = r[in_resource];
+ }
+}
+
+/* Check the availability of the given media unit resource and update
+ the number of cycles the current VLIW insn must wait until it is available.
+*/
+void
+vliw_wait_for_media_resource (SIM_CPU *cpu, INT in_resource)
+{
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ int *r = ps->media_busy;
+ /* If the latency of the resource is greater than the current wait
+ then update the current wait. */
+ if (r[in_resource] > ps->vliw_wait)
+ {
+ if (TRACE_INSN_P (cpu))
+ {
+ sprintf (hazard_name, "Resource hazard for media unit in slot M%d:", in_resource);
+ }
+ ps->vliw_wait = r[in_resource];
+ }
+}
+
/* Run the caches until all requests for the given register(s) are satisfied. */
void
load_wait_for_GR (SIM_CPU *cpu, INT in_GR)
@@ -1824,6 +1902,42 @@ post_wait_for_fsqrt (SIM_CPU *cpu, INT slot)
}
}
+int
+post_wait_for_float (SIM_CPU *cpu, INT slot)
+{
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ int *flt = ps->float_busy;
+
+ /* Multiple floating point square roots in the same slot need only wait 1
+ extra cycle. */
+ if (flt[slot] > ps->post_wait)
+ {
+ ps->post_wait = flt[slot];
+ if (TRACE_INSN_P (cpu))
+ {
+ sprintf (hazard_name, "Resource hazard for floating point unit in slot F%d:", slot);
+ }
+ }
+}
+
+int
+post_wait_for_media (SIM_CPU *cpu, INT slot)
+{
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ int *media = ps->media_busy;
+
+ /* Multiple floating point square roots in the same slot need only wait 1
+ extra cycle. */
+ if (media[slot] > ps->post_wait)
+ {
+ ps->post_wait = media[slot];
+ if (TRACE_INSN_P (cpu))
+ {
+ sprintf (hazard_name, "Resource hazard for media unit in slot M%d:", slot);
+ }
+ }
+}
+
/* Print cpu-specific profile information. */
#define COMMAS(n) sim_add_commas (comma_buf, sizeof (comma_buf), (n))
@@ -1863,8 +1977,8 @@ static char *
slot_names[] =
{
"none",
- "I0", "I1", "I01", "IALL",
- "FM0", "FM1", "FM01", "FMALL", "FMLOW",
+ "I0", "I1", "I01", "I2", "I3", "IALL",
+ "FM0", "FM1", "FM01", "FM2", "FM3", "FMALL", "FMLOW",
"B0", "B1", "B01",
"C"
};
diff --git a/sim/frv/profile.h b/sim/frv/profile.h
index 5570a5a..4c6e558 100644
--- a/sim/frv/profile.h
+++ b/sim/frv/profile.h
@@ -45,6 +45,8 @@ typedef struct
int idiv_busy[2]; /* Cycles until integer division unit is available. */
int fdiv_busy[2]; /* Cycles until float division unit is available. */
int fsqrt_busy[2]; /* Cycles until square root unit is available. */
+ int float_busy[4]; /* Cycles until floating point unit is available. */
+ int media_busy[4]; /* Cycles until media unit is available. */
int branch_penalty; /* Cycles until branch is complete. */
int gr_latency[64]; /* Cycles until target GR is available. */
@@ -72,6 +74,8 @@ typedef struct
int branch_hint; /* hint field from branch insn. */
USI branch_address; /* Address of predicted branch. */
USI insn_fetch_address;/* Address of sequential insns fetched. */
+ int mclracc_acc; /* ACC number of register cleared by mclracc. */
+ int mclracc_A; /* A field of mclracc. */
/* We need to know when the first branch of a vliw insn is taken, so that
we don't consider the remaining branches in the vliw insn. */
@@ -117,12 +121,15 @@ void decrease_ACC_busy (SIM_CPU *, INT, int);
void decrease_FR_busy (SIM_CPU *, INT, int);
void decrease_GR_busy (SIM_CPU *, INT, int);
void increase_FR_busy (SIM_CPU *, INT, int);
+void increase_ACC_busy (SIM_CPU *, INT, int);
void update_ACC_latency (SIM_CPU *, INT, int);
void update_CCR_latency (SIM_CPU *, INT, int);
void update_SPR_latency (SIM_CPU *, INT, int);
void update_idiv_resource_latency (SIM_CPU *, INT, int);
void update_fdiv_resource_latency (SIM_CPU *, INT, int);
void update_fsqrt_resource_latency (SIM_CPU *, INT, int);
+void update_float_resource_latency (SIM_CPU *, INT, int);
+void update_media_resource_latency (SIM_CPU *, INT, int);
void update_branch_penalty (SIM_CPU *, int);
void update_ACC_ptime (SIM_CPU *, INT, int);
void update_SPR_ptime (SIM_CPU *, INT, int);
@@ -136,11 +143,14 @@ void vliw_wait_for_SPR (SIM_CPU *, INT);
void vliw_wait_for_idiv_resource (SIM_CPU *, INT);
void vliw_wait_for_fdiv_resource (SIM_CPU *, INT);
void vliw_wait_for_fsqrt_resource (SIM_CPU *, INT);
+void vliw_wait_for_float_resource (SIM_CPU *, INT);
+void vliw_wait_for_media_resource (SIM_CPU *, INT);
void load_wait_for_GR (SIM_CPU *, INT);
void load_wait_for_FR (SIM_CPU *, INT);
void load_wait_for_GRdouble (SIM_CPU *, INT);
void load_wait_for_FRdouble (SIM_CPU *, INT);
void enforce_full_fr_latency (SIM_CPU *, INT);
+void enforce_full_acc_latency (SIM_CPU *, INT);
int post_wait_for_FR (SIM_CPU *, INT);
int post_wait_for_FRdouble (SIM_CPU *, INT);
int post_wait_for_ACC (SIM_CPU *, INT);
@@ -148,6 +158,8 @@ int post_wait_for_CCR (SIM_CPU *, INT);
int post_wait_for_SPR (SIM_CPU *, INT);
int post_wait_for_fdiv (SIM_CPU *, INT);
int post_wait_for_fsqrt (SIM_CPU *, INT);
+int post_wait_for_float (SIM_CPU *, INT);
+int post_wait_for_media (SIM_CPU *, INT);
void trace_vliw_wait_cycles (SIM_CPU *);
void handle_resource_wait (SIM_CPU *);
diff --git a/sim/frv/registers.c b/sim/frv/registers.c
index 2b76630..685e53f 100644
--- a/sim/frv/registers.c
+++ b/sim/frv/registers.c
@@ -165,10 +165,13 @@ static FRV_SPR_CONTROL_INFO frv_spr[] =
{0x00000000, 0x00000000, 0x00000000, 0x00000003, IMPL, USER}, /* LR */
{0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */
- /* spr registers 274-287 are reserved */
+ /* spr registers 274-279 and 282-287 are reserved. */
+ /* spr registers 280 and 281 are iacc0h and iacc0l (fr405). */
RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
- RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0H */
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0L */
+ RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED,
{0xe0000021, 0x20000000, 0xe0000000, 0xffffffc2, IMPL, USER}, /* ISR */
@@ -3055,6 +3058,1166 @@ static FRV_SPR_CONTROL_INFO fr500_spr[] =
RESERVED
};
+/* SPR definitions for the fr550 machine.
+ See the FR550 LSI for implementation details. */
+static FRV_SPR_CONTROL_INFO fr550_spr[] =
+{
+ {0x3000107e, 0x3000107c, 0xff0071fd, 0xffff9e00, IMPL, SUP}, /* PSR */
+ {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, SUP}, /* PCSR */
+ {0x00000000, 0x00000000, 0xffffffff, 0x00000003, IMPL, SUP}, /* BPCSR */
+ {0x00000000, 0x00000000, 0x0000000f, 0x000007ff, IMPL, SUP}, /* TBR */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffeffe, IMPL, SUP}, /* BPSR */
+
+ /* spr registers 5-15 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED,
+
+ {0x000003c0, 0x00000000, 0xce000c00, 0x313fec38, IMPL, SUP}, /* HSR0 */
+
+ /* HSR1-63 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 80-255 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* CCR */
+
+ /* spr registers 257-262 are reserved */
+ RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffff0000, IMPL, USER}, /* CCCR */
+
+ /* spr registers 264-271 are reserved */
+ RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, USER}, /* LR */
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */
+
+ /* spr registers 274-287 are reserved */
+ RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ {0x20000030, 0x20000000, 0xa0000000, 0xffffffd3, IMPL, USER}, /* ISR */
+
+ /* spr registers 289-351 are reserved */
+ RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ /* NEEAR0-31 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ /* NESR0-31 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ /* NECR is unimplemented on the fr550. */
+ RESERVED,
+
+ /* spr registers 417-431 are reserved */
+ RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* GNER0 */
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* GNER1 */
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* FNER0 */
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* FNER1 */
+
+ /* spr registers 436-511 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR0 */
+ RESERVED,
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR2 */
+
+ /* EPCR3-7 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR8 */
+
+ /* EPCR9-63 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED,
+
+ {0x00000100, 0x00000100, 0x00000100, 0xffffffff, IMPL, SUP}, /* ESR0 */
+ RESERVED,
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR2 */
+
+ /* ESR3-7 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ {0x00000200, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR8 */
+
+ /* ESR9-13 are unimplemented on the fr550. */
+ RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR14 */
+ {0x00000020, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+
+ /* ESR16-63 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* EIR0-31 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ /* ESFR0 is unimplemented on the fr550. */
+ RESERVED,
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESFR1 */
+
+ /* spr registers 674-767 are reserved */
+ RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ /* SR0-SR3 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 772-1023 are reserved */
+ RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00800000, 0x00800000, 0xc0e00000, 0xc0fe03ff, IMPL, USER}, /* FSR0 */
+
+ /* FSR1-63 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ /* FQ0-31 are unimplemented on the fr550. */
+ /* Each FQ register is a pair of 32 bit registers. */
+ RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ /* spr registers 1152-1271 are reserved */
+ RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ /* MCILR0-1 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+
+ /* spr registers 1274-1279 are reserved */
+ RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00001002, 0x00000000, 0x01e00000, 0x07ffffc2, IMPL, USER}, /* MSR0 */
+
+ /* MSR1-63 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* MQ0-31 are unimplemented on the fr550. */
+ /* Each MQ register is a pair of 32 bit registers. */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* Accumulators are read-only by the user except for special
+ insns and side effect of other insns. */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC0 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC7 */
+
+ /* ACC8-63 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* Accumulator guards are read-only by the user except for special
+ insns and side effect of other insns. */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG0 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG7 */
+
+ /* ACCG8-63 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* EAR0-7 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR8 */
+
+ /* EAR9-14 are unimplemented on the fr550. */
+ RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR15 */
+
+ /* EAR16-63 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* EDR0-63 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* IAMLR0 */
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* IAMLR8 */
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* IAMLR15 */
+
+ /* IAMLR16-63 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* IAMPR0 */
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* IAMPR8 */
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* IAMPR15 */
+
+ /* IAMPR16-63 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* DAMLR0 */
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* DAMLR8 */
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* DAMLR15 */
+
+ /* DAMLR16-63 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* DAMPR0 */
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* DAMPR8 */
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* DAMPR15 */
+
+ /* DAMPR16-63 are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00001010, 0x00001010, 0x0000ffff, 0xffffffff, IMPL, SUP}, /* AMCR */
+
+ /* STBAR, MMCR not implemented on the fr550. */
+ RESERVED, RESERVED,
+
+ /* spr registers 1923-2047 are reserved */
+ RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DCR */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* BRR */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* NMAR */
+
+ RESERVED, /* spr register 2051 */
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR0 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR3 */
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR0 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR3 */
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR00 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+
+ /* DBDR02-03 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR10 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+
+ /* DBDR12-13 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR20 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+
+ /* DBDR22-23 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR30 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+
+ /* DBDR32-33 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR00 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+
+ /* DBMR02-03 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR10 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+
+ /* DBMR12-13 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR20 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+
+ /* DBMR22-23 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR30 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+
+ /* DBMR32-33 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+
+ /* CPCFR, CPCR and CPSR are unimplemented on the fr550. */
+ RESERVED, RESERVED, RESERVED,
+
+ RESERVED, /* spr register 2095 */
+
+ /* CPESR0-1 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+
+ /* CPEMR0-1 are unimplemented on the fr550. */
+ RESERVED, RESERVED,
+
+ /* spr registers 2100-2199 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 2200-2299 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 2300-2399 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 2400-2499 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 2500-2599 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 2600-2699 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 2700-2799 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 2800-2899 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 2900-2999 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 3000-3099 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 3100-3199 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 3200-3299 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 3300-3399 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 3400-3499 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 3500-3599 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 3600-3699 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 3700-3799 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ /* spr registers 3800-3847 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ {0x00000001, 0x00000000, 0x00000000, 0xffff88fd, IMPL, SUP}, /* IHSR8 */
+
+ /* spr registers 3849-4095 are reserved */
+ RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED
+};
+
/* SPR definitions for the fr400 machine.
See the FR400 LSI for implementation details. */
static FRV_SPR_CONTROL_INFO fr400_spr[] =
@@ -3141,10 +4304,13 @@ static FRV_SPR_CONTROL_INFO fr400_spr[] =
{0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, USER}, /* LR */
{0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */
- /* spr registers 274-287 are reserved */
+ /* spr registers 274-279 and 282-287 are reserved. */
+ /* spr registers 280 and 281 are iacc0h and iacc0l (fr405). */
RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
- RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0H */
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0L */
+ RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED,
{0x20000021, 0x20000000, 0xa0000000, 0xffffffc2, IMPL, USER}, /* ISR */
@@ -4147,6 +5313,8 @@ frv_register_control_init (SIM_CPU *cpu)
abort ();
if (sizeof (fr500_spr) != FRV_MAX_SPR * sizeof (*fr500_spr))
abort ();
+ if (sizeof (fr550_spr) != FRV_MAX_SPR * sizeof (*fr550_spr))
+ abort ();
if (sizeof (frv_spr) != FRV_MAX_SPR * sizeof (*frv_spr))
abort ();
@@ -4158,6 +5326,11 @@ frv_register_control_init (SIM_CPU *cpu)
control->cpr = 0;
control->spr = fr500_spr;
return;
+ case bfd_mach_fr550:
+ control->fr = 1;
+ control->cpr = 0;
+ control->spr = fr550_spr;
+ return;
case bfd_mach_fr400:
control->fr = 1;
control->cpr = 0;
@@ -4273,20 +5446,22 @@ frv_check_spr_read_access (SIM_CPU *current_cpu, UINT spr)
if (! control->spr[spr].implemented)
{
SIM_DESC sd = CPU_STATE (current_cpu);
- if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+ switch (STATE_ARCHITECTURE (sd)->mach)
{
+ case bfd_mach_fr400:
/* On the fr400: if this is an unimplemented accumulator, then
generate an illegal_instruction_interrupt, otherwise no interrupt.
*/
if (spr >= H_SPR_ACC4 && spr <= H_SPR_ACC63
|| spr >= H_SPR_ACCG4 && spr <= H_SPR_ACCG63)
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
- }
- else
- {
- /* On other machines, it's a register_exception. */
- frv_queue_register_exception_interrupt (current_cpu,
- FRV_REC_UNIMPLEMENTED);
+ break;
+ case bfd_mach_fr550:
+ /* No interrupt on the fr550 */
+ break;
+ default:
+ frv_queue_register_exception_interrupt (current_cpu, FRV_REC_UNIMPLEMENTED);
+ break;
}
}
}
@@ -4364,16 +5539,17 @@ frv_check_register_access (
/* The register is not available. Generate an exception. */
sd = CPU_STATE (current_cpu);
- if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+ switch (STATE_ARCHITECTURE (sd)->mach)
{
- /* On the fr400 this generates an illegal_instruction interrupt. */
+ case bfd_mach_fr400:
+ case bfd_mach_fr550:
+ /* On some machines this generates an illegal_instruction interrupt. */
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
- }
- else
- {
+ break;
+ default:
/* On other machines, it's a register_exception. */
- frv_queue_register_exception_interrupt (current_cpu,
- FRV_REC_UNIMPLEMENTED);
+ frv_queue_register_exception_interrupt (current_cpu, FRV_REC_UNIMPLEMENTED);
+ break;
}
return 0;
}
diff --git a/sim/frv/sem.c b/sim/frv/sem.c
index f6356c3..f403a50 100644
--- a/sim/frv/sem.c
+++ b/sim/frv/sem.c
@@ -311,7 +311,7 @@ SEM_FN_NAME (frvbf,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
static SEM_PC
SEM_FN_NAME (frvbf,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_addcc.f
+#define FLD(f) abuf->fields.sfmt_scutss.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
@@ -449,6 +449,69 @@ SEM_FN_NAME (frvbf,umul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* smu: smu$pack $GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,smu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))));
+ sim_queue_fn_di_write (current_cpu, frvbf_h_iacc0_set, ((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "iacc0", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* smass: smass$pack $GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,smass) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = (ANDIF (ANDIF (GTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), GTDI (GET_H_IACC0 (((UINT) 0)), 0)), LTDI (SUBDI (9223372036854775807, MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (2147483647, 0xffffffff)) : (ANDIF (ANDIF (LTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), LTDI (GET_H_IACC0 (((UINT) 0)), 0)), GTDI (SUBDI (9223372036854775808, MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (0x80000000, 0)) : (ADDDI (GET_H_IACC0 (((UINT) 0)), MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))));
+ sim_queue_fn_di_write (current_cpu, frvbf_h_iacc0_set, ((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "iacc0", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* smsss: smsss$pack $GRi,$GRj */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,smsss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = (ANDIF (ANDIF (LTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), GTDI (GET_H_IACC0 (((UINT) 0)), 0)), LTDI (ADDDI (9223372036854775807, MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (2147483647, 0xffffffff)) : (ANDIF (ANDIF (GTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), LTDI (GET_H_IACC0 (((UINT) 0)), 0)), GTDI (ADDDI (9223372036854775808, MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (0x80000000, 0)) : (SUBDI (GET_H_IACC0 (((UINT) 0)), MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))));
+ sim_queue_fn_di_write (current_cpu, frvbf_h_iacc0_set, ((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "iacc0", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* sll: sll$pack $GRi,$GRj,$GRk */
static SEM_PC
@@ -512,6 +575,48 @@ SEM_FN_NAME (frvbf,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* slass: slass$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,slass) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = frvbf_shift_left_arith_saturate (current_cpu, GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+ sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* scutss: scutss$pack $GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,scutss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_scutss.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = frvbf_iacc_cut (current_cpu, GET_H_IACC0 (((UINT) 0)), GET_H_GR (FLD (f_GRj)));
+ sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* scan: scan$pack $GRi,$GRj,$GRk */
static SEM_PC
@@ -1949,6 +2054,66 @@ if (LTSI (tmp_tmp, 0)) {
#undef FLD
}
+/* addss: addss$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,addss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+ sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+if (ADDOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0)) {
+ {
+ SI opval = (GTSI (GET_H_GR (FLD (f_GRi)), 0)) ? (2147483647) : (LTSI (GET_H_GR (FLD (f_GRi)), 0)) ? (0x80000000) : (0);
+ sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* subss: subss$pack $GRi,$GRj,$GRk */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,subss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = SUBSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+ sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+if (SUBOFSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)), 0)) {
+ {
+ SI opval = (GTSI (GET_H_GR (FLD (f_GRi)), 0)) ? (2147483647) : (LTSI (GET_H_GR (FLD (f_GRi)), 0)) ? (0x80000000) : (0);
+ sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
/* addi: addi$pack $GRi,$s12,$GRk */
static SEM_PC
@@ -7515,6 +7680,7 @@ SEM_FN_NAME (frvbf,swap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SI tmp_address;
tmp_tmp = GET_H_GR (FLD (f_GRk));
tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_check_swap_address (current_cpu, tmp_address);
{
SI opval = frvbf_read_mem_WI (current_cpu, pc, tmp_address);
sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
@@ -7543,6 +7709,7 @@ SEM_FN_NAME (frvbf,swapi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SI tmp_address;
tmp_tmp = GET_H_GR (FLD (f_GRk));
tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
+frvbf_check_swap_address (current_cpu, tmp_address);
{
SI opval = frvbf_read_mem_WI (current_cpu, pc, tmp_address);
sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
@@ -7572,6 +7739,7 @@ if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
SI tmp_address;
tmp_tmp = GET_H_GR (FLD (f_GRk));
tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj)));
+frvbf_check_swap_address (current_cpu, tmp_address);
{
SI opval = frvbf_read_mem_WI (current_cpu, pc, tmp_address);
sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, FLD (f_GRk), opval);
@@ -22679,6 +22847,8 @@ SEM_FN_NAME (frvbf,maddaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Si))) {
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Si), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -22690,7 +22860,7 @@ if (GTDI (tmp_tmp, 549755813887)) {
{
DI opval = 549755813887;
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 3);
+ written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -22701,7 +22871,7 @@ if (LTDI (tmp_tmp, INVDI (549755813887))) {
{
DI opval = INVDI (549755813887);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 3);
+ written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -22710,13 +22880,15 @@ frvbf_media_overflow (current_cpu, 8);
{
DI opval = tmp_tmp;
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 3);
+ written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
}
}
}
}
+}
+}
abuf->written = written;
return vpc;
@@ -22734,6 +22906,8 @@ SEM_FN_NAME (frvbf,msubaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Si))) {
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Si), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -22745,7 +22919,7 @@ if (GTDI (tmp_tmp, 549755813887)) {
{
DI opval = 549755813887;
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 3);
+ written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -22756,7 +22930,7 @@ if (LTDI (tmp_tmp, INVDI (549755813887))) {
{
DI opval = INVDI (549755813887);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 3);
+ written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -22765,13 +22939,15 @@ frvbf_media_overflow (current_cpu, 8);
{
DI opval = tmp_tmp;
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 3);
+ written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
}
}
}
}
+}
+}
abuf->written = written;
return vpc;
@@ -22789,6 +22965,8 @@ SEM_FN_NAME (frvbf,mdaddaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Si))) {
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Si), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -22867,6 +23045,8 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
+}
abuf->written = written;
return vpc;
@@ -22884,6 +23064,8 @@ SEM_FN_NAME (frvbf,mdsubaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Si))) {
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Si), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -22962,6 +23144,8 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
+}
abuf->written = written;
return vpc;
@@ -22979,6 +23163,8 @@ SEM_FN_NAME (frvbf,masaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Si))) {
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Si), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -23057,6 +23243,8 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
+}
abuf->written = written;
return vpc;
@@ -23074,6 +23262,8 @@ SEM_FN_NAME (frvbf,mdasaccs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Si))) {
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Si), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -23220,6 +23410,8 @@ frvbf_media_overflow (current_cpu, 1);
}
}
}
+}
+}
abuf->written = written;
return vpc;
@@ -23237,6 +23429,7 @@ SEM_FN_NAME (frvbf,mmulhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -23265,6 +23458,7 @@ frvbf_media_acc_not_aligned (current_cpu);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -23282,6 +23476,7 @@ SEM_FN_NAME (frvbf,mmulhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -23310,6 +23505,7 @@ frvbf_media_acc_not_aligned (current_cpu);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -23327,6 +23523,7 @@ SEM_FN_NAME (frvbf,mmulxhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -23355,6 +23552,7 @@ frvbf_media_acc_not_aligned (current_cpu);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -23372,6 +23570,7 @@ SEM_FN_NAME (frvbf,mmulxhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -23400,6 +23599,7 @@ frvbf_media_acc_not_aligned (current_cpu);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -23417,6 +23617,7 @@ SEM_FN_NAME (frvbf,cmmulhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -23447,6 +23648,7 @@ if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
}
}
}
+}
abuf->written = written;
return vpc;
@@ -23464,6 +23666,7 @@ SEM_FN_NAME (frvbf,cmmulhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -23494,6 +23697,7 @@ if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
}
}
}
+}
abuf->written = written;
return vpc;
@@ -23511,6 +23715,7 @@ SEM_FN_NAME (frvbf,mqmulhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -23561,6 +23766,7 @@ frvbf_media_register_not_aligned (current_cpu);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -23578,6 +23784,7 @@ SEM_FN_NAME (frvbf,mqmulhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -23628,6 +23835,7 @@ frvbf_media_register_not_aligned (current_cpu);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -23645,6 +23853,7 @@ SEM_FN_NAME (frvbf,mqmulxhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -23695,6 +23904,7 @@ frvbf_media_register_not_aligned (current_cpu);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -23712,6 +23922,7 @@ SEM_FN_NAME (frvbf,mqmulxhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -23762,6 +23973,7 @@ frvbf_media_register_not_aligned (current_cpu);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -23779,6 +23991,7 @@ SEM_FN_NAME (frvbf,cmqmulhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -23831,6 +24044,7 @@ if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
}
}
}
+}
abuf->written = written;
return vpc;
@@ -23848,6 +24062,7 @@ SEM_FN_NAME (frvbf,cmqmulhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -23900,6 +24115,7 @@ if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
}
}
}
+}
abuf->written = written;
return vpc;
@@ -23917,6 +24133,7 @@ SEM_FN_NAME (frvbf,mmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -24001,6 +24218,7 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -24018,6 +24236,7 @@ SEM_FN_NAME (frvbf,mmachu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Uk))) {
if (ANDSI (FLD (f_ACC40Uk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -24102,6 +24321,7 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -24119,6 +24339,7 @@ SEM_FN_NAME (frvbf,mmrdhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -24203,6 +24424,7 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -24220,6 +24442,7 @@ SEM_FN_NAME (frvbf,mmrdhu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Uk))) {
if (ANDSI (FLD (f_ACC40Uk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -24304,6 +24527,7 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -24321,6 +24545,7 @@ SEM_FN_NAME (frvbf,cmmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -24407,6 +24632,7 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -24424,6 +24650,7 @@ SEM_FN_NAME (frvbf,cmmachu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Uk))) {
if (ANDSI (FLD (f_ACC40Uk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -24510,6 +24737,7 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -24527,6 +24755,7 @@ SEM_FN_NAME (frvbf,mqmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -24689,6 +24918,7 @@ frvbf_media_overflow (current_cpu, 1);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -24706,6 +24936,7 @@ SEM_FN_NAME (frvbf,mqmachu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Uk))) {
if (ANDSI (FLD (f_ACC40Uk), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -24868,6 +25099,7 @@ frvbf_media_overflow (current_cpu, 1);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -24885,6 +25117,7 @@ SEM_FN_NAME (frvbf,cmqmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -25049,6 +25282,7 @@ frvbf_media_overflow (current_cpu, 1);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -25066,6 +25300,7 @@ SEM_FN_NAME (frvbf,cmqmachu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Uk))) {
if (ANDSI (FLD (f_ACC40Uk), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -25230,6 +25465,7 @@ frvbf_media_overflow (current_cpu, 1);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -25247,6 +25483,7 @@ SEM_FN_NAME (frvbf,mqxmachs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -25409,6 +25646,7 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -25426,6 +25664,7 @@ SEM_FN_NAME (frvbf,mqxmacxhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -25588,6 +25827,7 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -25605,6 +25845,7 @@ SEM_FN_NAME (frvbf,mqmacxhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (4, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -25767,6 +26008,7 @@ frvbf_media_overflow (current_cpu, 1);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -25784,6 +26026,7 @@ SEM_FN_NAME (frvbf,mcpxrs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
{
HI tmp_argihi;
HI tmp_argilo;
@@ -25806,7 +26049,7 @@ if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) {
{
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 8);
+ written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -25817,7 +26060,7 @@ if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) {
{
DI opval = MAKEDI (0xffffff80, 0);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 8);
+ written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -25826,13 +26069,14 @@ frvbf_media_overflow (current_cpu, 8);
{
DI opval = tmp_tmp1;
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 8);
+ written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
}
}
}
}
+}
abuf->written = written;
return vpc;
@@ -25850,6 +26094,7 @@ SEM_FN_NAME (frvbf,mcpxru) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
{
UHI tmp_argihi;
UHI tmp_argilo;
@@ -25872,7 +26117,7 @@ if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) {
{
DI opval = MAKEDI (255, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 8);
+ written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -25883,7 +26128,7 @@ if (LTDI (tmp_tmp1, MAKEDI (0, 0))) {
{
DI opval = MAKEDI (0, 0);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 8);
+ written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -25892,13 +26137,14 @@ frvbf_media_overflow (current_cpu, 8);
{
DI opval = tmp_tmp1;
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 8);
+ written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
}
}
}
}
+}
abuf->written = written;
return vpc;
@@ -25916,6 +26162,7 @@ SEM_FN_NAME (frvbf,mcpxis) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
{
HI tmp_argihi;
HI tmp_argilo;
@@ -25938,7 +26185,7 @@ if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) {
{
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 8);
+ written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -25949,7 +26196,7 @@ if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) {
{
DI opval = MAKEDI (0xffffff80, 0);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 8);
+ written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -25958,13 +26205,14 @@ frvbf_media_overflow (current_cpu, 8);
{
DI opval = tmp_tmp1;
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 8);
+ written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
}
}
}
}
+}
abuf->written = written;
return vpc;
@@ -25982,6 +26230,7 @@ SEM_FN_NAME (frvbf,mcpxiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
{
UHI tmp_argihi;
UHI tmp_argilo;
@@ -26004,7 +26253,7 @@ if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) {
{
DI opval = MAKEDI (255, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 8);
+ written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -26015,7 +26264,7 @@ if (LTDI (tmp_tmp1, MAKEDI (0, 0))) {
{
DI opval = MAKEDI (0, 0);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 8);
+ written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -26024,13 +26273,14 @@ frvbf_media_overflow (current_cpu, 8);
{
DI opval = tmp_tmp1;
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 8);
+ written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
}
}
}
}
+}
abuf->written = written;
return vpc;
@@ -26049,6 +26299,7 @@ SEM_FN_NAME (frvbf,cmcpxrs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
{
HI tmp_argihi;
HI tmp_argilo;
@@ -26071,7 +26322,7 @@ if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) {
{
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 10);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -26082,7 +26333,7 @@ if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) {
{
DI opval = MAKEDI (0xffffff80, 0);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 10);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -26091,7 +26342,7 @@ frvbf_media_overflow (current_cpu, 8);
{
DI opval = tmp_tmp1;
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 10);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
}
@@ -26099,6 +26350,7 @@ frvbf_media_overflow (current_cpu, 8);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -26117,6 +26369,7 @@ SEM_FN_NAME (frvbf,cmcpxru) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
{
UHI tmp_argihi;
UHI tmp_argilo;
@@ -26139,7 +26392,7 @@ if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) {
{
DI opval = MAKEDI (255, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 10);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -26150,7 +26403,7 @@ if (LTDI (tmp_tmp1, MAKEDI (0, 0))) {
{
DI opval = MAKEDI (0, 0);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 10);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -26159,7 +26412,7 @@ frvbf_media_overflow (current_cpu, 8);
{
DI opval = tmp_tmp1;
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 10);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
}
@@ -26167,6 +26420,7 @@ frvbf_media_overflow (current_cpu, 8);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -26185,6 +26439,7 @@ SEM_FN_NAME (frvbf,cmcpxis) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
{
HI tmp_argihi;
HI tmp_argilo;
@@ -26207,7 +26462,7 @@ if (GTDI (tmp_tmp1, MAKEDI (127, 0xffffffff))) {
{
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 10);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -26218,7 +26473,7 @@ if (LTDI (tmp_tmp1, MAKEDI (0xffffff80, 0))) {
{
DI opval = MAKEDI (0xffffff80, 0);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 10);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -26227,7 +26482,7 @@ frvbf_media_overflow (current_cpu, 8);
{
DI opval = tmp_tmp1;
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 10);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
}
@@ -26235,6 +26490,7 @@ frvbf_media_overflow (current_cpu, 8);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -26253,6 +26509,7 @@ SEM_FN_NAME (frvbf,cmcpxiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) {
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
{
UHI tmp_argihi;
UHI tmp_argilo;
@@ -26275,7 +26532,7 @@ if (GTDI (tmp_tmp1, MAKEDI (255, 0xffffffff))) {
{
DI opval = MAKEDI (255, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 10);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -26286,7 +26543,7 @@ if (LTDI (tmp_tmp1, MAKEDI (0, 0))) {
{
DI opval = MAKEDI (0, 0);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 10);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
frvbf_media_overflow (current_cpu, 8);
@@ -26295,7 +26552,7 @@ frvbf_media_overflow (current_cpu, 8);
{
DI opval = tmp_tmp1;
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
- written |= (1 << 10);
+ written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
}
}
@@ -26303,6 +26560,7 @@ frvbf_media_overflow (current_cpu, 8);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -26320,6 +26578,7 @@ SEM_FN_NAME (frvbf,mqcpxrs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -26420,6 +26679,7 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -26437,6 +26697,7 @@ SEM_FN_NAME (frvbf,mqcpxru) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -26537,6 +26798,7 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -26554,6 +26816,7 @@ SEM_FN_NAME (frvbf,mqcpxis) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -26654,6 +26917,7 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -26671,6 +26935,7 @@ SEM_FN_NAME (frvbf,mqcpxiu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+if (frvbf_check_acc_range (current_cpu, FLD (f_ACC40Sk))) {
if (ANDSI (FLD (f_ACC40Sk), SUBSI (2, 1))) {
frvbf_media_acc_not_aligned (current_cpu);
} else {
@@ -26771,6 +27036,7 @@ frvbf_media_overflow (current_cpu, 4);
}
}
}
+}
abuf->written = written;
return vpc;
@@ -27833,9 +28099,14 @@ static const struct sem_fn_desc sem_fns[] = {
{ FRVBF_INSN_NUDIV, SEM_FN_NAME (frvbf,nudiv) },
{ FRVBF_INSN_SMUL, SEM_FN_NAME (frvbf,smul) },
{ FRVBF_INSN_UMUL, SEM_FN_NAME (frvbf,umul) },
+ { FRVBF_INSN_SMU, SEM_FN_NAME (frvbf,smu) },
+ { FRVBF_INSN_SMASS, SEM_FN_NAME (frvbf,smass) },
+ { FRVBF_INSN_SMSSS, SEM_FN_NAME (frvbf,smsss) },
{ FRVBF_INSN_SLL, SEM_FN_NAME (frvbf,sll) },
{ FRVBF_INSN_SRL, SEM_FN_NAME (frvbf,srl) },
{ FRVBF_INSN_SRA, SEM_FN_NAME (frvbf,sra) },
+ { FRVBF_INSN_SLASS, SEM_FN_NAME (frvbf,slass) },
+ { FRVBF_INSN_SCUTSS, SEM_FN_NAME (frvbf,scutss) },
{ FRVBF_INSN_SCAN, SEM_FN_NAME (frvbf,scan) },
{ FRVBF_INSN_CADD, SEM_FN_NAME (frvbf,cadd) },
{ FRVBF_INSN_CSUB, SEM_FN_NAME (frvbf,csub) },
@@ -27873,6 +28144,8 @@ static const struct sem_fn_desc sem_fns[] = {
{ FRVBF_INSN_SUBX, SEM_FN_NAME (frvbf,subx) },
{ FRVBF_INSN_ADDXCC, SEM_FN_NAME (frvbf,addxcc) },
{ FRVBF_INSN_SUBXCC, SEM_FN_NAME (frvbf,subxcc) },
+ { FRVBF_INSN_ADDSS, SEM_FN_NAME (frvbf,addss) },
+ { FRVBF_INSN_SUBSS, SEM_FN_NAME (frvbf,subss) },
{ FRVBF_INSN_ADDI, SEM_FN_NAME (frvbf,addi) },
{ FRVBF_INSN_SUBI, SEM_FN_NAME (frvbf,subi) },
{ FRVBF_INSN_ANDI, SEM_FN_NAME (frvbf,andi) },
diff --git a/sim/frv/traps.c b/sim/frv/traps.c
index 6ab8a2c..603dc21 100644
--- a/sim/frv/traps.c
+++ b/sim/frv/traps.c
@@ -1,5 +1,5 @@
/* frv trap support
- Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
+ Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU simulators.
@@ -30,6 +30,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "bfd.h"
#include "libiberty.h"
+CGEN_ATTR_VALUE_TYPE frv_current_fm_slot;
+
/* The semantic code invokes this for invalid (unrecognized) instructions. */
SEM_PC
@@ -276,9 +278,11 @@ frv_itrap (SIM_CPU *current_cpu, PCADDR pc, USI base, SI offset)
void
frv_mtrap (SIM_CPU *current_cpu)
{
+ SIM_DESC sd = CPU_STATE (current_cpu);
+
/* Check the status of media exceptions in MSR0. */
SI msr = GET_MSR (0);
- if (GET_MSR_AOVF (msr) || GET_MSR_MTT (msr))
+ if (GET_MSR_AOVF (msr) || GET_MSR_MTT (msr) && STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION);
}
@@ -584,11 +588,17 @@ frvbf_media_cr_not_aligned (SIM_CPU *current_cpu)
{
SIM_DESC sd = CPU_STATE (current_cpu);
- /* On the fr400 this generates an illegal_instruction interrupt. */
- if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
- frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
- else
- frv_set_mp_exception_registers (current_cpu, MTT_CR_NOT_ALIGNED, 0);
+ /* On some machines this generates an illegal_instruction interrupt. */
+ switch (STATE_ARCHITECTURE (sd)->mach)
+ {
+ case bfd_mach_fr400:
+ case bfd_mach_fr550:
+ frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+ break;
+ default:
+ frv_set_mp_exception_registers (current_cpu, MTT_CR_NOT_ALIGNED, 0);
+ break;
+ }
}
/* Record state for media exception: media_acc_not_aligned. */
@@ -597,11 +607,17 @@ frvbf_media_acc_not_aligned (SIM_CPU *current_cpu)
{
SIM_DESC sd = CPU_STATE (current_cpu);
- /* On the fr400 this generates an illegal_instruction interrupt. */
- if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
- frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
- else
- frv_set_mp_exception_registers (current_cpu, MTT_ACC_NOT_ALIGNED, 0);
+ /* On some machines this generates an illegal_instruction interrupt. */
+ switch (STATE_ARCHITECTURE (sd)->mach)
+ {
+ case bfd_mach_fr400:
+ case bfd_mach_fr550:
+ frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+ break;
+ default:
+ frv_set_mp_exception_registers (current_cpu, MTT_ACC_NOT_ALIGNED, 0);
+ break;
+ }
}
/* Record state for media exception: media_register_not_aligned. */
@@ -610,11 +626,17 @@ frvbf_media_register_not_aligned (SIM_CPU *current_cpu)
{
SIM_DESC sd = CPU_STATE (current_cpu);
- /* On the fr400 this generates an illegal_instruction interrupt. */
- if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
- frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
- else
- frv_set_mp_exception_registers (current_cpu, MTT_INVALID_FR, 0);
+ /* On some machines this generates an illegal_instruction interrupt. */
+ switch (STATE_ARCHITECTURE (sd)->mach)
+ {
+ case bfd_mach_fr400:
+ case bfd_mach_fr550:
+ frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+ break;
+ default:
+ frv_set_mp_exception_registers (current_cpu, MTT_INVALID_FR, 0);
+ break;
+ }
}
/* Record state for media exception: media_overflow. */
@@ -725,6 +747,50 @@ frvbf_check_recovering_store (
} /* loop over active neear registers. */
}
+SI
+frvbf_check_acc_range (SIM_CPU *current_cpu, SI regno)
+{
+ /* Only applicable to fr550 */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
+ return;
+
+ /* On the fr550, media insns in slots 0 and 2 can only access
+ accumulators acc0-acc3. Insns in slots 1 and 3 can only access
+ accumulators acc4-acc7 */
+ switch (frv_current_fm_slot)
+ {
+ case UNIT_FM0:
+ case UNIT_FM2:
+ if (regno <= 3)
+ return 1; /* all is ok */
+ break;
+ case UNIT_FM1:
+ case UNIT_FM3:
+ if (regno >= 4)
+ return 1; /* all is ok */
+ break;
+ }
+
+ /* The specified accumulator is out of range. Queue an illegal_instruction
+ interrupt. */
+ frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+ return 0;
+}
+
+void
+frvbf_check_swap_address (SIM_CPU *current_cpu, SI address)
+{
+ /* Only applicable to fr550 */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
+ return;
+
+ /* Adress must be aligned on a word boundary. */
+ if (address & 0x3)
+ frv_queue_data_access_exception_interrupt (current_cpu);
+}
+
static void
clear_nesr_neear (SIM_CPU *current_cpu, SI target_index, BI is_float)
{
generated by cgit v1.1 at 2024-12-12 05:16:54 +0000