diff options
| -rw-r--r-- | cpu/ChangeLog | 24 | ||||
| -rw-r--r-- | cpu/m32r.cpu | 541 | ||||
| -rw-r--r-- | cpu/m32r.opc | 54 |
3 files changed, 491 insertions, 128 deletions
diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 9d0f3e2..2a7b8c4 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,27 @@ +2004-02-23 Nick Clifton <nickc@redhat.com> + + * Apply these patches from Renesas: + + 2004-02-10 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> + + * cpu/m32r.opc (my_print_insn): Fixed incorrect output when + disassembling codes for 0x*2 addresses. + + 2003-12-15 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> + + * cpu/m32r.cpu: Add PIPE_O attribute to "pop" instruction. + + 2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> + + * cpu/m32r.cpu : Add new model m32r2. + Add new instructions. + Replace occurrances of 'Mitsubishi' with 'Renesas'. + Changed PIPE attr of push from O to OS. + Care for Little-endian of M32R. + * cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn): + Care for Little-endian of M32R. + (parse_slo16): signed extension for value. + 2004-02-20 Andrew Cagney <cagney@redhat.com> * m32r.opc, m32r.cpu: New files. Written by , Doug Evans, Nick diff --git a/cpu/m32r.cpu b/cpu/m32r.cpu index a2f94a8..c049b28 100644 --- a/cpu/m32r.cpu +++ b/cpu/m32r.cpu @@ -1,4 +1,4 @@ -; Mitsubishi M32R CPU description. -*- Scheme -*- +; Renesas M32R CPU description. -*- Scheme -*- ; ; Copyright 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. ; @@ -30,23 +30,25 @@ (define-arch (name m32r) ; name of cpu family - (comment "Mitsubishi M32R") + (comment "Renesas M32R") (default-alignment aligned) (insn-lsb0? #f) - (machs m32r m32rx) + (machs m32r m32rx m32r2) (isas m32r) ) ; Attributes. ; An attribute to describe which pipeline an insn runs in. +; O_OS is a special attribute for sll, sra, sla, slli, srai, slai. +; These instructions have O attribute for m32rx and OS attribute for m32r2. (define-attr (for insn) (type enum) (name PIPE) (comment "parallel execution pipeline selection") - (values NONE O S OS) + (values NONE O S OS O_OS) ) ; A derived attribute that says which insns can be executed in parallel @@ -159,8 +161,8 @@ ; The "b" suffix stands for "base" and is the convention. ; The "f" suffix stands for "family" and is the convention. (name m32rbf) - (comment "Mitsubishi M32R base family") - (endian big) + (comment "Renesas M32R base family") + (endian either) (word-bitsize 32) ; Override isa spec (??? keeps things simpler, though it was more true ; in the early days and not so much now). @@ -169,13 +171,22 @@ (define-cpu (name m32rxf) - (comment "Mitsubishi M32Rx family") - (endian big) + (comment "Renesas M32Rx family") + (endian either) (word-bitsize 32) ; Generated files have an "x" suffix. (file-transform "x") ) +(define-cpu + (name m32r2f) + (comment "Renesas M32R2 family") + (endian either) + (word-bitsize 32) + ; Generated files have an "2" suffix. + (file-transform "2") +) + (define-mach (name m32r) (comment "Generic M32R cpu") @@ -187,6 +198,12 @@ (comment "M32RX cpu") (cpu m32rxf) ) + +(define-mach + (name m32r2) + (comment "M32R2 cpu") + (cpu m32r2f) +) ; Model descriptions. @@ -327,6 +344,59 @@ () ; profile action (default) ) ) + +(define-model + (name m32r2) (comment "m32r2") (attrs) + (mach m32r2) + + ; ??? It's 6 stages but I forget the details right now. + (pipeline p-o "" () ((fetch) (decode) (execute) (writeback))) + (pipeline p-s "" () ((fetch) (decode) (execute) (writeback))) + (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback))) + + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () ; state + ((sr INT -1) (dr INT -1)) ; inputs + ((dr INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-cmp "Compare Unit" () + 1 1 ; issue done + () ; state + ((src1 INT -1) (src2 INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + (unit u-mac "Multiply/Accumulate Unit" () + 1 1 ; issue done + () ; state + ((src1 INT -1) (src2 INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + (unit u-cti "Branch Unit" () + 1 1 ; issue done + () ; state + ((sr INT -1)) ; inputs + ((pc)) ; outputs + () ; profile action (default) + ) + (unit u-load "Memory Load Unit" () + 1 1 ; issue done + () ; state + ((sr INT)) ; inputs + ((dr INT)) ; outputs + () ; profile action (default) + ) + (unit u-store "Memory Store Unit" () + 1 1 ; issue done + () ; state + ((src1 INT) (src2 INT)) ; inputs + () ; outputs + () ; profile action (default) + ) +) ; The instruction fetch/execute cycle. ; This is split into two parts as sometimes more than one instruction is @@ -397,8 +467,10 @@ (df f-simm8 "simm8" () 8 8 INT #f #f) (df f-simm16 "simm16" () 16 16 INT #f #f) (dnf f-shift-op2 "shift op2" () 8 3) +(dnf f-uimm3 "uimm3" () 5 3) (dnf f-uimm4 "uimm4" () 12 4) (dnf f-uimm5 "uimm5" () 11 5) +(dnf f-uimm8 "uimm8" () 8 8) (dnf f-uimm16 "uimm16" () 16 16) (dnf f-uimm24 "uimm24" (ABS-ADDR RELOC) 8 24) (dnf f-hi16 "high 16 bits" (SIGN-OPT) 16 16) @@ -418,6 +490,7 @@ (dnf f-accs "accs" () 12 2) (dnf f-accd "accd" () 4 2) (dnf f-bits67 "bits67" () 6 2) +(dnf f-bit4 "bit4" () 4 1) (dnf f-bit14 "bit14" () 14 1) (define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2") @@ -490,7 +563,7 @@ (print-name h-cr) (prefix "") (values (psw 0) (cbr 1) (spi 2) (spu 3) - (bpc 6) (bbpsw 8) (bbpc 14) + (bpc 6) (bbpsw 8) (bbpc 14) (evb 5) (cr0 0) (cr1 1) (cr2 2) (cr3 3) (cr4 4) (cr5 5) (cr6 6) (cr7 7) (cr8 8) (cr9 9) (cr10 10) (cr11 11) @@ -524,7 +597,7 @@ (define-hardware (name h-accums) (comment "accumulators") - (attrs (MACH m32rx)) + (attrs (MACH m32rx,m32r2)) (type register DI (2)) (indices keyword "" ((a0 0) (a1 1))) ; get/set so a0 accesses are redirected to h-accum. @@ -589,14 +662,16 @@ (dnop simm8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-simm8) (dnop simm16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-simm16) +(dnop uimm3 "3 bit unsigned number" (HASH-PREFIX) h-uint f-uimm3) (dnop uimm4 "4 bit trap number" (HASH-PREFIX) h-uint f-uimm4) (dnop uimm5 "5 bit shift count" (HASH-PREFIX) h-uint f-uimm5) +(dnop uimm8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm8) (dnop uimm16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm16) -(dnop imm1 "1 bit immediate" ((MACH m32rx) HASH-PREFIX) h-uint f-imm1) -(dnop accd "accumulator destination register" ((MACH m32rx)) h-accums f-accd) -(dnop accs "accumulator source register" ((MACH m32rx)) h-accums f-accs) -(dnop acc "accumulator reg (d)" ((MACH m32rx)) h-accums f-acc) +(dnop imm1 "1 bit immediate" ((MACH m32rx,m32r2) HASH-PREFIX) h-uint f-imm1) +(dnop accd "accumulator destination register" ((MACH m32rx,m32r2)) h-accums f-accd) +(dnop accs "accumulator source register" ((MACH m32rx,m32r2)) h-accums f-accs) +(dnop acc "accumulator reg (d)" ((MACH m32rx,m32r2)) h-accums f-acc) ; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases. ; e.g. add3 r3,r3,#1 and ld r3,@(4,r4). We could use HASH-PREFIX. @@ -694,6 +769,20 @@ (comment "non-public m32rx insn") ) +(define-attr + (for insn) + (type boolean) + (name SPECIAL_M32R) + (comment "non-public m32r insn") +) + +(define-attr + (for insn) + (type boolean) + (name SPECIAL_FLOAT) + (comment "floating point insn") +) + ; IDOC attribute for instruction documentation. (define-attr @@ -745,7 +834,8 @@ (+ OP1_4 dr simm8) (set dr (add dr simm8)) ((m32r/d (unit u-exec)) - (m32rx (unit u-exec))) + (m32rx (unit u-exec)) + (m32r2 (unit u-exec))) ) (dni addv "addv" @@ -784,7 +874,8 @@ (+ OP1_7 (f-r1 12) disp8) (if condbit (set pc disp8)) ((m32r/d (unit u-cti)) - (m32rx (unit u-cti))) + (m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dnmi bc8r "relaxable bc8" @@ -799,7 +890,8 @@ (+ OP1_15 (f-r1 12) disp24) (if condbit (set pc disp24)) ((m32r/d (unit u-cti)) - (m32rx (unit u-cti))) + (m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dnmi bc24r "relaxable bc24" @@ -814,7 +906,8 @@ (+ OP1_11 OP2_0 src1 src2 disp16) (if (eq src1 src2) (set pc disp16)) ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) - (m32rx (unit u-cti) (unit u-cmp (cycles 0)))) + (m32rx (unit u-cti) (unit u-cmp (cycles 0))) + (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) ) (define-pmacro (cbranch sym comment op2-op comp-op) @@ -823,7 +916,8 @@ (+ OP1_11 op2-op (f-r1 0) src2 disp16) (if (comp-op src2 (const WI 0)) (set pc disp16)) ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) - (m32rx (unit u-cti) (unit u-cmp (cycles 0)))) + (m32rx (unit u-cti) (unit u-cmp (cycles 0))) + (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) ) ) (cbranch beqz "beqz" OP2_8 eq) @@ -842,7 +936,8 @@ (add (and pc (const -4)) (const 4))) (set pc disp8)) ((m32r/d (unit u-cti)) - (m32rx (unit u-cti))) + (m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dnmi bl8r "relaxable bl8" @@ -859,7 +954,8 @@ (set (reg h-gr 14) (add pc (const 4))) (set pc disp24)) ((m32r/d (unit u-cti)) - (m32rx (unit u-cti))) + (m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dnmi bl24r "relaxable bl24" @@ -869,7 +965,7 @@ ) (dni bcl8 "bcl with 8 bit displacement" - (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) (IDOC BR)) + (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR)) "bcl.s $disp8" (+ OP1_7 (f-r1 8) disp8) (if condbit @@ -878,28 +974,30 @@ (add (and pc (const -4)) (const 4))) (set pc disp8))) - ((m32rx (unit u-cti))) + ((m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dnmi bcl8r "relaxable bcl8" - (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) RELAXABLE (IDOC BR)) + (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR)) "bcl $disp8" (emit bcl8 disp8) ) (dni bcl24 "bcl with 24 bit displacement" - (COND-CTI (MACH m32rx) (IDOC BR)) + (COND-CTI (MACH m32rx,m32r2) (IDOC BR)) "bcl.l $disp24" (+ OP1_15 (f-r1 8) disp24) (if condbit (sequence () (set (reg h-gr 14) (add pc (const 4))) (set pc disp24))) - ((m32rx (unit u-cti))) + ((m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dnmi bcl24r "relaxable bcl24" - (COND-CTI (MACH m32rx) RELAXED (IDOC BR)) + (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR)) "bcl $disp24" (emit bcl24 disp24) ) @@ -910,7 +1008,8 @@ (+ OP1_7 (f-r1 13) disp8) (if (not condbit) (set pc disp8)) ((m32r/d (unit u-cti)) - (m32rx (unit u-cti))) + (m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dnmi bnc8r "relaxable bnc8" @@ -925,7 +1024,8 @@ (+ OP1_15 (f-r1 13) disp24) (if (not condbit) (set pc disp24)) ((m32r/d (unit u-cti)) - (m32rx (unit u-cti))) + (m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dnmi bnc24r "relaxable bnc24" @@ -940,7 +1040,8 @@ (+ OP1_11 OP2_1 src1 src2 disp16) (if (ne src1 src2) (set pc disp16)) ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) - (m32rx (unit u-cti) (unit u-cmp (cycles 0)))) + (m32rx (unit u-cti) (unit u-cmp (cycles 0))) + (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) ) (dni bra8 "bra with 8 bit displacement" @@ -949,7 +1050,8 @@ (+ OP1_7 (f-r1 15) disp8) (set pc disp8) ((m32r/d (unit u-cti)) - (m32rx (unit u-cti))) + (m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dnmi bra8r "relaxable bra8" @@ -964,7 +1066,8 @@ (+ OP1_15 (f-r1 15) disp24) (set pc disp24) ((m32r/d (unit u-cti)) - (m32rx (unit u-cti))) + (m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dnmi bra24r "relaxable bra24" @@ -974,7 +1077,7 @@ ) (dni bncl8 "bncl with 8 bit displacement" - (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) (IDOC BR)) + (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR)) "bncl.s $disp8" (+ OP1_7 (f-r1 9) disp8) (if (not condbit) @@ -983,28 +1086,30 @@ (add (and pc (const -4)) (const 4))) (set pc disp8))) - ((m32rx (unit u-cti))) + ((m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dnmi bncl8r "relaxable bncl8" - (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) RELAXABLE (IDOC BR)) + (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR)) "bncl $disp8" (emit bncl8 disp8) ) (dni bncl24 "bncl with 24 bit displacement" - (COND-CTI (MACH m32rx) (IDOC BR)) + (COND-CTI (MACH m32rx,m32r2) (IDOC BR)) "bncl.l $disp24" (+ OP1_15 (f-r1 9) disp24) (if (not condbit) (sequence () (set (reg h-gr 14) (add pc (const 4))) (set pc disp24))) - ((m32rx (unit u-cti))) + ((m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dnmi bncl24r "relaxable bncl24" - (COND-CTI (MACH m32rx) RELAXED (IDOC BR)) + (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR)) "bncl $disp24" (emit bncl24 disp24) ) @@ -1015,7 +1120,8 @@ (+ OP1_0 OP2_4 src1 src2) (set condbit (lt src1 src2)) ((m32r/d (unit u-cmp)) - (m32rx (unit u-cmp))) + (m32rx (unit u-cmp)) + (m32r2 (unit u-cmp))) ) (dni cmpi "cmpi" @@ -1024,7 +1130,8 @@ (+ OP1_8 (f-r1 0) OP2_4 src2 simm16) (set condbit (lt src2 simm16)) ((m32r/d (unit u-cmp)) - (m32rx (unit u-cmp))) + (m32rx (unit u-cmp)) + (m32r2 (unit u-cmp))) ) (dni cmpu "cmpu" @@ -1033,7 +1140,8 @@ (+ OP1_0 OP2_5 src1 src2) (set condbit (ltu src1 src2)) ((m32r/d (unit u-cmp)) - (m32rx (unit u-cmp))) + (m32rx (unit u-cmp)) + (m32r2 (unit u-cmp))) ) (dni cmpui "cmpui" @@ -1042,23 +1150,26 @@ (+ OP1_8 (f-r1 0) OP2_5 src2 simm16) (set condbit (ltu src2 simm16)) ((m32r/d (unit u-cmp)) - (m32rx (unit u-cmp))) + (m32rx (unit u-cmp)) + (m32r2 (unit u-cmp))) ) (dni cmpeq "cmpeq" - ((MACH m32rx) (PIPE OS) (IDOC ALU)) + ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU)) "cmpeq $src1,$src2" (+ OP1_0 OP2_6 src1 src2) (set condbit (eq src1 src2)) - ((m32rx (unit u-cmp))) + ((m32rx (unit u-cmp)) + (m32r2 (unit u-cmp))) ) (dni cmpz "cmpz" - ((MACH m32rx) (PIPE OS) (IDOC ALU)) + ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU)) "cmpz $src2" (+ OP1_0 OP2_7 (f-r1 0) src2) (set condbit (eq src2 (const 0))) - ((m32rx (unit u-cmp))) + ((m32rx (unit u-cmp)) + (m32r2 (unit u-cmp))) ) (dni div "div" @@ -1067,7 +1178,8 @@ (+ OP1_9 OP2_0 dr sr (f-simm16 0)) (if (ne sr (const 0)) (set dr (div dr sr))) ((m32r/d (unit u-exec (cycles 37))) - (m32rx (unit u-exec (cycles 37)))) + (m32rx (unit u-exec (cycles 37))) + (m32r2 (unit u-exec (cycles 37)))) ) (dni divu "divu" @@ -1076,7 +1188,8 @@ (+ OP1_9 OP2_1 dr sr (f-simm16 0)) (if (ne sr (const 0)) (set dr (udiv dr sr))) ((m32r/d (unit u-exec (cycles 37))) - (m32rx (unit u-exec (cycles 37)))) + (m32rx (unit u-exec (cycles 37))) + (m32r2 (unit u-exec (cycles 37)))) ) (dni rem "rem" @@ -1086,7 +1199,8 @@ ; FIXME: Check rounding direction. (if (ne sr (const 0)) (set dr (mod dr sr))) ((m32r/d (unit u-exec (cycles 37))) - (m32rx (unit u-exec (cycles 37)))) + (m32rx (unit u-exec (cycles 37))) + (m32r2 (unit u-exec (cycles 37)))) ) (dni remu "remu" @@ -1096,31 +1210,95 @@ ; FIXME: Check rounding direction. (if (ne sr (const 0)) (set dr (umod dr sr))) ((m32r/d (unit u-exec (cycles 37))) - (m32rx (unit u-exec (cycles 37)))) + (m32rx (unit u-exec (cycles 37))) + (m32r2 (unit u-exec (cycles 37)))) +) + +(dni remh "remh" + ((MACH m32r2)) + "remh $dr,$sr" + (+ OP1_9 OP2_2 dr sr (f-simm16 #x10)) + ; FIXME: Check rounding direction. + (if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr))) + ((m32r2 (unit u-exec (cycles 21)))) +) + +(dni remuh "remuh" + ((MACH m32r2)) + "remuh $dr,$sr" + (+ OP1_9 OP2_3 dr sr (f-simm16 #x10)) + ; FIXME: Check rounding direction. + (if (ne sr (const 0)) (set dr (umod dr sr))) + ((m32r2 (unit u-exec (cycles 21)))) +) + +(dni remb "remb" + ((MACH m32r2)) + "remb $dr,$sr" + (+ OP1_9 OP2_2 dr sr (f-simm16 #x18)) + ; FIXME: Check rounding direction. + (if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr))) + ((m32r2 (unit u-exec (cycles 21)))) +) + +(dni remub "remub" + ((MACH m32r2)) + "remub $dr,$sr" + (+ OP1_9 OP2_3 dr sr (f-simm16 #x18)) + ; FIXME: Check rounding direction. + (if (ne sr (const 0)) (set dr (umod dr sr))) + ((m32r2 (unit u-exec (cycles 21)))) +) + +(dni divuh "divuh" + ((MACH m32r2)) + "divuh $dr,$sr" + (+ OP1_9 OP2_1 dr sr (f-simm16 #x10)) + (if (ne sr (const 0)) (set dr (udiv dr sr))) + ((m32r2 (unit u-exec (cycles 21)))) +) + +(dni divb "divb" + ((MACH m32r2)) + "divb $dr,$sr" + (+ OP1_9 OP2_0 dr sr (f-simm16 #x18)) + (if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr))) + ((m32r2 (unit u-exec (cycles 21)))) +) + +(dni divub "divub" + ((MACH m32r2)) + "divub $dr,$sr" + (+ OP1_9 OP2_1 dr sr (f-simm16 #x18)) + (if (ne sr (const 0)) (set dr (udiv dr sr))) + ((m32r2 (unit u-exec (cycles 21)))) ) (dni divh "divh" - ((MACH m32rx) (IDOC ALU)) + ((MACH m32rx,m32r2) (IDOC ALU)) "divh $dr,$sr" (+ OP1_9 OP2_0 dr sr (f-simm16 #x10)) (if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr))) - ((m32rx (unit u-exec (cycles 21)))) + ((m32rx (unit u-exec (cycles 21))) + (m32r2 (unit u-exec (cycles 21)))) ) (dni jc "jc" - (COND-CTI (MACH m32rx) (PIPE O) SPECIAL (IDOC BR)) + (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) "jc $sr" (+ OP1_1 (f-r1 12) OP2_12 sr) (if condbit (set pc (and sr (const -4)))) - ((m32rx (unit u-cti))) + ((m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dni jnc "jnc" - (COND-CTI (MACH m32rx) (PIPE O) SPECIAL (IDOC BR)) + (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) "jnc $sr" (+ OP1_1 (f-r1 13) OP2_12 sr) (if (not condbit) (set pc (and sr (const -4)))) - ((m32rx (unit u-cti))) + ((m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dni jl "jl" @@ -1132,7 +1310,8 @@ (add (and pc (const -4)) (const 4))) (set pc (and sr (const -4)))) ((m32r/d (unit u-cti)) - (m32rx (unit u-cti))) + (m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (dni jmp "jmp" @@ -1154,7 +1333,8 @@ ; (add WI (and WI pc (const WI -4)) (const WI 4)))) ; (set WI pc sr)) ((m32r/d (unit u-cti)) - (m32rx (unit u-cti))) + (m32rx (unit u-cti)) + (m32r2 (unit u-cti))) ) (define-pmacro (no-ext-expr mode expr) expr) @@ -1169,7 +1349,8 @@ (+ OP1_2 op2-op dr sr) (set dr (ext-op WI (mem mode sr))) ((m32r/d (unit u-load)) - (m32rx (unit u-load))) + (m32rx (unit u-load)) + (m32r2 (unit u-load))) ) (dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2") (NO-DIS (PIPE O) (IDOC MEM)) @@ -1181,7 +1362,8 @@ (+ OP1_10 op2-op dr sr slo16) (set dr (ext-op WI (mem mode (add sr slo16)))) ((m32r/d (unit u-load (cycles 2))) - (m32rx (unit u-load (cycles 2)))) + (m32rx (unit u-load (cycles 2))) + (m32r2 (unit u-load (cycles 2)))) ) (dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2") (NO-DIS (IDOC MEM)) @@ -1217,11 +1399,13 @@ (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) (m32rx (unit u-load) (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) + (m32r2 (unit u-load) + (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) ) ) (dnmi pop "pop" - ((IDOC MEM)) + ((PIPE O) (IDOC MEM)) "pop $dr" (emit ld-plus dr (sr 15)) ; "ld %0,@sp+" ) @@ -1272,7 +1456,8 @@ (set (reg h-lock) (const BI 1)) (set dr (mem WI sr))) ((m32r/d (unit u-load)) - (m32rx (unit u-load))) + (m32rx (unit u-load)) + (m32r2 (unit u-load))) ) (dni machi "machi" @@ -1299,7 +1484,7 @@ ) (dni machi-a "machi-a" - ((MACH m32rx) (PIPE S) (IDOC MAC)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) "machi $src1,$src2,$acc" (+ OP1_3 src1 acc (f-op23 4) src2) (set acc @@ -1312,7 +1497,8 @@ (ext DI (trunc HI (sra WI src2 (const 16)))))) (const 8)) (const 8))) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) (dni maclo "maclo" @@ -1333,7 +1519,7 @@ ) (dni maclo-a "maclo-a" - ((MACH m32rx) (PIPE S) (IDOC MAC)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) "maclo $src1,$src2,$acc" (+ OP1_3 src1 acc (f-op23 5) src2) (set acc @@ -1346,7 +1532,8 @@ (ext DI (trunc HI src2)))) (const 8)) (const 8))) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) (dni macwhi "macwhi" @@ -1367,7 +1554,7 @@ ) (dni macwhi-a "macwhi-a" - ((MACH m32rx) (PIPE S) SPECIAL (IDOC MAC)) + ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC)) "macwhi $src1,$src2,$acc" (+ OP1_3 src1 acc (f-op23 6) src2) ; Note that this doesn't do the sign extension, which is correct. @@ -1375,7 +1562,8 @@ (add acc (mul (ext DI src1) (ext DI (trunc HI (sra src2 (const 16))))))) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) (dni macwlo "macwlo" @@ -1396,7 +1584,7 @@ ) (dni macwlo-a "macwlo-a" - ((MACH m32rx) (PIPE S) SPECIAL (IDOC MAC)) + ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC)) "macwlo $src1,$src2,$acc" (+ OP1_3 src1 acc (f-op23 7) src2) ; Note that this doesn't do the sign extension, which is correct. @@ -1404,7 +1592,8 @@ (add acc (mul (ext DI src1) (ext DI (trunc HI src2))))) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) (dni mul "mul" @@ -1413,7 +1602,8 @@ (+ OP1_1 OP2_6 dr sr) (set dr (mul dr sr)) ((m32r/d (unit u-exec (cycles 4))) - (m32rx (unit u-exec (cycles 4)))) + (m32rx (unit u-exec (cycles 4))) + (m32r2 (unit u-exec (cycles 4)))) ) (dni mulhi "mulhi" @@ -1432,7 +1622,7 @@ ) (dni mulhi-a "mulhi-a" - ((MACH m32rx) (PIPE S) (IDOC ACCUM)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) "mulhi $src1,$src2,$acc" (+ OP1_3 (f-op23 0) src1 acc src2) (set acc @@ -1443,7 +1633,8 @@ (ext DI (trunc HI (sra WI src2 (const 16))))) (const 16)) (const 16))) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) (dni mullo "mullo" @@ -1462,7 +1653,7 @@ ) (dni mullo-a "mullo-a" - ((MACH m32rx) (PIPE S) (IDOC ACCUM)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) "mullo $src1,$src2,$acc" (+ OP1_3 src1 acc (f-op23 1) src2) (set acc @@ -1473,7 +1664,8 @@ (ext DI (trunc HI src2))) (const 16)) (const 16))) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) (dni mulwhi "mulwhi" @@ -1492,14 +1684,15 @@ ) (dni mulwhi-a "mulwhi-a" - ((MACH m32rx) (PIPE S) SPECIAL (IDOC ACCUM)) + ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM)) "mulwhi $src1,$src2,$acc" (+ OP1_3 src1 acc (f-op23 2) src2) ; Note that this doesn't do the sign extension, which is correct. (set acc (mul (ext DI src1) (ext DI (trunc HI (sra src2 (const 16)))))) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) (dni mulwlo "mulwlo" @@ -1518,14 +1711,15 @@ ) (dni mulwlo-a "mulwlo-a" - ((MACH m32rx) (PIPE S) SPECIAL (IDOC ACCUM)) + ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM)) "mulwlo $src1,$src2,$acc" (+ OP1_3 src1 acc (f-op23 3) src2) ; Note that this doesn't do the sign extension, which is correct. (set acc (mul (ext DI src1) (ext DI (trunc HI src2)))) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) (dni mv "mv" @@ -1545,11 +1739,12 @@ ) (dni mvfachi-a "mvfachi-a" - ((MACH m32rx) (PIPE S) (IDOC ACCUM)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) "mvfachi $dr,$accs" (+ OP1_5 dr OP2_15 accs (f-op3 0)) (set dr (trunc WI (sra DI accs (const 32)))) - ((m32rx (unit u-exec (cycles 2)))) + ((m32rx (unit u-exec (cycles 2))) + (m32r2 (unit u-exec (cycles 2)))) ) (dni mvfaclo "mvfaclo" @@ -1561,11 +1756,12 @@ ) (dni mvfaclo-a "mvfaclo-a" - ((MACH m32rx) (PIPE S) (IDOC ACCUM)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) "mvfaclo $dr,$accs" (+ OP1_5 dr OP2_15 accs (f-op3 1)) (set dr (trunc WI accs)) - ((m32rx (unit u-exec (cycles 2)))) + ((m32rx (unit u-exec (cycles 2))) + (m32r2 (unit u-exec (cycles 2)))) ) (dni mvfacmi "mvfacmi" @@ -1577,11 +1773,12 @@ ) (dni mvfacmi-a "mvfacmi-a" - ((MACH m32rx) (PIPE S) (IDOC ACCUM)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) "mvfacmi $dr,$accs" (+ OP1_5 dr OP2_15 accs (f-op3 2)) (set dr (trunc WI (sra DI accs (const 16)))) - ((m32rx (unit u-exec (cycles 2)))) + ((m32rx (unit u-exec (cycles 2))) + (m32r2 (unit u-exec (cycles 2)))) ) (dni mvfc "mvfc" @@ -1604,14 +1801,15 @@ ) (dni mvtachi-a "mvtachi-a" - ((MACH m32rx) (PIPE S) (IDOC ACCUM)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) "mvtachi $src1,$accs" (+ OP1_5 src1 OP2_7 accs (f-op3 0)) (set accs (or DI (and DI accs (const DI #xffffffff)) (sll DI (ext DI src1) (const 32)))) - ((m32rx (unit u-exec (in sr src1)))) + ((m32rx (unit u-exec (in sr src1))) + (m32r2 (unit u-exec (in sr src1)))) ) (dni mvtaclo "mvtaclo" @@ -1626,14 +1824,15 @@ ) (dni mvtaclo-a "mvtaclo-a" - ((MACH m32rx) (PIPE S) (IDOC ACCUM)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) "mvtaclo $src1,$accs" (+ OP1_5 src1 OP2_7 accs (f-op3 1)) (set accs (or DI (and DI accs (const DI #xffffffff00000000)) (zext DI src1))) - ((m32rx (unit u-exec (in sr src1)))) + ((m32rx (unit u-exec (in sr src1))) + (m32r2 (unit u-exec (in sr src1)))) ) (dni mvtc "mvtc" @@ -1660,7 +1859,8 @@ ; FIXME: quick hack: parallel nops don't contribute to cycle count. ; Other kinds of nops do however (which we currently ignore). ((m32r/d (unit u-exec (cycles 0))) - (m32rx (unit u-exec (cycles 0)))) + (m32rx (unit u-exec (cycles 0))) + (m32r2 (unit u-exec (cycles 0)))) ) (dni not "not" @@ -1690,7 +1890,7 @@ ) (dni rac-dsi "rac-dsi" - ((MACH m32rx) (PIPE S) (IDOC MAC)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) "rac $accd,$accs,$imm1" (+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1) (sequence ((DI tmp1)) @@ -1704,17 +1904,18 @@ (const DI #xffff800000000000)) (else (and tmp1 (const DI #xffffffffffff0000))))) ) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) (dnmi rac-d "rac-d" - ((MACH m32rx) (PIPE S) (IDOC MAC)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) "rac $accd" (emit rac-dsi accd (f-accs 0) (f-imm1 0)) ) (dnmi rac-ds "rac-ds" - ((MACH m32rx) (PIPE S) (IDOC MAC)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) "rac $accd,$accs" (emit rac-dsi accd accs (f-imm1 0)) ) @@ -1748,7 +1949,7 @@ ) (dni rach-dsi "rach-dsi" - ((MACH m32rx) (PIPE S) (IDOC MAC)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) "rach $accd,$accs,$imm1" (+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1) (sequence ((DI tmp1)) @@ -1762,17 +1963,18 @@ (const DI #xffff800000000000)) (else (and tmp1 (const DI #xffffffff00000000))))) ) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) (dnmi rach-d "rach-d" - ((MACH m32rx) (PIPE S) (IDOC MAC)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) "rach $accd" (emit rach-dsi accd (f-accs 0) (f-imm1 0)) ) (dnmi rach-ds "rach-ds" - ((MACH m32rx) (PIPE S) (IDOC MAC)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) "rach $accd,$accs" (emit rach-dsi accd accs (f-imm1 0)) ) @@ -1804,7 +2006,7 @@ (define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op) (begin - (dni sym sym ((PIPE O) (IDOC ALU)) + (dni sym sym ((PIPE O_OS) (IDOC ALU)) (.str sym " $dr,$sr") (+ OP1_1 op2-r-op dr sr) (set dr (sem-op dr (and sr (const 31)))) @@ -1816,7 +2018,7 @@ (set dr (sem-op sr (and WI simm16 (const 31)))) () ) - (dni (.sym sym "i") sym ((PIPE O) (IDOC ALU)) + (dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU)) (.str sym "i $dr,$uimm5") (+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5) (set dr (sem-op dr uimm5)) @@ -1836,7 +2038,8 @@ (+ OP1_2 op2-op src1 src2) (set mode (mem mode src2) src1) ((m32r/d (unit u-store (cycles 1))) - (m32rx (unit u-store (cycles 1)))) + (m32rx (unit u-store (cycles 1))) + (m32r2 (unit u-store (cycles 1)))) ) (dnmi (.sym st suffix "-2") (.str "st" suffix "-2") (NO-DIS (PIPE O) (IDOC MEM)) @@ -1848,7 +2051,8 @@ (+ OP1_10 op2-op src1 src2 slo16) (set mode (mem mode (add src2 slo16)) src1) ((m32r/d (unit u-store (cycles 2))) - (m32rx (unit u-store (cycles 2)))) + (m32rx (unit u-store (cycles 2))) + (m32r2 (unit u-store (cycles 2)))) ) (dnmi (.sym st suffix -d2) (.str "st" suffix "-d2") (NO-DIS (IDOC MEM)) @@ -1873,6 +2077,40 @@ (unit u-exec (in dr src2) (out dr src2) (cycles 0))) (m32rx (unit u-store) (unit u-exec (in dr src2) (out dr src2) (cycles 0))) + (m32r2 (unit u-store) + (unit u-exec (in dr src2) (out dr src2) (cycles 0))) + ) +) + +(dni sth-plus "sth+" + ((MACH m32rx,m32r2) (PIPE O) SPECIAL) + "sth $src1,@$src2+" + (+ OP1_2 OP2_3 src1 src2) + ; This has to be coded carefully to avoid an "earlyclobber" of src2. + (sequence ((HI new-src2)) + (set (mem HI new-src2) src1) + (set new-src2 (add src2 (const 2))) + (set src2 new-src2)) + ((m32rx (unit u-store) + (unit u-exec (in dr src2) (out dr src2) (cycles 0))) + (m32r2 (unit u-store) + (unit u-exec (in dr src2) (out dr src2) (cycles 0))) + ) +) + +(dni stb-plus "stb+" + ((MACH m32rx,m32r2) (PIPE O) SPECIAL) + "stb $src1,@$src2+" + (+ OP1_2 OP2_1 src1 src2) + ; This has to be coded carefully to avoid an "earlyclobber" of src2. + (sequence ((QI new-src2)) + (set (mem QI new-src2) src1) + (set new-src2 (add src2 (const 1))) + (set src2 new-src2)) + ((m32rx (unit u-store) + (unit u-exec (in dr src2) (out dr src2) (cycles 0))) + (m32r2 (unit u-store) + (unit u-exec (in dr src2) (out dr src2) (cycles 0))) ) ) @@ -1893,10 +2131,12 @@ (unit u-exec (in dr src2) (out dr src2) (cycles 0))) (m32rx (unit u-store) (unit u-exec (in dr src2) (out dr src2) (cycles 0))) + (m32r2 (unit u-store) + (unit u-exec (in dr src2) (out dr src2) (cycles 0))) ) ) -(dnmi push "push" ((IDOC MEM)) +(dnmi push "push" ((PIPE O) (IDOC MEM)) "push $src1" (emit st-minus src1 (src2 15)) ; "st %0,@-sp" ) @@ -1961,12 +2201,13 @@ (set (mem WI src2) src1)) (set (reg h-lock) (const BI 0))) ((m32r/d (unit u-load)) - (m32rx (unit u-load))) + (m32rx (unit u-load)) + (m32r2 (unit u-load))) ) ; Saturate into byte. (dni satb "satb" - ((MACH m32rx) (IDOC ALU)) + ((MACH m32rx,m32r2) (IDOC ALU)) "satb $dr,$sr" (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300)) (set dr @@ -1980,7 +2221,7 @@ ; Saturate into half word. (dni sath "sath" - ((MACH m32rx) (IDOC ALU)) + ((MACH m32rx,m32r2) (IDOC ALU)) "sath $dr,$sr" (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200)) (set dr @@ -1993,7 +2234,7 @@ ; Saturate word. (dni sat "sat" - ((MACH m32rx) SPECIAL (IDOC ALU)) + ((MACH m32rx,m32r2) SPECIAL (IDOC ALU)) "sat $dr,$sr" (+ OP1_8 dr OP2_6 sr (f-uimm16 0)) (set dr @@ -2008,7 +2249,7 @@ ; Parallel compare byte zeros. ; Set C bit in condition register if any byte in source register is zero. (dni pcmpbz "pcmpbz" - ((MACH m32rx) (PIPE OS) SPECIAL (IDOC ALU)) + ((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU)) "pcmpbz $src2" (+ OP1_0 (f-r1 3) OP2_7 src2) (set condbit @@ -2018,23 +2259,25 @@ ((eq (and src2 (const #xff0000)) (const 0)) (const BI 1)) ((eq (and src2 (const #xff000000)) (const 0)) (const BI 1)) (else (const BI 0)))) - ((m32rx (unit u-cmp))) + ((m32rx (unit u-cmp)) + (m32r2 (unit u-cmp))) ) ; Add accumulators (dni sadd "sadd" - ((MACH m32rx) (PIPE S) (IDOC ACCUM)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) "sadd" (+ OP1_5 (f-r1 0) OP2_14 (f-r2 4)) (set (reg h-accums 0) (add (sra (reg h-accums 1) (const 16)) (reg h-accums 0))) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) ; Multiply and add into accumulator 1 (dni macwu1 "macwu1" - ((MACH m32rx) (PIPE S) (IDOC MAC)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) "macwu1 $src1,$src2" (+ OP1_5 src1 OP2_11 src2) (set (reg h-accums 1) @@ -2047,12 +2290,13 @@ (ext DI (and src2 (const #xffff))))) (const 8)) (const 8))) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) ; Multiply and subtract from accumulator 0 (dni msblo "msblo" - ((MACH m32rx) (PIPE S) (IDOC MAC)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) "msblo $src1,$src2" (+ OP1_5 src1 OP2_13 src2) (set accum @@ -2068,12 +2312,13 @@ (const 16))) (const 8)) (const 8))) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) ; Multiply into accumulator 1 (dni mulwu1 "mulwu1" - ((MACH m32rx) (PIPE S) (IDOC MAC)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) "mulwu1 $src1,$src2" (+ OP1_5 src1 OP2_10 src2) (set (reg h-accums 1) @@ -2084,12 +2329,13 @@ (ext DI (and src2 (const #xffff)))) (const 16)) (const 16))) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) ; Multiply and add into accumulator 1 (dni maclh1 "maclh1" - ((MACH m32rx) (PIPE S) (IDOC MAC)) + ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) "maclh1 $src1,$src2" (+ OP1_5 src1 OP2_12 src2) (set (reg h-accums 1) @@ -2105,12 +2351,13 @@ (const 16))) (const 8)) (const 8))) - ((m32rx (unit u-mac))) + ((m32rx (unit u-mac)) + (m32r2 (unit u-mac))) ) ; skip instruction if C (dni sc "sc" - ((MACH m32rx) (PIPE O) SPECIAL (IDOC BR)) + ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) "sc" (+ OP1_7 (f-r1 4) OP2_0 (f-r2 1)) (skip (zext INT condbit)) @@ -2119,9 +2366,61 @@ ; skip instruction if not C (dni snc "snc" - ((MACH m32rx) (PIPE O) SPECIAL (IDOC BR)) + ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) "snc" (+ OP1_7 (f-r1 5) OP2_0 (f-r2 1)) (skip (zext INT (not condbit))) () ) + +; PSW &= ~((unsigned char) uimm8 | 0x000ff00) +(dni clrpsw "clrpsw" + ((PIPE O) SPECIAL_M32R) + "clrpsw $uimm8" + (+ OP1_7 (f-r1 2) uimm8) + (set USI (reg h-cr 0) + (and USI (reg h-cr 0) + (or USI (inv BI uimm8) (const #xff00)))) + () +) + +; PSW |= (unsigned char) uimm8 +(dni setpsw "setpsw" + ((PIPE O) SPECIAL_M32R) + "setpsw $uimm8" + (+ OP1_7 (f-r1 1) uimm8) + (set USI (reg h-cr 0) uimm8) + () +) + +; bset +(dni bset "bset" + (SPECIAL_M32R) + "bset $uimm3,@($slo16,$sr)" + (+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16) + (set QI (mem QI (add sr slo16)) + (or QI (mem QI (add sr slo16)) + (sll USI (const 1) (sub (const 7) uimm3)))) + () +) + +; bclr +(dni bclr "bclr" + (SPECIAL_M32R) + "bclr $uimm3,@($slo16,$sr)" + (+ OP1_10 (f-bit4 0) uimm3 OP2_7 sr slo16) + (set QI (mem QI (add sr slo16)) + (and QI (mem QI (add sr slo16)) + (inv QI (sll USI (const 1) (sub (const 7) uimm3))))) + () +) + +; btst +(dni btst "btst" + (SPECIAL_M32R (PIPE O)) + "btst $uimm3,$sr" + (+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr) + (set condbit (and QI (srl USI sr (sub (const 7) uimm3)) (const 1))) + () +) + diff --git a/cpu/m32r.opc b/cpu/m32r.opc index dbb6f1d..6764223 100644 --- a/cpu/m32r.opc +++ b/cpu/m32r.opc @@ -27,7 +27,6 @@ */ - /* This file is an addendum to m32r.cpu. Heavy use of C code isn't appropriate in .cpu files, so it resides here. This especially applies to assembly/disassembly where parsing/printing can be quite involved. @@ -49,6 +48,7 @@ #undef CGEN_DIS_HASH_SIZE #define CGEN_DIS_HASH_SIZE 256 #undef CGEN_DIS_HASH +#if 0 #define X(b) (((unsigned char *) (b))[0] & 0xf0) #define CGEN_DIS_HASH(buffer, value) \ (X (buffer) | \ @@ -56,9 +56,39 @@ : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \ : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \ : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4))) +#else +#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value) +extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT); +#endif /* -- */ +/* -- opc.c */ +unsigned int +m32r_cgen_dis_hash (buf, value) + const char * buf ATTRIBUTE_UNUSED; + CGEN_INSN_INT value; +{ + unsigned int x; + + if (value & 0xffff0000) /* 32bit instructions */ + value = (value >> 16) & 0xffff; + + x = (value>>8) & 0xf0; + if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50) + return x; + + if (x == 0x70 || x == 0xf0) + return x | ((value>>8) & 0x0f); + + if (x == 0x30) + return x | ((value & 0x70) >> 4); + else + return x | ((value & 0xf0) >> 4); +} + +/* -- */ + /* -- asm.c */ static const char * parse_hash PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); @@ -159,7 +189,11 @@ parse_slo16 (cd, strp, opindex, valuep) ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; + { + value &= 0xffff; + if (value & 0x8000) + value |= 0xffff0000; + } *valuep = value; return errmsg; } @@ -259,10 +293,13 @@ my_print_insn (cd, pc, info) char *buf = buffer; int status; int buflen = (pc & 3) == 0 ? 4 : 2; + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; + char *x; /* Read the base part of the insn. */ - status = (*info->read_memory_func) (pc, buf, buflen, info); + status = (*info->read_memory_func) (pc - ((!big_p && (pc & 3) != 0) ? 2 : 0), + buf, buflen, info); if (status != 0) { (*info->memory_error_func) (status, pc, info); @@ -270,22 +307,25 @@ my_print_insn (cd, pc, info) } /* 32 bit insn? */ - if ((pc & 3) == 0 && (buf[0] & 0x80) != 0) + x = (big_p ? &buf[0] : &buf[3]); + if ((pc & 3) == 0 && (*x & 0x80) != 0) return print_insn (cd, pc, info, buf, buflen); /* Print the first insn. */ if ((pc & 3) == 0) { + buf += (big_p ? 0 : 2); if (print_insn (cd, pc, info, buf, 2) == 0) (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - buf += 2; + buf += (big_p ? 2 : -2); } - if (buf[0] & 0x80) + x = (big_p ? &buf[0] : &buf[1]); + if (*x & 0x80) { /* Parallel. */ (*info->fprintf_func) (info->stream, " || "); - buf[0] &= 0x7f; + *x &= 0x7f; } else (*info->fprintf_func) (info->stream, " -> "); |