diff options
| -rw-r--r-- | sim/sh64/ChangeLog | 40 | ||||
| -rw-r--r-- | sim/sh64/Makefile.in | 36 | ||||
| -rw-r--r-- | sim/sh64/arch.c | 27 | ||||
| -rw-r--r-- | sim/sh64/arch.h | 187 | ||||
| -rw-r--r-- | sim/sh64/cpu.c | 70 | ||||
| -rw-r--r-- | sim/sh64/cpu.h | 96 | ||||
| -rw-r--r-- | sim/sh64/cpuall.h | 13 | ||||
| -rw-r--r-- | sim/sh64/decode-compact.c | 4736 | ||||
| -rw-r--r-- | sim/sh64/decode-compact.h | 270 | ||||
| -rw-r--r-- | sim/sh64/decode-media.c | 2401 | ||||
| -rw-r--r-- | sim/sh64/decode-media.h | 175 | ||||
| -rw-r--r-- | sim/sh64/defs-compact.h | 286 | ||||
| -rw-r--r-- | sim/sh64/defs-media.h | 563 | ||||
| -rw-r--r-- | sim/sh64/sem-compact-switch.c | 1266 | ||||
| -rw-r--r-- | sim/sh64/sem-compact.c | 1300 | ||||
| -rw-r--r-- | sim/sh64/sem-media-switch.c | 247 | ||||
| -rw-r--r-- | sim/sh64/sem-media.c | 247 | ||||
| -rw-r--r-- | sim/sh64/sh-desc.c | 2428 | ||||
| -rw-r--r-- | sim/sh64/sh-desc.h | 165 | ||||
| -rw-r--r-- | sim/sh64/sh-opc.h | 201 | ||||
| -rw-r--r-- | sim/sh64/sh64-sim.h | 10 | ||||
| -rw-r--r-- | sim/sh64/sh64.c | 147 |
22 files changed, 11325 insertions, 3586 deletions
diff --git a/sim/sh64/ChangeLog b/sim/sh64/ChangeLog index cb1855a..c3eb49d 100644 --- a/sim/sh64/ChangeLog +++ b/sim/sh64/ChangeLog @@ -1,3 +1,43 @@ +2006-10-18 Dave Brolley <brolley@redhat.com> + + * Contribute the following changes: + + 2006-06-14 Dave Brolley <brolley@redhat.com> + + * sh64-sim.h (sh64_fipr,sh64_fiprs,sh64_fldp,sh64_fstp,sh64_ftrv) + (sh64_fpref): New functions. + * sh64.c (sh64_fipr,sh64_fiprs,sh64_fldp,sh64_fstp,sh64_ftrv) + (sh64_fpref): New functions. + (sh_models): Add sh2e, sh2a, sh2a_nofpu, sh4_nofpu, sh4a, + sh4a_nofpu and sh4al. + (sh2e_mach): New MACH. + (sh2a_fpu_mach): New MACH. + (sh2a_nofpu_mach): New MACH. + (sh4_nofpu): New MACH. + (sh4a_mach): New MACH. + (sh4a_nofpu_mach): New MACH. + (sh4al_mach): New MACH. + * Makefile.in (stamp-*): Depend on $(CGEN_CPU_DIR)/sh-sim.cpu. Pass + archfile to CGEN script. + * arch.c: Regenerated. + * arch.h: Regenerated. + * cpu.c: Regenerated. + * cpu.h: Regenerated. + * cpuall.h: Regenerated. + * decode-compact.c: Regenerated. + * decode-compact.h: Regenerated. + * decode-media.c: Regenerated. + * decode-media.h: Regenerated. + * defs-compact.h: Regenerated. + * defs-media.h: Regenerated. + * sem-compact-switch.c: Regenerated. + * sem-compact.c: Regenerated. + * sem-media-switch.c: Regenerated. + * sem-media.c: Regenerated. + * sh-desc.c: Regenerated. + * sh-desc.h: Regenerated. + * sh-opc.h: Regenerated. + 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com> * configure: Regenerated. diff --git a/sim/sh64/Makefile.in b/sim/sh64/Makefile.in index b8cfb82..f8f3f45 100644 --- a/sim/sh64/Makefile.in +++ b/sim/sh64/Makefile.in @@ -104,50 +104,52 @@ stamp-all: stamp-arch stamp-desc stamp-cpu stamp-decode stamp-defs stamp-decode: stamp-decode-compact stamp-decode-media stamp-defs: stamp-defs-compact stamp-defs-media -stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile - $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all isa=compact,media \ +stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile + $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all isa=compact,media archfile=$(CGEN_CPU_DIR)/sh.cpu \ FLAGS="with-scache" touch $@ -arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch +arch.h ${srcdir}/arch.c cpuall.h: $(CGEN_MAINT) stamp-arch @true -stamp-desc: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu Makefile - $(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) cpu=sh64 mach=all isa=compact,media +stamp-desc: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile + $(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) cpu=sh64 mach=all isa=compact,media archfile=$(CGEN_CPU_DIR)/sh.cpu touch $@ desc.h: $(CGEN_MAINT) stamp-desc @true -stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu Makefile +stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile $(MAKE) cgen-cpu $(CGEN_FLAGS_TO_PASS) \ - cpu=sh64 mach=sh4,sh5 isa=compact,media FLAGS="with-multiple-isa with-scache" + cpu=sh64 mach=sh4,sh5 isa=compact,media FLAGS="with-multiple-isa with-scache" archfile=$(CGEN_CPU_DIR)/sh.cpu rm -f $(srcdir)/model.c touch $@ cpu.h: $(CGEN_MAINT) stamp-cpu @true -stamp-defs-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile +stamp-defs-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile $(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \ - cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact" + cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact" archfile=$(CGEN_CPU_DIR)/sh.cpu touch $@ defs-compact.h: $(CGEN_MAINT) stamp-defs-compact @true -stamp-defs-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu Makefile +stamp-defs-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile $(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \ - cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media" + cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media" archfile=$(CGEN_CPU_DIR)/sh.cpu touch $@ defs-media.h: $(CGEN_MAINT) stamp-defs-media -stamp-decode-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile +stamp-decode-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile $(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \ - cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)" + cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)" \ + archfile=$(CGEN_CPU_DIR)/sh.cpu touch $@ -sem-compact.c sem-compact-switch.c decode-compact.c decode-compact.h: $(CGEN_MAINT) stamp-compact +sem-compact.c sem-compact-switch.c decode-compact.c decode-compact.h: $(CGEN_MAINT) stamp-decode-compact @true -stamp-decode-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu Makefile +stamp-decode-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile $(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \ - cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)" + cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)" \ + archfile=$(CGEN_CPU_DIR)/sh.cpu touch $@ -sem-media.c sem-media-switch.c decode-media.c decode-media.h: $(CGEN_MAINT) stamp-media +sem-media.c sem-media-switch.c decode-media.c decode-media.h: $(CGEN_MAINT) stamp-decode-media @true diff --git a/sim/sh64/arch.c b/sim/sh64/arch.c index c1e8c77..cc05511 100644 --- a/sim/sh64/arch.c +++ b/sim/sh64/arch.c @@ -2,9 +2,9 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -31,15 +31,36 @@ const MACH *sim_machs[] = & sh2_mach, #endif #ifdef HAVE_CPU_SH64 + & sh2e_mach, +#endif +#ifdef HAVE_CPU_SH64 + & sh2a_fpu_mach, +#endif +#ifdef HAVE_CPU_SH64 + & sh2a_nofpu_mach, +#endif +#ifdef HAVE_CPU_SH64 & sh3_mach, #endif #ifdef HAVE_CPU_SH64 & sh3e_mach, #endif #ifdef HAVE_CPU_SH64 + & sh4_nofpu_mach, +#endif +#ifdef HAVE_CPU_SH64 & sh4_mach, #endif #ifdef HAVE_CPU_SH64 + & sh4a_nofpu_mach, +#endif +#ifdef HAVE_CPU_SH64 + & sh4a_mach, +#endif +#ifdef HAVE_CPU_SH64 + & sh4al_mach, +#endif +#ifdef HAVE_CPU_SH64 & sh5_mach, #endif 0 diff --git a/sim/sh64/arch.h b/sim/sh64/arch.h index 30820a0..162e961 100644 --- a/sim/sh64/arch.h +++ b/sim/sh64/arch.h @@ -2,9 +2,9 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -29,16 +29,191 @@ with this program; if not, write to the Free Software Foundation, Inc., /* Enum declaration for model types. */ typedef enum model_type { - MODEL_SH5, MODEL_MAX + MODEL_SH2A_NOFPU, MODEL_SH2A_FPU, MODEL_SH4_NOFPU, MODEL_SH4 + , MODEL_SH4A_NOFPU, MODEL_SH4A, MODEL_SH4AL, MODEL_SH5 + , MODEL_SH5_MEDIA, MODEL_SH2, MODEL_SH2E, MODEL_SH3 + , MODEL_SH3E, MODEL_MAX } MODEL_TYPE; #define MAX_MODELS ((int) MODEL_MAX) /* Enum declaration for unit types. */ typedef enum unit_type { - UNIT_NONE, UNIT_SH5_U_EXEC, UNIT_MAX + UNIT_NONE, UNIT_SH2A_NOFPU_U_MULR_GR, UNIT_SH2A_NOFPU_U_MULR, UNIT_SH2A_NOFPU_U_TRAP + , UNIT_SH2A_NOFPU_U_WRITE_BACK, UNIT_SH2A_NOFPU_U_USE_MULTIPLY_RESULT, UNIT_SH2A_NOFPU_U_SHIFT, UNIT_SH2A_NOFPU_U_TAS + , UNIT_SH2A_NOFPU_U_MULSW, UNIT_SH2A_NOFPU_U_MULL, UNIT_SH2A_NOFPU_U_DMUL, UNIT_SH2A_NOFPU_U_MACL + , UNIT_SH2A_NOFPU_U_MACW, UNIT_SH2A_NOFPU_U_MULTIPLY, UNIT_SH2A_NOFPU_U_SET_MAC, UNIT_SH2A_NOFPU_U_LOAD_MAC + , UNIT_SH2A_NOFPU_U_LOAD_VBR, UNIT_SH2A_NOFPU_U_LOAD_GBR, UNIT_SH2A_NOFPU_U_USE_GR, UNIT_SH2A_NOFPU_U_LOAD_GR + , UNIT_SH2A_NOFPU_U_STC_VBR, UNIT_SH2A_NOFPU_U_LDCL_VBR, UNIT_SH2A_NOFPU_U_LDCL, UNIT_SH2A_NOFPU_U_USE_TBIT + , UNIT_SH2A_NOFPU_U_LDC_GBR, UNIT_SH2A_NOFPU_U_LDC_SR, UNIT_SH2A_NOFPU_U_SET_SR_BIT, UNIT_SH2A_NOFPU_U_USE_PR + , UNIT_SH2A_NOFPU_U_LOAD_PR, UNIT_SH2A_NOFPU_U_STS_PR, UNIT_SH2A_NOFPU_U_LDS_PR, UNIT_SH2A_NOFPU_U_MEMORY_ACCESS + , UNIT_SH2A_NOFPU_U_LOGIC_B, UNIT_SH2A_NOFPU_U_JSR, UNIT_SH2A_NOFPU_U_JMP, UNIT_SH2A_NOFPU_U_BRANCH + , UNIT_SH2A_NOFPU_U_SX, UNIT_SH2A_NOFPU_U_EXEC, UNIT_SH2A_FPU_U_USE_DR, UNIT_SH2A_FPU_U_LOAD_DR + , UNIT_SH2A_FPU_U_SET_DR, UNIT_SH2A_FPU_U_MULR_GR, UNIT_SH2A_FPU_U_MULR, UNIT_SH2A_FPU_U_FCNV + , UNIT_SH2A_FPU_U_FCMP, UNIT_SH2A_FPU_U_FSQRT, UNIT_SH2A_FPU_U_FDIV, UNIT_SH2A_FPU_U_FPU_LOAD_GR + , UNIT_SH2A_FPU_U_USE_FPSCR, UNIT_SH2A_FPU_U_LDSL_FPSCR, UNIT_SH2A_FPU_U_LDS_FPSCR, UNIT_SH2A_FPU_U_USE_FPUL + , UNIT_SH2A_FPU_U_FLDS_FPUL, UNIT_SH2A_FPU_U_LOAD_FPUL, UNIT_SH2A_FPU_U_SET_FPUL, UNIT_SH2A_FPU_U_FPU_MEMORY_ACCESS + , UNIT_SH2A_FPU_U_USE_FR, UNIT_SH2A_FPU_U_SET_FR_0, UNIT_SH2A_FPU_U_SET_FR, UNIT_SH2A_FPU_U_LOAD_FR + , UNIT_SH2A_FPU_U_MAYBE_FPU, UNIT_SH2A_FPU_U_FPU, UNIT_SH2A_FPU_U_TRAP, UNIT_SH2A_FPU_U_WRITE_BACK + , UNIT_SH2A_FPU_U_USE_MULTIPLY_RESULT, UNIT_SH2A_FPU_U_SHIFT, UNIT_SH2A_FPU_U_TAS, UNIT_SH2A_FPU_U_MULSW + , UNIT_SH2A_FPU_U_MULL, UNIT_SH2A_FPU_U_DMUL, UNIT_SH2A_FPU_U_MACL, UNIT_SH2A_FPU_U_MACW + , UNIT_SH2A_FPU_U_MULTIPLY, UNIT_SH2A_FPU_U_SET_MAC, UNIT_SH2A_FPU_U_LOAD_MAC, UNIT_SH2A_FPU_U_LOAD_VBR + , UNIT_SH2A_FPU_U_LOAD_GBR, UNIT_SH2A_FPU_U_USE_GR, UNIT_SH2A_FPU_U_LOAD_GR, UNIT_SH2A_FPU_U_STC_VBR + , UNIT_SH2A_FPU_U_LDCL_VBR, UNIT_SH2A_FPU_U_LDCL, UNIT_SH2A_FPU_U_USE_TBIT, UNIT_SH2A_FPU_U_LDC_GBR + , UNIT_SH2A_FPU_U_LDC_SR, UNIT_SH2A_FPU_U_SET_SR_BIT, UNIT_SH2A_FPU_U_USE_PR, UNIT_SH2A_FPU_U_LOAD_PR + , UNIT_SH2A_FPU_U_STS_PR, UNIT_SH2A_FPU_U_LDS_PR, UNIT_SH2A_FPU_U_MEMORY_ACCESS, UNIT_SH2A_FPU_U_LOGIC_B + , UNIT_SH2A_FPU_U_JSR, UNIT_SH2A_FPU_U_JMP, UNIT_SH2A_FPU_U_BRANCH, UNIT_SH2A_FPU_U_SX + , UNIT_SH2A_FPU_U_EXEC, UNIT_SH4_NOFPU_U_OCB, UNIT_SH4_NOFPU_U_MULR_GR, UNIT_SH4_NOFPU_U_MULR + , UNIT_SH4_NOFPU_U_TRAP, UNIT_SH4_NOFPU_U_WRITE_BACK, UNIT_SH4_NOFPU_U_USE_MULTIPLY_RESULT, UNIT_SH4_NOFPU_U_SHIFT + , UNIT_SH4_NOFPU_U_TAS, UNIT_SH4_NOFPU_U_MULSW, UNIT_SH4_NOFPU_U_MULL, UNIT_SH4_NOFPU_U_DMUL + , UNIT_SH4_NOFPU_U_MACL, UNIT_SH4_NOFPU_U_MACW, UNIT_SH4_NOFPU_U_MULTIPLY, UNIT_SH4_NOFPU_U_SET_MAC + , UNIT_SH4_NOFPU_U_LOAD_MAC, UNIT_SH4_NOFPU_U_LOAD_VBR, UNIT_SH4_NOFPU_U_LOAD_GBR, UNIT_SH4_NOFPU_U_USE_GR + , UNIT_SH4_NOFPU_U_LOAD_GR, UNIT_SH4_NOFPU_U_STC_VBR, UNIT_SH4_NOFPU_U_LDCL_VBR, UNIT_SH4_NOFPU_U_LDCL + , UNIT_SH4_NOFPU_U_USE_TBIT, UNIT_SH4_NOFPU_U_LDC_GBR, UNIT_SH4_NOFPU_U_LDC_SR, UNIT_SH4_NOFPU_U_SET_SR_BIT + , UNIT_SH4_NOFPU_U_USE_PR, UNIT_SH4_NOFPU_U_LOAD_PR, UNIT_SH4_NOFPU_U_STS_PR, UNIT_SH4_NOFPU_U_LDS_PR + , UNIT_SH4_NOFPU_U_MEMORY_ACCESS, UNIT_SH4_NOFPU_U_LOGIC_B, UNIT_SH4_NOFPU_U_JSR, UNIT_SH4_NOFPU_U_JMP + , UNIT_SH4_NOFPU_U_BRANCH, UNIT_SH4_NOFPU_U_SX, UNIT_SH4_NOFPU_U_EXEC, UNIT_SH4_U_FTRV + , UNIT_SH4_U_FIPR, UNIT_SH4_U_OCB, UNIT_SH4_U_MULR_GR, UNIT_SH4_U_MULR + , UNIT_SH4_U_USE_DR, UNIT_SH4_U_LOAD_DR, UNIT_SH4_U_SET_DR, UNIT_SH4_U_FCNV + , UNIT_SH4_U_FCMP, UNIT_SH4_U_FSQRT, UNIT_SH4_U_FDIV, UNIT_SH4_U_FPU_LOAD_GR + , UNIT_SH4_U_USE_FPSCR, UNIT_SH4_U_LDSL_FPSCR, UNIT_SH4_U_LDS_FPSCR, UNIT_SH4_U_USE_FPUL + , UNIT_SH4_U_FLDS_FPUL, UNIT_SH4_U_LOAD_FPUL, UNIT_SH4_U_SET_FPUL, UNIT_SH4_U_FPU_MEMORY_ACCESS + , UNIT_SH4_U_USE_FR, UNIT_SH4_U_SET_FR_0, UNIT_SH4_U_SET_FR, UNIT_SH4_U_LOAD_FR + , UNIT_SH4_U_MAYBE_FPU, UNIT_SH4_U_FPU, UNIT_SH4_U_TRAP, UNIT_SH4_U_WRITE_BACK + , UNIT_SH4_U_USE_MULTIPLY_RESULT, UNIT_SH4_U_SHIFT, UNIT_SH4_U_TAS, UNIT_SH4_U_MULSW + , UNIT_SH4_U_MULL, UNIT_SH4_U_DMUL, UNIT_SH4_U_MACL, UNIT_SH4_U_MACW + , UNIT_SH4_U_MULTIPLY, UNIT_SH4_U_SET_MAC, UNIT_SH4_U_LOAD_MAC, UNIT_SH4_U_LOAD_VBR + , UNIT_SH4_U_LOAD_GBR, UNIT_SH4_U_USE_GR, UNIT_SH4_U_LOAD_GR, UNIT_SH4_U_STC_VBR + , UNIT_SH4_U_LDCL_VBR, UNIT_SH4_U_LDCL, UNIT_SH4_U_USE_TBIT, UNIT_SH4_U_LDC_GBR + , UNIT_SH4_U_LDC_SR, UNIT_SH4_U_SET_SR_BIT, UNIT_SH4_U_USE_PR, UNIT_SH4_U_LOAD_PR + , UNIT_SH4_U_STS_PR, UNIT_SH4_U_LDS_PR, UNIT_SH4_U_MEMORY_ACCESS, UNIT_SH4_U_LOGIC_B + , UNIT_SH4_U_JSR, UNIT_SH4_U_JMP, UNIT_SH4_U_BRANCH, UNIT_SH4_U_SX + , UNIT_SH4_U_EXEC, UNIT_SH4A_NOFPU_U_OCB, UNIT_SH4A_NOFPU_U_MULR_GR, UNIT_SH4A_NOFPU_U_MULR + , UNIT_SH4A_NOFPU_U_FCNV, UNIT_SH4A_NOFPU_U_FCMP, UNIT_SH4A_NOFPU_U_FSQRT, UNIT_SH4A_NOFPU_U_FDIV + , UNIT_SH4A_NOFPU_U_FPU_LOAD_GR, UNIT_SH4A_NOFPU_U_USE_FPSCR, UNIT_SH4A_NOFPU_U_LDSL_FPSCR, UNIT_SH4A_NOFPU_U_LDS_FPSCR + , UNIT_SH4A_NOFPU_U_USE_FPUL, UNIT_SH4A_NOFPU_U_FLDS_FPUL, UNIT_SH4A_NOFPU_U_LOAD_FPUL, UNIT_SH4A_NOFPU_U_SET_FPUL + , UNIT_SH4A_NOFPU_U_FPU_MEMORY_ACCESS, UNIT_SH4A_NOFPU_U_USE_FR, UNIT_SH4A_NOFPU_U_SET_FR_0, UNIT_SH4A_NOFPU_U_SET_FR + , UNIT_SH4A_NOFPU_U_LOAD_FR, UNIT_SH4A_NOFPU_U_MAYBE_FPU, UNIT_SH4A_NOFPU_U_FPU, UNIT_SH4A_NOFPU_U_TRAP + , UNIT_SH4A_NOFPU_U_WRITE_BACK, UNIT_SH4A_NOFPU_U_USE_MULTIPLY_RESULT, UNIT_SH4A_NOFPU_U_SHIFT, UNIT_SH4A_NOFPU_U_TAS + , UNIT_SH4A_NOFPU_U_MULSW, UNIT_SH4A_NOFPU_U_MULL, UNIT_SH4A_NOFPU_U_DMUL, UNIT_SH4A_NOFPU_U_MACL + , UNIT_SH4A_NOFPU_U_MACW, UNIT_SH4A_NOFPU_U_MULTIPLY, UNIT_SH4A_NOFPU_U_SET_MAC, UNIT_SH4A_NOFPU_U_LOAD_MAC + , UNIT_SH4A_NOFPU_U_LOAD_VBR, UNIT_SH4A_NOFPU_U_LOAD_GBR, UNIT_SH4A_NOFPU_U_USE_GR, UNIT_SH4A_NOFPU_U_LOAD_GR + , UNIT_SH4A_NOFPU_U_STC_VBR, UNIT_SH4A_NOFPU_U_LDCL_VBR, UNIT_SH4A_NOFPU_U_LDCL, UNIT_SH4A_NOFPU_U_USE_TBIT + , UNIT_SH4A_NOFPU_U_LDC_GBR, UNIT_SH4A_NOFPU_U_LDC_SR, UNIT_SH4A_NOFPU_U_SET_SR_BIT, UNIT_SH4A_NOFPU_U_USE_PR + , UNIT_SH4A_NOFPU_U_LOAD_PR, UNIT_SH4A_NOFPU_U_STS_PR, UNIT_SH4A_NOFPU_U_LDS_PR, UNIT_SH4A_NOFPU_U_MEMORY_ACCESS + , UNIT_SH4A_NOFPU_U_LOGIC_B, UNIT_SH4A_NOFPU_U_JSR, UNIT_SH4A_NOFPU_U_JMP, UNIT_SH4A_NOFPU_U_BRANCH + , UNIT_SH4A_NOFPU_U_SX, UNIT_SH4A_NOFPU_U_EXEC, UNIT_SH4A_U_FTRV, UNIT_SH4A_U_FIPR + , UNIT_SH4A_U_OCB, UNIT_SH4A_U_MULR_GR, UNIT_SH4A_U_MULR, UNIT_SH4A_U_FCNV + , UNIT_SH4A_U_FCMP, UNIT_SH4A_U_FSQRT, UNIT_SH4A_U_FDIV, UNIT_SH4A_U_FPU_LOAD_GR + , UNIT_SH4A_U_USE_FPSCR, UNIT_SH4A_U_LDSL_FPSCR, UNIT_SH4A_U_LDS_FPSCR, UNIT_SH4A_U_USE_FPUL + , UNIT_SH4A_U_FLDS_FPUL, UNIT_SH4A_U_LOAD_FPUL, UNIT_SH4A_U_SET_FPUL, UNIT_SH4A_U_FPU_MEMORY_ACCESS + , UNIT_SH4A_U_USE_FR, UNIT_SH4A_U_SET_FR_0, UNIT_SH4A_U_SET_FR, UNIT_SH4A_U_LOAD_FR + , UNIT_SH4A_U_MAYBE_FPU, UNIT_SH4A_U_FPU, UNIT_SH4A_U_TRAP, UNIT_SH4A_U_WRITE_BACK + , UNIT_SH4A_U_USE_MULTIPLY_RESULT, UNIT_SH4A_U_SHIFT, UNIT_SH4A_U_TAS, UNIT_SH4A_U_MULSW + , UNIT_SH4A_U_MULL, UNIT_SH4A_U_DMUL, UNIT_SH4A_U_MACL, UNIT_SH4A_U_MACW + , UNIT_SH4A_U_MULTIPLY, UNIT_SH4A_U_SET_MAC, UNIT_SH4A_U_LOAD_MAC, UNIT_SH4A_U_LOAD_VBR + , UNIT_SH4A_U_LOAD_GBR, UNIT_SH4A_U_USE_GR, UNIT_SH4A_U_LOAD_GR, UNIT_SH4A_U_STC_VBR + , UNIT_SH4A_U_LDCL_VBR, UNIT_SH4A_U_LDCL, UNIT_SH4A_U_USE_TBIT, UNIT_SH4A_U_LDC_GBR + , UNIT_SH4A_U_LDC_SR, UNIT_SH4A_U_SET_SR_BIT, UNIT_SH4A_U_USE_PR, UNIT_SH4A_U_LOAD_PR + , UNIT_SH4A_U_STS_PR, UNIT_SH4A_U_LDS_PR, UNIT_SH4A_U_MEMORY_ACCESS, UNIT_SH4A_U_LOGIC_B + , UNIT_SH4A_U_JSR, UNIT_SH4A_U_JMP, UNIT_SH4A_U_BRANCH, UNIT_SH4A_U_SX + , UNIT_SH4A_U_EXEC, UNIT_SH4AL_U_OCB, UNIT_SH4AL_U_MULR_GR, UNIT_SH4AL_U_MULR + , UNIT_SH4AL_U_FCNV, UNIT_SH4AL_U_FCMP, UNIT_SH4AL_U_FSQRT, UNIT_SH4AL_U_FDIV + , UNIT_SH4AL_U_FPU_LOAD_GR, UNIT_SH4AL_U_USE_FPSCR, UNIT_SH4AL_U_LDSL_FPSCR, UNIT_SH4AL_U_LDS_FPSCR + , UNIT_SH4AL_U_USE_FPUL, UNIT_SH4AL_U_FLDS_FPUL, UNIT_SH4AL_U_LOAD_FPUL, UNIT_SH4AL_U_SET_FPUL + , UNIT_SH4AL_U_FPU_MEMORY_ACCESS, UNIT_SH4AL_U_USE_FR, UNIT_SH4AL_U_SET_FR_0, UNIT_SH4AL_U_SET_FR + , UNIT_SH4AL_U_LOAD_FR, UNIT_SH4AL_U_MAYBE_FPU, UNIT_SH4AL_U_FPU, UNIT_SH4AL_U_TRAP + , UNIT_SH4AL_U_WRITE_BACK, UNIT_SH4AL_U_USE_MULTIPLY_RESULT, UNIT_SH4AL_U_SHIFT, UNIT_SH4AL_U_TAS + , UNIT_SH4AL_U_MULSW, UNIT_SH4AL_U_MULL, UNIT_SH4AL_U_DMUL, UNIT_SH4AL_U_MACL + , UNIT_SH4AL_U_MACW, UNIT_SH4AL_U_MULTIPLY, UNIT_SH4AL_U_SET_MAC, UNIT_SH4AL_U_LOAD_MAC + , UNIT_SH4AL_U_LOAD_VBR, UNIT_SH4AL_U_LOAD_GBR, UNIT_SH4AL_U_USE_GR, UNIT_SH4AL_U_LOAD_GR + , UNIT_SH4AL_U_STC_VBR, UNIT_SH4AL_U_LDCL_VBR, UNIT_SH4AL_U_LDCL, UNIT_SH4AL_U_USE_TBIT + , UNIT_SH4AL_U_LDC_GBR, UNIT_SH4AL_U_LDC_SR, UNIT_SH4AL_U_SET_SR_BIT, UNIT_SH4AL_U_USE_PR + , UNIT_SH4AL_U_LOAD_PR, UNIT_SH4AL_U_STS_PR, UNIT_SH4AL_U_LDS_PR, UNIT_SH4AL_U_MEMORY_ACCESS + , UNIT_SH4AL_U_LOGIC_B, UNIT_SH4AL_U_JSR, UNIT_SH4AL_U_JMP, UNIT_SH4AL_U_BRANCH + , UNIT_SH4AL_U_SX, UNIT_SH4AL_U_EXEC, UNIT_SH5_U_FTRV, UNIT_SH5_U_FIPR + , UNIT_SH5_U_OCB, UNIT_SH5_U_MULR_GR, UNIT_SH5_U_MULR, UNIT_SH5_U_USE_DR + , UNIT_SH5_U_LOAD_DR, UNIT_SH5_U_SET_DR, UNIT_SH5_U_FCNV, UNIT_SH5_U_FCMP + , UNIT_SH5_U_FSQRT, UNIT_SH5_U_FDIV, UNIT_SH5_U_FPU_LOAD_GR, UNIT_SH5_U_USE_FPSCR + , UNIT_SH5_U_LDSL_FPSCR, UNIT_SH5_U_LDS_FPSCR, UNIT_SH5_U_USE_FPUL, UNIT_SH5_U_FLDS_FPUL + , UNIT_SH5_U_LOAD_FPUL, UNIT_SH5_U_SET_FPUL, UNIT_SH5_U_FPU_MEMORY_ACCESS, UNIT_SH5_U_USE_FR + , UNIT_SH5_U_SET_FR_0, UNIT_SH5_U_SET_FR, UNIT_SH5_U_LOAD_FR, UNIT_SH5_U_MAYBE_FPU + , UNIT_SH5_U_FPU, UNIT_SH5_U_TRAP, UNIT_SH5_U_WRITE_BACK, UNIT_SH5_U_USE_MULTIPLY_RESULT + , UNIT_SH5_U_SHIFT, UNIT_SH5_U_TAS, UNIT_SH5_U_MULSW, UNIT_SH5_U_MULL + , UNIT_SH5_U_DMUL, UNIT_SH5_U_MACL, UNIT_SH5_U_MACW, UNIT_SH5_U_MULTIPLY + , UNIT_SH5_U_SET_MAC, UNIT_SH5_U_LOAD_MAC, UNIT_SH5_U_LOAD_VBR, UNIT_SH5_U_LOAD_GBR + , UNIT_SH5_U_USE_GR, UNIT_SH5_U_LOAD_GR, UNIT_SH5_U_STC_VBR, UNIT_SH5_U_LDCL_VBR + , UNIT_SH5_U_LDCL, UNIT_SH5_U_USE_TBIT, UNIT_SH5_U_LDC_GBR, UNIT_SH5_U_LDC_SR + , UNIT_SH5_U_SET_SR_BIT, UNIT_SH5_U_USE_PR, UNIT_SH5_U_LOAD_PR, UNIT_SH5_U_STS_PR + , UNIT_SH5_U_LDS_PR, UNIT_SH5_U_MEMORY_ACCESS, UNIT_SH5_U_LOGIC_B, UNIT_SH5_U_JSR + , UNIT_SH5_U_JMP, UNIT_SH5_U_BRANCH, UNIT_SH5_U_SX, UNIT_SH5_U_EXEC + , UNIT_SH5_MEDIA_U_PUTCFG, UNIT_SH5_MEDIA_U_GETCFG, UNIT_SH5_MEDIA_U_PT, UNIT_SH5_MEDIA_U_FTRVS + , UNIT_SH5_MEDIA_U_FSQRTD, UNIT_SH5_MEDIA_U_FDIVD, UNIT_SH5_MEDIA_U_COND_BRANCH, UNIT_SH5_MEDIA_U_BLINK + , UNIT_SH5_MEDIA_U_USE_TR, UNIT_SH5_MEDIA_U_USE_MTRX, UNIT_SH5_MEDIA_U_USE_FV, UNIT_SH5_MEDIA_U_USE_FP + , UNIT_SH5_MEDIA_U_LOAD_MTRX, UNIT_SH5_MEDIA_U_LOAD_FV, UNIT_SH5_MEDIA_U_LOAD_FP, UNIT_SH5_MEDIA_U_SET_MTRX + , UNIT_SH5_MEDIA_U_SET_FV, UNIT_SH5_MEDIA_U_SET_FP, UNIT_SH5_MEDIA_U_SET_GR, UNIT_SH5_MEDIA_U_FTRV + , UNIT_SH5_MEDIA_U_FIPR, UNIT_SH5_MEDIA_U_OCB, UNIT_SH5_MEDIA_U_MULR_GR, UNIT_SH5_MEDIA_U_MULR + , UNIT_SH5_MEDIA_U_USE_DR, UNIT_SH5_MEDIA_U_LOAD_DR, UNIT_SH5_MEDIA_U_SET_DR, UNIT_SH5_MEDIA_U_FCNV + , UNIT_SH5_MEDIA_U_FCMP, UNIT_SH5_MEDIA_U_FSQRT, UNIT_SH5_MEDIA_U_FDIV, UNIT_SH5_MEDIA_U_FPU_LOAD_GR + , UNIT_SH5_MEDIA_U_USE_FPSCR, UNIT_SH5_MEDIA_U_LDSL_FPSCR, UNIT_SH5_MEDIA_U_LDS_FPSCR, UNIT_SH5_MEDIA_U_USE_FPUL + , UNIT_SH5_MEDIA_U_FLDS_FPUL, UNIT_SH5_MEDIA_U_LOAD_FPUL, UNIT_SH5_MEDIA_U_SET_FPUL, UNIT_SH5_MEDIA_U_FPU_MEMORY_ACCESS + , UNIT_SH5_MEDIA_U_USE_FR, UNIT_SH5_MEDIA_U_SET_FR_0, UNIT_SH5_MEDIA_U_SET_FR, UNIT_SH5_MEDIA_U_LOAD_FR + , UNIT_SH5_MEDIA_U_MAYBE_FPU, UNIT_SH5_MEDIA_U_FPU, UNIT_SH5_MEDIA_U_TRAP, UNIT_SH5_MEDIA_U_WRITE_BACK + , UNIT_SH5_MEDIA_U_USE_MULTIPLY_RESULT, UNIT_SH5_MEDIA_U_SHIFT, UNIT_SH5_MEDIA_U_TAS, UNIT_SH5_MEDIA_U_MULSW + , UNIT_SH5_MEDIA_U_MULL, UNIT_SH5_MEDIA_U_DMUL, UNIT_SH5_MEDIA_U_MACL, UNIT_SH5_MEDIA_U_MACW + , UNIT_SH5_MEDIA_U_MULTIPLY, UNIT_SH5_MEDIA_U_SET_MAC, UNIT_SH5_MEDIA_U_LOAD_MAC, UNIT_SH5_MEDIA_U_LOAD_VBR + , UNIT_SH5_MEDIA_U_LOAD_GBR, UNIT_SH5_MEDIA_U_USE_GR, UNIT_SH5_MEDIA_U_LOAD_GR, UNIT_SH5_MEDIA_U_STC_VBR + , UNIT_SH5_MEDIA_U_LDCL_VBR, UNIT_SH5_MEDIA_U_LDCL, UNIT_SH5_MEDIA_U_USE_TBIT, UNIT_SH5_MEDIA_U_LDC_GBR + , UNIT_SH5_MEDIA_U_LDC_SR, UNIT_SH5_MEDIA_U_SET_SR_BIT, UNIT_SH5_MEDIA_U_USE_PR, UNIT_SH5_MEDIA_U_LOAD_PR + , UNIT_SH5_MEDIA_U_STS_PR, UNIT_SH5_MEDIA_U_LDS_PR, UNIT_SH5_MEDIA_U_MEMORY_ACCESS, UNIT_SH5_MEDIA_U_LOGIC_B + , UNIT_SH5_MEDIA_U_JSR, UNIT_SH5_MEDIA_U_JMP, UNIT_SH5_MEDIA_U_BRANCH, UNIT_SH5_MEDIA_U_SX + , UNIT_SH5_MEDIA_U_EXEC, UNIT_SH2_U_TRAP, UNIT_SH2_U_WRITE_BACK, UNIT_SH2_U_USE_MULTIPLY_RESULT + , UNIT_SH2_U_SHIFT, UNIT_SH2_U_TAS, UNIT_SH2_U_MULSW, UNIT_SH2_U_MULL + , UNIT_SH2_U_DMUL, UNIT_SH2_U_MACL, UNIT_SH2_U_MACW, UNIT_SH2_U_MULTIPLY + , UNIT_SH2_U_SET_MAC, UNIT_SH2_U_LOAD_MAC, UNIT_SH2_U_LOAD_VBR, UNIT_SH2_U_LOAD_GBR + , UNIT_SH2_U_USE_GR, UNIT_SH2_U_LOAD_GR, UNIT_SH2_U_STC_VBR, UNIT_SH2_U_LDCL_VBR + , UNIT_SH2_U_LDCL, UNIT_SH2_U_USE_TBIT, UNIT_SH2_U_LDC_GBR, UNIT_SH2_U_LDC_SR + , UNIT_SH2_U_SET_SR_BIT, UNIT_SH2_U_USE_PR, UNIT_SH2_U_LOAD_PR, UNIT_SH2_U_STS_PR + , UNIT_SH2_U_LDS_PR, UNIT_SH2_U_MEMORY_ACCESS, UNIT_SH2_U_LOGIC_B, UNIT_SH2_U_JSR + , UNIT_SH2_U_JMP, UNIT_SH2_U_BRANCH, UNIT_SH2_U_SX, UNIT_SH2_U_EXEC + , UNIT_SH2E_U_FCNV, UNIT_SH2E_U_FCMP, UNIT_SH2E_U_FSQRT, UNIT_SH2E_U_FDIV + , UNIT_SH2E_U_FPU_LOAD_GR, UNIT_SH2E_U_USE_FPSCR, UNIT_SH2E_U_LDSL_FPSCR, UNIT_SH2E_U_LDS_FPSCR + , UNIT_SH2E_U_USE_FPUL, UNIT_SH2E_U_FLDS_FPUL, UNIT_SH2E_U_LOAD_FPUL, UNIT_SH2E_U_SET_FPUL + , UNIT_SH2E_U_FPU_MEMORY_ACCESS, UNIT_SH2E_U_USE_FR, UNIT_SH2E_U_SET_FR_0, UNIT_SH2E_U_SET_FR + , UNIT_SH2E_U_LOAD_FR, UNIT_SH2E_U_MAYBE_FPU, UNIT_SH2E_U_FPU, UNIT_SH2E_U_TRAP + , UNIT_SH2E_U_WRITE_BACK, UNIT_SH2E_U_USE_MULTIPLY_RESULT, UNIT_SH2E_U_SHIFT, UNIT_SH2E_U_TAS + , UNIT_SH2E_U_MULSW, UNIT_SH2E_U_MULL, UNIT_SH2E_U_DMUL, UNIT_SH2E_U_MACL + , UNIT_SH2E_U_MACW, UNIT_SH2E_U_MULTIPLY, UNIT_SH2E_U_SET_MAC, UNIT_SH2E_U_LOAD_MAC + , UNIT_SH2E_U_LOAD_VBR, UNIT_SH2E_U_LOAD_GBR, UNIT_SH2E_U_USE_GR, UNIT_SH2E_U_LOAD_GR + , UNIT_SH2E_U_STC_VBR, UNIT_SH2E_U_LDCL_VBR, UNIT_SH2E_U_LDCL, UNIT_SH2E_U_USE_TBIT + , UNIT_SH2E_U_LDC_GBR, UNIT_SH2E_U_LDC_SR, UNIT_SH2E_U_SET_SR_BIT, UNIT_SH2E_U_USE_PR + , UNIT_SH2E_U_LOAD_PR, UNIT_SH2E_U_STS_PR, UNIT_SH2E_U_LDS_PR, UNIT_SH2E_U_MEMORY_ACCESS + , UNIT_SH2E_U_LOGIC_B, UNIT_SH2E_U_JSR, UNIT_SH2E_U_JMP, UNIT_SH2E_U_BRANCH + , UNIT_SH2E_U_SX, UNIT_SH2E_U_EXEC, UNIT_SH3_U_TRAP, UNIT_SH3_U_WRITE_BACK + , UNIT_SH3_U_USE_MULTIPLY_RESULT, UNIT_SH3_U_SHIFT, UNIT_SH3_U_TAS, UNIT_SH3_U_MULSW + , UNIT_SH3_U_MULL, UNIT_SH3_U_DMUL, UNIT_SH3_U_MACL, UNIT_SH3_U_MACW + , UNIT_SH3_U_MULTIPLY, UNIT_SH3_U_SET_MAC, UNIT_SH3_U_LOAD_MAC, UNIT_SH3_U_LOAD_VBR + , UNIT_SH3_U_LOAD_GBR, UNIT_SH3_U_USE_GR, UNIT_SH3_U_LOAD_GR, UNIT_SH3_U_STC_VBR + , UNIT_SH3_U_LDCL_VBR, UNIT_SH3_U_LDCL, UNIT_SH3_U_USE_TBIT, UNIT_SH3_U_LDC_GBR + , UNIT_SH3_U_LDC_SR, UNIT_SH3_U_SET_SR_BIT, UNIT_SH3_U_USE_PR, UNIT_SH3_U_LOAD_PR + , UNIT_SH3_U_STS_PR, UNIT_SH3_U_LDS_PR, UNIT_SH3_U_MEMORY_ACCESS, UNIT_SH3_U_LOGIC_B + , UNIT_SH3_U_JSR, UNIT_SH3_U_JMP, UNIT_SH3_U_BRANCH, UNIT_SH3_U_SX + , UNIT_SH3_U_EXEC, UNIT_SH3E_U_FCNV, UNIT_SH3E_U_FCMP, UNIT_SH3E_U_FSQRT + , UNIT_SH3E_U_FDIV, UNIT_SH3E_U_FPU_LOAD_GR, UNIT_SH3E_U_USE_FPSCR, UNIT_SH3E_U_LDSL_FPSCR + , UNIT_SH3E_U_LDS_FPSCR, UNIT_SH3E_U_USE_FPUL, UNIT_SH3E_U_FLDS_FPUL, UNIT_SH3E_U_LOAD_FPUL + , UNIT_SH3E_U_SET_FPUL, UNIT_SH3E_U_FPU_MEMORY_ACCESS, UNIT_SH3E_U_USE_FR, UNIT_SH3E_U_SET_FR_0 + , UNIT_SH3E_U_SET_FR, UNIT_SH3E_U_LOAD_FR, UNIT_SH3E_U_MAYBE_FPU, UNIT_SH3E_U_FPU + , UNIT_SH3E_U_TRAP, UNIT_SH3E_U_WRITE_BACK, UNIT_SH3E_U_USE_MULTIPLY_RESULT, UNIT_SH3E_U_SHIFT + , UNIT_SH3E_U_TAS, UNIT_SH3E_U_MULSW, UNIT_SH3E_U_MULL, UNIT_SH3E_U_DMUL + , UNIT_SH3E_U_MACL, UNIT_SH3E_U_MACW, UNIT_SH3E_U_MULTIPLY, UNIT_SH3E_U_SET_MAC + , UNIT_SH3E_U_LOAD_MAC, UNIT_SH3E_U_LOAD_VBR, UNIT_SH3E_U_LOAD_GBR, UNIT_SH3E_U_USE_GR + , UNIT_SH3E_U_LOAD_GR, UNIT_SH3E_U_STC_VBR, UNIT_SH3E_U_LDCL_VBR, UNIT_SH3E_U_LDCL + , UNIT_SH3E_U_USE_TBIT, UNIT_SH3E_U_LDC_GBR, UNIT_SH3E_U_LDC_SR, UNIT_SH3E_U_SET_SR_BIT + , UNIT_SH3E_U_USE_PR, UNIT_SH3E_U_LOAD_PR, UNIT_SH3E_U_STS_PR, UNIT_SH3E_U_LDS_PR + , UNIT_SH3E_U_MEMORY_ACCESS, UNIT_SH3E_U_LOGIC_B, UNIT_SH3E_U_JSR, UNIT_SH3E_U_JMP + , UNIT_SH3E_U_BRANCH, UNIT_SH3E_U_SX, UNIT_SH3E_U_EXEC, UNIT_MAX } UNIT_TYPE; -#define MAX_UNITS (1) +#define MAX_UNITS (9) #endif /* SH_ARCH_H */ diff --git a/sim/sh64/cpu.c b/sim/sh64/cpu.c index bf3e2b2..a4eb9fe 100644 --- a/sim/sh64/cpu.c +++ b/sim/sh64/cpu.c @@ -2,9 +2,9 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -238,18 +238,18 @@ sh64_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval) /* Get the value of h-fp. */ -DF +SF sh64_h_fp_get (SIM_CPU *current_cpu, UINT regno) { - return CPU (h_fp[regno]); + return GET_H_FP (regno); } /* Set a value for h-fp. */ void -sh64_h_fp_set (SIM_CPU *current_cpu, UINT regno, DF newval) +sh64_h_fp_set (SIM_CPU *current_cpu, UINT regno, SF newval) { - CPU (h_fp[regno]) = newval; + SET_H_FP (regno, newval); } /* Get the value of h-fv. */ @@ -300,6 +300,38 @@ sh64_h_dr_set (SIM_CPU *current_cpu, UINT regno, DF newval) SET_H_DR (regno, newval); } +/* Get the value of h-fsd. */ + +DF +sh64_h_fsd_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_FSD (regno); +} + +/* Set a value for h-fsd. */ + +void +sh64_h_fsd_set (SIM_CPU *current_cpu, UINT regno, DF newval) +{ + SET_H_FSD (regno, newval); +} + +/* Get the value of h-fmov. */ + +DF +sh64_h_fmov_get (SIM_CPU *current_cpu, UINT regno) +{ + return GET_H_FMOV (regno); +} + +/* Set a value for h-fmov. */ + +void +sh64_h_fmov_set (SIM_CPU *current_cpu, UINT regno, DF newval) +{ + SET_H_FMOV (regno, newval); +} + /* Get the value of h-tr. */ DI @@ -428,36 +460,36 @@ sh64_h_fvc_set (SIM_CPU *current_cpu, UINT regno, SF newval) SET_H_FVC (regno, newval); } -/* Get the value of h-fpccr. */ +/* Get the value of h-gbr. */ SI -sh64_h_fpccr_get (SIM_CPU *current_cpu) +sh64_h_gbr_get (SIM_CPU *current_cpu) { - return GET_H_FPCCR (); + return GET_H_GBR (); } -/* Set a value for h-fpccr. */ +/* Set a value for h-gbr. */ void -sh64_h_fpccr_set (SIM_CPU *current_cpu, SI newval) +sh64_h_gbr_set (SIM_CPU *current_cpu, SI newval) { - SET_H_FPCCR (newval); + SET_H_GBR (newval); } -/* Get the value of h-gbr. */ +/* Get the value of h-vbr. */ SI -sh64_h_gbr_get (SIM_CPU *current_cpu) +sh64_h_vbr_get (SIM_CPU *current_cpu) { - return GET_H_GBR (); + return GET_H_VBR (); } -/* Set a value for h-gbr. */ +/* Set a value for h-vbr. */ void -sh64_h_gbr_set (SIM_CPU *current_cpu, SI newval) +sh64_h_vbr_set (SIM_CPU *current_cpu, SI newval) { - SET_H_GBR (newval); + SET_H_VBR (newval); } /* Get the value of h-pr. */ diff --git a/sim/sh64/cpu.h b/sim/sh64/cpu.h index 6e0d358..a5d6f34b 100644 --- a/sim/sh64/cpu.h +++ b/sim/sh64/cpu.h @@ -2,9 +2,9 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -80,10 +80,32 @@ CPU (h_cr[(index)]) = (x);\ SF h_fr[64]; #define GET_H_FR(a1) CPU (h_fr)[a1] #define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x)) - /* Single precision floating point register pairs */ - DF h_fp[32]; -#define GET_H_FP(a1) CPU (h_fp)[a1] -#define SET_H_FP(a1, x) (CPU (h_fp)[a1] = (x)) + /* Single/Double precision floating point registers */ + DF h_fsd[16]; +#define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), CPU (h_fr[index])))) +#define SET_H_FSD(index, x) \ +do { \ +if (GET_H_PRBIT ()) {\ +SET_H_DRC ((index), (x));\ +} else {\ +SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\ +}\ +;} while (0) + /* floating point registers for fmov */ + DF h_fmov[16]; +#define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index))))) +#define SET_H_FMOV(index, x) \ +do { \ +if (NOTBI (GET_H_SZBIT ())) {\ +SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\ +} else {\ +if ((((((index)) & (1))) == (1))) {\ +SET_H_XD ((((index)) & ((~ (1)))), (x));\ +} else {\ +SET_H_DR ((index), (x));\ +}\ +}\ +;} while (0) /* Branch target registers */ DI h_tr[8]; #define GET_H_TR(a1) CPU (h_tr)[a1] @@ -106,20 +128,20 @@ cgen_rtx_error (current_cpu, "cannot set ism directly");\ do { \ CPU (h_gr[(index)]) = EXTSIDI ((x));\ ;} while (0) -#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_sr), 14), 1) +#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_fpscr), 21), 1) #define SET_H_FRBIT(x) \ do { \ -CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (14))))), SLLSI ((x), 14));\ +CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (21))))), SLLSI ((x), 21));\ ;} while (0) -#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_sr), 13), 1) +#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_fpscr), 20), 1) #define SET_H_SZBIT(x) \ do { \ -CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (13))))), SLLSI ((x), 13));\ +CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (20))))), SLLSI ((x), 20));\ ;} while (0) -#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_sr), 12), 1) +#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_fpscr), 19), 1) #define SET_H_PRBIT(x) \ do { \ -CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (12))))), SLLSI ((x), 12));\ +CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (19))))), SLLSI ((x), 19));\ ;} while (0) #define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1) #define SET_H_SBIT(x) \ @@ -136,15 +158,20 @@ CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\ do { \ CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\ ;} while (0) -#define GET_H_FV(index) CPU (h_fr[MULQI (ANDQI (index, 15), 4)]) +#define GET_H_FP(index) CPU (h_fr[index]) +#define SET_H_FP(index, x) \ +do { \ +CPU (h_fr[(index)]) = (x);\ +;} while (0) +#define GET_H_FV(index) CPU (h_fr[index]) #define SET_H_FV(index, x) \ do { \ -CPU (h_fr[MULQI (ANDQI ((index), 15), 4)]) = (x);\ +CPU (h_fr[(index)]) = (x);\ ;} while (0) -#define GET_H_FMTX(index) CPU (h_fr[MULQI (ANDQI (index, 3), 16)]) +#define GET_H_FMTX(index) CPU (h_fr[index]) #define SET_H_FMTX(index, x) \ do { \ -CPU (h_fr[MULQI (ANDQI ((index), 3), 16)]) = (x);\ +CPU (h_fr[(index)]) = (x);\ ;} while (0) #define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))]))))) #define SET_H_DR(index, x) \ @@ -184,21 +211,16 @@ SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\ do { \ CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\ ;} while (0) -#define GET_H_FPCCR() ORSI (ORSI (ORSI (CPU (h_fpscr), SLLSI (GET_H_PRBIT (), 19)), SLLSI (GET_H_SZBIT (), 20)), SLLSI (GET_H_FRBIT (), 21)) -#define SET_H_FPCCR(x) \ -do { \ -{\ -CPU (h_fpscr) = (x);\ -SET_H_PRBIT (ANDSI (SRLSI ((x), 19), 1));\ -SET_H_SZBIT (ANDSI (SRLSI ((x), 20), 1));\ -SET_H_FRBIT (ANDSI (SRLSI ((x), 21), 1));\ -}\ -;} while (0) #define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1) #define SET_H_GBR(x) \ do { \ CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\ ;} while (0) +#define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1) +#define SET_H_VBR(x) \ +do { \ +CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\ +;} while (0) #define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1) #define SET_H_PR(x) \ do { \ @@ -247,14 +269,18 @@ BI sh64_h_qbit_get (SIM_CPU *); void sh64_h_qbit_set (SIM_CPU *, BI); SF sh64_h_fr_get (SIM_CPU *, UINT); void sh64_h_fr_set (SIM_CPU *, UINT, SF); -DF sh64_h_fp_get (SIM_CPU *, UINT); -void sh64_h_fp_set (SIM_CPU *, UINT, DF); +SF sh64_h_fp_get (SIM_CPU *, UINT); +void sh64_h_fp_set (SIM_CPU *, UINT, SF); SF sh64_h_fv_get (SIM_CPU *, UINT); void sh64_h_fv_set (SIM_CPU *, UINT, SF); SF sh64_h_fmtx_get (SIM_CPU *, UINT); void sh64_h_fmtx_set (SIM_CPU *, UINT, SF); DF sh64_h_dr_get (SIM_CPU *, UINT); void sh64_h_dr_set (SIM_CPU *, UINT, DF); +DF sh64_h_fsd_get (SIM_CPU *, UINT); +void sh64_h_fsd_set (SIM_CPU *, UINT, DF); +DF sh64_h_fmov_get (SIM_CPU *, UINT); +void sh64_h_fmov_set (SIM_CPU *, UINT, DF); DI sh64_h_tr_get (SIM_CPU *, UINT); void sh64_h_tr_set (SIM_CPU *, UINT, DI); BI sh64_h_endian_get (SIM_CPU *); @@ -271,10 +297,10 @@ DF sh64_h_xd_get (SIM_CPU *, UINT); void sh64_h_xd_set (SIM_CPU *, UINT, DF); SF sh64_h_fvc_get (SIM_CPU *, UINT); void sh64_h_fvc_set (SIM_CPU *, UINT, SF); -SI sh64_h_fpccr_get (SIM_CPU *); -void sh64_h_fpccr_set (SIM_CPU *, SI); SI sh64_h_gbr_get (SIM_CPU *); void sh64_h_gbr_set (SIM_CPU *, SI); +SI sh64_h_vbr_get (SIM_CPU *); +void sh64_h_vbr_set (SIM_CPU *, SI); SI sh64_h_pr_get (SIM_CPU *); void sh64_h_pr_set (SIM_CPU *, SI); SI sh64_h_macl_get (SIM_CPU *); @@ -290,8 +316,16 @@ extern CPUREG_STORE_FN sh64_store_register; typedef struct { int empty; +} MODEL_SH4_DATA; + +typedef struct { + int empty; } MODEL_SH5_DATA; +typedef struct { + int empty; +} MODEL_SH5_MEDIA_DATA; + /* Collection of various things for the trace handler to use. */ typedef struct trace_record { diff --git a/sim/sh64/cpuall.h b/sim/sh64/cpuall.h index ba6a1e5..55a57ee 100644 --- a/sim/sh64/cpuall.h +++ b/sim/sh64/cpuall.h @@ -2,9 +2,9 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -35,9 +35,16 @@ with this program; if not, write to the Free Software Foundation, Inc., #endif extern const MACH sh2_mach; +extern const MACH sh2e_mach; +extern const MACH sh2a_fpu_mach; +extern const MACH sh2a_nofpu_mach; extern const MACH sh3_mach; extern const MACH sh3e_mach; +extern const MACH sh4_nofpu_mach; extern const MACH sh4_mach; +extern const MACH sh4a_nofpu_mach; +extern const MACH sh4a_mach; +extern const MACH sh4al_mach; extern const MACH sh5_mach; #ifndef WANT_CPU diff --git a/sim/sh64/decode-compact.c b/sim/sh64/decode-compact.c index ce85438..ed38ac8 100644 --- a/sim/sh64/decode-compact.c +++ b/sim/sh64/decode-compact.c @@ -2,9 +2,9 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -33,7 +33,7 @@ with this program; if not, write to the Free Software Foundation, Inc., teensy bit of cpu in the decoder. Moving it to malloc space is trivial but won't be done until necessary (we don't currently support the runtime addition of instructions nor an SMP machine with different cpus). */ -static IDESC sh64_compact_insn_data[SH64_COMPACT_INSN_MAX]; +static IDESC sh64_compact_insn_data[SH64_COMPACT_INSN__MAX]; /* Commas between elements are contained in the macros. Some of these are conditionally compiled out. */ @@ -54,14 +54,14 @@ static const struct insn_sem sh64_compact_insn_sem[] = { SH_INSN_ANDI_COMPACT, SH64_COMPACT_INSN_ANDI_COMPACT, SH64_COMPACT_SFMT_ANDI_COMPACT }, { SH_INSN_ANDB_COMPACT, SH64_COMPACT_INSN_ANDB_COMPACT, SH64_COMPACT_SFMT_ANDB_COMPACT }, { SH_INSN_BF_COMPACT, SH64_COMPACT_INSN_BF_COMPACT, SH64_COMPACT_SFMT_BF_COMPACT }, - { SH_INSN_BFS_COMPACT, SH64_COMPACT_INSN_BFS_COMPACT, SH64_COMPACT_SFMT_BF_COMPACT }, + { SH_INSN_BFS_COMPACT, SH64_COMPACT_INSN_BFS_COMPACT, SH64_COMPACT_SFMT_BFS_COMPACT }, { SH_INSN_BRA_COMPACT, SH64_COMPACT_INSN_BRA_COMPACT, SH64_COMPACT_SFMT_BRA_COMPACT }, { SH_INSN_BRAF_COMPACT, SH64_COMPACT_INSN_BRAF_COMPACT, SH64_COMPACT_SFMT_BRAF_COMPACT }, { SH_INSN_BRK_COMPACT, SH64_COMPACT_INSN_BRK_COMPACT, SH64_COMPACT_SFMT_BRK_COMPACT }, { SH_INSN_BSR_COMPACT, SH64_COMPACT_INSN_BSR_COMPACT, SH64_COMPACT_SFMT_BSR_COMPACT }, { SH_INSN_BSRF_COMPACT, SH64_COMPACT_INSN_BSRF_COMPACT, SH64_COMPACT_SFMT_BSRF_COMPACT }, { SH_INSN_BT_COMPACT, SH64_COMPACT_INSN_BT_COMPACT, SH64_COMPACT_SFMT_BF_COMPACT }, - { SH_INSN_BTS_COMPACT, SH64_COMPACT_INSN_BTS_COMPACT, SH64_COMPACT_SFMT_BF_COMPACT }, + { SH_INSN_BTS_COMPACT, SH64_COMPACT_INSN_BTS_COMPACT, SH64_COMPACT_SFMT_BFS_COMPACT }, { SH_INSN_CLRMAC_COMPACT, SH64_COMPACT_INSN_CLRMAC_COMPACT, SH64_COMPACT_SFMT_CLRMAC_COMPACT }, { SH_INSN_CLRS_COMPACT, SH64_COMPACT_INSN_CLRS_COMPACT, SH64_COMPACT_SFMT_CLRS_COMPACT }, { SH_INSN_CLRT_COMPACT, SH64_COMPACT_INSN_CLRT_COMPACT, SH64_COMPACT_SFMT_CLRT_COMPACT }, @@ -77,6 +77,8 @@ static const struct insn_sem sh64_compact_insn_sem[] = { SH_INSN_DIV0S_COMPACT, SH64_COMPACT_INSN_DIV0S_COMPACT, SH64_COMPACT_SFMT_DIV0S_COMPACT }, { SH_INSN_DIV0U_COMPACT, SH64_COMPACT_INSN_DIV0U_COMPACT, SH64_COMPACT_SFMT_DIV0U_COMPACT }, { SH_INSN_DIV1_COMPACT, SH64_COMPACT_INSN_DIV1_COMPACT, SH64_COMPACT_SFMT_DIV1_COMPACT }, + { SH_INSN_DIVU_COMPACT, SH64_COMPACT_INSN_DIVU_COMPACT, SH64_COMPACT_SFMT_DIVU_COMPACT }, + { SH_INSN_MULR_COMPACT, SH64_COMPACT_INSN_MULR_COMPACT, SH64_COMPACT_SFMT_DIVU_COMPACT }, { SH_INSN_DMULSL_COMPACT, SH64_COMPACT_INSN_DMULSL_COMPACT, SH64_COMPACT_SFMT_DMULSL_COMPACT }, { SH_INSN_DMULUL_COMPACT, SH64_COMPACT_INSN_DMULUL_COMPACT, SH64_COMPACT_SFMT_DMULSL_COMPACT }, { SH_INSN_DT_COMPACT, SH64_COMPACT_INSN_DT_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT }, @@ -104,6 +106,8 @@ static const struct insn_sem sh64_compact_insn_sem[] = { SH_INSN_FMOV5_COMPACT, SH64_COMPACT_INSN_FMOV5_COMPACT, SH64_COMPACT_SFMT_FMOV5_COMPACT }, { SH_INSN_FMOV6_COMPACT, SH64_COMPACT_INSN_FMOV6_COMPACT, SH64_COMPACT_SFMT_FMOV6_COMPACT }, { SH_INSN_FMOV7_COMPACT, SH64_COMPACT_INSN_FMOV7_COMPACT, SH64_COMPACT_SFMT_FMOV7_COMPACT }, + { SH_INSN_FMOV8_COMPACT, SH64_COMPACT_INSN_FMOV8_COMPACT, SH64_COMPACT_SFMT_FMOV8_COMPACT }, + { SH_INSN_FMOV9_COMPACT, SH64_COMPACT_INSN_FMOV9_COMPACT, SH64_COMPACT_SFMT_FMOV9_COMPACT }, { SH_INSN_FMUL_COMPACT, SH64_COMPACT_INSN_FMUL_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT }, { SH_INSN_FNEG_COMPACT, SH64_COMPACT_INSN_FNEG_COMPACT, SH64_COMPACT_SFMT_FABS_COMPACT }, { SH_INSN_FRCHG_COMPACT, SH64_COMPACT_INSN_FRCHG_COMPACT, SH64_COMPACT_SFMT_FRCHG_COMPACT }, @@ -113,10 +117,13 @@ static const struct insn_sem sh64_compact_insn_sem[] = { SH_INSN_FSUB_COMPACT, SH64_COMPACT_INSN_FSUB_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT }, { SH_INSN_FTRC_COMPACT, SH64_COMPACT_INSN_FTRC_COMPACT, SH64_COMPACT_SFMT_FTRC_COMPACT }, { SH_INSN_FTRV_COMPACT, SH64_COMPACT_INSN_FTRV_COMPACT, SH64_COMPACT_SFMT_FTRV_COMPACT }, - { SH_INSN_JMP_COMPACT, SH64_COMPACT_INSN_JMP_COMPACT, SH64_COMPACT_SFMT_JMP_COMPACT }, + { SH_INSN_JMP_COMPACT, SH64_COMPACT_INSN_JMP_COMPACT, SH64_COMPACT_SFMT_BRAF_COMPACT }, { SH_INSN_JSR_COMPACT, SH64_COMPACT_INSN_JSR_COMPACT, SH64_COMPACT_SFMT_BSRF_COMPACT }, - { SH_INSN_LDC_COMPACT, SH64_COMPACT_INSN_LDC_COMPACT, SH64_COMPACT_SFMT_LDC_COMPACT }, - { SH_INSN_LDCL_COMPACT, SH64_COMPACT_INSN_LDCL_COMPACT, SH64_COMPACT_SFMT_LDCL_COMPACT }, + { SH_INSN_LDC_GBR_COMPACT, SH64_COMPACT_INSN_LDC_GBR_COMPACT, SH64_COMPACT_SFMT_LDC_GBR_COMPACT }, + { SH_INSN_LDC_VBR_COMPACT, SH64_COMPACT_INSN_LDC_VBR_COMPACT, SH64_COMPACT_SFMT_LDC_VBR_COMPACT }, + { SH_INSN_LDC_SR_COMPACT, SH64_COMPACT_INSN_LDC_SR_COMPACT, SH64_COMPACT_SFMT_LDC_SR_COMPACT }, + { SH_INSN_LDCL_GBR_COMPACT, SH64_COMPACT_INSN_LDCL_GBR_COMPACT, SH64_COMPACT_SFMT_LDCL_GBR_COMPACT }, + { SH_INSN_LDCL_VBR_COMPACT, SH64_COMPACT_INSN_LDCL_VBR_COMPACT, SH64_COMPACT_SFMT_LDCL_VBR_COMPACT }, { SH_INSN_LDS_FPSCR_COMPACT, SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDS_FPSCR_COMPACT }, { SH_INSN_LDSL_FPSCR_COMPACT, SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDSL_FPSCR_COMPACT }, { SH_INSN_LDS_FPUL_COMPACT, SH64_COMPACT_INSN_LDS_FPUL_COMPACT, SH64_COMPACT_SFMT_LDS_FPUL_COMPACT }, @@ -131,6 +138,7 @@ static const struct insn_sem sh64_compact_insn_sem[] = { SH_INSN_MACW_COMPACT, SH64_COMPACT_INSN_MACW_COMPACT, SH64_COMPACT_SFMT_MACW_COMPACT }, { SH_INSN_MOV_COMPACT, SH64_COMPACT_INSN_MOV_COMPACT, SH64_COMPACT_SFMT_MOV_COMPACT }, { SH_INSN_MOVI_COMPACT, SH64_COMPACT_INSN_MOVI_COMPACT, SH64_COMPACT_SFMT_MOVI_COMPACT }, + { SH_INSN_MOVI20_COMPACT, SH64_COMPACT_INSN_MOVI20_COMPACT, SH64_COMPACT_SFMT_MOVI20_COMPACT }, { SH_INSN_MOVB1_COMPACT, SH64_COMPACT_INSN_MOVB1_COMPACT, SH64_COMPACT_SFMT_MOVB1_COMPACT }, { SH_INSN_MOVB2_COMPACT, SH64_COMPACT_INSN_MOVB2_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT }, { SH_INSN_MOVB3_COMPACT, SH64_COMPACT_INSN_MOVB3_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT }, @@ -141,31 +149,36 @@ static const struct insn_sem sh64_compact_insn_sem[] = { SH_INSN_MOVB8_COMPACT, SH64_COMPACT_INSN_MOVB8_COMPACT, SH64_COMPACT_SFMT_MOVB8_COMPACT }, { SH_INSN_MOVB9_COMPACT, SH64_COMPACT_INSN_MOVB9_COMPACT, SH64_COMPACT_SFMT_MOVB9_COMPACT }, { SH_INSN_MOVB10_COMPACT, SH64_COMPACT_INSN_MOVB10_COMPACT, SH64_COMPACT_SFMT_MOVB10_COMPACT }, - { SH_INSN_MOVL1_COMPACT, SH64_COMPACT_INSN_MOVL1_COMPACT, SH64_COMPACT_SFMT_MOVB1_COMPACT }, - { SH_INSN_MOVL2_COMPACT, SH64_COMPACT_INSN_MOVL2_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT }, - { SH_INSN_MOVL3_COMPACT, SH64_COMPACT_INSN_MOVL3_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT }, + { SH_INSN_MOVL1_COMPACT, SH64_COMPACT_INSN_MOVL1_COMPACT, SH64_COMPACT_SFMT_MOVL1_COMPACT }, + { SH_INSN_MOVL2_COMPACT, SH64_COMPACT_INSN_MOVL2_COMPACT, SH64_COMPACT_SFMT_MOVL2_COMPACT }, + { SH_INSN_MOVL3_COMPACT, SH64_COMPACT_INSN_MOVL3_COMPACT, SH64_COMPACT_SFMT_MOVL3_COMPACT }, { SH_INSN_MOVL4_COMPACT, SH64_COMPACT_INSN_MOVL4_COMPACT, SH64_COMPACT_SFMT_MOVL4_COMPACT }, { SH_INSN_MOVL5_COMPACT, SH64_COMPACT_INSN_MOVL5_COMPACT, SH64_COMPACT_SFMT_MOVL5_COMPACT }, - { SH_INSN_MOVL6_COMPACT, SH64_COMPACT_INSN_MOVL6_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT }, + { SH_INSN_MOVL6_COMPACT, SH64_COMPACT_INSN_MOVL6_COMPACT, SH64_COMPACT_SFMT_MOVL6_COMPACT }, { SH_INSN_MOVL7_COMPACT, SH64_COMPACT_INSN_MOVL7_COMPACT, SH64_COMPACT_SFMT_MOVL7_COMPACT }, - { SH_INSN_MOVL8_COMPACT, SH64_COMPACT_INSN_MOVL8_COMPACT, SH64_COMPACT_SFMT_MOVB8_COMPACT }, + { SH_INSN_MOVL8_COMPACT, SH64_COMPACT_INSN_MOVL8_COMPACT, SH64_COMPACT_SFMT_MOVL8_COMPACT }, { SH_INSN_MOVL9_COMPACT, SH64_COMPACT_INSN_MOVL9_COMPACT, SH64_COMPACT_SFMT_MOVL9_COMPACT }, { SH_INSN_MOVL10_COMPACT, SH64_COMPACT_INSN_MOVL10_COMPACT, SH64_COMPACT_SFMT_MOVL10_COMPACT }, { SH_INSN_MOVL11_COMPACT, SH64_COMPACT_INSN_MOVL11_COMPACT, SH64_COMPACT_SFMT_MOVL11_COMPACT }, - { SH_INSN_MOVW1_COMPACT, SH64_COMPACT_INSN_MOVW1_COMPACT, SH64_COMPACT_SFMT_MOVB1_COMPACT }, - { SH_INSN_MOVW2_COMPACT, SH64_COMPACT_INSN_MOVW2_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT }, - { SH_INSN_MOVW3_COMPACT, SH64_COMPACT_INSN_MOVW3_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT }, + { SH_INSN_MOVL12_COMPACT, SH64_COMPACT_INSN_MOVL12_COMPACT, SH64_COMPACT_SFMT_MOVL12_COMPACT }, + { SH_INSN_MOVL13_COMPACT, SH64_COMPACT_INSN_MOVL13_COMPACT, SH64_COMPACT_SFMT_MOVL13_COMPACT }, + { SH_INSN_MOVW1_COMPACT, SH64_COMPACT_INSN_MOVW1_COMPACT, SH64_COMPACT_SFMT_MOVW1_COMPACT }, + { SH_INSN_MOVW2_COMPACT, SH64_COMPACT_INSN_MOVW2_COMPACT, SH64_COMPACT_SFMT_MOVW2_COMPACT }, + { SH_INSN_MOVW3_COMPACT, SH64_COMPACT_INSN_MOVW3_COMPACT, SH64_COMPACT_SFMT_MOVW3_COMPACT }, { SH_INSN_MOVW4_COMPACT, SH64_COMPACT_INSN_MOVW4_COMPACT, SH64_COMPACT_SFMT_MOVW4_COMPACT }, { SH_INSN_MOVW5_COMPACT, SH64_COMPACT_INSN_MOVW5_COMPACT, SH64_COMPACT_SFMT_MOVW5_COMPACT }, - { SH_INSN_MOVW6_COMPACT, SH64_COMPACT_INSN_MOVW6_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT }, - { SH_INSN_MOVW7_COMPACT, SH64_COMPACT_INSN_MOVW7_COMPACT, SH64_COMPACT_SFMT_MOVB7_COMPACT }, - { SH_INSN_MOVW8_COMPACT, SH64_COMPACT_INSN_MOVW8_COMPACT, SH64_COMPACT_SFMT_MOVB8_COMPACT }, + { SH_INSN_MOVW6_COMPACT, SH64_COMPACT_INSN_MOVW6_COMPACT, SH64_COMPACT_SFMT_MOVW6_COMPACT }, + { SH_INSN_MOVW7_COMPACT, SH64_COMPACT_INSN_MOVW7_COMPACT, SH64_COMPACT_SFMT_MOVW7_COMPACT }, + { SH_INSN_MOVW8_COMPACT, SH64_COMPACT_INSN_MOVW8_COMPACT, SH64_COMPACT_SFMT_MOVW8_COMPACT }, { SH_INSN_MOVW9_COMPACT, SH64_COMPACT_INSN_MOVW9_COMPACT, SH64_COMPACT_SFMT_MOVW9_COMPACT }, { SH_INSN_MOVW10_COMPACT, SH64_COMPACT_INSN_MOVW10_COMPACT, SH64_COMPACT_SFMT_MOVW10_COMPACT }, { SH_INSN_MOVW11_COMPACT, SH64_COMPACT_INSN_MOVW11_COMPACT, SH64_COMPACT_SFMT_MOVW11_COMPACT }, { SH_INSN_MOVA_COMPACT, SH64_COMPACT_INSN_MOVA_COMPACT, SH64_COMPACT_SFMT_MOVA_COMPACT }, { SH_INSN_MOVCAL_COMPACT, SH64_COMPACT_INSN_MOVCAL_COMPACT, SH64_COMPACT_SFMT_MOVCAL_COMPACT }, + { SH_INSN_MOVCOL_COMPACT, SH64_COMPACT_INSN_MOVCOL_COMPACT, SH64_COMPACT_SFMT_MOVCOL_COMPACT }, { SH_INSN_MOVT_COMPACT, SH64_COMPACT_INSN_MOVT_COMPACT, SH64_COMPACT_SFMT_MOVT_COMPACT }, + { SH_INSN_MOVUAL_COMPACT, SH64_COMPACT_INSN_MOVUAL_COMPACT, SH64_COMPACT_SFMT_MOVUAL_COMPACT }, + { SH_INSN_MOVUAL2_COMPACT, SH64_COMPACT_INSN_MOVUAL2_COMPACT, SH64_COMPACT_SFMT_MOVUAL2_COMPACT }, { SH_INSN_MULL_COMPACT, SH64_COMPACT_INSN_MULL_COMPACT, SH64_COMPACT_SFMT_MULL_COMPACT }, { SH_INSN_MULSW_COMPACT, SH64_COMPACT_INSN_MULSW_COMPACT, SH64_COMPACT_SFMT_MULL_COMPACT }, { SH_INSN_MULUW_COMPACT, SH64_COMPACT_INSN_MULUW_COMPACT, SH64_COMPACT_SFMT_MULL_COMPACT }, @@ -173,13 +186,13 @@ static const struct insn_sem sh64_compact_insn_sem[] = { SH_INSN_NEGC_COMPACT, SH64_COMPACT_INSN_NEGC_COMPACT, SH64_COMPACT_SFMT_NEGC_COMPACT }, { SH_INSN_NOP_COMPACT, SH64_COMPACT_INSN_NOP_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT }, { SH_INSN_NOT_COMPACT, SH64_COMPACT_INSN_NOT_COMPACT, SH64_COMPACT_SFMT_MOV_COMPACT }, - { SH_INSN_OCBI_COMPACT, SH64_COMPACT_INSN_OCBI_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT }, - { SH_INSN_OCBP_COMPACT, SH64_COMPACT_INSN_OCBP_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT }, - { SH_INSN_OCBWB_COMPACT, SH64_COMPACT_INSN_OCBWB_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT }, + { SH_INSN_OCBI_COMPACT, SH64_COMPACT_INSN_OCBI_COMPACT, SH64_COMPACT_SFMT_MOVCOL_COMPACT }, + { SH_INSN_OCBP_COMPACT, SH64_COMPACT_INSN_OCBP_COMPACT, SH64_COMPACT_SFMT_MOVCOL_COMPACT }, + { SH_INSN_OCBWB_COMPACT, SH64_COMPACT_INSN_OCBWB_COMPACT, SH64_COMPACT_SFMT_MOVCOL_COMPACT }, { SH_INSN_OR_COMPACT, SH64_COMPACT_INSN_OR_COMPACT, SH64_COMPACT_SFMT_AND_COMPACT }, { SH_INSN_ORI_COMPACT, SH64_COMPACT_INSN_ORI_COMPACT, SH64_COMPACT_SFMT_ANDI_COMPACT }, { SH_INSN_ORB_COMPACT, SH64_COMPACT_INSN_ORB_COMPACT, SH64_COMPACT_SFMT_ANDB_COMPACT }, - { SH_INSN_PREF_COMPACT, SH64_COMPACT_INSN_PREF_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT }, + { SH_INSN_PREF_COMPACT, SH64_COMPACT_INSN_PREF_COMPACT, SH64_COMPACT_SFMT_PREF_COMPACT }, { SH_INSN_ROTCL_COMPACT, SH64_COMPACT_INSN_ROTCL_COMPACT, SH64_COMPACT_SFMT_ROTCL_COMPACT }, { SH_INSN_ROTCR_COMPACT, SH64_COMPACT_INSN_ROTCR_COMPACT, SH64_COMPACT_SFMT_ROTCL_COMPACT }, { SH_INSN_ROTL_COMPACT, SH64_COMPACT_INSN_ROTL_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT }, @@ -192,15 +205,17 @@ static const struct insn_sem sh64_compact_insn_sem[] = { SH_INSN_SHAR_COMPACT, SH64_COMPACT_INSN_SHAR_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT }, { SH_INSN_SHLD_COMPACT, SH64_COMPACT_INSN_SHLD_COMPACT, SH64_COMPACT_SFMT_SHAD_COMPACT }, { SH_INSN_SHLL_COMPACT, SH64_COMPACT_INSN_SHLL_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT }, - { SH_INSN_SHLL2_COMPACT, SH64_COMPACT_INSN_SHLL2_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT }, - { SH_INSN_SHLL8_COMPACT, SH64_COMPACT_INSN_SHLL8_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT }, - { SH_INSN_SHLL16_COMPACT, SH64_COMPACT_INSN_SHLL16_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT }, + { SH_INSN_SHLL2_COMPACT, SH64_COMPACT_INSN_SHLL2_COMPACT, SH64_COMPACT_SFMT_MOVCOL_COMPACT }, + { SH_INSN_SHLL8_COMPACT, SH64_COMPACT_INSN_SHLL8_COMPACT, SH64_COMPACT_SFMT_MOVCOL_COMPACT }, + { SH_INSN_SHLL16_COMPACT, SH64_COMPACT_INSN_SHLL16_COMPACT, SH64_COMPACT_SFMT_MOVCOL_COMPACT }, { SH_INSN_SHLR_COMPACT, SH64_COMPACT_INSN_SHLR_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT }, - { SH_INSN_SHLR2_COMPACT, SH64_COMPACT_INSN_SHLR2_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT }, - { SH_INSN_SHLR8_COMPACT, SH64_COMPACT_INSN_SHLR8_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT }, - { SH_INSN_SHLR16_COMPACT, SH64_COMPACT_INSN_SHLR16_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT }, + { SH_INSN_SHLR2_COMPACT, SH64_COMPACT_INSN_SHLR2_COMPACT, SH64_COMPACT_SFMT_MOVCOL_COMPACT }, + { SH_INSN_SHLR8_COMPACT, SH64_COMPACT_INSN_SHLR8_COMPACT, SH64_COMPACT_SFMT_MOVCOL_COMPACT }, + { SH_INSN_SHLR16_COMPACT, SH64_COMPACT_INSN_SHLR16_COMPACT, SH64_COMPACT_SFMT_MOVCOL_COMPACT }, { SH_INSN_STC_GBR_COMPACT, SH64_COMPACT_INSN_STC_GBR_COMPACT, SH64_COMPACT_SFMT_STC_GBR_COMPACT }, + { SH_INSN_STC_VBR_COMPACT, SH64_COMPACT_INSN_STC_VBR_COMPACT, SH64_COMPACT_SFMT_STC_VBR_COMPACT }, { SH_INSN_STCL_GBR_COMPACT, SH64_COMPACT_INSN_STCL_GBR_COMPACT, SH64_COMPACT_SFMT_STCL_GBR_COMPACT }, + { SH_INSN_STCL_VBR_COMPACT, SH64_COMPACT_INSN_STCL_VBR_COMPACT, SH64_COMPACT_SFMT_STCL_VBR_COMPACT }, { SH_INSN_STS_FPSCR_COMPACT, SH64_COMPACT_INSN_STS_FPSCR_COMPACT, SH64_COMPACT_SFMT_STS_FPSCR_COMPACT }, { SH_INSN_STSL_FPSCR_COMPACT, SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_STSL_FPSCR_COMPACT }, { SH_INSN_STS_FPUL_COMPACT, SH64_COMPACT_INSN_STS_FPUL_COMPACT, SH64_COMPACT_SFMT_STS_FPUL_COMPACT }, @@ -222,7 +237,7 @@ static const struct insn_sem sh64_compact_insn_sem[] = { SH_INSN_TSTI_COMPACT, SH64_COMPACT_INSN_TSTI_COMPACT, SH64_COMPACT_SFMT_TSTI_COMPACT }, { SH_INSN_TSTB_COMPACT, SH64_COMPACT_INSN_TSTB_COMPACT, SH64_COMPACT_SFMT_TSTB_COMPACT }, { SH_INSN_XOR_COMPACT, SH64_COMPACT_INSN_XOR_COMPACT, SH64_COMPACT_SFMT_AND_COMPACT }, - { SH_INSN_XORI_COMPACT, SH64_COMPACT_INSN_XORI_COMPACT, SH64_COMPACT_SFMT_XORI_COMPACT }, + { SH_INSN_XORI_COMPACT, SH64_COMPACT_INSN_XORI_COMPACT, SH64_COMPACT_SFMT_ANDI_COMPACT }, { SH_INSN_XORB_COMPACT, SH64_COMPACT_INSN_XORB_COMPACT, SH64_COMPACT_SFMT_ANDB_COMPACT }, { SH_INSN_XTRCT_COMPACT, SH64_COMPACT_INSN_XTRCT_COMPACT, SH64_COMPACT_SFMT_ADD_COMPACT }, }; @@ -266,7 +281,7 @@ sh64_compact_init_idesc_table (SIM_CPU *cpu) { IDESC *id,*tabend; const struct insn_sem *t,*tend; - int tabsize = SH64_COMPACT_INSN_MAX; + int tabsize = SH64_COMPACT_INSN__MAX; IDESC *table = sh64_compact_insn_data; memset (table, 0, tabsize * sizeof (IDESC)); @@ -301,175 +316,225 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_INT insn = base_insn; { - unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 0) & (15 << 0))); + unsigned int val = (((insn >> 5) & (15 << 7)) | ((insn >> 0) & (127 << 0))); switch (val) { - case 2 : itype = SH64_COMPACT_INSN_STC_GBR_COMPACT; goto extract_sfmt_stc_gbr_compact; case 3 : + case 0 : /* fall through */ + case 16 : /* fall through */ + case 32 : /* fall through */ + case 48 : /* fall through */ + case 64 : /* fall through */ + case 80 : /* fall through */ + case 96 : /* fall through */ + case 112 : + if ((entire_insn & 0xf00f0000) == 0x0) + { itype = SH64_COMPACT_INSN_MOVI20_COMPACT; goto extract_sfmt_movi20_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 3 : { - unsigned int val = (((insn >> 4) & (15 << 0))); + unsigned int val = (((insn >> 7) & (1 << 0))); switch (val) { - case 0 : itype = SH64_COMPACT_INSN_BSRF_COMPACT; goto extract_sfmt_bsrf_compact; case 2 : itype = SH64_COMPACT_INSN_BRAF_COMPACT; goto extract_sfmt_braf_compact; case 8 : itype = SH64_COMPACT_INSN_PREF_COMPACT; goto extract_sfmt_nop_compact; case 9 : itype = SH64_COMPACT_INSN_OCBI_COMPACT; goto extract_sfmt_nop_compact; case 10 : itype = SH64_COMPACT_INSN_OCBP_COMPACT; goto extract_sfmt_nop_compact; case 11 : itype = SH64_COMPACT_INSN_OCBWB_COMPACT; goto extract_sfmt_nop_compact; case 12 : itype = SH64_COMPACT_INSN_MOVCAL_COMPACT; goto extract_sfmt_movcal_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 4 : itype = SH64_COMPACT_INSN_MOVB3_COMPACT; goto extract_sfmt_movb3_compact; case 5 : itype = SH64_COMPACT_INSN_MOVW3_COMPACT; goto extract_sfmt_movb3_compact; case 6 : itype = SH64_COMPACT_INSN_MOVL3_COMPACT; goto extract_sfmt_movb3_compact; case 7 : itype = SH64_COMPACT_INSN_MULL_COMPACT; goto extract_sfmt_mull_compact; case 8 : - { - unsigned int val = (((insn >> 4) & (7 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_CLRT_COMPACT; goto extract_sfmt_clrt_compact; case 1 : itype = SH64_COMPACT_INSN_SETT_COMPACT; goto extract_sfmt_clrt_compact; case 2 : itype = SH64_COMPACT_INSN_CLRMAC_COMPACT; goto extract_sfmt_clrmac_compact; case 4 : itype = SH64_COMPACT_INSN_CLRS_COMPACT; goto extract_sfmt_clrs_compact; case 5 : itype = SH64_COMPACT_INSN_SETS_COMPACT; goto extract_sfmt_clrs_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 9 : - { - unsigned int val = (((insn >> 4) & (3 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_NOP_COMPACT; goto extract_sfmt_nop_compact; case 1 : itype = SH64_COMPACT_INSN_DIV0U_COMPACT; goto extract_sfmt_div0u_compact; case 2 : itype = SH64_COMPACT_INSN_MOVT_COMPACT; goto extract_sfmt_movt_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 10 : - { - unsigned int val = (((insn >> 4) & (7 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_STS_MACH_COMPACT; goto extract_sfmt_sts_mach_compact; case 1 : itype = SH64_COMPACT_INSN_STS_MACL_COMPACT; goto extract_sfmt_sts_macl_compact; case 2 : itype = SH64_COMPACT_INSN_STS_PR_COMPACT; goto extract_sfmt_sts_pr_compact; case 5 : itype = SH64_COMPACT_INSN_STS_FPUL_COMPACT; goto extract_sfmt_sts_fpul_compact; case 6 : itype = SH64_COMPACT_INSN_STS_FPSCR_COMPACT; goto extract_sfmt_sts_fpscr_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 11 : - { - unsigned int val = (((insn >> 4) & (3 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_RTS_COMPACT; goto extract_sfmt_rts_compact; case 3 : itype = SH64_COMPACT_INSN_BRK_COMPACT; goto extract_sfmt_brk_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 0 : + if ((entire_insn & 0xf0ff) == 0x3) + { itype = SH64_COMPACT_INSN_BSRF_COMPACT; goto extract_sfmt_bsrf_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xf0ff) == 0x83) + { itype = SH64_COMPACT_INSN_PREF_COMPACT; goto extract_sfmt_pref_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 12 : itype = SH64_COMPACT_INSN_MOVB8_COMPACT; goto extract_sfmt_movb8_compact; case 13 : itype = SH64_COMPACT_INSN_MOVW8_COMPACT; goto extract_sfmt_movb8_compact; case 14 : itype = SH64_COMPACT_INSN_MOVL8_COMPACT; goto extract_sfmt_movb8_compact; case 15 : itype = SH64_COMPACT_INSN_MACL_COMPACT; goto extract_sfmt_macl_compact; case 16 : /* fall through */ - case 17 : /* fall through */ - case 18 : /* fall through */ - case 19 : /* fall through */ + case 4 : /* fall through */ case 20 : /* fall through */ + case 36 : /* fall through */ + case 52 : /* fall through */ + case 68 : /* fall through */ + case 84 : /* fall through */ + case 100 : /* fall through */ + case 116 : + if ((entire_insn & 0xf00f) == 0x4) + { itype = SH64_COMPACT_INSN_MOVB3_COMPACT; goto extract_sfmt_movb3_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 5 : /* fall through */ case 21 : /* fall through */ + case 37 : /* fall through */ + case 53 : /* fall through */ + case 69 : /* fall through */ + case 85 : /* fall through */ + case 101 : /* fall through */ + case 117 : + if ((entire_insn & 0xf00f) == 0x5) + { itype = SH64_COMPACT_INSN_MOVW3_COMPACT; goto extract_sfmt_movw3_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 6 : /* fall through */ case 22 : /* fall through */ + case 38 : /* fall through */ + case 54 : /* fall through */ + case 70 : /* fall through */ + case 86 : /* fall through */ + case 102 : /* fall through */ + case 118 : + if ((entire_insn & 0xf00f) == 0x6) + { itype = SH64_COMPACT_INSN_MOVL3_COMPACT; goto extract_sfmt_movl3_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 7 : /* fall through */ case 23 : /* fall through */ - case 24 : /* fall through */ - case 25 : /* fall through */ - case 26 : /* fall through */ - case 27 : /* fall through */ + case 39 : /* fall through */ + case 55 : /* fall through */ + case 71 : /* fall through */ + case 87 : /* fall through */ + case 103 : /* fall through */ + case 119 : + if ((entire_insn & 0xf00f) == 0x7) + { itype = SH64_COMPACT_INSN_MULL_COMPACT; goto extract_sfmt_mull_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 8 : + if ((entire_insn & 0xffff) == 0x8) + { itype = SH64_COMPACT_INSN_CLRT_COMPACT; goto extract_sfmt_clrt_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 9 : + if ((entire_insn & 0xffff) == 0x9) + { itype = SH64_COMPACT_INSN_NOP_COMPACT; goto extract_sfmt_nop_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 10 : + if ((entire_insn & 0xf0ff) == 0xa) + { itype = SH64_COMPACT_INSN_STS_MACH_COMPACT; goto extract_sfmt_sts_mach_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 11 : + if ((entire_insn & 0xffff) == 0xb) + { itype = SH64_COMPACT_INSN_RTS_COMPACT; goto extract_sfmt_rts_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 12 : /* fall through */ case 28 : /* fall through */ + case 44 : /* fall through */ + case 60 : /* fall through */ + case 76 : /* fall through */ + case 92 : /* fall through */ + case 108 : /* fall through */ + case 124 : + if ((entire_insn & 0xf00f) == 0xc) + { itype = SH64_COMPACT_INSN_MOVB8_COMPACT; goto extract_sfmt_movb8_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 13 : /* fall through */ case 29 : /* fall through */ + case 45 : /* fall through */ + case 61 : /* fall through */ + case 77 : /* fall through */ + case 93 : /* fall through */ + case 109 : /* fall through */ + case 125 : + if ((entire_insn & 0xf00f) == 0xd) + { itype = SH64_COMPACT_INSN_MOVW8_COMPACT; goto extract_sfmt_movw8_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 14 : /* fall through */ case 30 : /* fall through */ - case 31 : itype = SH64_COMPACT_INSN_MOVL5_COMPACT; goto extract_sfmt_movl5_compact; case 32 : itype = SH64_COMPACT_INSN_MOVB1_COMPACT; goto extract_sfmt_movb1_compact; case 33 : itype = SH64_COMPACT_INSN_MOVW1_COMPACT; goto extract_sfmt_movb1_compact; case 34 : itype = SH64_COMPACT_INSN_MOVL1_COMPACT; goto extract_sfmt_movb1_compact; case 36 : itype = SH64_COMPACT_INSN_MOVB2_COMPACT; goto extract_sfmt_movb2_compact; case 37 : itype = SH64_COMPACT_INSN_MOVW2_COMPACT; goto extract_sfmt_movb2_compact; case 38 : itype = SH64_COMPACT_INSN_MOVL2_COMPACT; goto extract_sfmt_movb2_compact; case 39 : itype = SH64_COMPACT_INSN_DIV0S_COMPACT; goto extract_sfmt_div0s_compact; case 40 : itype = SH64_COMPACT_INSN_TST_COMPACT; goto extract_sfmt_cmpeq_compact; case 41 : itype = SH64_COMPACT_INSN_AND_COMPACT; goto extract_sfmt_and_compact; case 42 : itype = SH64_COMPACT_INSN_XOR_COMPACT; goto extract_sfmt_and_compact; case 43 : itype = SH64_COMPACT_INSN_OR_COMPACT; goto extract_sfmt_and_compact; case 44 : itype = SH64_COMPACT_INSN_CMPSTR_COMPACT; goto extract_sfmt_cmpeq_compact; case 45 : itype = SH64_COMPACT_INSN_XTRCT_COMPACT; goto extract_sfmt_add_compact; case 46 : itype = SH64_COMPACT_INSN_MULUW_COMPACT; goto extract_sfmt_mull_compact; case 47 : itype = SH64_COMPACT_INSN_MULSW_COMPACT; goto extract_sfmt_mull_compact; case 48 : itype = SH64_COMPACT_INSN_CMPEQ_COMPACT; goto extract_sfmt_cmpeq_compact; case 50 : itype = SH64_COMPACT_INSN_CMPHS_COMPACT; goto extract_sfmt_cmpeq_compact; case 51 : itype = SH64_COMPACT_INSN_CMPGE_COMPACT; goto extract_sfmt_cmpeq_compact; case 52 : itype = SH64_COMPACT_INSN_DIV1_COMPACT; goto extract_sfmt_div1_compact; case 53 : itype = SH64_COMPACT_INSN_DMULUL_COMPACT; goto extract_sfmt_dmulsl_compact; case 54 : itype = SH64_COMPACT_INSN_CMPHI_COMPACT; goto extract_sfmt_cmpeq_compact; case 55 : itype = SH64_COMPACT_INSN_CMPGT_COMPACT; goto extract_sfmt_cmpeq_compact; case 56 : itype = SH64_COMPACT_INSN_SUB_COMPACT; goto extract_sfmt_add_compact; case 58 : itype = SH64_COMPACT_INSN_SUBC_COMPACT; goto extract_sfmt_addc_compact; case 59 : itype = SH64_COMPACT_INSN_SUBV_COMPACT; goto extract_sfmt_addv_compact; case 60 : itype = SH64_COMPACT_INSN_ADD_COMPACT; goto extract_sfmt_add_compact; case 61 : itype = SH64_COMPACT_INSN_DMULSL_COMPACT; goto extract_sfmt_dmulsl_compact; case 62 : itype = SH64_COMPACT_INSN_ADDC_COMPACT; goto extract_sfmt_addc_compact; case 63 : itype = SH64_COMPACT_INSN_ADDV_COMPACT; goto extract_sfmt_addv_compact; case 64 : - { - unsigned int val = (((insn >> 4) & (3 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_SHLL_COMPACT; goto extract_sfmt_dt_compact; case 1 : itype = SH64_COMPACT_INSN_DT_COMPACT; goto extract_sfmt_dt_compact; case 2 : itype = SH64_COMPACT_INSN_SHAL_COMPACT; goto extract_sfmt_dt_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 65 : - { - unsigned int val = (((insn >> 4) & (3 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_SHLR_COMPACT; goto extract_sfmt_dt_compact; case 1 : itype = SH64_COMPACT_INSN_CMPPZ_COMPACT; goto extract_sfmt_cmppl_compact; case 2 : itype = SH64_COMPACT_INSN_SHAR_COMPACT; goto extract_sfmt_dt_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 66 : - { - unsigned int val = (((insn >> 4) & (7 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_STSL_MACH_COMPACT; goto extract_sfmt_stsl_mach_compact; case 1 : itype = SH64_COMPACT_INSN_STSL_MACL_COMPACT; goto extract_sfmt_stsl_macl_compact; case 2 : itype = SH64_COMPACT_INSN_STSL_PR_COMPACT; goto extract_sfmt_stsl_pr_compact; case 5 : itype = SH64_COMPACT_INSN_STSL_FPUL_COMPACT; goto extract_sfmt_stsl_fpul_compact; case 6 : itype = SH64_COMPACT_INSN_STSL_FPSCR_COMPACT; goto extract_sfmt_stsl_fpscr_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 67 : itype = SH64_COMPACT_INSN_STCL_GBR_COMPACT; goto extract_sfmt_stcl_gbr_compact; case 68 : - { - unsigned int val = (((insn >> 5) & (1 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_ROTL_COMPACT; goto extract_sfmt_dt_compact; case 1 : itype = SH64_COMPACT_INSN_ROTCL_COMPACT; goto extract_sfmt_rotcl_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 69 : - { - unsigned int val = (((insn >> 4) & (3 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_ROTR_COMPACT; goto extract_sfmt_dt_compact; case 1 : itype = SH64_COMPACT_INSN_CMPPL_COMPACT; goto extract_sfmt_cmppl_compact; case 2 : itype = SH64_COMPACT_INSN_ROTCR_COMPACT; goto extract_sfmt_rotcl_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 70 : - { - unsigned int val = (((insn >> 4) & (7 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_LDSL_MACH_COMPACT; goto extract_sfmt_ldsl_mach_compact; case 1 : itype = SH64_COMPACT_INSN_LDSL_MACL_COMPACT; goto extract_sfmt_ldsl_macl_compact; case 2 : itype = SH64_COMPACT_INSN_LDSL_PR_COMPACT; goto extract_sfmt_ldsl_pr_compact; case 5 : itype = SH64_COMPACT_INSN_LDSL_FPUL_COMPACT; goto extract_sfmt_ldsl_fpul_compact; case 6 : itype = SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT; goto extract_sfmt_ldsl_fpscr_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 71 : itype = SH64_COMPACT_INSN_LDCL_COMPACT; goto extract_sfmt_ldcl_compact; case 72 : - { - unsigned int val = (((insn >> 4) & (3 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_SHLL2_COMPACT; goto extract_sfmt_shll2_compact; case 1 : itype = SH64_COMPACT_INSN_SHLL8_COMPACT; goto extract_sfmt_shll2_compact; case 2 : itype = SH64_COMPACT_INSN_SHLL16_COMPACT; goto extract_sfmt_shll2_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 73 : - { - unsigned int val = (((insn >> 4) & (3 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_SHLR2_COMPACT; goto extract_sfmt_shll2_compact; case 1 : itype = SH64_COMPACT_INSN_SHLR8_COMPACT; goto extract_sfmt_shll2_compact; case 2 : itype = SH64_COMPACT_INSN_SHLR16_COMPACT; goto extract_sfmt_shll2_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 74 : - { - unsigned int val = (((insn >> 4) & (7 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_LDS_MACH_COMPACT; goto extract_sfmt_lds_mach_compact; case 1 : itype = SH64_COMPACT_INSN_LDS_MACL_COMPACT; goto extract_sfmt_lds_macl_compact; case 2 : itype = SH64_COMPACT_INSN_LDS_PR_COMPACT; goto extract_sfmt_lds_pr_compact; case 5 : itype = SH64_COMPACT_INSN_LDS_FPUL_COMPACT; goto extract_sfmt_lds_fpul_compact; case 6 : itype = SH64_COMPACT_INSN_LDS_FPSCR_COMPACT; goto extract_sfmt_lds_fpscr_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - case 75 : + case 46 : /* fall through */ + case 62 : /* fall through */ + case 78 : /* fall through */ + case 94 : /* fall through */ + case 110 : /* fall through */ + case 126 : + if ((entire_insn & 0xf00f) == 0xe) + { itype = SH64_COMPACT_INSN_MOVL8_COMPACT; goto extract_sfmt_movl8_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 15 : /* fall through */ + case 31 : /* fall through */ + case 47 : /* fall through */ + case 63 : /* fall through */ + case 79 : /* fall through */ + case 95 : /* fall through */ + case 111 : /* fall through */ + case 127 : + if ((entire_insn & 0xf00f) == 0xf) + { itype = SH64_COMPACT_INSN_MACL_COMPACT; goto extract_sfmt_macl_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 18 : + if ((entire_insn & 0xf0ff) == 0x12) + { itype = SH64_COMPACT_INSN_STC_GBR_COMPACT; goto extract_sfmt_stc_gbr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 19 : + if ((entire_insn & 0xf0ff) == 0x93) + { itype = SH64_COMPACT_INSN_OCBI_COMPACT; goto extract_sfmt_movcol_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 24 : + if ((entire_insn & 0xffff) == 0x18) + { itype = SH64_COMPACT_INSN_SETT_COMPACT; goto extract_sfmt_clrt_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 25 : + if ((entire_insn & 0xffff) == 0x19) + { itype = SH64_COMPACT_INSN_DIV0U_COMPACT; goto extract_sfmt_div0u_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 26 : + if ((entire_insn & 0xf0ff) == 0x1a) + { itype = SH64_COMPACT_INSN_STS_MACL_COMPACT; goto extract_sfmt_sts_macl_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 34 : + if ((entire_insn & 0xf0ff) == 0x22) + { itype = SH64_COMPACT_INSN_STC_VBR_COMPACT; goto extract_sfmt_stc_vbr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 35 : { - unsigned int val = (((insn >> 4) & (3 << 0))); + unsigned int val = (((insn >> 7) & (1 << 0))); switch (val) { - case 0 : itype = SH64_COMPACT_INSN_JSR_COMPACT; goto extract_sfmt_bsrf_compact; case 1 : itype = SH64_COMPACT_INSN_TASB_COMPACT; goto extract_sfmt_tasb_compact; case 2 : itype = SH64_COMPACT_INSN_JMP_COMPACT; goto extract_sfmt_jmp_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 0 : + if ((entire_insn & 0xf0ff) == 0x23) + { itype = SH64_COMPACT_INSN_BRAF_COMPACT; goto extract_sfmt_braf_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xf0ff) == 0xa3) + { itype = SH64_COMPACT_INSN_OCBP_COMPACT; goto extract_sfmt_movcol_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 76 : itype = SH64_COMPACT_INSN_SHAD_COMPACT; goto extract_sfmt_shad_compact; case 77 : itype = SH64_COMPACT_INSN_SHLD_COMPACT; goto extract_sfmt_shad_compact; case 78 : itype = SH64_COMPACT_INSN_LDC_COMPACT; goto extract_sfmt_ldc_compact; case 79 : itype = SH64_COMPACT_INSN_MACW_COMPACT; goto extract_sfmt_macw_compact; case 80 : /* fall through */ - case 81 : /* fall through */ - case 82 : /* fall through */ - case 83 : /* fall through */ - case 84 : /* fall through */ - case 85 : /* fall through */ - case 86 : /* fall through */ - case 87 : /* fall through */ - case 88 : /* fall through */ - case 89 : /* fall through */ - case 90 : /* fall through */ - case 91 : /* fall through */ - case 92 : /* fall through */ - case 93 : /* fall through */ - case 94 : /* fall through */ - case 95 : itype = SH64_COMPACT_INSN_MOVL11_COMPACT; goto extract_sfmt_movl11_compact; case 96 : itype = SH64_COMPACT_INSN_MOVB6_COMPACT; goto extract_sfmt_movb6_compact; case 97 : itype = SH64_COMPACT_INSN_MOVW6_COMPACT; goto extract_sfmt_movb6_compact; case 98 : itype = SH64_COMPACT_INSN_MOVL6_COMPACT; goto extract_sfmt_movb6_compact; case 99 : itype = SH64_COMPACT_INSN_MOV_COMPACT; goto extract_sfmt_mov_compact; case 100 : itype = SH64_COMPACT_INSN_MOVB7_COMPACT; goto extract_sfmt_movb7_compact; case 101 : itype = SH64_COMPACT_INSN_MOVW7_COMPACT; goto extract_sfmt_movb7_compact; case 102 : itype = SH64_COMPACT_INSN_MOVL7_COMPACT; goto extract_sfmt_movl7_compact; case 103 : itype = SH64_COMPACT_INSN_NOT_COMPACT; goto extract_sfmt_mov_compact; case 104 : itype = SH64_COMPACT_INSN_SWAPB_COMPACT; goto extract_sfmt_extsb_compact; case 105 : itype = SH64_COMPACT_INSN_SWAPW_COMPACT; goto extract_sfmt_extsb_compact; case 106 : itype = SH64_COMPACT_INSN_NEGC_COMPACT; goto extract_sfmt_negc_compact; case 107 : itype = SH64_COMPACT_INSN_NEG_COMPACT; goto extract_sfmt_extsb_compact; case 108 : itype = SH64_COMPACT_INSN_EXTUB_COMPACT; goto extract_sfmt_extsb_compact; case 109 : itype = SH64_COMPACT_INSN_EXTUW_COMPACT; goto extract_sfmt_extsb_compact; case 110 : itype = SH64_COMPACT_INSN_EXTSB_COMPACT; goto extract_sfmt_extsb_compact; case 111 : itype = SH64_COMPACT_INSN_EXTSW_COMPACT; goto extract_sfmt_extsb_compact; case 112 : /* fall through */ - case 113 : /* fall through */ - case 114 : /* fall through */ - case 115 : /* fall through */ - case 116 : /* fall through */ - case 117 : /* fall through */ - case 118 : /* fall through */ - case 119 : /* fall through */ - case 120 : /* fall through */ - case 121 : /* fall through */ - case 122 : /* fall through */ - case 123 : /* fall through */ - case 124 : /* fall through */ - case 125 : /* fall through */ - case 126 : /* fall through */ - case 127 : itype = SH64_COMPACT_INSN_ADDI_COMPACT; goto extract_sfmt_addi_compact; case 128 : /* fall through */ + case 40 : + if ((entire_insn & 0xffff) == 0x28) + { itype = SH64_COMPACT_INSN_CLRMAC_COMPACT; goto extract_sfmt_clrmac_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 41 : + if ((entire_insn & 0xf0ff) == 0x29) + { itype = SH64_COMPACT_INSN_MOVT_COMPACT; goto extract_sfmt_movt_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 42 : + if ((entire_insn & 0xf0ff) == 0x2a) + { itype = SH64_COMPACT_INSN_STS_PR_COMPACT; goto extract_sfmt_sts_pr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 51 : + if ((entire_insn & 0xf0ff) == 0xb3) + { itype = SH64_COMPACT_INSN_OCBWB_COMPACT; goto extract_sfmt_movcol_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 59 : + if ((entire_insn & 0xffff) == 0x3b) + { itype = SH64_COMPACT_INSN_BRK_COMPACT; goto extract_sfmt_brk_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 67 : + if ((entire_insn & 0xf0ff) == 0xc3) + { itype = SH64_COMPACT_INSN_MOVCAL_COMPACT; goto extract_sfmt_movcal_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 72 : + if ((entire_insn & 0xffff) == 0x48) + { itype = SH64_COMPACT_INSN_CLRS_COMPACT; goto extract_sfmt_clrs_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 88 : + if ((entire_insn & 0xffff) == 0x58) + { itype = SH64_COMPACT_INSN_SETS_COMPACT; goto extract_sfmt_clrs_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 90 : + if ((entire_insn & 0xf0ff) == 0x5a) + { itype = SH64_COMPACT_INSN_STS_FPUL_COMPACT; goto extract_sfmt_sts_fpul_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 106 : + if ((entire_insn & 0xf0ff) == 0x6a) + { itype = SH64_COMPACT_INSN_STS_FPSCR_COMPACT; goto extract_sfmt_sts_fpscr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 115 : + if ((entire_insn & 0xf0ff) == 0x73) + { itype = SH64_COMPACT_INSN_MOVCOL_COMPACT; goto extract_sfmt_movcol_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 128 : /* fall through */ case 129 : /* fall through */ case 130 : /* fall through */ case 131 : /* fall through */ @@ -484,14 +549,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, case 140 : /* fall through */ case 141 : /* fall through */ case 142 : /* fall through */ - case 143 : - { - unsigned int val = (((insn >> 8) & (15 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_MOVB5_COMPACT; goto extract_sfmt_movb5_compact; case 1 : itype = SH64_COMPACT_INSN_MOVW5_COMPACT; goto extract_sfmt_movw5_compact; case 4 : itype = SH64_COMPACT_INSN_MOVB10_COMPACT; goto extract_sfmt_movb10_compact; case 5 : itype = SH64_COMPACT_INSN_MOVW11_COMPACT; goto extract_sfmt_movw11_compact; case 8 : itype = SH64_COMPACT_INSN_CMPEQI_COMPACT; goto extract_sfmt_cmpeqi_compact; case 9 : itype = SH64_COMPACT_INSN_BT_COMPACT; goto extract_sfmt_bf_compact; case 11 : itype = SH64_COMPACT_INSN_BF_COMPACT; goto extract_sfmt_bf_compact; case 13 : itype = SH64_COMPACT_INSN_BTS_COMPACT; goto extract_sfmt_bf_compact; case 15 : itype = SH64_COMPACT_INSN_BFS_COMPACT; goto extract_sfmt_bf_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } + case 143 : /* fall through */ case 144 : /* fall through */ case 145 : /* fall through */ case 146 : /* fall through */ @@ -507,7 +565,8 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, case 156 : /* fall through */ case 157 : /* fall through */ case 158 : /* fall through */ - case 159 : itype = SH64_COMPACT_INSN_MOVW10_COMPACT; goto extract_sfmt_movw10_compact; case 160 : /* fall through */ + case 159 : /* fall through */ + case 160 : /* fall through */ case 161 : /* fall through */ case 162 : /* fall through */ case 163 : /* fall through */ @@ -522,7 +581,8 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, case 172 : /* fall through */ case 173 : /* fall through */ case 174 : /* fall through */ - case 175 : itype = SH64_COMPACT_INSN_BRA_COMPACT; goto extract_sfmt_bra_compact; case 176 : /* fall through */ + case 175 : /* fall through */ + case 176 : /* fall through */ case 177 : /* fall through */ case 178 : /* fall through */ case 179 : /* fall through */ @@ -537,7 +597,8 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, case 188 : /* fall through */ case 189 : /* fall through */ case 190 : /* fall through */ - case 191 : itype = SH64_COMPACT_INSN_BSR_COMPACT; goto extract_sfmt_bsr_compact; case 192 : /* fall through */ + case 191 : /* fall through */ + case 192 : /* fall through */ case 193 : /* fall through */ case 194 : /* fall through */ case 195 : /* fall through */ @@ -552,14 +613,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, case 204 : /* fall through */ case 205 : /* fall through */ case 206 : /* fall through */ - case 207 : - { - unsigned int val = (((insn >> 8) & (15 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_MOVB4_COMPACT; goto extract_sfmt_movb4_compact; case 1 : itype = SH64_COMPACT_INSN_MOVW4_COMPACT; goto extract_sfmt_movw4_compact; case 2 : itype = SH64_COMPACT_INSN_MOVL4_COMPACT; goto extract_sfmt_movl4_compact; case 3 : itype = SH64_COMPACT_INSN_TRAPA_COMPACT; goto extract_sfmt_trapa_compact; case 4 : itype = SH64_COMPACT_INSN_MOVB9_COMPACT; goto extract_sfmt_movb9_compact; case 5 : itype = SH64_COMPACT_INSN_MOVW9_COMPACT; goto extract_sfmt_movw9_compact; case 6 : itype = SH64_COMPACT_INSN_MOVL9_COMPACT; goto extract_sfmt_movl9_compact; case 7 : itype = SH64_COMPACT_INSN_MOVA_COMPACT; goto extract_sfmt_mova_compact; case 8 : itype = SH64_COMPACT_INSN_TSTI_COMPACT; goto extract_sfmt_tsti_compact; case 9 : itype = SH64_COMPACT_INSN_ANDI_COMPACT; goto extract_sfmt_andi_compact; case 10 : itype = SH64_COMPACT_INSN_XORI_COMPACT; goto extract_sfmt_xori_compact; case 11 : itype = SH64_COMPACT_INSN_ORI_COMPACT; goto extract_sfmt_andi_compact; case 12 : itype = SH64_COMPACT_INSN_TSTB_COMPACT; goto extract_sfmt_tstb_compact; case 13 : itype = SH64_COMPACT_INSN_ANDB_COMPACT; goto extract_sfmt_andb_compact; case 14 : itype = SH64_COMPACT_INSN_XORB_COMPACT; goto extract_sfmt_andb_compact; case 15 : itype = SH64_COMPACT_INSN_ORB_COMPACT; goto extract_sfmt_andb_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } + case 207 : /* fall through */ case 208 : /* fall through */ case 209 : /* fall through */ case 210 : /* fall through */ @@ -575,7 +629,8 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, case 220 : /* fall through */ case 221 : /* fall through */ case 222 : /* fall through */ - case 223 : itype = SH64_COMPACT_INSN_MOVL10_COMPACT; goto extract_sfmt_movl10_compact; case 224 : /* fall through */ + case 223 : /* fall through */ + case 224 : /* fall through */ case 225 : /* fall through */ case 226 : /* fall through */ case 227 : /* fall through */ @@ -590,31 +645,2363 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, case 236 : /* fall through */ case 237 : /* fall through */ case 238 : /* fall through */ - case 239 : itype = SH64_COMPACT_INSN_MOVI_COMPACT; goto extract_sfmt_movi_compact; case 240 : itype = SH64_COMPACT_INSN_FADD_COMPACT; goto extract_sfmt_fadd_compact; case 241 : itype = SH64_COMPACT_INSN_FSUB_COMPACT; goto extract_sfmt_fadd_compact; case 242 : itype = SH64_COMPACT_INSN_FMUL_COMPACT; goto extract_sfmt_fadd_compact; case 243 : itype = SH64_COMPACT_INSN_FDIV_COMPACT; goto extract_sfmt_fadd_compact; case 244 : itype = SH64_COMPACT_INSN_FCMPEQ_COMPACT; goto extract_sfmt_fcmpeq_compact; case 245 : itype = SH64_COMPACT_INSN_FCMPGT_COMPACT; goto extract_sfmt_fcmpeq_compact; case 246 : itype = SH64_COMPACT_INSN_FMOV4_COMPACT; goto extract_sfmt_fmov4_compact; case 247 : itype = SH64_COMPACT_INSN_FMOV7_COMPACT; goto extract_sfmt_fmov7_compact; case 248 : itype = SH64_COMPACT_INSN_FMOV2_COMPACT; goto extract_sfmt_fmov2_compact; case 249 : itype = SH64_COMPACT_INSN_FMOV3_COMPACT; goto extract_sfmt_fmov3_compact; case 250 : itype = SH64_COMPACT_INSN_FMOV5_COMPACT; goto extract_sfmt_fmov5_compact; case 251 : itype = SH64_COMPACT_INSN_FMOV6_COMPACT; goto extract_sfmt_fmov6_compact; case 252 : itype = SH64_COMPACT_INSN_FMOV1_COMPACT; goto extract_sfmt_fmov1_compact; case 253 : + case 239 : /* fall through */ + case 240 : /* fall through */ + case 241 : /* fall through */ + case 242 : /* fall through */ + case 243 : /* fall through */ + case 244 : /* fall through */ + case 245 : /* fall through */ + case 246 : /* fall through */ + case 247 : /* fall through */ + case 248 : /* fall through */ + case 249 : /* fall through */ + case 250 : /* fall through */ + case 251 : /* fall through */ + case 252 : /* fall through */ + case 253 : /* fall through */ + case 254 : /* fall through */ + case 255 : + if ((entire_insn & 0xf000) == 0x1000) + { itype = SH64_COMPACT_INSN_MOVL5_COMPACT; goto extract_sfmt_movl5_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 256 : /* fall through */ + case 272 : /* fall through */ + case 288 : /* fall through */ + case 304 : /* fall through */ + case 320 : /* fall through */ + case 336 : /* fall through */ + case 352 : /* fall through */ + case 368 : + if ((entire_insn & 0xf00f) == 0x2000) + { itype = SH64_COMPACT_INSN_MOVB1_COMPACT; goto extract_sfmt_movb1_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 257 : /* fall through */ + case 273 : /* fall through */ + case 289 : /* fall through */ + case 305 : /* fall through */ + case 321 : /* fall through */ + case 337 : /* fall through */ + case 353 : /* fall through */ + case 369 : + if ((entire_insn & 0xf00f) == 0x2001) + { itype = SH64_COMPACT_INSN_MOVW1_COMPACT; goto extract_sfmt_movw1_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 258 : /* fall through */ + case 274 : /* fall through */ + case 290 : /* fall through */ + case 306 : /* fall through */ + case 322 : /* fall through */ + case 338 : /* fall through */ + case 354 : /* fall through */ + case 370 : + if ((entire_insn & 0xf00f) == 0x2002) + { itype = SH64_COMPACT_INSN_MOVL1_COMPACT; goto extract_sfmt_movl1_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 260 : /* fall through */ + case 276 : /* fall through */ + case 292 : /* fall through */ + case 308 : /* fall through */ + case 324 : /* fall through */ + case 340 : /* fall through */ + case 356 : /* fall through */ + case 372 : + if ((entire_insn & 0xf00f) == 0x2004) + { itype = SH64_COMPACT_INSN_MOVB2_COMPACT; goto extract_sfmt_movb2_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 261 : /* fall through */ + case 277 : /* fall through */ + case 293 : /* fall through */ + case 309 : /* fall through */ + case 325 : /* fall through */ + case 341 : /* fall through */ + case 357 : /* fall through */ + case 373 : + if ((entire_insn & 0xf00f) == 0x2005) + { itype = SH64_COMPACT_INSN_MOVW2_COMPACT; goto extract_sfmt_movw2_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 262 : /* fall through */ + case 278 : /* fall through */ + case 294 : /* fall through */ + case 310 : /* fall through */ + case 326 : /* fall through */ + case 342 : /* fall through */ + case 358 : /* fall through */ + case 374 : + if ((entire_insn & 0xf00f) == 0x2006) + { itype = SH64_COMPACT_INSN_MOVL2_COMPACT; goto extract_sfmt_movl2_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 263 : /* fall through */ + case 279 : /* fall through */ + case 295 : /* fall through */ + case 311 : /* fall through */ + case 327 : /* fall through */ + case 343 : /* fall through */ + case 359 : /* fall through */ + case 375 : + if ((entire_insn & 0xf00f) == 0x2007) + { itype = SH64_COMPACT_INSN_DIV0S_COMPACT; goto extract_sfmt_div0s_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 264 : /* fall through */ + case 280 : /* fall through */ + case 296 : /* fall through */ + case 312 : /* fall through */ + case 328 : /* fall through */ + case 344 : /* fall through */ + case 360 : /* fall through */ + case 376 : + if ((entire_insn & 0xf00f) == 0x2008) + { itype = SH64_COMPACT_INSN_TST_COMPACT; goto extract_sfmt_cmpeq_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 265 : /* fall through */ + case 281 : /* fall through */ + case 297 : /* fall through */ + case 313 : /* fall through */ + case 329 : /* fall through */ + case 345 : /* fall through */ + case 361 : /* fall through */ + case 377 : + if ((entire_insn & 0xf00f) == 0x2009) + { itype = SH64_COMPACT_INSN_AND_COMPACT; goto extract_sfmt_and_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 266 : /* fall through */ + case 282 : /* fall through */ + case 298 : /* fall through */ + case 314 : /* fall through */ + case 330 : /* fall through */ + case 346 : /* fall through */ + case 362 : /* fall through */ + case 378 : + if ((entire_insn & 0xf00f) == 0x200a) + { itype = SH64_COMPACT_INSN_XOR_COMPACT; goto extract_sfmt_and_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 267 : /* fall through */ + case 283 : /* fall through */ + case 299 : /* fall through */ + case 315 : /* fall through */ + case 331 : /* fall through */ + case 347 : /* fall through */ + case 363 : /* fall through */ + case 379 : + if ((entire_insn & 0xf00f) == 0x200b) + { itype = SH64_COMPACT_INSN_OR_COMPACT; goto extract_sfmt_and_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 268 : /* fall through */ + case 284 : /* fall through */ + case 300 : /* fall through */ + case 316 : /* fall through */ + case 332 : /* fall through */ + case 348 : /* fall through */ + case 364 : /* fall through */ + case 380 : + if ((entire_insn & 0xf00f) == 0x200c) + { itype = SH64_COMPACT_INSN_CMPSTR_COMPACT; goto extract_sfmt_cmpeq_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 269 : /* fall through */ + case 285 : /* fall through */ + case 301 : /* fall through */ + case 317 : /* fall through */ + case 333 : /* fall through */ + case 349 : /* fall through */ + case 365 : /* fall through */ + case 381 : + if ((entire_insn & 0xf00f) == 0x200d) + { itype = SH64_COMPACT_INSN_XTRCT_COMPACT; goto extract_sfmt_add_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 270 : /* fall through */ + case 286 : /* fall through */ + case 302 : /* fall through */ + case 318 : /* fall through */ + case 334 : /* fall through */ + case 350 : /* fall through */ + case 366 : /* fall through */ + case 382 : + if ((entire_insn & 0xf00f) == 0x200e) + { itype = SH64_COMPACT_INSN_MULUW_COMPACT; goto extract_sfmt_mull_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 271 : /* fall through */ + case 287 : /* fall through */ + case 303 : /* fall through */ + case 319 : /* fall through */ + case 335 : /* fall through */ + case 351 : /* fall through */ + case 367 : /* fall through */ + case 383 : + if ((entire_insn & 0xf00f) == 0x200f) + { itype = SH64_COMPACT_INSN_MULSW_COMPACT; goto extract_sfmt_mull_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 384 : /* fall through */ + case 400 : /* fall through */ + case 416 : /* fall through */ + case 432 : /* fall through */ + case 448 : /* fall through */ + case 464 : /* fall through */ + case 480 : /* fall through */ + case 496 : + if ((entire_insn & 0xf00f) == 0x3000) + { itype = SH64_COMPACT_INSN_CMPEQ_COMPACT; goto extract_sfmt_cmpeq_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 385 : /* fall through */ + case 417 : /* fall through */ + case 449 : /* fall through */ + case 481 : + { + unsigned int val = (((insn >> -3) & (1 << 1)) | ((insn >> -4) & (1 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xf00ff000) == 0x30012000) + { itype = SH64_COMPACT_INSN_MOVL13_COMPACT; goto extract_sfmt_movl13_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xf01ff000) == 0x30013000) + { itype = SH64_COMPACT_INSN_FMOV9_COMPACT; goto extract_sfmt_fmov9_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 2 : + if ((entire_insn & 0xf00ff000) == 0x30016000) + { itype = SH64_COMPACT_INSN_MOVL12_COMPACT; goto extract_sfmt_movl12_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 3 : + if ((entire_insn & 0xf10ff000) == 0x30017000) + { itype = SH64_COMPACT_INSN_FMOV8_COMPACT; goto extract_sfmt_fmov8_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 386 : /* fall through */ + case 402 : /* fall through */ + case 418 : /* fall through */ + case 434 : /* fall through */ + case 450 : /* fall through */ + case 466 : /* fall through */ + case 482 : /* fall through */ + case 498 : + if ((entire_insn & 0xf00f) == 0x3002) + { itype = SH64_COMPACT_INSN_CMPHS_COMPACT; goto extract_sfmt_cmpeq_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 387 : /* fall through */ + case 403 : /* fall through */ + case 419 : /* fall through */ + case 435 : /* fall through */ + case 451 : /* fall through */ + case 467 : /* fall through */ + case 483 : /* fall through */ + case 499 : + if ((entire_insn & 0xf00f) == 0x3003) + { itype = SH64_COMPACT_INSN_CMPGE_COMPACT; goto extract_sfmt_cmpeq_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 388 : /* fall through */ + case 404 : /* fall through */ + case 420 : /* fall through */ + case 436 : /* fall through */ + case 452 : /* fall through */ + case 468 : /* fall through */ + case 484 : /* fall through */ + case 500 : + if ((entire_insn & 0xf00f) == 0x3004) + { itype = SH64_COMPACT_INSN_DIV1_COMPACT; goto extract_sfmt_div1_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 389 : /* fall through */ + case 405 : /* fall through */ + case 421 : /* fall through */ + case 437 : /* fall through */ + case 453 : /* fall through */ + case 469 : /* fall through */ + case 485 : /* fall through */ + case 501 : + if ((entire_insn & 0xf00f) == 0x3005) + { itype = SH64_COMPACT_INSN_DMULUL_COMPACT; goto extract_sfmt_dmulsl_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 390 : /* fall through */ + case 406 : /* fall through */ + case 422 : /* fall through */ + case 438 : /* fall through */ + case 454 : /* fall through */ + case 470 : /* fall through */ + case 486 : /* fall through */ + case 502 : + if ((entire_insn & 0xf00f) == 0x3006) + { itype = SH64_COMPACT_INSN_CMPHI_COMPACT; goto extract_sfmt_cmpeq_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 391 : /* fall through */ + case 407 : /* fall through */ + case 423 : /* fall through */ + case 439 : /* fall through */ + case 455 : /* fall through */ + case 471 : /* fall through */ + case 487 : /* fall through */ + case 503 : + if ((entire_insn & 0xf00f) == 0x3007) + { itype = SH64_COMPACT_INSN_CMPGT_COMPACT; goto extract_sfmt_cmpeq_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 392 : /* fall through */ + case 408 : /* fall through */ + case 424 : /* fall through */ + case 440 : /* fall through */ + case 456 : /* fall through */ + case 472 : /* fall through */ + case 488 : /* fall through */ + case 504 : + if ((entire_insn & 0xf00f) == 0x3008) + { itype = SH64_COMPACT_INSN_SUB_COMPACT; goto extract_sfmt_add_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 394 : /* fall through */ + case 410 : /* fall through */ + case 426 : /* fall through */ + case 442 : /* fall through */ + case 458 : /* fall through */ + case 474 : /* fall through */ + case 490 : /* fall through */ + case 506 : + if ((entire_insn & 0xf00f) == 0x300a) + { itype = SH64_COMPACT_INSN_SUBC_COMPACT; goto extract_sfmt_addc_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 395 : /* fall through */ + case 411 : /* fall through */ + case 427 : /* fall through */ + case 443 : /* fall through */ + case 459 : /* fall through */ + case 475 : /* fall through */ + case 491 : /* fall through */ + case 507 : + if ((entire_insn & 0xf00f) == 0x300b) + { itype = SH64_COMPACT_INSN_SUBV_COMPACT; goto extract_sfmt_addv_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 396 : /* fall through */ + case 412 : /* fall through */ + case 428 : /* fall through */ + case 444 : /* fall through */ + case 460 : /* fall through */ + case 476 : /* fall through */ + case 492 : /* fall through */ + case 508 : + if ((entire_insn & 0xf00f) == 0x300c) + { itype = SH64_COMPACT_INSN_ADD_COMPACT; goto extract_sfmt_add_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 397 : /* fall through */ + case 413 : /* fall through */ + case 429 : /* fall through */ + case 445 : /* fall through */ + case 461 : /* fall through */ + case 477 : /* fall through */ + case 493 : /* fall through */ + case 509 : + if ((entire_insn & 0xf00f) == 0x300d) + { itype = SH64_COMPACT_INSN_DMULSL_COMPACT; goto extract_sfmt_dmulsl_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 398 : /* fall through */ + case 414 : /* fall through */ + case 430 : /* fall through */ + case 446 : /* fall through */ + case 462 : /* fall through */ + case 478 : /* fall through */ + case 494 : /* fall through */ + case 510 : + if ((entire_insn & 0xf00f) == 0x300e) + { itype = SH64_COMPACT_INSN_ADDC_COMPACT; goto extract_sfmt_addc_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 399 : /* fall through */ + case 415 : /* fall through */ + case 431 : /* fall through */ + case 447 : /* fall through */ + case 463 : /* fall through */ + case 479 : /* fall through */ + case 495 : /* fall through */ + case 511 : + if ((entire_insn & 0xf00f) == 0x300f) + { itype = SH64_COMPACT_INSN_ADDV_COMPACT; goto extract_sfmt_addv_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 401 : /* fall through */ + case 433 : /* fall through */ + case 465 : /* fall through */ + case 497 : + { + unsigned int val = (((insn >> -3) & (1 << 1)) | ((insn >> -4) & (1 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xf00ff000) == 0x30012000) + { itype = SH64_COMPACT_INSN_MOVL13_COMPACT; goto extract_sfmt_movl13_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 2 : + if ((entire_insn & 0xf00ff000) == 0x30016000) + { itype = SH64_COMPACT_INSN_MOVL12_COMPACT; goto extract_sfmt_movl12_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 3 : + if ((entire_insn & 0xf10ff000) == 0x30017000) + { itype = SH64_COMPACT_INSN_FMOV8_COMPACT; goto extract_sfmt_fmov8_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 512 : + { + unsigned int val = (((insn >> 7) & (1 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xf0ff) == 0x4000) + { itype = SH64_COMPACT_INSN_SHLL_COMPACT; goto extract_sfmt_dt_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xf0ff) == 0x4080) + { itype = SH64_COMPACT_INSN_MULR_COMPACT; goto extract_sfmt_divu_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 513 : + if ((entire_insn & 0xf0ff) == 0x4001) + { itype = SH64_COMPACT_INSN_SHLR_COMPACT; goto extract_sfmt_dt_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 514 : + if ((entire_insn & 0xf0ff) == 0x4002) + { itype = SH64_COMPACT_INSN_STSL_MACH_COMPACT; goto extract_sfmt_stsl_mach_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 516 : + { + unsigned int val = (((insn >> 7) & (1 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xf0ff) == 0x4004) + { itype = SH64_COMPACT_INSN_ROTL_COMPACT; goto extract_sfmt_dt_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xf0ff) == 0x4084) + { itype = SH64_COMPACT_INSN_DIVU_COMPACT; goto extract_sfmt_divu_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 517 : + if ((entire_insn & 0xf0ff) == 0x4005) + { itype = SH64_COMPACT_INSN_ROTR_COMPACT; goto extract_sfmt_dt_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 518 : + if ((entire_insn & 0xf0ff) == 0x4006) + { itype = SH64_COMPACT_INSN_LDSL_MACH_COMPACT; goto extract_sfmt_ldsl_mach_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 520 : + if ((entire_insn & 0xf0ff) == 0x4008) + { itype = SH64_COMPACT_INSN_SHLL2_COMPACT; goto extract_sfmt_movcol_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 521 : + if ((entire_insn & 0xf0ff) == 0x4009) + { itype = SH64_COMPACT_INSN_SHLR2_COMPACT; goto extract_sfmt_movcol_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 522 : + if ((entire_insn & 0xf0ff) == 0x400a) + { itype = SH64_COMPACT_INSN_LDS_MACH_COMPACT; goto extract_sfmt_lds_mach_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 523 : + if ((entire_insn & 0xf0ff) == 0x400b) + { itype = SH64_COMPACT_INSN_JSR_COMPACT; goto extract_sfmt_bsrf_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 524 : /* fall through */ + case 540 : /* fall through */ + case 556 : /* fall through */ + case 572 : /* fall through */ + case 588 : /* fall through */ + case 604 : /* fall through */ + case 620 : /* fall through */ + case 636 : + if ((entire_insn & 0xf00f) == 0x400c) + { itype = SH64_COMPACT_INSN_SHAD_COMPACT; goto extract_sfmt_shad_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 525 : /* fall through */ + case 541 : /* fall through */ + case 557 : /* fall through */ + case 573 : /* fall through */ + case 589 : /* fall through */ + case 605 : /* fall through */ + case 621 : /* fall through */ + case 637 : + if ((entire_insn & 0xf00f) == 0x400d) + { itype = SH64_COMPACT_INSN_SHLD_COMPACT; goto extract_sfmt_shad_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 526 : + if ((entire_insn & 0xf0ff) == 0x400e) + { itype = SH64_COMPACT_INSN_LDC_SR_COMPACT; goto extract_sfmt_ldc_sr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 527 : /* fall through */ + case 543 : /* fall through */ + case 559 : /* fall through */ + case 575 : /* fall through */ + case 591 : /* fall through */ + case 607 : /* fall through */ + case 623 : /* fall through */ + case 639 : + if ((entire_insn & 0xf00f) == 0x400f) + { itype = SH64_COMPACT_INSN_MACW_COMPACT; goto extract_sfmt_macw_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 528 : + if ((entire_insn & 0xf0ff) == 0x4010) + { itype = SH64_COMPACT_INSN_DT_COMPACT; goto extract_sfmt_dt_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 529 : + if ((entire_insn & 0xf0ff) == 0x4011) + { itype = SH64_COMPACT_INSN_CMPPZ_COMPACT; goto extract_sfmt_cmppl_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 530 : + if ((entire_insn & 0xf0ff) == 0x4012) + { itype = SH64_COMPACT_INSN_STSL_MACL_COMPACT; goto extract_sfmt_stsl_macl_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 531 : + if ((entire_insn & 0xf0ff) == 0x4013) + { itype = SH64_COMPACT_INSN_STCL_GBR_COMPACT; goto extract_sfmt_stcl_gbr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 533 : + if ((entire_insn & 0xf0ff) == 0x4015) + { itype = SH64_COMPACT_INSN_CMPPL_COMPACT; goto extract_sfmt_cmppl_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 534 : + if ((entire_insn & 0xf0ff) == 0x4016) + { itype = SH64_COMPACT_INSN_LDSL_MACL_COMPACT; goto extract_sfmt_ldsl_macl_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 535 : + if ((entire_insn & 0xf0ff) == 0x4017) + { itype = SH64_COMPACT_INSN_LDCL_GBR_COMPACT; goto extract_sfmt_ldcl_gbr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 536 : + if ((entire_insn & 0xf0ff) == 0x4018) + { itype = SH64_COMPACT_INSN_SHLL8_COMPACT; goto extract_sfmt_movcol_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 537 : + if ((entire_insn & 0xf0ff) == 0x4019) + { itype = SH64_COMPACT_INSN_SHLR8_COMPACT; goto extract_sfmt_movcol_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 538 : + if ((entire_insn & 0xf0ff) == 0x401a) + { itype = SH64_COMPACT_INSN_LDS_MACL_COMPACT; goto extract_sfmt_lds_macl_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 539 : + if ((entire_insn & 0xf0ff) == 0x401b) + { itype = SH64_COMPACT_INSN_TASB_COMPACT; goto extract_sfmt_tasb_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 542 : + if ((entire_insn & 0xf0ff) == 0x401e) + { itype = SH64_COMPACT_INSN_LDC_GBR_COMPACT; goto extract_sfmt_ldc_gbr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 544 : + if ((entire_insn & 0xf0ff) == 0x4020) + { itype = SH64_COMPACT_INSN_SHAL_COMPACT; goto extract_sfmt_dt_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 545 : + if ((entire_insn & 0xf0ff) == 0x4021) + { itype = SH64_COMPACT_INSN_SHAR_COMPACT; goto extract_sfmt_dt_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 546 : + if ((entire_insn & 0xf0ff) == 0x4022) + { itype = SH64_COMPACT_INSN_STSL_PR_COMPACT; goto extract_sfmt_stsl_pr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 547 : + if ((entire_insn & 0xf0ff) == 0x4023) + { itype = SH64_COMPACT_INSN_STCL_VBR_COMPACT; goto extract_sfmt_stcl_vbr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 548 : + if ((entire_insn & 0xf0ff) == 0x4024) + { itype = SH64_COMPACT_INSN_ROTCL_COMPACT; goto extract_sfmt_rotcl_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 549 : + if ((entire_insn & 0xf0ff) == 0x4025) + { itype = SH64_COMPACT_INSN_ROTCR_COMPACT; goto extract_sfmt_rotcl_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 550 : + if ((entire_insn & 0xf0ff) == 0x4026) + { itype = SH64_COMPACT_INSN_LDSL_PR_COMPACT; goto extract_sfmt_ldsl_pr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 551 : + if ((entire_insn & 0xf0ff) == 0x4027) + { itype = SH64_COMPACT_INSN_LDCL_VBR_COMPACT; goto extract_sfmt_ldcl_vbr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 552 : + if ((entire_insn & 0xf0ff) == 0x4028) + { itype = SH64_COMPACT_INSN_SHLL16_COMPACT; goto extract_sfmt_movcol_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 553 : + { + unsigned int val = (((insn >> 7) & (1 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xf0ff) == 0x4029) + { itype = SH64_COMPACT_INSN_SHLR16_COMPACT; goto extract_sfmt_movcol_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xf0ff) == 0x40a9) + { itype = SH64_COMPACT_INSN_MOVUAL_COMPACT; goto extract_sfmt_movual_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 554 : + if ((entire_insn & 0xf0ff) == 0x402a) + { itype = SH64_COMPACT_INSN_LDS_PR_COMPACT; goto extract_sfmt_lds_pr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 555 : + if ((entire_insn & 0xf0ff) == 0x402b) + { itype = SH64_COMPACT_INSN_JMP_COMPACT; goto extract_sfmt_braf_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 558 : + if ((entire_insn & 0xf0ff) == 0x402e) + { itype = SH64_COMPACT_INSN_LDC_VBR_COMPACT; goto extract_sfmt_ldc_vbr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 594 : + if ((entire_insn & 0xf0ff) == 0x4052) + { itype = SH64_COMPACT_INSN_STSL_FPUL_COMPACT; goto extract_sfmt_stsl_fpul_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 598 : + if ((entire_insn & 0xf0ff) == 0x4056) + { itype = SH64_COMPACT_INSN_LDSL_FPUL_COMPACT; goto extract_sfmt_ldsl_fpul_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 602 : + if ((entire_insn & 0xf0ff) == 0x405a) + { itype = SH64_COMPACT_INSN_LDS_FPUL_COMPACT; goto extract_sfmt_lds_fpul_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 610 : + if ((entire_insn & 0xf0ff) == 0x4062) + { itype = SH64_COMPACT_INSN_STSL_FPSCR_COMPACT; goto extract_sfmt_stsl_fpscr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 614 : + if ((entire_insn & 0xf0ff) == 0x4066) + { itype = SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT; goto extract_sfmt_ldsl_fpscr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 617 : + if ((entire_insn & 0xf0ff) == 0x40e9) + { itype = SH64_COMPACT_INSN_MOVUAL2_COMPACT; goto extract_sfmt_movual2_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 618 : + if ((entire_insn & 0xf0ff) == 0x406a) + { itype = SH64_COMPACT_INSN_LDS_FPSCR_COMPACT; goto extract_sfmt_lds_fpscr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 640 : /* fall through */ + case 641 : /* fall through */ + case 642 : /* fall through */ + case 643 : /* fall through */ + case 644 : /* fall through */ + case 645 : /* fall through */ + case 646 : /* fall through */ + case 647 : /* fall through */ + case 648 : /* fall through */ + case 649 : /* fall through */ + case 650 : /* fall through */ + case 651 : /* fall through */ + case 652 : /* fall through */ + case 653 : /* fall through */ + case 654 : /* fall through */ + case 655 : /* fall through */ + case 656 : /* fall through */ + case 657 : /* fall through */ + case 658 : /* fall through */ + case 659 : /* fall through */ + case 660 : /* fall through */ + case 661 : /* fall through */ + case 662 : /* fall through */ + case 663 : /* fall through */ + case 664 : /* fall through */ + case 665 : /* fall through */ + case 666 : /* fall through */ + case 667 : /* fall through */ + case 668 : /* fall through */ + case 669 : /* fall through */ + case 670 : /* fall through */ + case 671 : /* fall through */ + case 672 : /* fall through */ + case 673 : /* fall through */ + case 674 : /* fall through */ + case 675 : /* fall through */ + case 676 : /* fall through */ + case 677 : /* fall through */ + case 678 : /* fall through */ + case 679 : /* fall through */ + case 680 : /* fall through */ + case 681 : /* fall through */ + case 682 : /* fall through */ + case 683 : /* fall through */ + case 684 : /* fall through */ + case 685 : /* fall through */ + case 686 : /* fall through */ + case 687 : /* fall through */ + case 688 : /* fall through */ + case 689 : /* fall through */ + case 690 : /* fall through */ + case 691 : /* fall through */ + case 692 : /* fall through */ + case 693 : /* fall through */ + case 694 : /* fall through */ + case 695 : /* fall through */ + case 696 : /* fall through */ + case 697 : /* fall through */ + case 698 : /* fall through */ + case 699 : /* fall through */ + case 700 : /* fall through */ + case 701 : /* fall through */ + case 702 : /* fall through */ + case 703 : /* fall through */ + case 704 : /* fall through */ + case 705 : /* fall through */ + case 706 : /* fall through */ + case 707 : /* fall through */ + case 708 : /* fall through */ + case 709 : /* fall through */ + case 710 : /* fall through */ + case 711 : /* fall through */ + case 712 : /* fall through */ + case 713 : /* fall through */ + case 714 : /* fall through */ + case 715 : /* fall through */ + case 716 : /* fall through */ + case 717 : /* fall through */ + case 718 : /* fall through */ + case 719 : /* fall through */ + case 720 : /* fall through */ + case 721 : /* fall through */ + case 722 : /* fall through */ + case 723 : /* fall through */ + case 724 : /* fall through */ + case 725 : /* fall through */ + case 726 : /* fall through */ + case 727 : /* fall through */ + case 728 : /* fall through */ + case 729 : /* fall through */ + case 730 : /* fall through */ + case 731 : /* fall through */ + case 732 : /* fall through */ + case 733 : /* fall through */ + case 734 : /* fall through */ + case 735 : /* fall through */ + case 736 : /* fall through */ + case 737 : /* fall through */ + case 738 : /* fall through */ + case 739 : /* fall through */ + case 740 : /* fall through */ + case 741 : /* fall through */ + case 742 : /* fall through */ + case 743 : /* fall through */ + case 744 : /* fall through */ + case 745 : /* fall through */ + case 746 : /* fall through */ + case 747 : /* fall through */ + case 748 : /* fall through */ + case 749 : /* fall through */ + case 750 : /* fall through */ + case 751 : /* fall through */ + case 752 : /* fall through */ + case 753 : /* fall through */ + case 754 : /* fall through */ + case 755 : /* fall through */ + case 756 : /* fall through */ + case 757 : /* fall through */ + case 758 : /* fall through */ + case 759 : /* fall through */ + case 760 : /* fall through */ + case 761 : /* fall through */ + case 762 : /* fall through */ + case 763 : /* fall through */ + case 764 : /* fall through */ + case 765 : /* fall through */ + case 766 : /* fall through */ + case 767 : + if ((entire_insn & 0xf000) == 0x5000) + { itype = SH64_COMPACT_INSN_MOVL11_COMPACT; goto extract_sfmt_movl11_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 768 : /* fall through */ + case 784 : /* fall through */ + case 800 : /* fall through */ + case 816 : /* fall through */ + case 832 : /* fall through */ + case 848 : /* fall through */ + case 864 : /* fall through */ + case 880 : + if ((entire_insn & 0xf00f) == 0x6000) + { itype = SH64_COMPACT_INSN_MOVB6_COMPACT; goto extract_sfmt_movb6_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 769 : /* fall through */ + case 785 : /* fall through */ + case 801 : /* fall through */ + case 817 : /* fall through */ + case 833 : /* fall through */ + case 849 : /* fall through */ + case 865 : /* fall through */ + case 881 : + if ((entire_insn & 0xf00f) == 0x6001) + { itype = SH64_COMPACT_INSN_MOVW6_COMPACT; goto extract_sfmt_movw6_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 770 : /* fall through */ + case 786 : /* fall through */ + case 802 : /* fall through */ + case 818 : /* fall through */ + case 834 : /* fall through */ + case 850 : /* fall through */ + case 866 : /* fall through */ + case 882 : + if ((entire_insn & 0xf00f) == 0x6002) + { itype = SH64_COMPACT_INSN_MOVL6_COMPACT; goto extract_sfmt_movl6_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 771 : /* fall through */ + case 787 : /* fall through */ + case 803 : /* fall through */ + case 819 : /* fall through */ + case 835 : /* fall through */ + case 851 : /* fall through */ + case 867 : /* fall through */ + case 883 : + if ((entire_insn & 0xf00f) == 0x6003) + { itype = SH64_COMPACT_INSN_MOV_COMPACT; goto extract_sfmt_mov_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 772 : /* fall through */ + case 788 : /* fall through */ + case 804 : /* fall through */ + case 820 : /* fall through */ + case 836 : /* fall through */ + case 852 : /* fall through */ + case 868 : /* fall through */ + case 884 : + if ((entire_insn & 0xf00f) == 0x6004) + { itype = SH64_COMPACT_INSN_MOVB7_COMPACT; goto extract_sfmt_movb7_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 773 : /* fall through */ + case 789 : /* fall through */ + case 805 : /* fall through */ + case 821 : /* fall through */ + case 837 : /* fall through */ + case 853 : /* fall through */ + case 869 : /* fall through */ + case 885 : + if ((entire_insn & 0xf00f) == 0x6005) + { itype = SH64_COMPACT_INSN_MOVW7_COMPACT; goto extract_sfmt_movw7_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 774 : /* fall through */ + case 790 : /* fall through */ + case 806 : /* fall through */ + case 822 : /* fall through */ + case 838 : /* fall through */ + case 854 : /* fall through */ + case 870 : /* fall through */ + case 886 : + if ((entire_insn & 0xf00f) == 0x6006) + { itype = SH64_COMPACT_INSN_MOVL7_COMPACT; goto extract_sfmt_movl7_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 775 : /* fall through */ + case 791 : /* fall through */ + case 807 : /* fall through */ + case 823 : /* fall through */ + case 839 : /* fall through */ + case 855 : /* fall through */ + case 871 : /* fall through */ + case 887 : + if ((entire_insn & 0xf00f) == 0x6007) + { itype = SH64_COMPACT_INSN_NOT_COMPACT; goto extract_sfmt_mov_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 776 : /* fall through */ + case 792 : /* fall through */ + case 808 : /* fall through */ + case 824 : /* fall through */ + case 840 : /* fall through */ + case 856 : /* fall through */ + case 872 : /* fall through */ + case 888 : + if ((entire_insn & 0xf00f) == 0x6008) + { itype = SH64_COMPACT_INSN_SWAPB_COMPACT; goto extract_sfmt_extsb_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 777 : /* fall through */ + case 793 : /* fall through */ + case 809 : /* fall through */ + case 825 : /* fall through */ + case 841 : /* fall through */ + case 857 : /* fall through */ + case 873 : /* fall through */ + case 889 : + if ((entire_insn & 0xf00f) == 0x6009) + { itype = SH64_COMPACT_INSN_SWAPW_COMPACT; goto extract_sfmt_extsb_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 778 : /* fall through */ + case 794 : /* fall through */ + case 810 : /* fall through */ + case 826 : /* fall through */ + case 842 : /* fall through */ + case 858 : /* fall through */ + case 874 : /* fall through */ + case 890 : + if ((entire_insn & 0xf00f) == 0x600a) + { itype = SH64_COMPACT_INSN_NEGC_COMPACT; goto extract_sfmt_negc_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 779 : /* fall through */ + case 795 : /* fall through */ + case 811 : /* fall through */ + case 827 : /* fall through */ + case 843 : /* fall through */ + case 859 : /* fall through */ + case 875 : /* fall through */ + case 891 : + if ((entire_insn & 0xf00f) == 0x600b) + { itype = SH64_COMPACT_INSN_NEG_COMPACT; goto extract_sfmt_extsb_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 780 : /* fall through */ + case 796 : /* fall through */ + case 812 : /* fall through */ + case 828 : /* fall through */ + case 844 : /* fall through */ + case 860 : /* fall through */ + case 876 : /* fall through */ + case 892 : + if ((entire_insn & 0xf00f) == 0x600c) + { itype = SH64_COMPACT_INSN_EXTUB_COMPACT; goto extract_sfmt_extsb_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 781 : /* fall through */ + case 797 : /* fall through */ + case 813 : /* fall through */ + case 829 : /* fall through */ + case 845 : /* fall through */ + case 861 : /* fall through */ + case 877 : /* fall through */ + case 893 : + if ((entire_insn & 0xf00f) == 0x600d) + { itype = SH64_COMPACT_INSN_EXTUW_COMPACT; goto extract_sfmt_extsb_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 782 : /* fall through */ + case 798 : /* fall through */ + case 814 : /* fall through */ + case 830 : /* fall through */ + case 846 : /* fall through */ + case 862 : /* fall through */ + case 878 : /* fall through */ + case 894 : + if ((entire_insn & 0xf00f) == 0x600e) + { itype = SH64_COMPACT_INSN_EXTSB_COMPACT; goto extract_sfmt_extsb_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 783 : /* fall through */ + case 799 : /* fall through */ + case 815 : /* fall through */ + case 831 : /* fall through */ + case 847 : /* fall through */ + case 863 : /* fall through */ + case 879 : /* fall through */ + case 895 : + if ((entire_insn & 0xf00f) == 0x600f) + { itype = SH64_COMPACT_INSN_EXTSW_COMPACT; goto extract_sfmt_extsb_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 896 : /* fall through */ + case 897 : /* fall through */ + case 898 : /* fall through */ + case 899 : /* fall through */ + case 900 : /* fall through */ + case 901 : /* fall through */ + case 902 : /* fall through */ + case 903 : /* fall through */ + case 904 : /* fall through */ + case 905 : /* fall through */ + case 906 : /* fall through */ + case 907 : /* fall through */ + case 908 : /* fall through */ + case 909 : /* fall through */ + case 910 : /* fall through */ + case 911 : /* fall through */ + case 912 : /* fall through */ + case 913 : /* fall through */ + case 914 : /* fall through */ + case 915 : /* fall through */ + case 916 : /* fall through */ + case 917 : /* fall through */ + case 918 : /* fall through */ + case 919 : /* fall through */ + case 920 : /* fall through */ + case 921 : /* fall through */ + case 922 : /* fall through */ + case 923 : /* fall through */ + case 924 : /* fall through */ + case 925 : /* fall through */ + case 926 : /* fall through */ + case 927 : /* fall through */ + case 928 : /* fall through */ + case 929 : /* fall through */ + case 930 : /* fall through */ + case 931 : /* fall through */ + case 932 : /* fall through */ + case 933 : /* fall through */ + case 934 : /* fall through */ + case 935 : /* fall through */ + case 936 : /* fall through */ + case 937 : /* fall through */ + case 938 : /* fall through */ + case 939 : /* fall through */ + case 940 : /* fall through */ + case 941 : /* fall through */ + case 942 : /* fall through */ + case 943 : /* fall through */ + case 944 : /* fall through */ + case 945 : /* fall through */ + case 946 : /* fall through */ + case 947 : /* fall through */ + case 948 : /* fall through */ + case 949 : /* fall through */ + case 950 : /* fall through */ + case 951 : /* fall through */ + case 952 : /* fall through */ + case 953 : /* fall through */ + case 954 : /* fall through */ + case 955 : /* fall through */ + case 956 : /* fall through */ + case 957 : /* fall through */ + case 958 : /* fall through */ + case 959 : /* fall through */ + case 960 : /* fall through */ + case 961 : /* fall through */ + case 962 : /* fall through */ + case 963 : /* fall through */ + case 964 : /* fall through */ + case 965 : /* fall through */ + case 966 : /* fall through */ + case 967 : /* fall through */ + case 968 : /* fall through */ + case 969 : /* fall through */ + case 970 : /* fall through */ + case 971 : /* fall through */ + case 972 : /* fall through */ + case 973 : /* fall through */ + case 974 : /* fall through */ + case 975 : /* fall through */ + case 976 : /* fall through */ + case 977 : /* fall through */ + case 978 : /* fall through */ + case 979 : /* fall through */ + case 980 : /* fall through */ + case 981 : /* fall through */ + case 982 : /* fall through */ + case 983 : /* fall through */ + case 984 : /* fall through */ + case 985 : /* fall through */ + case 986 : /* fall through */ + case 987 : /* fall through */ + case 988 : /* fall through */ + case 989 : /* fall through */ + case 990 : /* fall through */ + case 991 : /* fall through */ + case 992 : /* fall through */ + case 993 : /* fall through */ + case 994 : /* fall through */ + case 995 : /* fall through */ + case 996 : /* fall through */ + case 997 : /* fall through */ + case 998 : /* fall through */ + case 999 : /* fall through */ + case 1000 : /* fall through */ + case 1001 : /* fall through */ + case 1002 : /* fall through */ + case 1003 : /* fall through */ + case 1004 : /* fall through */ + case 1005 : /* fall through */ + case 1006 : /* fall through */ + case 1007 : /* fall through */ + case 1008 : /* fall through */ + case 1009 : /* fall through */ + case 1010 : /* fall through */ + case 1011 : /* fall through */ + case 1012 : /* fall through */ + case 1013 : /* fall through */ + case 1014 : /* fall through */ + case 1015 : /* fall through */ + case 1016 : /* fall through */ + case 1017 : /* fall through */ + case 1018 : /* fall through */ + case 1019 : /* fall through */ + case 1020 : /* fall through */ + case 1021 : /* fall through */ + case 1022 : /* fall through */ + case 1023 : + if ((entire_insn & 0xf000) == 0x7000) + { itype = SH64_COMPACT_INSN_ADDI_COMPACT; goto extract_sfmt_addi_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1024 : /* fall through */ + case 1025 : /* fall through */ + case 1026 : /* fall through */ + case 1027 : /* fall through */ + case 1028 : /* fall through */ + case 1029 : /* fall through */ + case 1030 : /* fall through */ + case 1031 : /* fall through */ + case 1032 : /* fall through */ + case 1033 : /* fall through */ + case 1034 : /* fall through */ + case 1035 : /* fall through */ + case 1036 : /* fall through */ + case 1037 : /* fall through */ + case 1038 : /* fall through */ + case 1039 : /* fall through */ + case 1040 : /* fall through */ + case 1041 : /* fall through */ + case 1042 : /* fall through */ + case 1043 : /* fall through */ + case 1044 : /* fall through */ + case 1045 : /* fall through */ + case 1046 : /* fall through */ + case 1047 : /* fall through */ + case 1048 : /* fall through */ + case 1049 : /* fall through */ + case 1050 : /* fall through */ + case 1051 : /* fall through */ + case 1052 : /* fall through */ + case 1053 : /* fall through */ + case 1054 : /* fall through */ + case 1055 : /* fall through */ + case 1056 : /* fall through */ + case 1057 : /* fall through */ + case 1058 : /* fall through */ + case 1059 : /* fall through */ + case 1060 : /* fall through */ + case 1061 : /* fall through */ + case 1062 : /* fall through */ + case 1063 : /* fall through */ + case 1064 : /* fall through */ + case 1065 : /* fall through */ + case 1066 : /* fall through */ + case 1067 : /* fall through */ + case 1068 : /* fall through */ + case 1069 : /* fall through */ + case 1070 : /* fall through */ + case 1071 : /* fall through */ + case 1072 : /* fall through */ + case 1073 : /* fall through */ + case 1074 : /* fall through */ + case 1075 : /* fall through */ + case 1076 : /* fall through */ + case 1077 : /* fall through */ + case 1078 : /* fall through */ + case 1079 : /* fall through */ + case 1080 : /* fall through */ + case 1081 : /* fall through */ + case 1082 : /* fall through */ + case 1083 : /* fall through */ + case 1084 : /* fall through */ + case 1085 : /* fall through */ + case 1086 : /* fall through */ + case 1087 : /* fall through */ + case 1088 : /* fall through */ + case 1089 : /* fall through */ + case 1090 : /* fall through */ + case 1091 : /* fall through */ + case 1092 : /* fall through */ + case 1093 : /* fall through */ + case 1094 : /* fall through */ + case 1095 : /* fall through */ + case 1096 : /* fall through */ + case 1097 : /* fall through */ + case 1098 : /* fall through */ + case 1099 : /* fall through */ + case 1100 : /* fall through */ + case 1101 : /* fall through */ + case 1102 : /* fall through */ + case 1103 : /* fall through */ + case 1104 : /* fall through */ + case 1105 : /* fall through */ + case 1106 : /* fall through */ + case 1107 : /* fall through */ + case 1108 : /* fall through */ + case 1109 : /* fall through */ + case 1110 : /* fall through */ + case 1111 : /* fall through */ + case 1112 : /* fall through */ + case 1113 : /* fall through */ + case 1114 : /* fall through */ + case 1115 : /* fall through */ + case 1116 : /* fall through */ + case 1117 : /* fall through */ + case 1118 : /* fall through */ + case 1119 : /* fall through */ + case 1120 : /* fall through */ + case 1121 : /* fall through */ + case 1122 : /* fall through */ + case 1123 : /* fall through */ + case 1124 : /* fall through */ + case 1125 : /* fall through */ + case 1126 : /* fall through */ + case 1127 : /* fall through */ + case 1128 : /* fall through */ + case 1129 : /* fall through */ + case 1130 : /* fall through */ + case 1131 : /* fall through */ + case 1132 : /* fall through */ + case 1133 : /* fall through */ + case 1134 : /* fall through */ + case 1135 : /* fall through */ + case 1136 : /* fall through */ + case 1137 : /* fall through */ + case 1138 : /* fall through */ + case 1139 : /* fall through */ + case 1140 : /* fall through */ + case 1141 : /* fall through */ + case 1142 : /* fall through */ + case 1143 : /* fall through */ + case 1144 : /* fall through */ + case 1145 : /* fall through */ + case 1146 : /* fall through */ + case 1147 : /* fall through */ + case 1148 : /* fall through */ + case 1149 : /* fall through */ + case 1150 : /* fall through */ + case 1151 : + { + unsigned int val = (((insn >> 8) & (15 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xff00) == 0x8000) + { itype = SH64_COMPACT_INSN_MOVB5_COMPACT; goto extract_sfmt_movb5_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xff00) == 0x8100) + { itype = SH64_COMPACT_INSN_MOVW5_COMPACT; goto extract_sfmt_movw5_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 4 : + if ((entire_insn & 0xff00) == 0x8400) + { itype = SH64_COMPACT_INSN_MOVB10_COMPACT; goto extract_sfmt_movb10_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 5 : + if ((entire_insn & 0xff00) == 0x8500) + { itype = SH64_COMPACT_INSN_MOVW11_COMPACT; goto extract_sfmt_movw11_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 8 : + if ((entire_insn & 0xff00) == 0x8800) + { itype = SH64_COMPACT_INSN_CMPEQI_COMPACT; goto extract_sfmt_cmpeqi_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 9 : + if ((entire_insn & 0xff00) == 0x8900) + { itype = SH64_COMPACT_INSN_BT_COMPACT; goto extract_sfmt_bf_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 11 : + if ((entire_insn & 0xff00) == 0x8b00) + { itype = SH64_COMPACT_INSN_BF_COMPACT; goto extract_sfmt_bf_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 13 : + if ((entire_insn & 0xff00) == 0x8d00) + { itype = SH64_COMPACT_INSN_BTS_COMPACT; goto extract_sfmt_bfs_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 15 : + if ((entire_insn & 0xff00) == 0x8f00) + { itype = SH64_COMPACT_INSN_BFS_COMPACT; goto extract_sfmt_bfs_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 1152 : /* fall through */ + case 1153 : /* fall through */ + case 1154 : /* fall through */ + case 1155 : /* fall through */ + case 1156 : /* fall through */ + case 1157 : /* fall through */ + case 1158 : /* fall through */ + case 1159 : /* fall through */ + case 1160 : /* fall through */ + case 1161 : /* fall through */ + case 1162 : /* fall through */ + case 1163 : /* fall through */ + case 1164 : /* fall through */ + case 1165 : /* fall through */ + case 1166 : /* fall through */ + case 1167 : /* fall through */ + case 1168 : /* fall through */ + case 1169 : /* fall through */ + case 1170 : /* fall through */ + case 1171 : /* fall through */ + case 1172 : /* fall through */ + case 1173 : /* fall through */ + case 1174 : /* fall through */ + case 1175 : /* fall through */ + case 1176 : /* fall through */ + case 1177 : /* fall through */ + case 1178 : /* fall through */ + case 1179 : /* fall through */ + case 1180 : /* fall through */ + case 1181 : /* fall through */ + case 1182 : /* fall through */ + case 1183 : /* fall through */ + case 1184 : /* fall through */ + case 1185 : /* fall through */ + case 1186 : /* fall through */ + case 1187 : /* fall through */ + case 1188 : /* fall through */ + case 1189 : /* fall through */ + case 1190 : /* fall through */ + case 1191 : /* fall through */ + case 1192 : /* fall through */ + case 1193 : /* fall through */ + case 1194 : /* fall through */ + case 1195 : /* fall through */ + case 1196 : /* fall through */ + case 1197 : /* fall through */ + case 1198 : /* fall through */ + case 1199 : /* fall through */ + case 1200 : /* fall through */ + case 1201 : /* fall through */ + case 1202 : /* fall through */ + case 1203 : /* fall through */ + case 1204 : /* fall through */ + case 1205 : /* fall through */ + case 1206 : /* fall through */ + case 1207 : /* fall through */ + case 1208 : /* fall through */ + case 1209 : /* fall through */ + case 1210 : /* fall through */ + case 1211 : /* fall through */ + case 1212 : /* fall through */ + case 1213 : /* fall through */ + case 1214 : /* fall through */ + case 1215 : /* fall through */ + case 1216 : /* fall through */ + case 1217 : /* fall through */ + case 1218 : /* fall through */ + case 1219 : /* fall through */ + case 1220 : /* fall through */ + case 1221 : /* fall through */ + case 1222 : /* fall through */ + case 1223 : /* fall through */ + case 1224 : /* fall through */ + case 1225 : /* fall through */ + case 1226 : /* fall through */ + case 1227 : /* fall through */ + case 1228 : /* fall through */ + case 1229 : /* fall through */ + case 1230 : /* fall through */ + case 1231 : /* fall through */ + case 1232 : /* fall through */ + case 1233 : /* fall through */ + case 1234 : /* fall through */ + case 1235 : /* fall through */ + case 1236 : /* fall through */ + case 1237 : /* fall through */ + case 1238 : /* fall through */ + case 1239 : /* fall through */ + case 1240 : /* fall through */ + case 1241 : /* fall through */ + case 1242 : /* fall through */ + case 1243 : /* fall through */ + case 1244 : /* fall through */ + case 1245 : /* fall through */ + case 1246 : /* fall through */ + case 1247 : /* fall through */ + case 1248 : /* fall through */ + case 1249 : /* fall through */ + case 1250 : /* fall through */ + case 1251 : /* fall through */ + case 1252 : /* fall through */ + case 1253 : /* fall through */ + case 1254 : /* fall through */ + case 1255 : /* fall through */ + case 1256 : /* fall through */ + case 1257 : /* fall through */ + case 1258 : /* fall through */ + case 1259 : /* fall through */ + case 1260 : /* fall through */ + case 1261 : /* fall through */ + case 1262 : /* fall through */ + case 1263 : /* fall through */ + case 1264 : /* fall through */ + case 1265 : /* fall through */ + case 1266 : /* fall through */ + case 1267 : /* fall through */ + case 1268 : /* fall through */ + case 1269 : /* fall through */ + case 1270 : /* fall through */ + case 1271 : /* fall through */ + case 1272 : /* fall through */ + case 1273 : /* fall through */ + case 1274 : /* fall through */ + case 1275 : /* fall through */ + case 1276 : /* fall through */ + case 1277 : /* fall through */ + case 1278 : /* fall through */ + case 1279 : + if ((entire_insn & 0xf000) == 0x9000) + { itype = SH64_COMPACT_INSN_MOVW10_COMPACT; goto extract_sfmt_movw10_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1280 : /* fall through */ + case 1281 : /* fall through */ + case 1282 : /* fall through */ + case 1283 : /* fall through */ + case 1284 : /* fall through */ + case 1285 : /* fall through */ + case 1286 : /* fall through */ + case 1287 : /* fall through */ + case 1288 : /* fall through */ + case 1289 : /* fall through */ + case 1290 : /* fall through */ + case 1291 : /* fall through */ + case 1292 : /* fall through */ + case 1293 : /* fall through */ + case 1294 : /* fall through */ + case 1295 : /* fall through */ + case 1296 : /* fall through */ + case 1297 : /* fall through */ + case 1298 : /* fall through */ + case 1299 : /* fall through */ + case 1300 : /* fall through */ + case 1301 : /* fall through */ + case 1302 : /* fall through */ + case 1303 : /* fall through */ + case 1304 : /* fall through */ + case 1305 : /* fall through */ + case 1306 : /* fall through */ + case 1307 : /* fall through */ + case 1308 : /* fall through */ + case 1309 : /* fall through */ + case 1310 : /* fall through */ + case 1311 : /* fall through */ + case 1312 : /* fall through */ + case 1313 : /* fall through */ + case 1314 : /* fall through */ + case 1315 : /* fall through */ + case 1316 : /* fall through */ + case 1317 : /* fall through */ + case 1318 : /* fall through */ + case 1319 : /* fall through */ + case 1320 : /* fall through */ + case 1321 : /* fall through */ + case 1322 : /* fall through */ + case 1323 : /* fall through */ + case 1324 : /* fall through */ + case 1325 : /* fall through */ + case 1326 : /* fall through */ + case 1327 : /* fall through */ + case 1328 : /* fall through */ + case 1329 : /* fall through */ + case 1330 : /* fall through */ + case 1331 : /* fall through */ + case 1332 : /* fall through */ + case 1333 : /* fall through */ + case 1334 : /* fall through */ + case 1335 : /* fall through */ + case 1336 : /* fall through */ + case 1337 : /* fall through */ + case 1338 : /* fall through */ + case 1339 : /* fall through */ + case 1340 : /* fall through */ + case 1341 : /* fall through */ + case 1342 : /* fall through */ + case 1343 : /* fall through */ + case 1344 : /* fall through */ + case 1345 : /* fall through */ + case 1346 : /* fall through */ + case 1347 : /* fall through */ + case 1348 : /* fall through */ + case 1349 : /* fall through */ + case 1350 : /* fall through */ + case 1351 : /* fall through */ + case 1352 : /* fall through */ + case 1353 : /* fall through */ + case 1354 : /* fall through */ + case 1355 : /* fall through */ + case 1356 : /* fall through */ + case 1357 : /* fall through */ + case 1358 : /* fall through */ + case 1359 : /* fall through */ + case 1360 : /* fall through */ + case 1361 : /* fall through */ + case 1362 : /* fall through */ + case 1363 : /* fall through */ + case 1364 : /* fall through */ + case 1365 : /* fall through */ + case 1366 : /* fall through */ + case 1367 : /* fall through */ + case 1368 : /* fall through */ + case 1369 : /* fall through */ + case 1370 : /* fall through */ + case 1371 : /* fall through */ + case 1372 : /* fall through */ + case 1373 : /* fall through */ + case 1374 : /* fall through */ + case 1375 : /* fall through */ + case 1376 : /* fall through */ + case 1377 : /* fall through */ + case 1378 : /* fall through */ + case 1379 : /* fall through */ + case 1380 : /* fall through */ + case 1381 : /* fall through */ + case 1382 : /* fall through */ + case 1383 : /* fall through */ + case 1384 : /* fall through */ + case 1385 : /* fall through */ + case 1386 : /* fall through */ + case 1387 : /* fall through */ + case 1388 : /* fall through */ + case 1389 : /* fall through */ + case 1390 : /* fall through */ + case 1391 : /* fall through */ + case 1392 : /* fall through */ + case 1393 : /* fall through */ + case 1394 : /* fall through */ + case 1395 : /* fall through */ + case 1396 : /* fall through */ + case 1397 : /* fall through */ + case 1398 : /* fall through */ + case 1399 : /* fall through */ + case 1400 : /* fall through */ + case 1401 : /* fall through */ + case 1402 : /* fall through */ + case 1403 : /* fall through */ + case 1404 : /* fall through */ + case 1405 : /* fall through */ + case 1406 : /* fall through */ + case 1407 : + if ((entire_insn & 0xf000) == 0xa000) + { itype = SH64_COMPACT_INSN_BRA_COMPACT; goto extract_sfmt_bra_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1408 : /* fall through */ + case 1409 : /* fall through */ + case 1410 : /* fall through */ + case 1411 : /* fall through */ + case 1412 : /* fall through */ + case 1413 : /* fall through */ + case 1414 : /* fall through */ + case 1415 : /* fall through */ + case 1416 : /* fall through */ + case 1417 : /* fall through */ + case 1418 : /* fall through */ + case 1419 : /* fall through */ + case 1420 : /* fall through */ + case 1421 : /* fall through */ + case 1422 : /* fall through */ + case 1423 : /* fall through */ + case 1424 : /* fall through */ + case 1425 : /* fall through */ + case 1426 : /* fall through */ + case 1427 : /* fall through */ + case 1428 : /* fall through */ + case 1429 : /* fall through */ + case 1430 : /* fall through */ + case 1431 : /* fall through */ + case 1432 : /* fall through */ + case 1433 : /* fall through */ + case 1434 : /* fall through */ + case 1435 : /* fall through */ + case 1436 : /* fall through */ + case 1437 : /* fall through */ + case 1438 : /* fall through */ + case 1439 : /* fall through */ + case 1440 : /* fall through */ + case 1441 : /* fall through */ + case 1442 : /* fall through */ + case 1443 : /* fall through */ + case 1444 : /* fall through */ + case 1445 : /* fall through */ + case 1446 : /* fall through */ + case 1447 : /* fall through */ + case 1448 : /* fall through */ + case 1449 : /* fall through */ + case 1450 : /* fall through */ + case 1451 : /* fall through */ + case 1452 : /* fall through */ + case 1453 : /* fall through */ + case 1454 : /* fall through */ + case 1455 : /* fall through */ + case 1456 : /* fall through */ + case 1457 : /* fall through */ + case 1458 : /* fall through */ + case 1459 : /* fall through */ + case 1460 : /* fall through */ + case 1461 : /* fall through */ + case 1462 : /* fall through */ + case 1463 : /* fall through */ + case 1464 : /* fall through */ + case 1465 : /* fall through */ + case 1466 : /* fall through */ + case 1467 : /* fall through */ + case 1468 : /* fall through */ + case 1469 : /* fall through */ + case 1470 : /* fall through */ + case 1471 : /* fall through */ + case 1472 : /* fall through */ + case 1473 : /* fall through */ + case 1474 : /* fall through */ + case 1475 : /* fall through */ + case 1476 : /* fall through */ + case 1477 : /* fall through */ + case 1478 : /* fall through */ + case 1479 : /* fall through */ + case 1480 : /* fall through */ + case 1481 : /* fall through */ + case 1482 : /* fall through */ + case 1483 : /* fall through */ + case 1484 : /* fall through */ + case 1485 : /* fall through */ + case 1486 : /* fall through */ + case 1487 : /* fall through */ + case 1488 : /* fall through */ + case 1489 : /* fall through */ + case 1490 : /* fall through */ + case 1491 : /* fall through */ + case 1492 : /* fall through */ + case 1493 : /* fall through */ + case 1494 : /* fall through */ + case 1495 : /* fall through */ + case 1496 : /* fall through */ + case 1497 : /* fall through */ + case 1498 : /* fall through */ + case 1499 : /* fall through */ + case 1500 : /* fall through */ + case 1501 : /* fall through */ + case 1502 : /* fall through */ + case 1503 : /* fall through */ + case 1504 : /* fall through */ + case 1505 : /* fall through */ + case 1506 : /* fall through */ + case 1507 : /* fall through */ + case 1508 : /* fall through */ + case 1509 : /* fall through */ + case 1510 : /* fall through */ + case 1511 : /* fall through */ + case 1512 : /* fall through */ + case 1513 : /* fall through */ + case 1514 : /* fall through */ + case 1515 : /* fall through */ + case 1516 : /* fall through */ + case 1517 : /* fall through */ + case 1518 : /* fall through */ + case 1519 : /* fall through */ + case 1520 : /* fall through */ + case 1521 : /* fall through */ + case 1522 : /* fall through */ + case 1523 : /* fall through */ + case 1524 : /* fall through */ + case 1525 : /* fall through */ + case 1526 : /* fall through */ + case 1527 : /* fall through */ + case 1528 : /* fall through */ + case 1529 : /* fall through */ + case 1530 : /* fall through */ + case 1531 : /* fall through */ + case 1532 : /* fall through */ + case 1533 : /* fall through */ + case 1534 : /* fall through */ + case 1535 : + if ((entire_insn & 0xf000) == 0xb000) + { itype = SH64_COMPACT_INSN_BSR_COMPACT; goto extract_sfmt_bsr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1536 : /* fall through */ + case 1537 : /* fall through */ + case 1538 : /* fall through */ + case 1539 : /* fall through */ + case 1540 : /* fall through */ + case 1541 : /* fall through */ + case 1542 : /* fall through */ + case 1543 : /* fall through */ + case 1544 : /* fall through */ + case 1545 : /* fall through */ + case 1546 : /* fall through */ + case 1547 : /* fall through */ + case 1548 : /* fall through */ + case 1549 : /* fall through */ + case 1550 : /* fall through */ + case 1551 : /* fall through */ + case 1552 : /* fall through */ + case 1553 : /* fall through */ + case 1554 : /* fall through */ + case 1555 : /* fall through */ + case 1556 : /* fall through */ + case 1557 : /* fall through */ + case 1558 : /* fall through */ + case 1559 : /* fall through */ + case 1560 : /* fall through */ + case 1561 : /* fall through */ + case 1562 : /* fall through */ + case 1563 : /* fall through */ + case 1564 : /* fall through */ + case 1565 : /* fall through */ + case 1566 : /* fall through */ + case 1567 : /* fall through */ + case 1568 : /* fall through */ + case 1569 : /* fall through */ + case 1570 : /* fall through */ + case 1571 : /* fall through */ + case 1572 : /* fall through */ + case 1573 : /* fall through */ + case 1574 : /* fall through */ + case 1575 : /* fall through */ + case 1576 : /* fall through */ + case 1577 : /* fall through */ + case 1578 : /* fall through */ + case 1579 : /* fall through */ + case 1580 : /* fall through */ + case 1581 : /* fall through */ + case 1582 : /* fall through */ + case 1583 : /* fall through */ + case 1584 : /* fall through */ + case 1585 : /* fall through */ + case 1586 : /* fall through */ + case 1587 : /* fall through */ + case 1588 : /* fall through */ + case 1589 : /* fall through */ + case 1590 : /* fall through */ + case 1591 : /* fall through */ + case 1592 : /* fall through */ + case 1593 : /* fall through */ + case 1594 : /* fall through */ + case 1595 : /* fall through */ + case 1596 : /* fall through */ + case 1597 : /* fall through */ + case 1598 : /* fall through */ + case 1599 : /* fall through */ + case 1600 : /* fall through */ + case 1601 : /* fall through */ + case 1602 : /* fall through */ + case 1603 : /* fall through */ + case 1604 : /* fall through */ + case 1605 : /* fall through */ + case 1606 : /* fall through */ + case 1607 : /* fall through */ + case 1608 : /* fall through */ + case 1609 : /* fall through */ + case 1610 : /* fall through */ + case 1611 : /* fall through */ + case 1612 : /* fall through */ + case 1613 : /* fall through */ + case 1614 : /* fall through */ + case 1615 : /* fall through */ + case 1616 : /* fall through */ + case 1617 : /* fall through */ + case 1618 : /* fall through */ + case 1619 : /* fall through */ + case 1620 : /* fall through */ + case 1621 : /* fall through */ + case 1622 : /* fall through */ + case 1623 : /* fall through */ + case 1624 : /* fall through */ + case 1625 : /* fall through */ + case 1626 : /* fall through */ + case 1627 : /* fall through */ + case 1628 : /* fall through */ + case 1629 : /* fall through */ + case 1630 : /* fall through */ + case 1631 : /* fall through */ + case 1632 : /* fall through */ + case 1633 : /* fall through */ + case 1634 : /* fall through */ + case 1635 : /* fall through */ + case 1636 : /* fall through */ + case 1637 : /* fall through */ + case 1638 : /* fall through */ + case 1639 : /* fall through */ + case 1640 : /* fall through */ + case 1641 : /* fall through */ + case 1642 : /* fall through */ + case 1643 : /* fall through */ + case 1644 : /* fall through */ + case 1645 : /* fall through */ + case 1646 : /* fall through */ + case 1647 : /* fall through */ + case 1648 : /* fall through */ + case 1649 : /* fall through */ + case 1650 : /* fall through */ + case 1651 : /* fall through */ + case 1652 : /* fall through */ + case 1653 : /* fall through */ + case 1654 : /* fall through */ + case 1655 : /* fall through */ + case 1656 : /* fall through */ + case 1657 : /* fall through */ + case 1658 : /* fall through */ + case 1659 : /* fall through */ + case 1660 : /* fall through */ + case 1661 : /* fall through */ + case 1662 : /* fall through */ + case 1663 : + { + unsigned int val = (((insn >> 8) & (15 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xff00) == 0xc000) + { itype = SH64_COMPACT_INSN_MOVB4_COMPACT; goto extract_sfmt_movb4_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xff00) == 0xc100) + { itype = SH64_COMPACT_INSN_MOVW4_COMPACT; goto extract_sfmt_movw4_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 2 : + if ((entire_insn & 0xff00) == 0xc200) + { itype = SH64_COMPACT_INSN_MOVL4_COMPACT; goto extract_sfmt_movl4_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 3 : + if ((entire_insn & 0xff00) == 0xc300) + { itype = SH64_COMPACT_INSN_TRAPA_COMPACT; goto extract_sfmt_trapa_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 4 : + if ((entire_insn & 0xff00) == 0xc400) + { itype = SH64_COMPACT_INSN_MOVB9_COMPACT; goto extract_sfmt_movb9_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 5 : + if ((entire_insn & 0xff00) == 0xc500) + { itype = SH64_COMPACT_INSN_MOVW9_COMPACT; goto extract_sfmt_movw9_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 6 : + if ((entire_insn & 0xff00) == 0xc600) + { itype = SH64_COMPACT_INSN_MOVL9_COMPACT; goto extract_sfmt_movl9_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 7 : + if ((entire_insn & 0xff00) == 0xc700) + { itype = SH64_COMPACT_INSN_MOVA_COMPACT; goto extract_sfmt_mova_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 8 : + if ((entire_insn & 0xff00) == 0xc800) + { itype = SH64_COMPACT_INSN_TSTI_COMPACT; goto extract_sfmt_tsti_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 9 : + if ((entire_insn & 0xff00) == 0xc900) + { itype = SH64_COMPACT_INSN_ANDI_COMPACT; goto extract_sfmt_andi_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 10 : + if ((entire_insn & 0xff00) == 0xca00) + { itype = SH64_COMPACT_INSN_XORI_COMPACT; goto extract_sfmt_andi_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 11 : + if ((entire_insn & 0xff00) == 0xcb00) + { itype = SH64_COMPACT_INSN_ORI_COMPACT; goto extract_sfmt_andi_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 12 : + if ((entire_insn & 0xff00) == 0xcc00) + { itype = SH64_COMPACT_INSN_TSTB_COMPACT; goto extract_sfmt_tstb_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 13 : + if ((entire_insn & 0xff00) == 0xcd00) + { itype = SH64_COMPACT_INSN_ANDB_COMPACT; goto extract_sfmt_andb_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 14 : + if ((entire_insn & 0xff00) == 0xce00) + { itype = SH64_COMPACT_INSN_XORB_COMPACT; goto extract_sfmt_andb_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 15 : + if ((entire_insn & 0xff00) == 0xcf00) + { itype = SH64_COMPACT_INSN_ORB_COMPACT; goto extract_sfmt_andb_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 1664 : /* fall through */ + case 1665 : /* fall through */ + case 1666 : /* fall through */ + case 1667 : /* fall through */ + case 1668 : /* fall through */ + case 1669 : /* fall through */ + case 1670 : /* fall through */ + case 1671 : /* fall through */ + case 1672 : /* fall through */ + case 1673 : /* fall through */ + case 1674 : /* fall through */ + case 1675 : /* fall through */ + case 1676 : /* fall through */ + case 1677 : /* fall through */ + case 1678 : /* fall through */ + case 1679 : /* fall through */ + case 1680 : /* fall through */ + case 1681 : /* fall through */ + case 1682 : /* fall through */ + case 1683 : /* fall through */ + case 1684 : /* fall through */ + case 1685 : /* fall through */ + case 1686 : /* fall through */ + case 1687 : /* fall through */ + case 1688 : /* fall through */ + case 1689 : /* fall through */ + case 1690 : /* fall through */ + case 1691 : /* fall through */ + case 1692 : /* fall through */ + case 1693 : /* fall through */ + case 1694 : /* fall through */ + case 1695 : /* fall through */ + case 1696 : /* fall through */ + case 1697 : /* fall through */ + case 1698 : /* fall through */ + case 1699 : /* fall through */ + case 1700 : /* fall through */ + case 1701 : /* fall through */ + case 1702 : /* fall through */ + case 1703 : /* fall through */ + case 1704 : /* fall through */ + case 1705 : /* fall through */ + case 1706 : /* fall through */ + case 1707 : /* fall through */ + case 1708 : /* fall through */ + case 1709 : /* fall through */ + case 1710 : /* fall through */ + case 1711 : /* fall through */ + case 1712 : /* fall through */ + case 1713 : /* fall through */ + case 1714 : /* fall through */ + case 1715 : /* fall through */ + case 1716 : /* fall through */ + case 1717 : /* fall through */ + case 1718 : /* fall through */ + case 1719 : /* fall through */ + case 1720 : /* fall through */ + case 1721 : /* fall through */ + case 1722 : /* fall through */ + case 1723 : /* fall through */ + case 1724 : /* fall through */ + case 1725 : /* fall through */ + case 1726 : /* fall through */ + case 1727 : /* fall through */ + case 1728 : /* fall through */ + case 1729 : /* fall through */ + case 1730 : /* fall through */ + case 1731 : /* fall through */ + case 1732 : /* fall through */ + case 1733 : /* fall through */ + case 1734 : /* fall through */ + case 1735 : /* fall through */ + case 1736 : /* fall through */ + case 1737 : /* fall through */ + case 1738 : /* fall through */ + case 1739 : /* fall through */ + case 1740 : /* fall through */ + case 1741 : /* fall through */ + case 1742 : /* fall through */ + case 1743 : /* fall through */ + case 1744 : /* fall through */ + case 1745 : /* fall through */ + case 1746 : /* fall through */ + case 1747 : /* fall through */ + case 1748 : /* fall through */ + case 1749 : /* fall through */ + case 1750 : /* fall through */ + case 1751 : /* fall through */ + case 1752 : /* fall through */ + case 1753 : /* fall through */ + case 1754 : /* fall through */ + case 1755 : /* fall through */ + case 1756 : /* fall through */ + case 1757 : /* fall through */ + case 1758 : /* fall through */ + case 1759 : /* fall through */ + case 1760 : /* fall through */ + case 1761 : /* fall through */ + case 1762 : /* fall through */ + case 1763 : /* fall through */ + case 1764 : /* fall through */ + case 1765 : /* fall through */ + case 1766 : /* fall through */ + case 1767 : /* fall through */ + case 1768 : /* fall through */ + case 1769 : /* fall through */ + case 1770 : /* fall through */ + case 1771 : /* fall through */ + case 1772 : /* fall through */ + case 1773 : /* fall through */ + case 1774 : /* fall through */ + case 1775 : /* fall through */ + case 1776 : /* fall through */ + case 1777 : /* fall through */ + case 1778 : /* fall through */ + case 1779 : /* fall through */ + case 1780 : /* fall through */ + case 1781 : /* fall through */ + case 1782 : /* fall through */ + case 1783 : /* fall through */ + case 1784 : /* fall through */ + case 1785 : /* fall through */ + case 1786 : /* fall through */ + case 1787 : /* fall through */ + case 1788 : /* fall through */ + case 1789 : /* fall through */ + case 1790 : /* fall through */ + case 1791 : + if ((entire_insn & 0xf000) == 0xd000) + { itype = SH64_COMPACT_INSN_MOVL10_COMPACT; goto extract_sfmt_movl10_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1792 : /* fall through */ + case 1793 : /* fall through */ + case 1794 : /* fall through */ + case 1795 : /* fall through */ + case 1796 : /* fall through */ + case 1797 : /* fall through */ + case 1798 : /* fall through */ + case 1799 : /* fall through */ + case 1800 : /* fall through */ + case 1801 : /* fall through */ + case 1802 : /* fall through */ + case 1803 : /* fall through */ + case 1804 : /* fall through */ + case 1805 : /* fall through */ + case 1806 : /* fall through */ + case 1807 : /* fall through */ + case 1808 : /* fall through */ + case 1809 : /* fall through */ + case 1810 : /* fall through */ + case 1811 : /* fall through */ + case 1812 : /* fall through */ + case 1813 : /* fall through */ + case 1814 : /* fall through */ + case 1815 : /* fall through */ + case 1816 : /* fall through */ + case 1817 : /* fall through */ + case 1818 : /* fall through */ + case 1819 : /* fall through */ + case 1820 : /* fall through */ + case 1821 : /* fall through */ + case 1822 : /* fall through */ + case 1823 : /* fall through */ + case 1824 : /* fall through */ + case 1825 : /* fall through */ + case 1826 : /* fall through */ + case 1827 : /* fall through */ + case 1828 : /* fall through */ + case 1829 : /* fall through */ + case 1830 : /* fall through */ + case 1831 : /* fall through */ + case 1832 : /* fall through */ + case 1833 : /* fall through */ + case 1834 : /* fall through */ + case 1835 : /* fall through */ + case 1836 : /* fall through */ + case 1837 : /* fall through */ + case 1838 : /* fall through */ + case 1839 : /* fall through */ + case 1840 : /* fall through */ + case 1841 : /* fall through */ + case 1842 : /* fall through */ + case 1843 : /* fall through */ + case 1844 : /* fall through */ + case 1845 : /* fall through */ + case 1846 : /* fall through */ + case 1847 : /* fall through */ + case 1848 : /* fall through */ + case 1849 : /* fall through */ + case 1850 : /* fall through */ + case 1851 : /* fall through */ + case 1852 : /* fall through */ + case 1853 : /* fall through */ + case 1854 : /* fall through */ + case 1855 : /* fall through */ + case 1856 : /* fall through */ + case 1857 : /* fall through */ + case 1858 : /* fall through */ + case 1859 : /* fall through */ + case 1860 : /* fall through */ + case 1861 : /* fall through */ + case 1862 : /* fall through */ + case 1863 : /* fall through */ + case 1864 : /* fall through */ + case 1865 : /* fall through */ + case 1866 : /* fall through */ + case 1867 : /* fall through */ + case 1868 : /* fall through */ + case 1869 : /* fall through */ + case 1870 : /* fall through */ + case 1871 : /* fall through */ + case 1872 : /* fall through */ + case 1873 : /* fall through */ + case 1874 : /* fall through */ + case 1875 : /* fall through */ + case 1876 : /* fall through */ + case 1877 : /* fall through */ + case 1878 : /* fall through */ + case 1879 : /* fall through */ + case 1880 : /* fall through */ + case 1881 : /* fall through */ + case 1882 : /* fall through */ + case 1883 : /* fall through */ + case 1884 : /* fall through */ + case 1885 : /* fall through */ + case 1886 : /* fall through */ + case 1887 : /* fall through */ + case 1888 : /* fall through */ + case 1889 : /* fall through */ + case 1890 : /* fall through */ + case 1891 : /* fall through */ + case 1892 : /* fall through */ + case 1893 : /* fall through */ + case 1894 : /* fall through */ + case 1895 : /* fall through */ + case 1896 : /* fall through */ + case 1897 : /* fall through */ + case 1898 : /* fall through */ + case 1899 : /* fall through */ + case 1900 : /* fall through */ + case 1901 : /* fall through */ + case 1902 : /* fall through */ + case 1903 : /* fall through */ + case 1904 : /* fall through */ + case 1905 : /* fall through */ + case 1906 : /* fall through */ + case 1907 : /* fall through */ + case 1908 : /* fall through */ + case 1909 : /* fall through */ + case 1910 : /* fall through */ + case 1911 : /* fall through */ + case 1912 : /* fall through */ + case 1913 : /* fall through */ + case 1914 : /* fall through */ + case 1915 : /* fall through */ + case 1916 : /* fall through */ + case 1917 : /* fall through */ + case 1918 : /* fall through */ + case 1919 : + if ((entire_insn & 0xf000) == 0xe000) + { itype = SH64_COMPACT_INSN_MOVI_COMPACT; goto extract_sfmt_movi_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1920 : /* fall through */ + case 1936 : /* fall through */ + case 1952 : /* fall through */ + case 1968 : /* fall through */ + case 1984 : /* fall through */ + case 2000 : /* fall through */ + case 2016 : /* fall through */ + case 2032 : + if ((entire_insn & 0xf00f) == 0xf000) + { itype = SH64_COMPACT_INSN_FADD_COMPACT; goto extract_sfmt_fadd_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1921 : /* fall through */ + case 1937 : /* fall through */ + case 1953 : /* fall through */ + case 1969 : /* fall through */ + case 1985 : /* fall through */ + case 2001 : /* fall through */ + case 2017 : /* fall through */ + case 2033 : + if ((entire_insn & 0xf00f) == 0xf001) + { itype = SH64_COMPACT_INSN_FSUB_COMPACT; goto extract_sfmt_fadd_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1922 : /* fall through */ + case 1938 : /* fall through */ + case 1954 : /* fall through */ + case 1970 : /* fall through */ + case 1986 : /* fall through */ + case 2002 : /* fall through */ + case 2018 : /* fall through */ + case 2034 : + if ((entire_insn & 0xf00f) == 0xf002) + { itype = SH64_COMPACT_INSN_FMUL_COMPACT; goto extract_sfmt_fadd_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1923 : /* fall through */ + case 1939 : /* fall through */ + case 1955 : /* fall through */ + case 1971 : /* fall through */ + case 1987 : /* fall through */ + case 2003 : /* fall through */ + case 2019 : /* fall through */ + case 2035 : + if ((entire_insn & 0xf00f) == 0xf003) + { itype = SH64_COMPACT_INSN_FDIV_COMPACT; goto extract_sfmt_fadd_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1924 : /* fall through */ + case 1940 : /* fall through */ + case 1956 : /* fall through */ + case 1972 : /* fall through */ + case 1988 : /* fall through */ + case 2004 : /* fall through */ + case 2020 : /* fall through */ + case 2036 : + if ((entire_insn & 0xf00f) == 0xf004) + { itype = SH64_COMPACT_INSN_FCMPEQ_COMPACT; goto extract_sfmt_fcmpeq_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1925 : /* fall through */ + case 1941 : /* fall through */ + case 1957 : /* fall through */ + case 1973 : /* fall through */ + case 1989 : /* fall through */ + case 2005 : /* fall through */ + case 2021 : /* fall through */ + case 2037 : + if ((entire_insn & 0xf00f) == 0xf005) + { itype = SH64_COMPACT_INSN_FCMPGT_COMPACT; goto extract_sfmt_fcmpeq_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1926 : /* fall through */ + case 1942 : /* fall through */ + case 1958 : /* fall through */ + case 1974 : /* fall through */ + case 1990 : /* fall through */ + case 2006 : /* fall through */ + case 2022 : /* fall through */ + case 2038 : + if ((entire_insn & 0xf00f) == 0xf006) + { itype = SH64_COMPACT_INSN_FMOV4_COMPACT; goto extract_sfmt_fmov4_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1927 : /* fall through */ + case 1943 : /* fall through */ + case 1959 : /* fall through */ + case 1975 : /* fall through */ + case 1991 : /* fall through */ + case 2007 : /* fall through */ + case 2023 : /* fall through */ + case 2039 : + if ((entire_insn & 0xf00f) == 0xf007) + { itype = SH64_COMPACT_INSN_FMOV7_COMPACT; goto extract_sfmt_fmov7_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1928 : /* fall through */ + case 1944 : /* fall through */ + case 1960 : /* fall through */ + case 1976 : /* fall through */ + case 1992 : /* fall through */ + case 2008 : /* fall through */ + case 2024 : /* fall through */ + case 2040 : + if ((entire_insn & 0xf00f) == 0xf008) + { itype = SH64_COMPACT_INSN_FMOV2_COMPACT; goto extract_sfmt_fmov2_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1929 : /* fall through */ + case 1945 : /* fall through */ + case 1961 : /* fall through */ + case 1977 : /* fall through */ + case 1993 : /* fall through */ + case 2009 : /* fall through */ + case 2025 : /* fall through */ + case 2041 : + if ((entire_insn & 0xf00f) == 0xf009) + { itype = SH64_COMPACT_INSN_FMOV3_COMPACT; goto extract_sfmt_fmov3_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1930 : /* fall through */ + case 1946 : /* fall through */ + case 1962 : /* fall through */ + case 1978 : /* fall through */ + case 1994 : /* fall through */ + case 2010 : /* fall through */ + case 2026 : /* fall through */ + case 2042 : + if ((entire_insn & 0xf00f) == 0xf00a) + { itype = SH64_COMPACT_INSN_FMOV5_COMPACT; goto extract_sfmt_fmov5_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1931 : /* fall through */ + case 1947 : /* fall through */ + case 1963 : /* fall through */ + case 1979 : /* fall through */ + case 1995 : /* fall through */ + case 2011 : /* fall through */ + case 2027 : /* fall through */ + case 2043 : + if ((entire_insn & 0xf00f) == 0xf00b) + { itype = SH64_COMPACT_INSN_FMOV6_COMPACT; goto extract_sfmt_fmov6_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1932 : /* fall through */ + case 1948 : /* fall through */ + case 1964 : /* fall through */ + case 1980 : /* fall through */ + case 1996 : /* fall through */ + case 2012 : /* fall through */ + case 2028 : /* fall through */ + case 2044 : + if ((entire_insn & 0xf00f) == 0xf00c) + { itype = SH64_COMPACT_INSN_FMOV1_COMPACT; goto extract_sfmt_fmov1_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1933 : + { + unsigned int val = (((insn >> 7) & (1 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xf0ff) == 0xf00d) + { itype = SH64_COMPACT_INSN_FSTS_COMPACT; goto extract_sfmt_fsts_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xf0ff) == 0xf08d) + { itype = SH64_COMPACT_INSN_FLDI0_COMPACT; goto extract_sfmt_fldi0_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 1934 : /* fall through */ + case 1950 : /* fall through */ + case 1966 : /* fall through */ + case 1982 : /* fall through */ + case 1998 : /* fall through */ + case 2014 : /* fall through */ + case 2030 : /* fall through */ + case 2046 : + if ((entire_insn & 0xf00f) == 0xf00e) + { itype = SH64_COMPACT_INSN_FMAC_COMPACT; goto extract_sfmt_fmac_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1949 : + { + unsigned int val = (((insn >> 7) & (1 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xf0ff) == 0xf01d) + { itype = SH64_COMPACT_INSN_FLDS_COMPACT; goto extract_sfmt_flds_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xf0ff) == 0xf09d) + { itype = SH64_COMPACT_INSN_FLDI1_COMPACT; goto extract_sfmt_fldi0_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 1965 : + { + unsigned int val = (((insn >> 7) & (1 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xf0ff) == 0xf02d) + { itype = SH64_COMPACT_INSN_FLOAT_COMPACT; goto extract_sfmt_float_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xf1ff) == 0xf0ad) + { itype = SH64_COMPACT_INSN_FCNVSD_COMPACT; goto extract_sfmt_fcnvsd_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 1981 : + { + unsigned int val = (((insn >> 7) & (1 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xf0ff) == 0xf03d) + { itype = SH64_COMPACT_INSN_FTRC_COMPACT; goto extract_sfmt_ftrc_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xf1ff) == 0xf0bd) + { itype = SH64_COMPACT_INSN_FCNVDS_COMPACT; goto extract_sfmt_fcnvds_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 1997 : + if ((entire_insn & 0xf0ff) == 0xf04d) + { itype = SH64_COMPACT_INSN_FNEG_COMPACT; goto extract_sfmt_fabs_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 2013 : + if ((entire_insn & 0xf0ff) == 0xf05d) + { itype = SH64_COMPACT_INSN_FABS_COMPACT; goto extract_sfmt_fabs_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 2029 : + { + unsigned int val = (((insn >> 7) & (1 << 0))); + switch (val) + { + case 0 : + if ((entire_insn & 0xf0ff) == 0xf06d) + { itype = SH64_COMPACT_INSN_FSQRT_COMPACT; goto extract_sfmt_fabs_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xf0ff) == 0xf0ed) + { itype = SH64_COMPACT_INSN_FIPR_COMPACT; goto extract_sfmt_fipr_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + case 2045 : { - unsigned int val = (((insn >> 4) & (15 << 0))); + unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); switch (val) { - case 0 : itype = SH64_COMPACT_INSN_FSTS_COMPACT; goto extract_sfmt_fsts_compact; case 1 : itype = SH64_COMPACT_INSN_FLDS_COMPACT; goto extract_sfmt_flds_compact; case 2 : itype = SH64_COMPACT_INSN_FLOAT_COMPACT; goto extract_sfmt_float_compact; case 3 : itype = SH64_COMPACT_INSN_FTRC_COMPACT; goto extract_sfmt_ftrc_compact; case 4 : itype = SH64_COMPACT_INSN_FNEG_COMPACT; goto extract_sfmt_fabs_compact; case 5 : itype = SH64_COMPACT_INSN_FABS_COMPACT; goto extract_sfmt_fabs_compact; case 6 : itype = SH64_COMPACT_INSN_FSQRT_COMPACT; goto extract_sfmt_fabs_compact; case 8 : itype = SH64_COMPACT_INSN_FLDI0_COMPACT; goto extract_sfmt_fldi0_compact; case 9 : itype = SH64_COMPACT_INSN_FLDI1_COMPACT; goto extract_sfmt_fldi0_compact; case 10 : itype = SH64_COMPACT_INSN_FCNVSD_COMPACT; goto extract_sfmt_fcnvsd_compact; case 11 : itype = SH64_COMPACT_INSN_FCNVDS_COMPACT; goto extract_sfmt_fcnvds_compact; case 14 : itype = SH64_COMPACT_INSN_FIPR_COMPACT; goto extract_sfmt_fipr_compact; case 15 : - { - unsigned int val = (((insn >> 9) & (1 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_FTRV_COMPACT; goto extract_sfmt_ftrv_compact; case 1 : - { - unsigned int val = (((insn >> 11) & (1 << 0))); - switch (val) - { - case 0 : itype = SH64_COMPACT_INSN_FSCHG_COMPACT; goto extract_sfmt_fschg_compact; case 1 : itype = SH64_COMPACT_INSN_FRCHG_COMPACT; goto extract_sfmt_frchg_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } - default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; - } - } + case 0 : /* fall through */ + case 2 : + if ((entire_insn & 0xf3ff) == 0xf1fd) + { itype = SH64_COMPACT_INSN_FTRV_COMPACT; goto extract_sfmt_ftrv_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 1 : + if ((entire_insn & 0xffff) == 0xf3fd) + { itype = SH64_COMPACT_INSN_FSCHG_COMPACT; goto extract_sfmt_fschg_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + case 3 : + if ((entire_insn & 0xffff) == 0xfbfd) + { itype = SH64_COMPACT_INSN_FRCHG_COMPACT; goto extract_sfmt_frchg_compact; } + itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; } } - case 254 : itype = SH64_COMPACT_INSN_FMAC_COMPACT; goto extract_sfmt_fmac_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty; } } } @@ -638,18 +3025,27 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -662,14 +3058,22 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_rn; UINT f_imm8; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_imm8) = f_imm8; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi_compact", "f_imm8 0x%x", 'x', f_imm8, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -678,18 +3082,27 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addc_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -698,18 +3111,27 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -718,18 +3140,27 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm64) = f_rm; + FLD (in_rn64) = f_rn; + FLD (out_rn64) = f_rn; + } +#endif #undef FLD return idesc; } @@ -741,12 +3172,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; - f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); + f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_imm8) = f_imm8; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andi_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + FLD (out_r0) = 0; + } +#endif #undef FLD return idesc; } @@ -758,12 +3197,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; - f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); + f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_imm8) = f_imm8; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andb_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + } +#endif #undef FLD return idesc; } @@ -775,12 +3221,41 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_bf_compact.f SI f_disp8; - f_disp8 = ((((EXTRACT_LSB0_INT (insn, 16, 7, 8)) << (1))) + (((pc) + (4)))); + f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (4)))); /* Record the fields for the semantic handler. */ FLD (i_disp8) = f_disp8; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bf_compact", "disp8 0x%x", 'x', f_disp8, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_bfs_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_bf_compact.f + SI f_disp8; + + f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (4)))); + + /* Record the fields for the semantic handler. */ + FLD (i_disp8) = f_disp8; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bfs_compact", "disp8 0x%x", 'x', f_disp8, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif #undef FLD return idesc; } @@ -792,12 +3267,18 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_bra_compact.f SI f_disp12; - f_disp12 = ((((EXTRACT_LSB0_INT (insn, 16, 11, 12)) << (1))) + (((pc) + (4)))); + f_disp12 = ((((EXTRACT_MSB0_INT (insn, 16, 4, 12)) << (1))) + (((pc) + (4)))); /* Record the fields for the semantic handler. */ FLD (i_disp12) = f_disp12; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra_compact", "disp12 0x%x", 'x', f_disp12, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif #undef FLD return idesc; } @@ -809,12 +3290,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_braf_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -828,6 +3316,12 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brk_compact", (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif #undef FLD return idesc; } @@ -839,12 +3333,18 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_bra_compact.f SI f_disp12; - f_disp12 = ((((EXTRACT_LSB0_INT (insn, 16, 11, 12)) << (1))) + (((pc) + (4)))); + f_disp12 = ((((EXTRACT_MSB0_INT (insn, 16, 4, 12)) << (1))) + (((pc) + (4)))); /* Record the fields for the semantic handler. */ FLD (i_disp12) = f_disp12; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bsr_compact", "disp12 0x%x", 'x', f_disp12, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif #undef FLD return idesc; } @@ -856,12 +3356,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bsrf_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -909,18 +3416,26 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpeq_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -932,12 +3447,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; - f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); + f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_imm8) = f_imm8; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpeqi_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + } +#endif #undef FLD return idesc; } @@ -949,12 +3471,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmppl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -963,18 +3492,26 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div0s_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -996,18 +3533,53 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div1_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_divu_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + UINT f_rn; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divu_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1016,18 +3588,26 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmulsl_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1039,12 +3619,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dt_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1053,18 +3641,26 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_extsb_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1076,12 +3672,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fabs_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fsdn) = f_rn; + FLD (out_fsdn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1090,18 +3694,27 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fadd_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fsdm) = f_rm; + FLD (in_fsdn) = f_rn; + FLD (out_fsdn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1110,18 +3723,26 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcmpeq_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fsdm) = f_rm; + FLD (in_fsdn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1130,15 +3751,23 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f +#define FLD(f) abuf->fields.sfmt_fmov8_compact.f SI f_dn; - f_dn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 3)) << (1)); + f_dn = ((EXTRACT_MSB0_UINT (insn, 16, 4, 3)) << (1)); /* Record the fields for the semantic handler. */ FLD (f_dn) = f_dn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcnvds_compact", "f_dn 0x%x", 'x', f_dn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_drn) = f_dn; + FLD (out_fpul) = 32; + } +#endif #undef FLD return idesc; } @@ -1147,15 +3776,23 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f +#define FLD(f) abuf->fields.sfmt_fmov8_compact.f SI f_dn; - f_dn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 3)) << (1)); + f_dn = ((EXTRACT_MSB0_UINT (insn, 16, 4, 3)) << (1)); /* Record the fields for the semantic handler. */ FLD (f_dn) = f_dn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcnvsd_compact", "f_dn 0x%x", 'x', f_dn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fpul) = 32; + FLD (out_drn) = f_dn; + } +#endif #undef FLD return idesc; } @@ -1168,8 +3805,8 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, SI f_vn; SI f_vm; - f_vn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 2)) << (2)); - f_vm = ((EXTRACT_LSB0_UINT (insn, 16, 9, 2)) << (2)); + f_vn = ((EXTRACT_MSB0_UINT (insn, 16, 4, 2)) << (2)); + f_vm = ((EXTRACT_MSB0_UINT (insn, 16, 6, 2)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_vm) = f_vm; @@ -1187,12 +3824,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flds_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_frn) = f_rn; + FLD (out_fpul) = 32; + } +#endif #undef FLD return idesc; } @@ -1204,12 +3849,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldi0_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_frn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1221,12 +3873,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_float_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fpul) = 32; + FLD (out_fsdn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1235,18 +3895,28 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmac_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fr0) = 0; + FLD (in_frm) = f_rm; + FLD (in_frn) = f_rn; + FLD (out_frn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1255,18 +3925,26 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov1_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fmovm) = f_rm; + FLD (out_fmovn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1275,18 +3953,26 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ - FLD (f_rn) = f_rn; FLD (f_rm) = f_rm; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov2_compact", "f_rn 0x%x", 'x', f_rn, "f_rm 0x%x", 'x', f_rm, (char *) 0)); + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov2_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (out_fmovn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1295,18 +3981,27 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ - FLD (f_rn) = f_rn; FLD (f_rm) = f_rm; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov3_compact", "f_rn 0x%x", 'x', f_rn, "f_rm 0x%x", 'x', f_rm, (char *) 0)); + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov3_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (out_fmovn) = f_rn; + FLD (out_rm) = f_rm; + } +#endif #undef FLD return idesc; } @@ -1315,18 +4010,27 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ - FLD (f_rn) = f_rn; FLD (f_rm) = f_rm; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov4_compact", "f_rn 0x%x", 'x', f_rn, "f_rm 0x%x", 'x', f_rm, (char *) 0)); + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov4_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + FLD (in_rm) = f_rm; + FLD (out_fmovn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1335,18 +4039,26 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov5_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fmovm) = f_rm; + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1355,18 +4067,27 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov6_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fmovm) = f_rm; + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1375,18 +4096,89 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov7_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fmovm) = f_rm; + FLD (in_r0) = 0; + FLD (in_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fmov8_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fmov8_compact.f + SI f_dn; + UINT f_rm; + SI f_imm12x8; + + f_dn = ((EXTRACT_MSB0_UINT (insn, 32, 4, 3)) << (1)); + f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4); + f_imm12x8 = ((EXTRACT_MSB0_INT (insn, 32, 20, 12)) << (3)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm12x8) = f_imm12x8; + FLD (f_rm) = f_rm; + FLD (f_dn) = f_dn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov8_compact", "f_imm12x8 0x%x", 'x', f_imm12x8, "f_rm 0x%x", 'x', f_rm, "f_dn 0x%x", 'x', f_dn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (out_drn) = f_dn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fmov9_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_fmov9_compact.f + UINT f_rn; + SI f_dm; + SI f_imm12x8; + + f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_dm = ((EXTRACT_MSB0_UINT (insn, 32, 8, 3)) << (1)); + f_imm12x8 = ((EXTRACT_MSB0_INT (insn, 32, 20, 12)) << (3)); + + /* Record the fields for the semantic handler. */ + FLD (f_dm) = f_dm; + FLD (f_imm12x8) = f_imm12x8; + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov9_compact", "f_dm 0x%x", 'x', f_dm, "f_imm12x8 0x%x", 'x', f_imm12x8, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_drm) = f_dm; + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1424,12 +4216,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fsts_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fpul) = 32; + FLD (out_frn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1441,12 +4241,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ftrc_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fsdn) = f_rn; + FLD (out_fpul) = 32; + } +#endif #undef FLD return idesc; } @@ -1458,7 +4266,7 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_fipr_compact.f SI f_vn; - f_vn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 2)) << (2)); + f_vn = ((EXTRACT_MSB0_UINT (insn, 16, 4, 2)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_vn) = f_vn; @@ -1468,53 +4276,124 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } - extract_sfmt_jmp_compact: + extract_sfmt_ldc_gbr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldc_gbr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } - extract_sfmt_ldc_compact: + extract_sfmt_ldc_vbr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldc_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldc_vbr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } - extract_sfmt_ldcl_compact: + extract_sfmt_ldc_sr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldcl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldc_sr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldcl_gbr_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + UINT f_rn; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldcl_gbr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldcl_vbr_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + UINT f_rn; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldcl_vbr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1526,12 +4405,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_fpscr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1543,12 +4429,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_fpscr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1560,12 +4454,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_fpul_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_fpul) = 32; + } +#endif #undef FLD return idesc; } @@ -1577,12 +4479,21 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_fpul_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_fpul) = 32; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1594,12 +4505,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_mach_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1611,12 +4529,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_mach_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1628,12 +4554,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_macl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1645,12 +4578,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_macl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1662,12 +4603,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_pr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1679,12 +4627,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_pr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1693,18 +4649,28 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macl_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + FLD (out_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1713,18 +4679,28 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macw_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + FLD (out_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1733,18 +4709,26 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm64) = f_rm; + FLD (out_rn64) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1757,14 +4741,52 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_rn; UINT f_imm8; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_imm8) = f_imm8; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movi_compact", "f_imm8 0x%x", 'x', f_imm8, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movi20_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movi20_compact.f + UINT f_rn; + INT f_imm20_hi; + UINT f_imm20_lo; + INT f_imm20; + + f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_imm20_hi = EXTRACT_MSB0_INT (insn, 32, 8, 4); + f_imm20_lo = EXTRACT_MSB0_UINT (insn, 32, 16, 16); + f_imm20 = ((((f_imm20_hi) << (16))) | (f_imm20_lo)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm20) = f_imm20; + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movi20_compact", "f_imm20 0x%x", 'x', f_imm20, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1773,18 +4795,26 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb1_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1793,18 +4823,27 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb2_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1813,18 +4852,27 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb3_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1836,12 +4884,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; - f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); + f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_imm8) = f_imm8; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb4_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + } +#endif #undef FLD return idesc; } @@ -1854,14 +4909,22 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_rm; UINT f_imm4; - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); - f_imm4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + f_imm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (f_imm4) = f_imm4; FLD (f_rm) = f_rm; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb5_compact", "f_imm4 0x%x", 'x', f_imm4, "f_rm 0x%x", 'x', f_rm, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + FLD (in_rm) = f_rm; + } +#endif #undef FLD return idesc; } @@ -1870,18 +4933,26 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb6_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1890,18 +4961,27 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb7_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (out_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1910,18 +4990,27 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb8_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + FLD (in_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1933,12 +5022,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; - f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); + f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_imm8) = f_imm8; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb9_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_r0) = 0; + } +#endif #undef FLD return idesc; } @@ -1951,14 +5047,108 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_rm; UINT f_imm4; - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); - f_imm4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + f_imm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); /* Record the fields for the semantic handler. */ FLD (f_imm4) = f_imm4; FLD (f_rm) = f_rm; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb10_compact", "f_imm4 0x%x", 'x', f_imm4, "f_rm 0x%x", 'x', f_rm, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (out_r0) = 0; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movl1_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + UINT f_rn; + UINT f_rm; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rm) = f_rm; + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl1_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movl2_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + UINT f_rn; + UINT f_rm; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rm) = f_rm; + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl2_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movl3_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + UINT f_rn; + UINT f_rm; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rm) = f_rm; + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl3_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -1970,12 +5160,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movl10_compact.f SI f_imm8x4; - f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2)); + f_imm8x4 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_imm8x4) = f_imm8x4; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl4_compact", "f_imm8x4 0x%x", 'x', f_imm8x4, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + } +#endif #undef FLD return idesc; } @@ -1989,9 +5186,9 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_rm; SI f_imm4x4; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); - f_imm4x4 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (2)); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + f_imm4x4 = ((EXTRACT_MSB0_UINT (insn, 16, 12, 4)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_imm4x4) = f_imm4x4; @@ -1999,6 +5196,42 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl5_compact", "f_imm4x4 0x%x", 'x', f_imm4x4, "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movl6_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + UINT f_rn; + UINT f_rm; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rm) = f_rm; + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl6_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2007,18 +5240,57 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl7_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + FLD (out_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movl8_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + UINT f_rn; + UINT f_rm; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rm) = f_rm; + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl8_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + FLD (in_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2030,12 +5302,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movl10_compact.f SI f_imm8x4; - f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2)); + f_imm8x4 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_imm8x4) = f_imm8x4; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl9_compact", "f_imm8x4 0x%x", 'x', f_imm8x4, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_r0) = 0; + } +#endif #undef FLD return idesc; } @@ -2048,14 +5327,21 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_rn; SI f_imm8x4; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2)); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_imm8x4 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_imm8x4) = f_imm8x4; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl10_compact", "f_imm8x4 0x%x", 'x', f_imm8x4, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2069,9 +5355,9 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_rm; SI f_imm4x4; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); - f_imm4x4 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (2)); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + f_imm4x4 = ((EXTRACT_MSB0_UINT (insn, 16, 12, 4)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_imm4x4) = f_imm4x4; @@ -2079,6 +5365,162 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl11_compact", "f_imm4x4 0x%x", 'x', f_imm4x4, "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movl12_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + UINT f_rn; + UINT f_rm; + SI f_imm12x4; + + f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4); + f_imm12x4 = ((EXTRACT_MSB0_INT (insn, 32, 20, 12)) << (2)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm12x4) = f_imm12x4; + FLD (f_rm) = f_rm; + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl12_compact", "f_imm12x4 0x%x", 'x', f_imm12x4, "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movl13_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + UINT f_rn; + UINT f_rm; + SI f_imm12x4; + + f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4); + f_imm12x4 = ((EXTRACT_MSB0_INT (insn, 32, 20, 12)) << (2)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm12x4) = f_imm12x4; + FLD (f_rm) = f_rm; + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl13_compact", "f_imm12x4 0x%x", 'x', f_imm12x4, "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movw1_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + UINT f_rn; + UINT f_rm; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rm) = f_rm; + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw1_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movw2_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + UINT f_rn; + UINT f_rm; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rm) = f_rm; + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw2_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movw3_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + UINT f_rn; + UINT f_rm; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rm) = f_rm; + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw3_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2090,12 +5532,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f SI f_imm8x2; - f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1)); + f_imm8x2 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); /* Record the fields for the semantic handler. */ FLD (f_imm8x2) = f_imm8x2; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw4_compact", "f_imm8x2 0x%x", 'x', f_imm8x2, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + } +#endif #undef FLD return idesc; } @@ -2105,17 +5554,111 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw5_compact.f - UINT f_rn; + UINT f_rm; SI f_imm4x2; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_imm4x2 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + f_imm4x2 = ((EXTRACT_MSB0_UINT (insn, 16, 12, 4)) << (1)); /* Record the fields for the semantic handler. */ FLD (f_imm4x2) = f_imm4x2; + FLD (f_rm) = f_rm; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw5_compact", "f_imm4x2 0x%x", 'x', f_imm4x2, "f_rm 0x%x", 'x', f_rm, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + FLD (in_rm) = f_rm; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movw6_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + UINT f_rn; + UINT f_rm; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw5_compact", "f_imm4x2 0x%x", 'x', f_imm4x2, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw6_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movw7_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + UINT f_rn; + UINT f_rm; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rm) = f_rm; + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw7_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (out_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movw8_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + UINT f_rn; + UINT f_rm; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rm) = f_rm; + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw8_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + FLD (in_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2127,12 +5670,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f SI f_imm8x2; - f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1)); + f_imm8x2 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); /* Record the fields for the semantic handler. */ FLD (f_imm8x2) = f_imm8x2; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw9_compact", "f_imm8x2 0x%x", 'x', f_imm8x2, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_r0) = 0; + } +#endif #undef FLD return idesc; } @@ -2145,14 +5695,21 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_rn; SI f_imm8x2; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1)); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_imm8x2 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); /* Record the fields for the semantic handler. */ FLD (f_imm8x2) = f_imm8x2; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw10_compact", "f_imm8x2 0x%x", 'x', f_imm8x2, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2161,18 +5718,26 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movw11_compact.f +#define FLD(f) abuf->fields.sfmt_movw5_compact.f UINT f_rm; SI f_imm4x2; - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); - f_imm4x2 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); + f_imm4x2 = ((EXTRACT_MSB0_UINT (insn, 16, 12, 4)) << (1)); /* Record the fields for the semantic handler. */ FLD (f_imm4x2) = f_imm4x2; FLD (f_rm) = f_rm; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw11_compact", "f_imm4x2 0x%x", 'x', f_imm4x2, "f_rm 0x%x", 'x', f_rm, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (out_r0) = 0; + } +#endif #undef FLD return idesc; } @@ -2184,12 +5749,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movl10_compact.f SI f_imm8x4; - f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2)); + f_imm8x4 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); /* Record the fields for the semantic handler. */ FLD (f_imm8x4) = f_imm8x4; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mova_compact", "f_imm8x4 0x%x", 'x', f_imm8x4, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_r0) = 0; + } +#endif #undef FLD return idesc; } @@ -2201,12 +5773,45 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movcal_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + FLD (in_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movcol_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + UINT f_rn; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movcol_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2218,12 +5823,70 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movt_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movual_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + UINT f_rn; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movual_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_r0) = 0; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_movual2_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + UINT f_rn; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movual2_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_r0) = 0; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2232,18 +5895,26 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mull_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2252,18 +5923,26 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_negc_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2281,6 +5960,30 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, return idesc; } + extract_sfmt_pref_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + UINT f_rn; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_pref_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + extract_sfmt_rotcl_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; @@ -2288,12 +5991,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rotcl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2307,6 +6018,12 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rts_compact", (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif #undef FLD return idesc; } @@ -2315,52 +6032,75 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f UINT f_rn; UINT f_rm; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); /* Record the fields for the semantic handler. */ FLD (f_rm) = f_rm; FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shad_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_rm; + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } - extract_sfmt_shll2_compact: + extract_sfmt_stc_gbr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shll2_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stc_gbr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } - extract_sfmt_stc_gbr_compact: + extract_sfmt_stc_vbr_compact: { const IDESC *idesc = &sh64_compact_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stc_gbr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stc_vbr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2372,12 +6112,45 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stcl_gbr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stcl_vbr_compact: + { + const IDESC *idesc = &sh64_compact_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + UINT f_rn; + + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); + + /* Record the fields for the semantic handler. */ + FLD (f_rn) = f_rn; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stcl_vbr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2389,12 +6162,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_fpscr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2406,12 +6186,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_fpscr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2423,12 +6211,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_fpul_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fpul) = 32; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2440,12 +6236,21 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_fpul_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fpul) = 32; + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2457,12 +6262,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_mach_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2474,12 +6286,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_mach_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2491,12 +6311,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_macl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2508,12 +6335,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_macl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2525,12 +6360,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_pr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2542,12 +6384,20 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_pr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + FLD (out_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2559,12 +6409,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_movw10_compact.f UINT f_rn; - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); /* Record the fields for the semantic handler. */ FLD (f_rn) = f_rn; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tasb_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_rn; + } +#endif #undef FLD return idesc; } @@ -2576,12 +6433,18 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; - f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); + f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_imm8) = f_imm8; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trapa_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif #undef FLD return idesc; } @@ -2593,12 +6456,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; - f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); + f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_imm8) = f_imm8; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tsti_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + } +#endif #undef FLD return idesc; } @@ -2610,29 +6480,19 @@ sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_addi_compact.f UINT f_imm8; - f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); + f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); /* Record the fields for the semantic handler. */ FLD (f_imm8) = f_imm8; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tstb_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0)); -#undef FLD - return idesc; - } - - extract_sfmt_xori_compact: - { - const IDESC *idesc = &sh64_compact_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_addi_compact.f - UINT f_imm8; - - f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); - - /* Record the fields for the semantic handler. */ - FLD (f_imm8) = f_imm8; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xori_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0)); - +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_r0) = 0; + } +#endif #undef FLD return idesc; } diff --git a/sim/sh64/decode-compact.h b/sim/sh64/decode-compact.h index 8ca92a9..86ff47a 100644 --- a/sim/sh64/decode-compact.h +++ b/sim/sh64/decode-compact.h @@ -2,9 +2,9 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -43,82 +43,234 @@ typedef enum sh64_compact_insn_type { , SH64_COMPACT_INSN_CLRT_COMPACT, SH64_COMPACT_INSN_CMPEQ_COMPACT, SH64_COMPACT_INSN_CMPEQI_COMPACT, SH64_COMPACT_INSN_CMPGE_COMPACT , SH64_COMPACT_INSN_CMPGT_COMPACT, SH64_COMPACT_INSN_CMPHI_COMPACT, SH64_COMPACT_INSN_CMPHS_COMPACT, SH64_COMPACT_INSN_CMPPL_COMPACT , SH64_COMPACT_INSN_CMPPZ_COMPACT, SH64_COMPACT_INSN_CMPSTR_COMPACT, SH64_COMPACT_INSN_DIV0S_COMPACT, SH64_COMPACT_INSN_DIV0U_COMPACT - , SH64_COMPACT_INSN_DIV1_COMPACT, SH64_COMPACT_INSN_DMULSL_COMPACT, SH64_COMPACT_INSN_DMULUL_COMPACT, SH64_COMPACT_INSN_DT_COMPACT - , SH64_COMPACT_INSN_EXTSB_COMPACT, SH64_COMPACT_INSN_EXTSW_COMPACT, SH64_COMPACT_INSN_EXTUB_COMPACT, SH64_COMPACT_INSN_EXTUW_COMPACT - , SH64_COMPACT_INSN_FABS_COMPACT, SH64_COMPACT_INSN_FADD_COMPACT, SH64_COMPACT_INSN_FCMPEQ_COMPACT, SH64_COMPACT_INSN_FCMPGT_COMPACT - , SH64_COMPACT_INSN_FCNVDS_COMPACT, SH64_COMPACT_INSN_FCNVSD_COMPACT, SH64_COMPACT_INSN_FDIV_COMPACT, SH64_COMPACT_INSN_FIPR_COMPACT - , SH64_COMPACT_INSN_FLDS_COMPACT, SH64_COMPACT_INSN_FLDI0_COMPACT, SH64_COMPACT_INSN_FLDI1_COMPACT, SH64_COMPACT_INSN_FLOAT_COMPACT - , SH64_COMPACT_INSN_FMAC_COMPACT, SH64_COMPACT_INSN_FMOV1_COMPACT, SH64_COMPACT_INSN_FMOV2_COMPACT, SH64_COMPACT_INSN_FMOV3_COMPACT - , SH64_COMPACT_INSN_FMOV4_COMPACT, SH64_COMPACT_INSN_FMOV5_COMPACT, SH64_COMPACT_INSN_FMOV6_COMPACT, SH64_COMPACT_INSN_FMOV7_COMPACT + , SH64_COMPACT_INSN_DIV1_COMPACT, SH64_COMPACT_INSN_DIVU_COMPACT, SH64_COMPACT_INSN_MULR_COMPACT, SH64_COMPACT_INSN_DMULSL_COMPACT + , SH64_COMPACT_INSN_DMULUL_COMPACT, SH64_COMPACT_INSN_DT_COMPACT, SH64_COMPACT_INSN_EXTSB_COMPACT, SH64_COMPACT_INSN_EXTSW_COMPACT + , SH64_COMPACT_INSN_EXTUB_COMPACT, SH64_COMPACT_INSN_EXTUW_COMPACT, SH64_COMPACT_INSN_FABS_COMPACT, SH64_COMPACT_INSN_FADD_COMPACT + , SH64_COMPACT_INSN_FCMPEQ_COMPACT, SH64_COMPACT_INSN_FCMPGT_COMPACT, SH64_COMPACT_INSN_FCNVDS_COMPACT, SH64_COMPACT_INSN_FCNVSD_COMPACT + , SH64_COMPACT_INSN_FDIV_COMPACT, SH64_COMPACT_INSN_FIPR_COMPACT, SH64_COMPACT_INSN_FLDS_COMPACT, SH64_COMPACT_INSN_FLDI0_COMPACT + , SH64_COMPACT_INSN_FLDI1_COMPACT, SH64_COMPACT_INSN_FLOAT_COMPACT, SH64_COMPACT_INSN_FMAC_COMPACT, SH64_COMPACT_INSN_FMOV1_COMPACT + , SH64_COMPACT_INSN_FMOV2_COMPACT, SH64_COMPACT_INSN_FMOV3_COMPACT, SH64_COMPACT_INSN_FMOV4_COMPACT, SH64_COMPACT_INSN_FMOV5_COMPACT + , SH64_COMPACT_INSN_FMOV6_COMPACT, SH64_COMPACT_INSN_FMOV7_COMPACT, SH64_COMPACT_INSN_FMOV8_COMPACT, SH64_COMPACT_INSN_FMOV9_COMPACT , SH64_COMPACT_INSN_FMUL_COMPACT, SH64_COMPACT_INSN_FNEG_COMPACT, SH64_COMPACT_INSN_FRCHG_COMPACT, SH64_COMPACT_INSN_FSCHG_COMPACT , SH64_COMPACT_INSN_FSQRT_COMPACT, SH64_COMPACT_INSN_FSTS_COMPACT, SH64_COMPACT_INSN_FSUB_COMPACT, SH64_COMPACT_INSN_FTRC_COMPACT - , SH64_COMPACT_INSN_FTRV_COMPACT, SH64_COMPACT_INSN_JMP_COMPACT, SH64_COMPACT_INSN_JSR_COMPACT, SH64_COMPACT_INSN_LDC_COMPACT - , SH64_COMPACT_INSN_LDCL_COMPACT, SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, SH64_COMPACT_INSN_LDS_FPUL_COMPACT - , SH64_COMPACT_INSN_LDSL_FPUL_COMPACT, SH64_COMPACT_INSN_LDS_MACH_COMPACT, SH64_COMPACT_INSN_LDSL_MACH_COMPACT, SH64_COMPACT_INSN_LDS_MACL_COMPACT - , SH64_COMPACT_INSN_LDSL_MACL_COMPACT, SH64_COMPACT_INSN_LDS_PR_COMPACT, SH64_COMPACT_INSN_LDSL_PR_COMPACT, SH64_COMPACT_INSN_MACL_COMPACT - , SH64_COMPACT_INSN_MACW_COMPACT, SH64_COMPACT_INSN_MOV_COMPACT, SH64_COMPACT_INSN_MOVI_COMPACT, SH64_COMPACT_INSN_MOVB1_COMPACT + , SH64_COMPACT_INSN_FTRV_COMPACT, SH64_COMPACT_INSN_JMP_COMPACT, SH64_COMPACT_INSN_JSR_COMPACT, SH64_COMPACT_INSN_LDC_GBR_COMPACT + , SH64_COMPACT_INSN_LDC_VBR_COMPACT, SH64_COMPACT_INSN_LDC_SR_COMPACT, SH64_COMPACT_INSN_LDCL_GBR_COMPACT, SH64_COMPACT_INSN_LDCL_VBR_COMPACT + , SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, SH64_COMPACT_INSN_LDS_FPUL_COMPACT, SH64_COMPACT_INSN_LDSL_FPUL_COMPACT + , SH64_COMPACT_INSN_LDS_MACH_COMPACT, SH64_COMPACT_INSN_LDSL_MACH_COMPACT, SH64_COMPACT_INSN_LDS_MACL_COMPACT, SH64_COMPACT_INSN_LDSL_MACL_COMPACT + , SH64_COMPACT_INSN_LDS_PR_COMPACT, SH64_COMPACT_INSN_LDSL_PR_COMPACT, SH64_COMPACT_INSN_MACL_COMPACT, SH64_COMPACT_INSN_MACW_COMPACT + , SH64_COMPACT_INSN_MOV_COMPACT, SH64_COMPACT_INSN_MOVI_COMPACT, SH64_COMPACT_INSN_MOVI20_COMPACT, SH64_COMPACT_INSN_MOVB1_COMPACT , SH64_COMPACT_INSN_MOVB2_COMPACT, SH64_COMPACT_INSN_MOVB3_COMPACT, SH64_COMPACT_INSN_MOVB4_COMPACT, SH64_COMPACT_INSN_MOVB5_COMPACT , SH64_COMPACT_INSN_MOVB6_COMPACT, SH64_COMPACT_INSN_MOVB7_COMPACT, SH64_COMPACT_INSN_MOVB8_COMPACT, SH64_COMPACT_INSN_MOVB9_COMPACT , SH64_COMPACT_INSN_MOVB10_COMPACT, SH64_COMPACT_INSN_MOVL1_COMPACT, SH64_COMPACT_INSN_MOVL2_COMPACT, SH64_COMPACT_INSN_MOVL3_COMPACT , SH64_COMPACT_INSN_MOVL4_COMPACT, SH64_COMPACT_INSN_MOVL5_COMPACT, SH64_COMPACT_INSN_MOVL6_COMPACT, SH64_COMPACT_INSN_MOVL7_COMPACT , SH64_COMPACT_INSN_MOVL8_COMPACT, SH64_COMPACT_INSN_MOVL9_COMPACT, SH64_COMPACT_INSN_MOVL10_COMPACT, SH64_COMPACT_INSN_MOVL11_COMPACT - , SH64_COMPACT_INSN_MOVW1_COMPACT, SH64_COMPACT_INSN_MOVW2_COMPACT, SH64_COMPACT_INSN_MOVW3_COMPACT, SH64_COMPACT_INSN_MOVW4_COMPACT - , SH64_COMPACT_INSN_MOVW5_COMPACT, SH64_COMPACT_INSN_MOVW6_COMPACT, SH64_COMPACT_INSN_MOVW7_COMPACT, SH64_COMPACT_INSN_MOVW8_COMPACT - , SH64_COMPACT_INSN_MOVW9_COMPACT, SH64_COMPACT_INSN_MOVW10_COMPACT, SH64_COMPACT_INSN_MOVW11_COMPACT, SH64_COMPACT_INSN_MOVA_COMPACT - , SH64_COMPACT_INSN_MOVCAL_COMPACT, SH64_COMPACT_INSN_MOVT_COMPACT, SH64_COMPACT_INSN_MULL_COMPACT, SH64_COMPACT_INSN_MULSW_COMPACT - , SH64_COMPACT_INSN_MULUW_COMPACT, SH64_COMPACT_INSN_NEG_COMPACT, SH64_COMPACT_INSN_NEGC_COMPACT, SH64_COMPACT_INSN_NOP_COMPACT - , SH64_COMPACT_INSN_NOT_COMPACT, SH64_COMPACT_INSN_OCBI_COMPACT, SH64_COMPACT_INSN_OCBP_COMPACT, SH64_COMPACT_INSN_OCBWB_COMPACT - , SH64_COMPACT_INSN_OR_COMPACT, SH64_COMPACT_INSN_ORI_COMPACT, SH64_COMPACT_INSN_ORB_COMPACT, SH64_COMPACT_INSN_PREF_COMPACT - , SH64_COMPACT_INSN_ROTCL_COMPACT, SH64_COMPACT_INSN_ROTCR_COMPACT, SH64_COMPACT_INSN_ROTL_COMPACT, SH64_COMPACT_INSN_ROTR_COMPACT - , SH64_COMPACT_INSN_RTS_COMPACT, SH64_COMPACT_INSN_SETS_COMPACT, SH64_COMPACT_INSN_SETT_COMPACT, SH64_COMPACT_INSN_SHAD_COMPACT - , SH64_COMPACT_INSN_SHAL_COMPACT, SH64_COMPACT_INSN_SHAR_COMPACT, SH64_COMPACT_INSN_SHLD_COMPACT, SH64_COMPACT_INSN_SHLL_COMPACT - , SH64_COMPACT_INSN_SHLL2_COMPACT, SH64_COMPACT_INSN_SHLL8_COMPACT, SH64_COMPACT_INSN_SHLL16_COMPACT, SH64_COMPACT_INSN_SHLR_COMPACT - , SH64_COMPACT_INSN_SHLR2_COMPACT, SH64_COMPACT_INSN_SHLR8_COMPACT, SH64_COMPACT_INSN_SHLR16_COMPACT, SH64_COMPACT_INSN_STC_GBR_COMPACT - , SH64_COMPACT_INSN_STCL_GBR_COMPACT, SH64_COMPACT_INSN_STS_FPSCR_COMPACT, SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, SH64_COMPACT_INSN_STS_FPUL_COMPACT - , SH64_COMPACT_INSN_STSL_FPUL_COMPACT, SH64_COMPACT_INSN_STS_MACH_COMPACT, SH64_COMPACT_INSN_STSL_MACH_COMPACT, SH64_COMPACT_INSN_STS_MACL_COMPACT - , SH64_COMPACT_INSN_STSL_MACL_COMPACT, SH64_COMPACT_INSN_STS_PR_COMPACT, SH64_COMPACT_INSN_STSL_PR_COMPACT, SH64_COMPACT_INSN_SUB_COMPACT - , SH64_COMPACT_INSN_SUBC_COMPACT, SH64_COMPACT_INSN_SUBV_COMPACT, SH64_COMPACT_INSN_SWAPB_COMPACT, SH64_COMPACT_INSN_SWAPW_COMPACT - , SH64_COMPACT_INSN_TASB_COMPACT, SH64_COMPACT_INSN_TRAPA_COMPACT, SH64_COMPACT_INSN_TST_COMPACT, SH64_COMPACT_INSN_TSTI_COMPACT - , SH64_COMPACT_INSN_TSTB_COMPACT, SH64_COMPACT_INSN_XOR_COMPACT, SH64_COMPACT_INSN_XORI_COMPACT, SH64_COMPACT_INSN_XORB_COMPACT - , SH64_COMPACT_INSN_XTRCT_COMPACT, SH64_COMPACT_INSN_MAX + , SH64_COMPACT_INSN_MOVL12_COMPACT, SH64_COMPACT_INSN_MOVL13_COMPACT, SH64_COMPACT_INSN_MOVW1_COMPACT, SH64_COMPACT_INSN_MOVW2_COMPACT + , SH64_COMPACT_INSN_MOVW3_COMPACT, SH64_COMPACT_INSN_MOVW4_COMPACT, SH64_COMPACT_INSN_MOVW5_COMPACT, SH64_COMPACT_INSN_MOVW6_COMPACT + , SH64_COMPACT_INSN_MOVW7_COMPACT, SH64_COMPACT_INSN_MOVW8_COMPACT, SH64_COMPACT_INSN_MOVW9_COMPACT, SH64_COMPACT_INSN_MOVW10_COMPACT + , SH64_COMPACT_INSN_MOVW11_COMPACT, SH64_COMPACT_INSN_MOVA_COMPACT, SH64_COMPACT_INSN_MOVCAL_COMPACT, SH64_COMPACT_INSN_MOVCOL_COMPACT + , SH64_COMPACT_INSN_MOVT_COMPACT, SH64_COMPACT_INSN_MOVUAL_COMPACT, SH64_COMPACT_INSN_MOVUAL2_COMPACT, SH64_COMPACT_INSN_MULL_COMPACT + , SH64_COMPACT_INSN_MULSW_COMPACT, SH64_COMPACT_INSN_MULUW_COMPACT, SH64_COMPACT_INSN_NEG_COMPACT, SH64_COMPACT_INSN_NEGC_COMPACT + , SH64_COMPACT_INSN_NOP_COMPACT, SH64_COMPACT_INSN_NOT_COMPACT, SH64_COMPACT_INSN_OCBI_COMPACT, SH64_COMPACT_INSN_OCBP_COMPACT + , SH64_COMPACT_INSN_OCBWB_COMPACT, SH64_COMPACT_INSN_OR_COMPACT, SH64_COMPACT_INSN_ORI_COMPACT, SH64_COMPACT_INSN_ORB_COMPACT + , SH64_COMPACT_INSN_PREF_COMPACT, SH64_COMPACT_INSN_ROTCL_COMPACT, SH64_COMPACT_INSN_ROTCR_COMPACT, SH64_COMPACT_INSN_ROTL_COMPACT + , SH64_COMPACT_INSN_ROTR_COMPACT, SH64_COMPACT_INSN_RTS_COMPACT, SH64_COMPACT_INSN_SETS_COMPACT, SH64_COMPACT_INSN_SETT_COMPACT + , SH64_COMPACT_INSN_SHAD_COMPACT, SH64_COMPACT_INSN_SHAL_COMPACT, SH64_COMPACT_INSN_SHAR_COMPACT, SH64_COMPACT_INSN_SHLD_COMPACT + , SH64_COMPACT_INSN_SHLL_COMPACT, SH64_COMPACT_INSN_SHLL2_COMPACT, SH64_COMPACT_INSN_SHLL8_COMPACT, SH64_COMPACT_INSN_SHLL16_COMPACT + , SH64_COMPACT_INSN_SHLR_COMPACT, SH64_COMPACT_INSN_SHLR2_COMPACT, SH64_COMPACT_INSN_SHLR8_COMPACT, SH64_COMPACT_INSN_SHLR16_COMPACT + , SH64_COMPACT_INSN_STC_GBR_COMPACT, SH64_COMPACT_INSN_STC_VBR_COMPACT, SH64_COMPACT_INSN_STCL_GBR_COMPACT, SH64_COMPACT_INSN_STCL_VBR_COMPACT + , SH64_COMPACT_INSN_STS_FPSCR_COMPACT, SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, SH64_COMPACT_INSN_STS_FPUL_COMPACT, SH64_COMPACT_INSN_STSL_FPUL_COMPACT + , SH64_COMPACT_INSN_STS_MACH_COMPACT, SH64_COMPACT_INSN_STSL_MACH_COMPACT, SH64_COMPACT_INSN_STS_MACL_COMPACT, SH64_COMPACT_INSN_STSL_MACL_COMPACT + , SH64_COMPACT_INSN_STS_PR_COMPACT, SH64_COMPACT_INSN_STSL_PR_COMPACT, SH64_COMPACT_INSN_SUB_COMPACT, SH64_COMPACT_INSN_SUBC_COMPACT + , SH64_COMPACT_INSN_SUBV_COMPACT, SH64_COMPACT_INSN_SWAPB_COMPACT, SH64_COMPACT_INSN_SWAPW_COMPACT, SH64_COMPACT_INSN_TASB_COMPACT + , SH64_COMPACT_INSN_TRAPA_COMPACT, SH64_COMPACT_INSN_TST_COMPACT, SH64_COMPACT_INSN_TSTI_COMPACT, SH64_COMPACT_INSN_TSTB_COMPACT + , SH64_COMPACT_INSN_XOR_COMPACT, SH64_COMPACT_INSN_XORI_COMPACT, SH64_COMPACT_INSN_XORB_COMPACT, SH64_COMPACT_INSN_XTRCT_COMPACT + , SH64_COMPACT_INSN__MAX } SH64_COMPACT_INSN_TYPE; /* Enum declaration for semantic formats in cpu family sh64. */ typedef enum sh64_compact_sfmt_type { SH64_COMPACT_SFMT_EMPTY, SH64_COMPACT_SFMT_ADD_COMPACT, SH64_COMPACT_SFMT_ADDI_COMPACT, SH64_COMPACT_SFMT_ADDC_COMPACT , SH64_COMPACT_SFMT_ADDV_COMPACT, SH64_COMPACT_SFMT_AND_COMPACT, SH64_COMPACT_SFMT_ANDI_COMPACT, SH64_COMPACT_SFMT_ANDB_COMPACT - , SH64_COMPACT_SFMT_BF_COMPACT, SH64_COMPACT_SFMT_BRA_COMPACT, SH64_COMPACT_SFMT_BRAF_COMPACT, SH64_COMPACT_SFMT_BRK_COMPACT - , SH64_COMPACT_SFMT_BSR_COMPACT, SH64_COMPACT_SFMT_BSRF_COMPACT, SH64_COMPACT_SFMT_CLRMAC_COMPACT, SH64_COMPACT_SFMT_CLRS_COMPACT - , SH64_COMPACT_SFMT_CLRT_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT, SH64_COMPACT_SFMT_CMPEQI_COMPACT, SH64_COMPACT_SFMT_CMPPL_COMPACT - , SH64_COMPACT_SFMT_DIV0S_COMPACT, SH64_COMPACT_SFMT_DIV0U_COMPACT, SH64_COMPACT_SFMT_DIV1_COMPACT, SH64_COMPACT_SFMT_DMULSL_COMPACT - , SH64_COMPACT_SFMT_DT_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT, SH64_COMPACT_SFMT_FABS_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT - , SH64_COMPACT_SFMT_FCMPEQ_COMPACT, SH64_COMPACT_SFMT_FCNVDS_COMPACT, SH64_COMPACT_SFMT_FCNVSD_COMPACT, SH64_COMPACT_SFMT_FIPR_COMPACT - , SH64_COMPACT_SFMT_FLDS_COMPACT, SH64_COMPACT_SFMT_FLDI0_COMPACT, SH64_COMPACT_SFMT_FLOAT_COMPACT, SH64_COMPACT_SFMT_FMAC_COMPACT - , SH64_COMPACT_SFMT_FMOV1_COMPACT, SH64_COMPACT_SFMT_FMOV2_COMPACT, SH64_COMPACT_SFMT_FMOV3_COMPACT, SH64_COMPACT_SFMT_FMOV4_COMPACT - , SH64_COMPACT_SFMT_FMOV5_COMPACT, SH64_COMPACT_SFMT_FMOV6_COMPACT, SH64_COMPACT_SFMT_FMOV7_COMPACT, SH64_COMPACT_SFMT_FRCHG_COMPACT + , SH64_COMPACT_SFMT_BF_COMPACT, SH64_COMPACT_SFMT_BFS_COMPACT, SH64_COMPACT_SFMT_BRA_COMPACT, SH64_COMPACT_SFMT_BRAF_COMPACT + , SH64_COMPACT_SFMT_BRK_COMPACT, SH64_COMPACT_SFMT_BSR_COMPACT, SH64_COMPACT_SFMT_BSRF_COMPACT, SH64_COMPACT_SFMT_CLRMAC_COMPACT + , SH64_COMPACT_SFMT_CLRS_COMPACT, SH64_COMPACT_SFMT_CLRT_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT, SH64_COMPACT_SFMT_CMPEQI_COMPACT + , SH64_COMPACT_SFMT_CMPPL_COMPACT, SH64_COMPACT_SFMT_DIV0S_COMPACT, SH64_COMPACT_SFMT_DIV0U_COMPACT, SH64_COMPACT_SFMT_DIV1_COMPACT + , SH64_COMPACT_SFMT_DIVU_COMPACT, SH64_COMPACT_SFMT_DMULSL_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT + , SH64_COMPACT_SFMT_FABS_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT, SH64_COMPACT_SFMT_FCMPEQ_COMPACT, SH64_COMPACT_SFMT_FCNVDS_COMPACT + , SH64_COMPACT_SFMT_FCNVSD_COMPACT, SH64_COMPACT_SFMT_FIPR_COMPACT, SH64_COMPACT_SFMT_FLDS_COMPACT, SH64_COMPACT_SFMT_FLDI0_COMPACT + , SH64_COMPACT_SFMT_FLOAT_COMPACT, SH64_COMPACT_SFMT_FMAC_COMPACT, SH64_COMPACT_SFMT_FMOV1_COMPACT, SH64_COMPACT_SFMT_FMOV2_COMPACT + , SH64_COMPACT_SFMT_FMOV3_COMPACT, SH64_COMPACT_SFMT_FMOV4_COMPACT, SH64_COMPACT_SFMT_FMOV5_COMPACT, SH64_COMPACT_SFMT_FMOV6_COMPACT + , SH64_COMPACT_SFMT_FMOV7_COMPACT, SH64_COMPACT_SFMT_FMOV8_COMPACT, SH64_COMPACT_SFMT_FMOV9_COMPACT, SH64_COMPACT_SFMT_FRCHG_COMPACT , SH64_COMPACT_SFMT_FSCHG_COMPACT, SH64_COMPACT_SFMT_FSTS_COMPACT, SH64_COMPACT_SFMT_FTRC_COMPACT, SH64_COMPACT_SFMT_FTRV_COMPACT - , SH64_COMPACT_SFMT_JMP_COMPACT, SH64_COMPACT_SFMT_LDC_COMPACT, SH64_COMPACT_SFMT_LDCL_COMPACT, SH64_COMPACT_SFMT_LDS_FPSCR_COMPACT - , SH64_COMPACT_SFMT_LDSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDS_FPUL_COMPACT, SH64_COMPACT_SFMT_LDSL_FPUL_COMPACT, SH64_COMPACT_SFMT_LDS_MACH_COMPACT - , SH64_COMPACT_SFMT_LDSL_MACH_COMPACT, SH64_COMPACT_SFMT_LDS_MACL_COMPACT, SH64_COMPACT_SFMT_LDSL_MACL_COMPACT, SH64_COMPACT_SFMT_LDS_PR_COMPACT - , SH64_COMPACT_SFMT_LDSL_PR_COMPACT, SH64_COMPACT_SFMT_MACL_COMPACT, SH64_COMPACT_SFMT_MACW_COMPACT, SH64_COMPACT_SFMT_MOV_COMPACT - , SH64_COMPACT_SFMT_MOVI_COMPACT, SH64_COMPACT_SFMT_MOVB1_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT - , SH64_COMPACT_SFMT_MOVB4_COMPACT, SH64_COMPACT_SFMT_MOVB5_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT, SH64_COMPACT_SFMT_MOVB7_COMPACT - , SH64_COMPACT_SFMT_MOVB8_COMPACT, SH64_COMPACT_SFMT_MOVB9_COMPACT, SH64_COMPACT_SFMT_MOVB10_COMPACT, SH64_COMPACT_SFMT_MOVL4_COMPACT - , SH64_COMPACT_SFMT_MOVL5_COMPACT, SH64_COMPACT_SFMT_MOVL7_COMPACT, SH64_COMPACT_SFMT_MOVL9_COMPACT, SH64_COMPACT_SFMT_MOVL10_COMPACT - , SH64_COMPACT_SFMT_MOVL11_COMPACT, SH64_COMPACT_SFMT_MOVW4_COMPACT, SH64_COMPACT_SFMT_MOVW5_COMPACT, SH64_COMPACT_SFMT_MOVW9_COMPACT + , SH64_COMPACT_SFMT_LDC_GBR_COMPACT, SH64_COMPACT_SFMT_LDC_VBR_COMPACT, SH64_COMPACT_SFMT_LDC_SR_COMPACT, SH64_COMPACT_SFMT_LDCL_GBR_COMPACT + , SH64_COMPACT_SFMT_LDCL_VBR_COMPACT, SH64_COMPACT_SFMT_LDS_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDS_FPUL_COMPACT + , SH64_COMPACT_SFMT_LDSL_FPUL_COMPACT, SH64_COMPACT_SFMT_LDS_MACH_COMPACT, SH64_COMPACT_SFMT_LDSL_MACH_COMPACT, SH64_COMPACT_SFMT_LDS_MACL_COMPACT + , SH64_COMPACT_SFMT_LDSL_MACL_COMPACT, SH64_COMPACT_SFMT_LDS_PR_COMPACT, SH64_COMPACT_SFMT_LDSL_PR_COMPACT, SH64_COMPACT_SFMT_MACL_COMPACT + , SH64_COMPACT_SFMT_MACW_COMPACT, SH64_COMPACT_SFMT_MOV_COMPACT, SH64_COMPACT_SFMT_MOVI_COMPACT, SH64_COMPACT_SFMT_MOVI20_COMPACT + , SH64_COMPACT_SFMT_MOVB1_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT, SH64_COMPACT_SFMT_MOVB4_COMPACT + , SH64_COMPACT_SFMT_MOVB5_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT, SH64_COMPACT_SFMT_MOVB7_COMPACT, SH64_COMPACT_SFMT_MOVB8_COMPACT + , SH64_COMPACT_SFMT_MOVB9_COMPACT, SH64_COMPACT_SFMT_MOVB10_COMPACT, SH64_COMPACT_SFMT_MOVL1_COMPACT, SH64_COMPACT_SFMT_MOVL2_COMPACT + , SH64_COMPACT_SFMT_MOVL3_COMPACT, SH64_COMPACT_SFMT_MOVL4_COMPACT, SH64_COMPACT_SFMT_MOVL5_COMPACT, SH64_COMPACT_SFMT_MOVL6_COMPACT + , SH64_COMPACT_SFMT_MOVL7_COMPACT, SH64_COMPACT_SFMT_MOVL8_COMPACT, SH64_COMPACT_SFMT_MOVL9_COMPACT, SH64_COMPACT_SFMT_MOVL10_COMPACT + , SH64_COMPACT_SFMT_MOVL11_COMPACT, SH64_COMPACT_SFMT_MOVL12_COMPACT, SH64_COMPACT_SFMT_MOVL13_COMPACT, SH64_COMPACT_SFMT_MOVW1_COMPACT + , SH64_COMPACT_SFMT_MOVW2_COMPACT, SH64_COMPACT_SFMT_MOVW3_COMPACT, SH64_COMPACT_SFMT_MOVW4_COMPACT, SH64_COMPACT_SFMT_MOVW5_COMPACT + , SH64_COMPACT_SFMT_MOVW6_COMPACT, SH64_COMPACT_SFMT_MOVW7_COMPACT, SH64_COMPACT_SFMT_MOVW8_COMPACT, SH64_COMPACT_SFMT_MOVW9_COMPACT , SH64_COMPACT_SFMT_MOVW10_COMPACT, SH64_COMPACT_SFMT_MOVW11_COMPACT, SH64_COMPACT_SFMT_MOVA_COMPACT, SH64_COMPACT_SFMT_MOVCAL_COMPACT - , SH64_COMPACT_SFMT_MOVT_COMPACT, SH64_COMPACT_SFMT_MULL_COMPACT, SH64_COMPACT_SFMT_NEGC_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT - , SH64_COMPACT_SFMT_ROTCL_COMPACT, SH64_COMPACT_SFMT_RTS_COMPACT, SH64_COMPACT_SFMT_SHAD_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT - , SH64_COMPACT_SFMT_STC_GBR_COMPACT, SH64_COMPACT_SFMT_STCL_GBR_COMPACT, SH64_COMPACT_SFMT_STS_FPSCR_COMPACT, SH64_COMPACT_SFMT_STSL_FPSCR_COMPACT - , SH64_COMPACT_SFMT_STS_FPUL_COMPACT, SH64_COMPACT_SFMT_STSL_FPUL_COMPACT, SH64_COMPACT_SFMT_STS_MACH_COMPACT, SH64_COMPACT_SFMT_STSL_MACH_COMPACT - , SH64_COMPACT_SFMT_STS_MACL_COMPACT, SH64_COMPACT_SFMT_STSL_MACL_COMPACT, SH64_COMPACT_SFMT_STS_PR_COMPACT, SH64_COMPACT_SFMT_STSL_PR_COMPACT - , SH64_COMPACT_SFMT_TASB_COMPACT, SH64_COMPACT_SFMT_TRAPA_COMPACT, SH64_COMPACT_SFMT_TSTI_COMPACT, SH64_COMPACT_SFMT_TSTB_COMPACT - , SH64_COMPACT_SFMT_XORI_COMPACT + , SH64_COMPACT_SFMT_MOVCOL_COMPACT, SH64_COMPACT_SFMT_MOVT_COMPACT, SH64_COMPACT_SFMT_MOVUAL_COMPACT, SH64_COMPACT_SFMT_MOVUAL2_COMPACT + , SH64_COMPACT_SFMT_MULL_COMPACT, SH64_COMPACT_SFMT_NEGC_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT, SH64_COMPACT_SFMT_PREF_COMPACT + , SH64_COMPACT_SFMT_ROTCL_COMPACT, SH64_COMPACT_SFMT_RTS_COMPACT, SH64_COMPACT_SFMT_SHAD_COMPACT, SH64_COMPACT_SFMT_STC_GBR_COMPACT + , SH64_COMPACT_SFMT_STC_VBR_COMPACT, SH64_COMPACT_SFMT_STCL_GBR_COMPACT, SH64_COMPACT_SFMT_STCL_VBR_COMPACT, SH64_COMPACT_SFMT_STS_FPSCR_COMPACT + , SH64_COMPACT_SFMT_STSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_STS_FPUL_COMPACT, SH64_COMPACT_SFMT_STSL_FPUL_COMPACT, SH64_COMPACT_SFMT_STS_MACH_COMPACT + , SH64_COMPACT_SFMT_STSL_MACH_COMPACT, SH64_COMPACT_SFMT_STS_MACL_COMPACT, SH64_COMPACT_SFMT_STSL_MACL_COMPACT, SH64_COMPACT_SFMT_STS_PR_COMPACT + , SH64_COMPACT_SFMT_STSL_PR_COMPACT, SH64_COMPACT_SFMT_TASB_COMPACT, SH64_COMPACT_SFMT_TRAPA_COMPACT, SH64_COMPACT_SFMT_TSTI_COMPACT + , SH64_COMPACT_SFMT_TSTB_COMPACT } SH64_COMPACT_SFMT_TYPE; /* Function unit handlers (user written). */ +extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/); +extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/); +extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_fcnv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_fcmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_fsqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_fdiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_fpu_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_use_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_ldsl_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_lds_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_use_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_flds_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_load_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_set_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_fpu_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_use_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_u_set_fr_0 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_set_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_load_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_maybe_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_write_back (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_use_multiply_result (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_shift (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_tas (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_mulsw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_mull (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_dmul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_macl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_macw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_set_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_load_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_load_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_load_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_use_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_u_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_stc_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_ldcl_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_ldcl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_use_tbit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_ldc_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_ldc_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_set_sr_bit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_use_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_load_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_sts_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_lds_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_logic_b (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_jsr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_jmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_sx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); extern int sh64_model_sh5_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_putcfg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_getcfg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_pt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/); +extern int sh64_model_sh5_media_u_ftrvs (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_fsqrtd (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_fdivd (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_cond_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/); +extern int sh64_model_sh5_media_u_blink (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/); +extern int sh64_model_sh5_media_u_use_tr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_media_u_use_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_media_u_use_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_media_u_use_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_media_u_load_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_load_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_load_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_set_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_set_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_set_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_set_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/); +extern int sh64_model_sh5_media_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/); +extern int sh64_model_sh5_media_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_media_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_fcnv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_fcmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_fsqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_fdiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_fpu_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_use_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_ldsl_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_lds_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_use_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_flds_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_load_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_set_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_fpu_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_use_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_media_u_set_fr_0 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_set_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_load_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_maybe_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_write_back (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_use_multiply_result (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_shift (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_tas (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_mulsw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_mull (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_dmul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_macl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_macw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_set_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_load_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_load_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_load_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_use_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_media_u_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_stc_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_ldcl_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_ldcl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_use_tbit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_ldc_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_ldc_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_set_sr_bit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_use_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_load_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_sts_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_lds_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_logic_b (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_jsr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_jmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_sx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); /* Profiling before/after handlers (user written) */ diff --git a/sim/sh64/decode-media.c b/sim/sh64/decode-media.c index f1471f3..3df625d 100644 --- a/sim/sh64/decode-media.c +++ b/sim/sh64/decode-media.c @@ -2,9 +2,9 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -33,7 +33,7 @@ with this program; if not, write to the Free Software Foundation, Inc., teensy bit of cpu in the decoder. Moving it to malloc space is trivial but won't be done until necessary (we don't currently support the runtime addition of instructions nor an SMP machine with different cpus). */ -static IDESC sh64_media_insn_data[SH64_MEDIA_INSN_MAX]; +static IDESC sh64_media_insn_data[SH64_MEDIA_INSN__MAX]; /* Commas between elements are contained in the macros. Some of these are conditionally compiled out. */ @@ -87,7 +87,7 @@ static const struct insn_sem sh64_media_insn_sem[] = { SH_INSN_FCNVSD, SH64_MEDIA_INSN_FCNVSD, SH64_MEDIA_SFMT_FCNVSD }, { SH_INSN_FDIVD, SH64_MEDIA_INSN_FDIVD, SH64_MEDIA_SFMT_FADDD }, { SH_INSN_FDIVS, SH64_MEDIA_INSN_FDIVS, SH64_MEDIA_SFMT_FADDS }, - { SH_INSN_FGETSCR, SH64_MEDIA_INSN_FGETSCR, SH64_MEDIA_SFMT_ALLOCO }, + { SH_INSN_FGETSCR, SH64_MEDIA_INSN_FGETSCR, SH64_MEDIA_SFMT_FGETSCR }, { SH_INSN_FIPRS, SH64_MEDIA_INSN_FIPRS, SH64_MEDIA_SFMT_FIPRS }, { SH_INSN_FLDD, SH64_MEDIA_INSN_FLDD, SH64_MEDIA_SFMT_FLDD }, { SH_INSN_FLDP, SH64_MEDIA_INSN_FLDP, SH64_MEDIA_SFMT_FLDP }, @@ -110,14 +110,14 @@ static const struct insn_sem sh64_media_insn_sem[] = { SH_INSN_FMULS, SH64_MEDIA_INSN_FMULS, SH64_MEDIA_SFMT_FADDS }, { SH_INSN_FNEGD, SH64_MEDIA_INSN_FNEGD, SH64_MEDIA_SFMT_FABSD }, { SH_INSN_FNEGS, SH64_MEDIA_INSN_FNEGS, SH64_MEDIA_SFMT_FABSS }, - { SH_INSN_FPUTSCR, SH64_MEDIA_INSN_FPUTSCR, SH64_MEDIA_SFMT_ALLOCO }, + { SH_INSN_FPUTSCR, SH64_MEDIA_INSN_FPUTSCR, SH64_MEDIA_SFMT_FPUTSCR }, { SH_INSN_FSQRTD, SH64_MEDIA_INSN_FSQRTD, SH64_MEDIA_SFMT_FABSD }, { SH_INSN_FSQRTS, SH64_MEDIA_INSN_FSQRTS, SH64_MEDIA_SFMT_FABSS }, { SH_INSN_FSTD, SH64_MEDIA_INSN_FSTD, SH64_MEDIA_SFMT_FSTD }, - { SH_INSN_FSTP, SH64_MEDIA_INSN_FSTP, SH64_MEDIA_SFMT_FSTP }, + { SH_INSN_FSTP, SH64_MEDIA_INSN_FSTP, SH64_MEDIA_SFMT_FLDP }, { SH_INSN_FSTS, SH64_MEDIA_INSN_FSTS, SH64_MEDIA_SFMT_FSTS }, { SH_INSN_FSTXD, SH64_MEDIA_INSN_FSTXD, SH64_MEDIA_SFMT_FSTXD }, - { SH_INSN_FSTXP, SH64_MEDIA_INSN_FSTXP, SH64_MEDIA_SFMT_FSTXP }, + { SH_INSN_FSTXP, SH64_MEDIA_INSN_FSTXP, SH64_MEDIA_SFMT_FLDXP }, { SH_INSN_FSTXS, SH64_MEDIA_INSN_FSTXS, SH64_MEDIA_SFMT_FSTXS }, { SH_INSN_FSUBD, SH64_MEDIA_INSN_FSUBD, SH64_MEDIA_SFMT_FADDD }, { SH_INSN_FSUBS, SH64_MEDIA_INSN_FSUBS, SH64_MEDIA_SFMT_FADDS }, @@ -126,7 +126,7 @@ static const struct insn_sem sh64_media_insn_sem[] = { SH_INSN_FTRCDQ, SH64_MEDIA_INSN_FTRCDQ, SH64_MEDIA_SFMT_FABSD }, { SH_INSN_FTRCSQ, SH64_MEDIA_INSN_FTRCSQ, SH64_MEDIA_SFMT_FCNVSD }, { SH_INSN_FTRVS, SH64_MEDIA_INSN_FTRVS, SH64_MEDIA_SFMT_FTRVS }, - { SH_INSN_GETCFG, SH64_MEDIA_INSN_GETCFG, SH64_MEDIA_SFMT_ALLOCO }, + { SH_INSN_GETCFG, SH64_MEDIA_INSN_GETCFG, SH64_MEDIA_SFMT_GETCFG }, { SH_INSN_GETCON, SH64_MEDIA_INSN_GETCON, SH64_MEDIA_SFMT_GETCON }, { SH_INSN_GETTR, SH64_MEDIA_INSN_GETTR, SH64_MEDIA_SFMT_GETTR }, { SH_INSN_ICBI, SH64_MEDIA_INSN_ICBI, SH64_MEDIA_SFMT_ALLOCO }, @@ -136,16 +136,16 @@ static const struct insn_sem sh64_media_insn_sem[] = { SH_INSN_LDUB, SH64_MEDIA_INSN_LDUB, SH64_MEDIA_SFMT_LDB }, { SH_INSN_LDUW, SH64_MEDIA_INSN_LDUW, SH64_MEDIA_SFMT_LDUW }, { SH_INSN_LDW, SH64_MEDIA_INSN_LDW, SH64_MEDIA_SFMT_LDUW }, - { SH_INSN_LDHIL, SH64_MEDIA_INSN_LDHIL, SH64_MEDIA_SFMT_ALLOCO }, - { SH_INSN_LDHIQ, SH64_MEDIA_INSN_LDHIQ, SH64_MEDIA_SFMT_ALLOCO }, - { SH_INSN_LDLOL, SH64_MEDIA_INSN_LDLOL, SH64_MEDIA_SFMT_ALLOCO }, - { SH_INSN_LDLOQ, SH64_MEDIA_INSN_LDLOQ, SH64_MEDIA_SFMT_ALLOCO }, + { SH_INSN_LDHIL, SH64_MEDIA_INSN_LDHIL, SH64_MEDIA_SFMT_LDHIL }, + { SH_INSN_LDHIQ, SH64_MEDIA_INSN_LDHIQ, SH64_MEDIA_SFMT_LDHIQ }, + { SH_INSN_LDLOL, SH64_MEDIA_INSN_LDLOL, SH64_MEDIA_SFMT_LDLOL }, + { SH_INSN_LDLOQ, SH64_MEDIA_INSN_LDLOQ, SH64_MEDIA_SFMT_LDLOQ }, { SH_INSN_LDXB, SH64_MEDIA_INSN_LDXB, SH64_MEDIA_SFMT_LDXB }, - { SH_INSN_LDXL, SH64_MEDIA_INSN_LDXL, SH64_MEDIA_SFMT_LDXB }, - { SH_INSN_LDXQ, SH64_MEDIA_INSN_LDXQ, SH64_MEDIA_SFMT_LDXB }, - { SH_INSN_LDXUB, SH64_MEDIA_INSN_LDXUB, SH64_MEDIA_SFMT_LDXB }, - { SH_INSN_LDXUW, SH64_MEDIA_INSN_LDXUW, SH64_MEDIA_SFMT_LDXB }, - { SH_INSN_LDXW, SH64_MEDIA_INSN_LDXW, SH64_MEDIA_SFMT_LDXB }, + { SH_INSN_LDXL, SH64_MEDIA_INSN_LDXL, SH64_MEDIA_SFMT_LDXL }, + { SH_INSN_LDXQ, SH64_MEDIA_INSN_LDXQ, SH64_MEDIA_SFMT_LDXQ }, + { SH_INSN_LDXUB, SH64_MEDIA_INSN_LDXUB, SH64_MEDIA_SFMT_LDXUB }, + { SH_INSN_LDXUW, SH64_MEDIA_INSN_LDXUW, SH64_MEDIA_SFMT_LDXUW }, + { SH_INSN_LDXW, SH64_MEDIA_INSN_LDXW, SH64_MEDIA_SFMT_LDXW }, { SH_INSN_MABSL, SH64_MEDIA_INSN_MABSL, SH64_MEDIA_SFMT_BYTEREV }, { SH_INSN_MABSW, SH64_MEDIA_INSN_MABSW, SH64_MEDIA_SFMT_BYTEREV }, { SH_INSN_MADDL, SH64_MEDIA_INSN_MADDL, SH64_MEDIA_SFMT_ADD }, @@ -205,7 +205,7 @@ static const struct insn_sem sh64_media_insn_sem[] = { SH_INSN_MSUBSW, SH64_MEDIA_INSN_MSUBSW, SH64_MEDIA_SFMT_ADD }, { SH_INSN_MULSL, SH64_MEDIA_INSN_MULSL, SH64_MEDIA_SFMT_ADD }, { SH_INSN_MULUL, SH64_MEDIA_INSN_MULUL, SH64_MEDIA_SFMT_ADD }, - { SH_INSN_NOP, SH64_MEDIA_INSN_NOP, SH64_MEDIA_SFMT_ALLOCO }, + { SH_INSN_NOP, SH64_MEDIA_INSN_NOP, SH64_MEDIA_SFMT_NOP }, { SH_INSN_NSB, SH64_MEDIA_INSN_NSB, SH64_MEDIA_SFMT_BYTEREV }, { SH_INSN_OCBI, SH64_MEDIA_INSN_OCBI, SH64_MEDIA_SFMT_ALLOCO }, { SH_INSN_OCBP, SH64_MEDIA_INSN_OCBP, SH64_MEDIA_SFMT_ALLOCO }, @@ -217,9 +217,9 @@ static const struct insn_sem sh64_media_insn_sem[] = { SH_INSN_PTABS, SH64_MEDIA_INSN_PTABS, SH64_MEDIA_SFMT_PTABS }, { SH_INSN_PTB, SH64_MEDIA_INSN_PTB, SH64_MEDIA_SFMT_PTA }, { SH_INSN_PTREL, SH64_MEDIA_INSN_PTREL, SH64_MEDIA_SFMT_PTREL }, - { SH_INSN_PUTCFG, SH64_MEDIA_INSN_PUTCFG, SH64_MEDIA_SFMT_ALLOCO }, + { SH_INSN_PUTCFG, SH64_MEDIA_INSN_PUTCFG, SH64_MEDIA_SFMT_PUTCFG }, { SH_INSN_PUTCON, SH64_MEDIA_INSN_PUTCON, SH64_MEDIA_SFMT_PUTCON }, - { SH_INSN_RTE, SH64_MEDIA_INSN_RTE, SH64_MEDIA_SFMT_ALLOCO }, + { SH_INSN_RTE, SH64_MEDIA_INSN_RTE, SH64_MEDIA_SFMT_NOP }, { SH_INSN_SHARD, SH64_MEDIA_INSN_SHARD, SH64_MEDIA_SFMT_ADD }, { SH_INSN_SHARDL, SH64_MEDIA_INSN_SHARDL, SH64_MEDIA_SFMT_ADD }, { SH_INSN_SHARI, SH64_MEDIA_INSN_SHARI, SH64_MEDIA_SFMT_SHARI }, @@ -233,24 +233,24 @@ static const struct insn_sem sh64_media_insn_sem[] = { SH_INSN_SHLRI, SH64_MEDIA_INSN_SHLRI, SH64_MEDIA_SFMT_SHARI }, { SH_INSN_SHLRIL, SH64_MEDIA_INSN_SHLRIL, SH64_MEDIA_SFMT_SHARIL }, { SH_INSN_SHORI, SH64_MEDIA_INSN_SHORI, SH64_MEDIA_SFMT_SHORI }, - { SH_INSN_SLEEP, SH64_MEDIA_INSN_SLEEP, SH64_MEDIA_SFMT_ALLOCO }, + { SH_INSN_SLEEP, SH64_MEDIA_INSN_SLEEP, SH64_MEDIA_SFMT_NOP }, { SH_INSN_STB, SH64_MEDIA_INSN_STB, SH64_MEDIA_SFMT_STB }, { SH_INSN_STL, SH64_MEDIA_INSN_STL, SH64_MEDIA_SFMT_STL }, { SH_INSN_STQ, SH64_MEDIA_INSN_STQ, SH64_MEDIA_SFMT_STQ }, { SH_INSN_STW, SH64_MEDIA_INSN_STW, SH64_MEDIA_SFMT_STW }, { SH_INSN_STHIL, SH64_MEDIA_INSN_STHIL, SH64_MEDIA_SFMT_STHIL }, - { SH_INSN_STHIQ, SH64_MEDIA_INSN_STHIQ, SH64_MEDIA_SFMT_STHIL }, - { SH_INSN_STLOL, SH64_MEDIA_INSN_STLOL, SH64_MEDIA_SFMT_ALLOCO }, - { SH_INSN_STLOQ, SH64_MEDIA_INSN_STLOQ, SH64_MEDIA_SFMT_ALLOCO }, + { SH_INSN_STHIQ, SH64_MEDIA_INSN_STHIQ, SH64_MEDIA_SFMT_STHIQ }, + { SH_INSN_STLOL, SH64_MEDIA_INSN_STLOL, SH64_MEDIA_SFMT_STLOL }, + { SH_INSN_STLOQ, SH64_MEDIA_INSN_STLOQ, SH64_MEDIA_SFMT_STLOQ }, { SH_INSN_STXB, SH64_MEDIA_INSN_STXB, SH64_MEDIA_SFMT_STXB }, - { SH_INSN_STXL, SH64_MEDIA_INSN_STXL, SH64_MEDIA_SFMT_STXB }, - { SH_INSN_STXQ, SH64_MEDIA_INSN_STXQ, SH64_MEDIA_SFMT_STXB }, - { SH_INSN_STXW, SH64_MEDIA_INSN_STXW, SH64_MEDIA_SFMT_STXB }, + { SH_INSN_STXL, SH64_MEDIA_INSN_STXL, SH64_MEDIA_SFMT_STXL }, + { SH_INSN_STXQ, SH64_MEDIA_INSN_STXQ, SH64_MEDIA_SFMT_STXQ }, + { SH_INSN_STXW, SH64_MEDIA_INSN_STXW, SH64_MEDIA_SFMT_STXW }, { SH_INSN_SUB, SH64_MEDIA_INSN_SUB, SH64_MEDIA_SFMT_ADD }, { SH_INSN_SUBL, SH64_MEDIA_INSN_SUBL, SH64_MEDIA_SFMT_ADD }, { SH_INSN_SWAPQ, SH64_MEDIA_INSN_SWAPQ, SH64_MEDIA_SFMT_SWAPQ }, - { SH_INSN_SYNCI, SH64_MEDIA_INSN_SYNCI, SH64_MEDIA_SFMT_ALLOCO }, - { SH_INSN_SYNCO, SH64_MEDIA_INSN_SYNCO, SH64_MEDIA_SFMT_ALLOCO }, + { SH_INSN_SYNCI, SH64_MEDIA_INSN_SYNCI, SH64_MEDIA_SFMT_NOP }, + { SH_INSN_SYNCO, SH64_MEDIA_INSN_SYNCO, SH64_MEDIA_SFMT_NOP }, { SH_INSN_TRAPA, SH64_MEDIA_INSN_TRAPA, SH64_MEDIA_SFMT_TRAPA }, { SH_INSN_XOR, SH64_MEDIA_INSN_XOR, SH64_MEDIA_SFMT_ADD }, { SH_INSN_XORI, SH64_MEDIA_INSN_XORI, SH64_MEDIA_SFMT_XORI }, @@ -295,7 +295,7 @@ sh64_media_init_idesc_table (SIM_CPU *cpu) { IDESC *id,*tabend; const struct insn_sem *t,*tend; - int tabsize = SH64_MEDIA_INSN_MAX; + int tabsize = SH64_MEDIA_INSN__MAX; IDESC *table = sh64_media_insn_data; memset (table, 0, tabsize * sizeof (IDESC)); @@ -333,7 +333,643 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, unsigned int val = (((insn >> 22) & (63 << 4)) | ((insn >> 16) & (15 << 0))); switch (val) { - case 1 : itype = SH64_MEDIA_INSN_CMPEQ; goto extract_sfmt_add; case 3 : itype = SH64_MEDIA_INSN_CMPGT; goto extract_sfmt_add; case 7 : itype = SH64_MEDIA_INSN_CMPGTU; goto extract_sfmt_add; case 8 : itype = SH64_MEDIA_INSN_ADDL; goto extract_sfmt_add; case 9 : itype = SH64_MEDIA_INSN_ADD; goto extract_sfmt_add; case 10 : itype = SH64_MEDIA_INSN_SUBL; goto extract_sfmt_add; case 11 : itype = SH64_MEDIA_INSN_SUB; goto extract_sfmt_add; case 12 : itype = SH64_MEDIA_INSN_ADDZL; goto extract_sfmt_add; case 13 : itype = SH64_MEDIA_INSN_NSB; goto extract_sfmt_byterev; case 14 : itype = SH64_MEDIA_INSN_MULUL; goto extract_sfmt_add; case 15 : itype = SH64_MEDIA_INSN_BYTEREV; goto extract_sfmt_byterev; case 16 : itype = SH64_MEDIA_INSN_SHLLDL; goto extract_sfmt_add; case 17 : itype = SH64_MEDIA_INSN_SHLLD; goto extract_sfmt_add; case 18 : itype = SH64_MEDIA_INSN_SHLRDL; goto extract_sfmt_add; case 19 : itype = SH64_MEDIA_INSN_SHLRD; goto extract_sfmt_add; case 22 : itype = SH64_MEDIA_INSN_SHARDL; goto extract_sfmt_add; case 23 : itype = SH64_MEDIA_INSN_SHARD; goto extract_sfmt_add; case 25 : itype = SH64_MEDIA_INSN_OR; goto extract_sfmt_add; case 27 : itype = SH64_MEDIA_INSN_AND; goto extract_sfmt_add; case 29 : itype = SH64_MEDIA_INSN_XOR; goto extract_sfmt_add; case 30 : itype = SH64_MEDIA_INSN_MULSL; goto extract_sfmt_add; case 31 : itype = SH64_MEDIA_INSN_ANDC; goto extract_sfmt_add; case 33 : itype = SH64_MEDIA_INSN_MADDW; goto extract_sfmt_add; case 34 : itype = SH64_MEDIA_INSN_MADDL; goto extract_sfmt_add; case 36 : itype = SH64_MEDIA_INSN_MADDSUB; goto extract_sfmt_add; case 37 : itype = SH64_MEDIA_INSN_MADDSW; goto extract_sfmt_add; case 38 : itype = SH64_MEDIA_INSN_MADDSL; goto extract_sfmt_add; case 41 : itype = SH64_MEDIA_INSN_MSUBW; goto extract_sfmt_add; case 42 : itype = SH64_MEDIA_INSN_MSUBL; goto extract_sfmt_add; case 44 : itype = SH64_MEDIA_INSN_MSUBSUB; goto extract_sfmt_add; case 45 : itype = SH64_MEDIA_INSN_MSUBSW; goto extract_sfmt_add; case 46 : itype = SH64_MEDIA_INSN_MSUBSL; goto extract_sfmt_add; case 49 : itype = SH64_MEDIA_INSN_MSHLLDW; goto extract_sfmt_add; case 50 : itype = SH64_MEDIA_INSN_MSHLLDL; goto extract_sfmt_add; case 53 : itype = SH64_MEDIA_INSN_MSHALDSW; goto extract_sfmt_add; case 54 : itype = SH64_MEDIA_INSN_MSHALDSL; goto extract_sfmt_add; case 57 : itype = SH64_MEDIA_INSN_MSHARDW; goto extract_sfmt_add; case 58 : itype = SH64_MEDIA_INSN_MSHARDL; goto extract_sfmt_add; case 59 : itype = SH64_MEDIA_INSN_MSHARDSQ; goto extract_sfmt_add; case 61 : itype = SH64_MEDIA_INSN_MSHLRDW; goto extract_sfmt_add; case 62 : itype = SH64_MEDIA_INSN_MSHLRDL; goto extract_sfmt_add; case 86 : itype = SH64_MEDIA_INSN_FIPRS; goto extract_sfmt_fiprs; case 94 : itype = SH64_MEDIA_INSN_FTRVS; goto extract_sfmt_ftrvs; case 96 : itype = SH64_MEDIA_INSN_FABSS; goto extract_sfmt_fabss; case 97 : itype = SH64_MEDIA_INSN_FABSD; goto extract_sfmt_fabsd; case 98 : itype = SH64_MEDIA_INSN_FNEGS; goto extract_sfmt_fabss; case 99 : itype = SH64_MEDIA_INSN_FNEGD; goto extract_sfmt_fabsd; case 112 : itype = SH64_MEDIA_INSN_FMOVLS; goto extract_sfmt_fmovls; case 113 : itype = SH64_MEDIA_INSN_FMOVQD; goto extract_sfmt_fmovqd; case 114 : itype = SH64_MEDIA_INSN_FGETSCR; goto extract_sfmt_alloco; case 120 : itype = SH64_MEDIA_INSN_FLDXS; goto extract_sfmt_fldxs; case 121 : itype = SH64_MEDIA_INSN_FLDXD; goto extract_sfmt_fldxd; case 125 : itype = SH64_MEDIA_INSN_FLDXP; goto extract_sfmt_fldxp; case 129 : itype = SH64_MEDIA_INSN_CMVEQ; goto extract_sfmt_cmveq; case 131 : itype = SH64_MEDIA_INSN_SWAPQ; goto extract_sfmt_swapq; case 133 : itype = SH64_MEDIA_INSN_CMVNE; goto extract_sfmt_cmveq; case 159 : itype = SH64_MEDIA_INSN_GETCON; goto extract_sfmt_getcon; case 160 : itype = SH64_MEDIA_INSN_MCMPEQB; goto extract_sfmt_add; case 161 : itype = SH64_MEDIA_INSN_MCMPEQW; goto extract_sfmt_add; case 162 : itype = SH64_MEDIA_INSN_MCMPEQL; goto extract_sfmt_add; case 164 : itype = SH64_MEDIA_INSN_MCMPGTUB; goto extract_sfmt_add; case 165 : itype = SH64_MEDIA_INSN_MCMPGTW; goto extract_sfmt_add; case 166 : itype = SH64_MEDIA_INSN_MCMPGTL; goto extract_sfmt_add; case 167 : itype = SH64_MEDIA_INSN_MEXTR1; goto extract_sfmt_add; case 169 : itype = SH64_MEDIA_INSN_MABSW; goto extract_sfmt_byterev; case 170 : itype = SH64_MEDIA_INSN_MABSL; goto extract_sfmt_byterev; case 171 : itype = SH64_MEDIA_INSN_MEXTR2; goto extract_sfmt_add; case 173 : itype = SH64_MEDIA_INSN_MPERMW; goto extract_sfmt_mpermw; case 175 : itype = SH64_MEDIA_INSN_MEXTR3; goto extract_sfmt_add; case 176 : itype = SH64_MEDIA_INSN_MSHFLOB; goto extract_sfmt_add; case 177 : itype = SH64_MEDIA_INSN_MSHFLOW; goto extract_sfmt_add; case 178 : itype = SH64_MEDIA_INSN_MSHFLOL; goto extract_sfmt_add; case 179 : itype = SH64_MEDIA_INSN_MEXTR4; goto extract_sfmt_add; case 180 : itype = SH64_MEDIA_INSN_MSHFHIB; goto extract_sfmt_add; case 181 : itype = SH64_MEDIA_INSN_MSHFHIW; goto extract_sfmt_add; case 182 : itype = SH64_MEDIA_INSN_MSHFHIL; goto extract_sfmt_add; case 183 : itype = SH64_MEDIA_INSN_MEXTR5; goto extract_sfmt_add; case 187 : itype = SH64_MEDIA_INSN_MEXTR6; goto extract_sfmt_add; case 191 : itype = SH64_MEDIA_INSN_MEXTR7; goto extract_sfmt_add; case 192 : itype = SH64_MEDIA_INSN_FMOVSL; goto extract_sfmt_fmovsl; case 193 : itype = SH64_MEDIA_INSN_FMOVDQ; goto extract_sfmt_fmovdq; case 194 : itype = SH64_MEDIA_INSN_FPUTSCR; goto extract_sfmt_alloco; case 200 : itype = SH64_MEDIA_INSN_FCMPEQS; goto extract_sfmt_fcmpeqs; case 201 : itype = SH64_MEDIA_INSN_FCMPEQD; goto extract_sfmt_fcmpeqd; case 202 : itype = SH64_MEDIA_INSN_FCMPUNS; goto extract_sfmt_fcmpeqs; case 203 : itype = SH64_MEDIA_INSN_FCMPUND; goto extract_sfmt_fcmpeqd; case 204 : itype = SH64_MEDIA_INSN_FCMPGTS; goto extract_sfmt_fcmpeqs; case 205 : itype = SH64_MEDIA_INSN_FCMPGTD; goto extract_sfmt_fcmpeqd; case 206 : itype = SH64_MEDIA_INSN_FCMPGES; goto extract_sfmt_fcmpeqs; case 207 : itype = SH64_MEDIA_INSN_FCMPGED; goto extract_sfmt_fcmpeqd; case 208 : itype = SH64_MEDIA_INSN_FADDS; goto extract_sfmt_fadds; case 209 : itype = SH64_MEDIA_INSN_FADDD; goto extract_sfmt_faddd; case 210 : itype = SH64_MEDIA_INSN_FSUBS; goto extract_sfmt_fadds; case 211 : itype = SH64_MEDIA_INSN_FSUBD; goto extract_sfmt_faddd; case 212 : itype = SH64_MEDIA_INSN_FDIVS; goto extract_sfmt_fadds; case 213 : itype = SH64_MEDIA_INSN_FDIVD; goto extract_sfmt_faddd; case 214 : itype = SH64_MEDIA_INSN_FMULS; goto extract_sfmt_fadds; case 215 : itype = SH64_MEDIA_INSN_FMULD; goto extract_sfmt_faddd; case 222 : itype = SH64_MEDIA_INSN_FMACS; goto extract_sfmt_fmacs; case 224 : itype = SH64_MEDIA_INSN_FMOVS; goto extract_sfmt_fabss; case 225 : itype = SH64_MEDIA_INSN_FMOVD; goto extract_sfmt_fabsd; case 228 : itype = SH64_MEDIA_INSN_FSQRTS; goto extract_sfmt_fabss; case 229 : itype = SH64_MEDIA_INSN_FSQRTD; goto extract_sfmt_fabsd; case 230 : itype = SH64_MEDIA_INSN_FCNVSD; goto extract_sfmt_fcnvsd; case 231 : itype = SH64_MEDIA_INSN_FCNVDS; goto extract_sfmt_fcnvds; case 232 : itype = SH64_MEDIA_INSN_FTRCSL; goto extract_sfmt_fabss; case 233 : itype = SH64_MEDIA_INSN_FTRCDQ; goto extract_sfmt_fabsd; case 234 : itype = SH64_MEDIA_INSN_FTRCSQ; goto extract_sfmt_fcnvsd; case 235 : itype = SH64_MEDIA_INSN_FTRCDL; goto extract_sfmt_fcnvds; case 236 : itype = SH64_MEDIA_INSN_FLOATLS; goto extract_sfmt_fabss; case 237 : itype = SH64_MEDIA_INSN_FLOATQD; goto extract_sfmt_fabsd; case 238 : itype = SH64_MEDIA_INSN_FLOATLD; goto extract_sfmt_fcnvsd; case 239 : itype = SH64_MEDIA_INSN_FLOATQS; goto extract_sfmt_fcnvds; case 248 : itype = SH64_MEDIA_INSN_FSTXS; goto extract_sfmt_fstxs; case 249 : itype = SH64_MEDIA_INSN_FSTXD; goto extract_sfmt_fstxd; case 253 : itype = SH64_MEDIA_INSN_FSTXP; goto extract_sfmt_fstxp; case 256 : itype = SH64_MEDIA_INSN_LDXB; goto extract_sfmt_ldxb; case 257 : itype = SH64_MEDIA_INSN_LDXW; goto extract_sfmt_ldxb; case 258 : itype = SH64_MEDIA_INSN_LDXL; goto extract_sfmt_ldxb; case 259 : itype = SH64_MEDIA_INSN_LDXQ; goto extract_sfmt_ldxb; case 260 : itype = SH64_MEDIA_INSN_LDXUB; goto extract_sfmt_ldxb; case 261 : itype = SH64_MEDIA_INSN_LDXUW; goto extract_sfmt_ldxb; case 273 : itype = SH64_MEDIA_INSN_BLINK; goto extract_sfmt_blink; case 277 : itype = SH64_MEDIA_INSN_GETTR; goto extract_sfmt_gettr; case 288 : itype = SH64_MEDIA_INSN_MSADUBQ; goto extract_sfmt_mcmv; case 289 : itype = SH64_MEDIA_INSN_MMACFXWL; goto extract_sfmt_mcmv; case 291 : itype = SH64_MEDIA_INSN_MCMV; goto extract_sfmt_mcmv; case 293 : itype = SH64_MEDIA_INSN_MMACNFX_WL; goto extract_sfmt_mcmv; case 297 : itype = SH64_MEDIA_INSN_MMULSUMWQ; goto extract_sfmt_mcmv; case 305 : itype = SH64_MEDIA_INSN_MMULW; goto extract_sfmt_add; case 306 : itype = SH64_MEDIA_INSN_MMULL; goto extract_sfmt_add; case 309 : itype = SH64_MEDIA_INSN_MMULFXW; goto extract_sfmt_add; case 310 : itype = SH64_MEDIA_INSN_MMULFXL; goto extract_sfmt_add; case 312 : itype = SH64_MEDIA_INSN_MCNVSWB; goto extract_sfmt_add; case 313 : itype = SH64_MEDIA_INSN_MMULFXRPW; goto extract_sfmt_add; case 314 : itype = SH64_MEDIA_INSN_MMULLOWL; goto extract_sfmt_add; case 316 : itype = SH64_MEDIA_INSN_MCNVSWUB; goto extract_sfmt_add; case 317 : itype = SH64_MEDIA_INSN_MCNVSLW; goto extract_sfmt_add; case 318 : itype = SH64_MEDIA_INSN_MMULHIWL; goto extract_sfmt_add; case 384 : itype = SH64_MEDIA_INSN_STXB; goto extract_sfmt_stxb; case 385 : itype = SH64_MEDIA_INSN_STXW; goto extract_sfmt_stxb; case 386 : itype = SH64_MEDIA_INSN_STXL; goto extract_sfmt_stxb; case 387 : itype = SH64_MEDIA_INSN_STXQ; goto extract_sfmt_stxb; case 401 : itype = SH64_MEDIA_INSN_BEQ; goto extract_sfmt_beq; case 403 : itype = SH64_MEDIA_INSN_BGE; goto extract_sfmt_beq; case 405 : itype = SH64_MEDIA_INSN_BNE; goto extract_sfmt_beq; case 407 : itype = SH64_MEDIA_INSN_BGT; goto extract_sfmt_beq; case 411 : itype = SH64_MEDIA_INSN_BGEU; goto extract_sfmt_beq; case 415 : itype = SH64_MEDIA_INSN_BGTU; goto extract_sfmt_beq; case 417 : itype = SH64_MEDIA_INSN_PTABS; goto extract_sfmt_ptabs; case 421 : itype = SH64_MEDIA_INSN_PTREL; goto extract_sfmt_ptrel; case 432 : itype = SH64_MEDIA_INSN_NOP; goto extract_sfmt_alloco; case 433 : itype = SH64_MEDIA_INSN_TRAPA; goto extract_sfmt_trapa; case 434 : itype = SH64_MEDIA_INSN_SYNCI; goto extract_sfmt_alloco; case 435 : itype = SH64_MEDIA_INSN_RTE; goto extract_sfmt_alloco; case 437 : itype = SH64_MEDIA_INSN_BRK; goto extract_sfmt_brk; case 438 : itype = SH64_MEDIA_INSN_SYNCO; goto extract_sfmt_alloco; case 439 : itype = SH64_MEDIA_INSN_SLEEP; goto extract_sfmt_alloco; case 447 : itype = SH64_MEDIA_INSN_PUTCON; goto extract_sfmt_putcon; case 512 : /* fall through */ + case 1 : + if ((entire_insn & 0xfc0f000f) == 0x10000) + { itype = SH64_MEDIA_INSN_CMPEQ; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 3 : + if ((entire_insn & 0xfc0f000f) == 0x30000) + { itype = SH64_MEDIA_INSN_CMPGT; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 7 : + if ((entire_insn & 0xfc0f000f) == 0x70000) + { itype = SH64_MEDIA_INSN_CMPGTU; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 8 : + if ((entire_insn & 0xfc0f000f) == 0x80000) + { itype = SH64_MEDIA_INSN_ADDL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 9 : + if ((entire_insn & 0xfc0f000f) == 0x90000) + { itype = SH64_MEDIA_INSN_ADD; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 10 : + if ((entire_insn & 0xfc0f000f) == 0xa0000) + { itype = SH64_MEDIA_INSN_SUBL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 11 : + if ((entire_insn & 0xfc0f000f) == 0xb0000) + { itype = SH64_MEDIA_INSN_SUB; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 12 : + if ((entire_insn & 0xfc0f000f) == 0xc0000) + { itype = SH64_MEDIA_INSN_ADDZL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 13 : + if ((entire_insn & 0xfc0ffc0f) == 0xdfc00) + { itype = SH64_MEDIA_INSN_NSB; goto extract_sfmt_byterev; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 14 : + if ((entire_insn & 0xfc0f000f) == 0xe0000) + { itype = SH64_MEDIA_INSN_MULUL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 15 : + if ((entire_insn & 0xfc0ffc0f) == 0xffc00) + { itype = SH64_MEDIA_INSN_BYTEREV; goto extract_sfmt_byterev; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 16 : + if ((entire_insn & 0xfc0f000f) == 0x4000000) + { itype = SH64_MEDIA_INSN_SHLLDL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 17 : + if ((entire_insn & 0xfc0f000f) == 0x4010000) + { itype = SH64_MEDIA_INSN_SHLLD; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 18 : + if ((entire_insn & 0xfc0f000f) == 0x4020000) + { itype = SH64_MEDIA_INSN_SHLRDL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 19 : + if ((entire_insn & 0xfc0f000f) == 0x4030000) + { itype = SH64_MEDIA_INSN_SHLRD; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 22 : + if ((entire_insn & 0xfc0f000f) == 0x4060000) + { itype = SH64_MEDIA_INSN_SHARDL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 23 : + if ((entire_insn & 0xfc0f000f) == 0x4070000) + { itype = SH64_MEDIA_INSN_SHARD; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 25 : + if ((entire_insn & 0xfc0f000f) == 0x4090000) + { itype = SH64_MEDIA_INSN_OR; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 27 : + if ((entire_insn & 0xfc0f000f) == 0x40b0000) + { itype = SH64_MEDIA_INSN_AND; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 29 : + if ((entire_insn & 0xfc0f000f) == 0x40d0000) + { itype = SH64_MEDIA_INSN_XOR; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 30 : + if ((entire_insn & 0xfc0f000f) == 0x40e0000) + { itype = SH64_MEDIA_INSN_MULSL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 31 : + if ((entire_insn & 0xfc0f000f) == 0x40f0000) + { itype = SH64_MEDIA_INSN_ANDC; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 33 : + if ((entire_insn & 0xfc0f000f) == 0x8010000) + { itype = SH64_MEDIA_INSN_MADDW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 34 : + if ((entire_insn & 0xfc0f000f) == 0x8020000) + { itype = SH64_MEDIA_INSN_MADDL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 36 : + if ((entire_insn & 0xfc0f000f) == 0x8040000) + { itype = SH64_MEDIA_INSN_MADDSUB; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 37 : + if ((entire_insn & 0xfc0f000f) == 0x8050000) + { itype = SH64_MEDIA_INSN_MADDSW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 38 : + if ((entire_insn & 0xfc0f000f) == 0x8060000) + { itype = SH64_MEDIA_INSN_MADDSL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 41 : + if ((entire_insn & 0xfc0f000f) == 0x8090000) + { itype = SH64_MEDIA_INSN_MSUBW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 42 : + if ((entire_insn & 0xfc0f000f) == 0x80a0000) + { itype = SH64_MEDIA_INSN_MSUBL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 44 : + if ((entire_insn & 0xfc0f000f) == 0x80c0000) + { itype = SH64_MEDIA_INSN_MSUBSUB; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 45 : + if ((entire_insn & 0xfc0f000f) == 0x80d0000) + { itype = SH64_MEDIA_INSN_MSUBSW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 46 : + if ((entire_insn & 0xfc0f000f) == 0x80e0000) + { itype = SH64_MEDIA_INSN_MSUBSL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 49 : + if ((entire_insn & 0xfc0f000f) == 0xc010000) + { itype = SH64_MEDIA_INSN_MSHLLDW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 50 : + if ((entire_insn & 0xfc0f000f) == 0xc020000) + { itype = SH64_MEDIA_INSN_MSHLLDL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 53 : + if ((entire_insn & 0xfc0f000f) == 0xc050000) + { itype = SH64_MEDIA_INSN_MSHALDSW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 54 : + if ((entire_insn & 0xfc0f000f) == 0xc060000) + { itype = SH64_MEDIA_INSN_MSHALDSL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 57 : + if ((entire_insn & 0xfc0f000f) == 0xc090000) + { itype = SH64_MEDIA_INSN_MSHARDW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 58 : + if ((entire_insn & 0xfc0f000f) == 0xc0a0000) + { itype = SH64_MEDIA_INSN_MSHARDL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 59 : + if ((entire_insn & 0xfc0f000f) == 0xc0b0000) + { itype = SH64_MEDIA_INSN_MSHARDSQ; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 61 : + if ((entire_insn & 0xfc0f000f) == 0xc0d0000) + { itype = SH64_MEDIA_INSN_MSHLRDW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 62 : + if ((entire_insn & 0xfc0f000f) == 0xc0e0000) + { itype = SH64_MEDIA_INSN_MSHLRDL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 86 : + if ((entire_insn & 0xfc0f000f) == 0x14060000) + { itype = SH64_MEDIA_INSN_FIPRS; goto extract_sfmt_fiprs; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 94 : + if ((entire_insn & 0xfc0f000f) == 0x140e0000) + { itype = SH64_MEDIA_INSN_FTRVS; goto extract_sfmt_ftrvs; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 96 : + if ((entire_insn & 0xfc0f000f) == 0x18000000) + { itype = SH64_MEDIA_INSN_FABSS; goto extract_sfmt_fabss; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 97 : + if ((entire_insn & 0xfc0f000f) == 0x18010000) + { itype = SH64_MEDIA_INSN_FABSD; goto extract_sfmt_fabsd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 98 : + if ((entire_insn & 0xfc0f000f) == 0x18020000) + { itype = SH64_MEDIA_INSN_FNEGS; goto extract_sfmt_fabss; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 99 : + if ((entire_insn & 0xfc0f000f) == 0x18030000) + { itype = SH64_MEDIA_INSN_FNEGD; goto extract_sfmt_fabsd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 112 : + if ((entire_insn & 0xfc0ffc0f) == 0x1c00fc00) + { itype = SH64_MEDIA_INSN_FMOVLS; goto extract_sfmt_fmovls; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 113 : + if ((entire_insn & 0xfc0ffc0f) == 0x1c01fc00) + { itype = SH64_MEDIA_INSN_FMOVQD; goto extract_sfmt_fmovqd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 114 : + if ((entire_insn & 0xfffffc0f) == 0x1ff2fc00) + { itype = SH64_MEDIA_INSN_FGETSCR; goto extract_sfmt_fgetscr; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 120 : + if ((entire_insn & 0xfc0f000f) == 0x1c080000) + { itype = SH64_MEDIA_INSN_FLDXS; goto extract_sfmt_fldxs; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 121 : + if ((entire_insn & 0xfc0f000f) == 0x1c090000) + { itype = SH64_MEDIA_INSN_FLDXD; goto extract_sfmt_fldxd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 125 : + if ((entire_insn & 0xfc0f000f) == 0x1c0d0000) + { itype = SH64_MEDIA_INSN_FLDXP; goto extract_sfmt_fldxp; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 129 : + if ((entire_insn & 0xfc0f000f) == 0x20010000) + { itype = SH64_MEDIA_INSN_CMVEQ; goto extract_sfmt_cmveq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 131 : + if ((entire_insn & 0xfc0f000f) == 0x20030000) + { itype = SH64_MEDIA_INSN_SWAPQ; goto extract_sfmt_swapq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 133 : + if ((entire_insn & 0xfc0f000f) == 0x20050000) + { itype = SH64_MEDIA_INSN_CMVNE; goto extract_sfmt_cmveq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 159 : + if ((entire_insn & 0xfc0ffc0f) == 0x240ffc00) + { itype = SH64_MEDIA_INSN_GETCON; goto extract_sfmt_getcon; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 160 : + if ((entire_insn & 0xfc0f000f) == 0x28000000) + { itype = SH64_MEDIA_INSN_MCMPEQB; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 161 : + if ((entire_insn & 0xfc0f000f) == 0x28010000) + { itype = SH64_MEDIA_INSN_MCMPEQW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 162 : + if ((entire_insn & 0xfc0f000f) == 0x28020000) + { itype = SH64_MEDIA_INSN_MCMPEQL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 164 : + if ((entire_insn & 0xfc0f000f) == 0x28040000) + { itype = SH64_MEDIA_INSN_MCMPGTUB; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 165 : + if ((entire_insn & 0xfc0f000f) == 0x28050000) + { itype = SH64_MEDIA_INSN_MCMPGTW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 166 : + if ((entire_insn & 0xfc0f000f) == 0x28060000) + { itype = SH64_MEDIA_INSN_MCMPGTL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 167 : + if ((entire_insn & 0xfc0f000f) == 0x28070000) + { itype = SH64_MEDIA_INSN_MEXTR1; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 169 : + if ((entire_insn & 0xfc0ffc0f) == 0x2809fc00) + { itype = SH64_MEDIA_INSN_MABSW; goto extract_sfmt_byterev; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 170 : + if ((entire_insn & 0xfc0ffc0f) == 0x280afc00) + { itype = SH64_MEDIA_INSN_MABSL; goto extract_sfmt_byterev; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 171 : + if ((entire_insn & 0xfc0f000f) == 0x280b0000) + { itype = SH64_MEDIA_INSN_MEXTR2; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 173 : + if ((entire_insn & 0xfc0f000f) == 0x280d0000) + { itype = SH64_MEDIA_INSN_MPERMW; goto extract_sfmt_mpermw; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 175 : + if ((entire_insn & 0xfc0f000f) == 0x280f0000) + { itype = SH64_MEDIA_INSN_MEXTR3; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 176 : + if ((entire_insn & 0xfc0f000f) == 0x2c000000) + { itype = SH64_MEDIA_INSN_MSHFLOB; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 177 : + if ((entire_insn & 0xfc0f000f) == 0x2c010000) + { itype = SH64_MEDIA_INSN_MSHFLOW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 178 : + if ((entire_insn & 0xfc0f000f) == 0x2c020000) + { itype = SH64_MEDIA_INSN_MSHFLOL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 179 : + if ((entire_insn & 0xfc0f000f) == 0x2c030000) + { itype = SH64_MEDIA_INSN_MEXTR4; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 180 : + if ((entire_insn & 0xfc0f000f) == 0x2c040000) + { itype = SH64_MEDIA_INSN_MSHFHIB; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 181 : + if ((entire_insn & 0xfc0f000f) == 0x2c050000) + { itype = SH64_MEDIA_INSN_MSHFHIW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 182 : + if ((entire_insn & 0xfc0f000f) == 0x2c060000) + { itype = SH64_MEDIA_INSN_MSHFHIL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 183 : + if ((entire_insn & 0xfc0f000f) == 0x2c070000) + { itype = SH64_MEDIA_INSN_MEXTR5; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 187 : + if ((entire_insn & 0xfc0f000f) == 0x2c0b0000) + { itype = SH64_MEDIA_INSN_MEXTR6; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 191 : + if ((entire_insn & 0xfc0f000f) == 0x2c0f0000) + { itype = SH64_MEDIA_INSN_MEXTR7; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 192 : + if ((entire_insn & 0xfc0f000f) == 0x30000000) + { itype = SH64_MEDIA_INSN_FMOVSL; goto extract_sfmt_fmovsl; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 193 : + if ((entire_insn & 0xfc0f000f) == 0x30010000) + { itype = SH64_MEDIA_INSN_FMOVDQ; goto extract_sfmt_fmovdq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 194 : + if ((entire_insn & 0xfc0f03ff) == 0x300203f0) + { itype = SH64_MEDIA_INSN_FPUTSCR; goto extract_sfmt_fputscr; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 200 : + if ((entire_insn & 0xfc0f000f) == 0x30080000) + { itype = SH64_MEDIA_INSN_FCMPEQS; goto extract_sfmt_fcmpeqs; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 201 : + if ((entire_insn & 0xfc0f000f) == 0x30090000) + { itype = SH64_MEDIA_INSN_FCMPEQD; goto extract_sfmt_fcmpeqd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 202 : + if ((entire_insn & 0xfc0f000f) == 0x300a0000) + { itype = SH64_MEDIA_INSN_FCMPUNS; goto extract_sfmt_fcmpeqs; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 203 : + if ((entire_insn & 0xfc0f000f) == 0x300b0000) + { itype = SH64_MEDIA_INSN_FCMPUND; goto extract_sfmt_fcmpeqd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 204 : + if ((entire_insn & 0xfc0f000f) == 0x300c0000) + { itype = SH64_MEDIA_INSN_FCMPGTS; goto extract_sfmt_fcmpeqs; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 205 : + if ((entire_insn & 0xfc0f000f) == 0x300d0000) + { itype = SH64_MEDIA_INSN_FCMPGTD; goto extract_sfmt_fcmpeqd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 206 : + if ((entire_insn & 0xfc0f000f) == 0x300e0000) + { itype = SH64_MEDIA_INSN_FCMPGES; goto extract_sfmt_fcmpeqs; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 207 : + if ((entire_insn & 0xfc0f000f) == 0x300f0000) + { itype = SH64_MEDIA_INSN_FCMPGED; goto extract_sfmt_fcmpeqd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 208 : + if ((entire_insn & 0xfc0f000f) == 0x34000000) + { itype = SH64_MEDIA_INSN_FADDS; goto extract_sfmt_fadds; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 209 : + if ((entire_insn & 0xfc0f000f) == 0x34010000) + { itype = SH64_MEDIA_INSN_FADDD; goto extract_sfmt_faddd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 210 : + if ((entire_insn & 0xfc0f000f) == 0x34020000) + { itype = SH64_MEDIA_INSN_FSUBS; goto extract_sfmt_fadds; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 211 : + if ((entire_insn & 0xfc0f000f) == 0x34030000) + { itype = SH64_MEDIA_INSN_FSUBD; goto extract_sfmt_faddd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 212 : + if ((entire_insn & 0xfc0f000f) == 0x34040000) + { itype = SH64_MEDIA_INSN_FDIVS; goto extract_sfmt_fadds; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 213 : + if ((entire_insn & 0xfc0f000f) == 0x34050000) + { itype = SH64_MEDIA_INSN_FDIVD; goto extract_sfmt_faddd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 214 : + if ((entire_insn & 0xfc0f000f) == 0x34060000) + { itype = SH64_MEDIA_INSN_FMULS; goto extract_sfmt_fadds; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 215 : + if ((entire_insn & 0xfc0f000f) == 0x34070000) + { itype = SH64_MEDIA_INSN_FMULD; goto extract_sfmt_faddd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 222 : + if ((entire_insn & 0xfc0f000f) == 0x340e0000) + { itype = SH64_MEDIA_INSN_FMACS; goto extract_sfmt_fmacs; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 224 : + if ((entire_insn & 0xfc0f000f) == 0x38000000) + { itype = SH64_MEDIA_INSN_FMOVS; goto extract_sfmt_fabss; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 225 : + if ((entire_insn & 0xfc0f000f) == 0x38010000) + { itype = SH64_MEDIA_INSN_FMOVD; goto extract_sfmt_fabsd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 228 : + if ((entire_insn & 0xfc0f000f) == 0x38040000) + { itype = SH64_MEDIA_INSN_FSQRTS; goto extract_sfmt_fabss; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 229 : + if ((entire_insn & 0xfc0f000f) == 0x38050000) + { itype = SH64_MEDIA_INSN_FSQRTD; goto extract_sfmt_fabsd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 230 : + if ((entire_insn & 0xfc0f000f) == 0x38060000) + { itype = SH64_MEDIA_INSN_FCNVSD; goto extract_sfmt_fcnvsd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 231 : + if ((entire_insn & 0xfc0f000f) == 0x38070000) + { itype = SH64_MEDIA_INSN_FCNVDS; goto extract_sfmt_fcnvds; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 232 : + if ((entire_insn & 0xfc0f000f) == 0x38080000) + { itype = SH64_MEDIA_INSN_FTRCSL; goto extract_sfmt_fabss; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 233 : + if ((entire_insn & 0xfc0f000f) == 0x38090000) + { itype = SH64_MEDIA_INSN_FTRCDQ; goto extract_sfmt_fabsd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 234 : + if ((entire_insn & 0xfc0f000f) == 0x380a0000) + { itype = SH64_MEDIA_INSN_FTRCSQ; goto extract_sfmt_fcnvsd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 235 : + if ((entire_insn & 0xfc0f000f) == 0x380b0000) + { itype = SH64_MEDIA_INSN_FTRCDL; goto extract_sfmt_fcnvds; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 236 : + if ((entire_insn & 0xfc0f000f) == 0x380c0000) + { itype = SH64_MEDIA_INSN_FLOATLS; goto extract_sfmt_fabss; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 237 : + if ((entire_insn & 0xfc0f000f) == 0x380d0000) + { itype = SH64_MEDIA_INSN_FLOATQD; goto extract_sfmt_fabsd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 238 : + if ((entire_insn & 0xfc0f000f) == 0x380e0000) + { itype = SH64_MEDIA_INSN_FLOATLD; goto extract_sfmt_fcnvsd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 239 : + if ((entire_insn & 0xfc0f000f) == 0x380f0000) + { itype = SH64_MEDIA_INSN_FLOATQS; goto extract_sfmt_fcnvds; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 248 : + if ((entire_insn & 0xfc0f000f) == 0x3c080000) + { itype = SH64_MEDIA_INSN_FSTXS; goto extract_sfmt_fstxs; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 249 : + if ((entire_insn & 0xfc0f000f) == 0x3c090000) + { itype = SH64_MEDIA_INSN_FSTXD; goto extract_sfmt_fstxd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 253 : + if ((entire_insn & 0xfc0f000f) == 0x3c0d0000) + { itype = SH64_MEDIA_INSN_FSTXP; goto extract_sfmt_fldxp; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 256 : + if ((entire_insn & 0xfc0f000f) == 0x40000000) + { itype = SH64_MEDIA_INSN_LDXB; goto extract_sfmt_ldxb; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 257 : + if ((entire_insn & 0xfc0f000f) == 0x40010000) + { itype = SH64_MEDIA_INSN_LDXW; goto extract_sfmt_ldxw; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 258 : + if ((entire_insn & 0xfc0f000f) == 0x40020000) + { itype = SH64_MEDIA_INSN_LDXL; goto extract_sfmt_ldxl; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 259 : + if ((entire_insn & 0xfc0f000f) == 0x40030000) + { itype = SH64_MEDIA_INSN_LDXQ; goto extract_sfmt_ldxq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 260 : + if ((entire_insn & 0xfc0f000f) == 0x40040000) + { itype = SH64_MEDIA_INSN_LDXUB; goto extract_sfmt_ldxub; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 261 : + if ((entire_insn & 0xfc0f000f) == 0x40050000) + { itype = SH64_MEDIA_INSN_LDXUW; goto extract_sfmt_ldxuw; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 273 : + if ((entire_insn & 0xff8ffc0f) == 0x4401fc00) + { itype = SH64_MEDIA_INSN_BLINK; goto extract_sfmt_blink; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 277 : + if ((entire_insn & 0xff8ffc0f) == 0x4405fc00) + { itype = SH64_MEDIA_INSN_GETTR; goto extract_sfmt_gettr; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 288 : + if ((entire_insn & 0xfc0f000f) == 0x48000000) + { itype = SH64_MEDIA_INSN_MSADUBQ; goto extract_sfmt_mcmv; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 289 : + if ((entire_insn & 0xfc0f000f) == 0x48010000) + { itype = SH64_MEDIA_INSN_MMACFXWL; goto extract_sfmt_mcmv; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 291 : + if ((entire_insn & 0xfc0f000f) == 0x48030000) + { itype = SH64_MEDIA_INSN_MCMV; goto extract_sfmt_mcmv; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 293 : + if ((entire_insn & 0xfc0f000f) == 0x48050000) + { itype = SH64_MEDIA_INSN_MMACNFX_WL; goto extract_sfmt_mcmv; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 297 : + if ((entire_insn & 0xfc0f000f) == 0x48090000) + { itype = SH64_MEDIA_INSN_MMULSUMWQ; goto extract_sfmt_mcmv; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 305 : + if ((entire_insn & 0xfc0f000f) == 0x4c010000) + { itype = SH64_MEDIA_INSN_MMULW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 306 : + if ((entire_insn & 0xfc0f000f) == 0x4c020000) + { itype = SH64_MEDIA_INSN_MMULL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 309 : + if ((entire_insn & 0xfc0f000f) == 0x4c050000) + { itype = SH64_MEDIA_INSN_MMULFXW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 310 : + if ((entire_insn & 0xfc0f000f) == 0x4c060000) + { itype = SH64_MEDIA_INSN_MMULFXL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 312 : + if ((entire_insn & 0xfc0f000f) == 0x4c080000) + { itype = SH64_MEDIA_INSN_MCNVSWB; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 313 : + if ((entire_insn & 0xfc0f000f) == 0x4c090000) + { itype = SH64_MEDIA_INSN_MMULFXRPW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 314 : + if ((entire_insn & 0xfc0f000f) == 0x4c0a0000) + { itype = SH64_MEDIA_INSN_MMULLOWL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 316 : + if ((entire_insn & 0xfc0f000f) == 0x4c0c0000) + { itype = SH64_MEDIA_INSN_MCNVSWUB; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 317 : + if ((entire_insn & 0xfc0f000f) == 0x4c0d0000) + { itype = SH64_MEDIA_INSN_MCNVSLW; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 318 : + if ((entire_insn & 0xfc0f000f) == 0x4c0e0000) + { itype = SH64_MEDIA_INSN_MMULHIWL; goto extract_sfmt_add; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 384 : + if ((entire_insn & 0xfc0f000f) == 0x60000000) + { itype = SH64_MEDIA_INSN_STXB; goto extract_sfmt_stxb; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 385 : + if ((entire_insn & 0xfc0f000f) == 0x60010000) + { itype = SH64_MEDIA_INSN_STXW; goto extract_sfmt_stxw; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 386 : + if ((entire_insn & 0xfc0f000f) == 0x60020000) + { itype = SH64_MEDIA_INSN_STXL; goto extract_sfmt_stxl; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 387 : + if ((entire_insn & 0xfc0f000f) == 0x60030000) + { itype = SH64_MEDIA_INSN_STXQ; goto extract_sfmt_stxq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 401 : + if ((entire_insn & 0xfc0f018f) == 0x64010000) + { itype = SH64_MEDIA_INSN_BEQ; goto extract_sfmt_beq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 403 : + if ((entire_insn & 0xfc0f018f) == 0x64030000) + { itype = SH64_MEDIA_INSN_BGE; goto extract_sfmt_beq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 405 : + if ((entire_insn & 0xfc0f018f) == 0x64050000) + { itype = SH64_MEDIA_INSN_BNE; goto extract_sfmt_beq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 407 : + if ((entire_insn & 0xfc0f018f) == 0x64070000) + { itype = SH64_MEDIA_INSN_BGT; goto extract_sfmt_beq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 411 : + if ((entire_insn & 0xfc0f018f) == 0x640b0000) + { itype = SH64_MEDIA_INSN_BGEU; goto extract_sfmt_beq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 415 : + if ((entire_insn & 0xfc0f018f) == 0x640f0000) + { itype = SH64_MEDIA_INSN_BGTU; goto extract_sfmt_beq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 417 : + if ((entire_insn & 0xffff018f) == 0x6bf10000) + { itype = SH64_MEDIA_INSN_PTABS; goto extract_sfmt_ptabs; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 421 : + if ((entire_insn & 0xffff018f) == 0x6bf50000) + { itype = SH64_MEDIA_INSN_PTREL; goto extract_sfmt_ptrel; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 432 : + if ((entire_insn & 0xffffffff) == 0x6ff0fff0) + { itype = SH64_MEDIA_INSN_NOP; goto extract_sfmt_nop; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 433 : + if ((entire_insn & 0xfc0fffff) == 0x6c01fff0) + { itype = SH64_MEDIA_INSN_TRAPA; goto extract_sfmt_trapa; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 434 : + if ((entire_insn & 0xffffffff) == 0x6ff2fff0) + { itype = SH64_MEDIA_INSN_SYNCI; goto extract_sfmt_nop; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 435 : + if ((entire_insn & 0xffffffff) == 0x6ff3fff0) + { itype = SH64_MEDIA_INSN_RTE; goto extract_sfmt_nop; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 437 : + if ((entire_insn & 0xffffffff) == 0x6ff5fff0) + { itype = SH64_MEDIA_INSN_BRK; goto extract_sfmt_brk; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 438 : + if ((entire_insn & 0xffffffff) == 0x6ff6fff0) + { itype = SH64_MEDIA_INSN_SYNCO; goto extract_sfmt_nop; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 439 : + if ((entire_insn & 0xffffffff) == 0x6ff7fff0) + { itype = SH64_MEDIA_INSN_SLEEP; goto extract_sfmt_nop; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 447 : + if ((entire_insn & 0xfc0ffc0f) == 0x6c0ffc00) + { itype = SH64_MEDIA_INSN_PUTCON; goto extract_sfmt_putcon; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 512 : /* fall through */ case 513 : /* fall through */ case 514 : /* fall through */ case 515 : /* fall through */ @@ -348,7 +984,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 524 : /* fall through */ case 525 : /* fall through */ case 526 : /* fall through */ - case 527 : itype = SH64_MEDIA_INSN_LDB; goto extract_sfmt_ldb; case 528 : /* fall through */ + case 527 : + if ((entire_insn & 0xfc00000f) == 0x80000000) + { itype = SH64_MEDIA_INSN_LDB; goto extract_sfmt_ldb; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 528 : /* fall through */ case 529 : /* fall through */ case 530 : /* fall through */ case 531 : /* fall through */ @@ -363,7 +1003,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 540 : /* fall through */ case 541 : /* fall through */ case 542 : /* fall through */ - case 543 : itype = SH64_MEDIA_INSN_LDW; goto extract_sfmt_lduw; case 544 : /* fall through */ + case 543 : + if ((entire_insn & 0xfc00000f) == 0x84000000) + { itype = SH64_MEDIA_INSN_LDW; goto extract_sfmt_lduw; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 544 : /* fall through */ case 545 : /* fall through */ case 546 : /* fall through */ case 547 : /* fall through */ @@ -378,7 +1022,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 556 : /* fall through */ case 557 : /* fall through */ case 558 : /* fall through */ - case 559 : itype = SH64_MEDIA_INSN_LDL; goto extract_sfmt_ldl; case 560 : /* fall through */ + case 559 : + if ((entire_insn & 0xfc00000f) == 0x88000000) + { itype = SH64_MEDIA_INSN_LDL; goto extract_sfmt_ldl; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 560 : /* fall through */ case 561 : /* fall through */ case 562 : /* fall through */ case 563 : /* fall through */ @@ -393,7 +1041,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 572 : /* fall through */ case 573 : /* fall through */ case 574 : /* fall through */ - case 575 : itype = SH64_MEDIA_INSN_LDQ; goto extract_sfmt_ldq; case 576 : /* fall through */ + case 575 : + if ((entire_insn & 0xfc00000f) == 0x8c000000) + { itype = SH64_MEDIA_INSN_LDQ; goto extract_sfmt_ldq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 576 : /* fall through */ case 577 : /* fall through */ case 578 : /* fall through */ case 579 : /* fall through */ @@ -408,7 +1060,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 588 : /* fall through */ case 589 : /* fall through */ case 590 : /* fall through */ - case 591 : itype = SH64_MEDIA_INSN_LDUB; goto extract_sfmt_ldb; case 592 : /* fall through */ + case 591 : + if ((entire_insn & 0xfc00000f) == 0x90000000) + { itype = SH64_MEDIA_INSN_LDUB; goto extract_sfmt_ldb; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 592 : /* fall through */ case 593 : /* fall through */ case 594 : /* fall through */ case 595 : /* fall through */ @@ -423,7 +1079,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 604 : /* fall through */ case 605 : /* fall through */ case 606 : /* fall through */ - case 607 : itype = SH64_MEDIA_INSN_FLDS; goto extract_sfmt_flds; case 608 : /* fall through */ + case 607 : + if ((entire_insn & 0xfc00000f) == 0x94000000) + { itype = SH64_MEDIA_INSN_FLDS; goto extract_sfmt_flds; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 608 : /* fall through */ case 609 : /* fall through */ case 610 : /* fall through */ case 611 : /* fall through */ @@ -438,7 +1098,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 620 : /* fall through */ case 621 : /* fall through */ case 622 : /* fall through */ - case 623 : itype = SH64_MEDIA_INSN_FLDP; goto extract_sfmt_fldp; case 624 : /* fall through */ + case 623 : + if ((entire_insn & 0xfc00000f) == 0x98000000) + { itype = SH64_MEDIA_INSN_FLDP; goto extract_sfmt_fldp; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 624 : /* fall through */ case 625 : /* fall through */ case 626 : /* fall through */ case 627 : /* fall through */ @@ -453,7 +1117,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 636 : /* fall through */ case 637 : /* fall through */ case 638 : /* fall through */ - case 639 : itype = SH64_MEDIA_INSN_FLDD; goto extract_sfmt_fldd; case 640 : /* fall through */ + case 639 : + if ((entire_insn & 0xfc00000f) == 0x9c000000) + { itype = SH64_MEDIA_INSN_FLDD; goto extract_sfmt_fldd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 640 : /* fall through */ case 641 : /* fall through */ case 642 : /* fall through */ case 643 : /* fall through */ @@ -468,7 +1136,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 652 : /* fall through */ case 653 : /* fall through */ case 654 : /* fall through */ - case 655 : itype = SH64_MEDIA_INSN_STB; goto extract_sfmt_stb; case 656 : /* fall through */ + case 655 : + if ((entire_insn & 0xfc00000f) == 0xa0000000) + { itype = SH64_MEDIA_INSN_STB; goto extract_sfmt_stb; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 656 : /* fall through */ case 657 : /* fall through */ case 658 : /* fall through */ case 659 : /* fall through */ @@ -483,7 +1155,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 668 : /* fall through */ case 669 : /* fall through */ case 670 : /* fall through */ - case 671 : itype = SH64_MEDIA_INSN_STW; goto extract_sfmt_stw; case 672 : /* fall through */ + case 671 : + if ((entire_insn & 0xfc00000f) == 0xa4000000) + { itype = SH64_MEDIA_INSN_STW; goto extract_sfmt_stw; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 672 : /* fall through */ case 673 : /* fall through */ case 674 : /* fall through */ case 675 : /* fall through */ @@ -498,7 +1174,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 684 : /* fall through */ case 685 : /* fall through */ case 686 : /* fall through */ - case 687 : itype = SH64_MEDIA_INSN_STL; goto extract_sfmt_stl; case 688 : /* fall through */ + case 687 : + if ((entire_insn & 0xfc00000f) == 0xa8000000) + { itype = SH64_MEDIA_INSN_STL; goto extract_sfmt_stl; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 688 : /* fall through */ case 689 : /* fall through */ case 690 : /* fall through */ case 691 : /* fall through */ @@ -513,7 +1193,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 700 : /* fall through */ case 701 : /* fall through */ case 702 : /* fall through */ - case 703 : itype = SH64_MEDIA_INSN_STQ; goto extract_sfmt_stq; case 704 : /* fall through */ + case 703 : + if ((entire_insn & 0xfc00000f) == 0xac000000) + { itype = SH64_MEDIA_INSN_STQ; goto extract_sfmt_stq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 704 : /* fall through */ case 705 : /* fall through */ case 706 : /* fall through */ case 707 : /* fall through */ @@ -528,7 +1212,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 716 : /* fall through */ case 717 : /* fall through */ case 718 : /* fall through */ - case 719 : itype = SH64_MEDIA_INSN_LDUW; goto extract_sfmt_lduw; case 720 : /* fall through */ + case 719 : + if ((entire_insn & 0xfc00000f) == 0xb0000000) + { itype = SH64_MEDIA_INSN_LDUW; goto extract_sfmt_lduw; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 720 : /* fall through */ case 721 : /* fall through */ case 722 : /* fall through */ case 723 : /* fall through */ @@ -543,7 +1231,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 732 : /* fall through */ case 733 : /* fall through */ case 734 : /* fall through */ - case 735 : itype = SH64_MEDIA_INSN_FSTS; goto extract_sfmt_fsts; case 736 : /* fall through */ + case 735 : + if ((entire_insn & 0xfc00000f) == 0xb4000000) + { itype = SH64_MEDIA_INSN_FSTS; goto extract_sfmt_fsts; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 736 : /* fall through */ case 737 : /* fall through */ case 738 : /* fall through */ case 739 : /* fall through */ @@ -558,7 +1250,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 748 : /* fall through */ case 749 : /* fall through */ case 750 : /* fall through */ - case 751 : itype = SH64_MEDIA_INSN_FSTP; goto extract_sfmt_fstp; case 752 : /* fall through */ + case 751 : + if ((entire_insn & 0xfc00000f) == 0xb8000000) + { itype = SH64_MEDIA_INSN_FSTP; goto extract_sfmt_fldp; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 752 : /* fall through */ case 753 : /* fall through */ case 754 : /* fall through */ case 755 : /* fall through */ @@ -573,7 +1269,59 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 764 : /* fall through */ case 765 : /* fall through */ case 766 : /* fall through */ - case 767 : itype = SH64_MEDIA_INSN_FSTD; goto extract_sfmt_fstd; case 770 : itype = SH64_MEDIA_INSN_LDLOL; goto extract_sfmt_alloco; case 771 : itype = SH64_MEDIA_INSN_LDLOQ; goto extract_sfmt_alloco; case 774 : itype = SH64_MEDIA_INSN_LDHIL; goto extract_sfmt_alloco; case 775 : itype = SH64_MEDIA_INSN_LDHIQ; goto extract_sfmt_alloco; case 783 : itype = SH64_MEDIA_INSN_GETCFG; goto extract_sfmt_alloco; case 784 : itype = SH64_MEDIA_INSN_SHLLIL; goto extract_sfmt_sharil; case 785 : itype = SH64_MEDIA_INSN_SHLLI; goto extract_sfmt_shari; case 786 : itype = SH64_MEDIA_INSN_SHLRIL; goto extract_sfmt_sharil; case 787 : itype = SH64_MEDIA_INSN_SHLRI; goto extract_sfmt_shari; case 790 : itype = SH64_MEDIA_INSN_SHARIL; goto extract_sfmt_sharil; case 791 : itype = SH64_MEDIA_INSN_SHARI; goto extract_sfmt_shari; case 797 : itype = SH64_MEDIA_INSN_XORI; goto extract_sfmt_xori; case 800 : /* fall through */ + case 767 : + if ((entire_insn & 0xfc00000f) == 0xbc000000) + { itype = SH64_MEDIA_INSN_FSTD; goto extract_sfmt_fstd; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 770 : + if ((entire_insn & 0xfc0f000f) == 0xc0020000) + { itype = SH64_MEDIA_INSN_LDLOL; goto extract_sfmt_ldlol; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 771 : + if ((entire_insn & 0xfc0f000f) == 0xc0030000) + { itype = SH64_MEDIA_INSN_LDLOQ; goto extract_sfmt_ldloq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 774 : + if ((entire_insn & 0xfc0f000f) == 0xc0060000) + { itype = SH64_MEDIA_INSN_LDHIL; goto extract_sfmt_ldhil; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 775 : + if ((entire_insn & 0xfc0f000f) == 0xc0070000) + { itype = SH64_MEDIA_INSN_LDHIQ; goto extract_sfmt_ldhiq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 783 : + if ((entire_insn & 0xfc0f000f) == 0xc00f0000) + { itype = SH64_MEDIA_INSN_GETCFG; goto extract_sfmt_getcfg; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 784 : + if ((entire_insn & 0xfc0f000f) == 0xc4000000) + { itype = SH64_MEDIA_INSN_SHLLIL; goto extract_sfmt_sharil; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 785 : + if ((entire_insn & 0xfc0f000f) == 0xc4010000) + { itype = SH64_MEDIA_INSN_SHLLI; goto extract_sfmt_shari; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 786 : + if ((entire_insn & 0xfc0f000f) == 0xc4020000) + { itype = SH64_MEDIA_INSN_SHLRIL; goto extract_sfmt_sharil; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 787 : + if ((entire_insn & 0xfc0f000f) == 0xc4030000) + { itype = SH64_MEDIA_INSN_SHLRI; goto extract_sfmt_shari; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 790 : + if ((entire_insn & 0xfc0f000f) == 0xc4060000) + { itype = SH64_MEDIA_INSN_SHARIL; goto extract_sfmt_sharil; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 791 : + if ((entire_insn & 0xfc0f000f) == 0xc4070000) + { itype = SH64_MEDIA_INSN_SHARI; goto extract_sfmt_shari; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 797 : + if ((entire_insn & 0xfc0f000f) == 0xc40d0000) + { itype = SH64_MEDIA_INSN_XORI; goto extract_sfmt_xori; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 800 : /* fall through */ case 801 : /* fall through */ case 802 : /* fall through */ case 803 : /* fall through */ @@ -588,7 +1336,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 812 : /* fall through */ case 813 : /* fall through */ case 814 : /* fall through */ - case 815 : itype = SH64_MEDIA_INSN_SHORI; goto extract_sfmt_shori; case 816 : /* fall through */ + case 815 : + if ((entire_insn & 0xfc00000f) == 0xc8000000) + { itype = SH64_MEDIA_INSN_SHORI; goto extract_sfmt_shori; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 816 : /* fall through */ case 817 : /* fall through */ case 818 : /* fall through */ case 819 : /* fall through */ @@ -603,7 +1355,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 828 : /* fall through */ case 829 : /* fall through */ case 830 : /* fall through */ - case 831 : itype = SH64_MEDIA_INSN_MOVI; goto extract_sfmt_movi; case 832 : /* fall through */ + case 831 : + if ((entire_insn & 0xfc00000f) == 0xcc000000) + { itype = SH64_MEDIA_INSN_MOVI; goto extract_sfmt_movi; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 832 : /* fall through */ case 833 : /* fall through */ case 834 : /* fall through */ case 835 : /* fall through */ @@ -618,7 +1374,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 844 : /* fall through */ case 845 : /* fall through */ case 846 : /* fall through */ - case 847 : itype = SH64_MEDIA_INSN_ADDI; goto extract_sfmt_addi; case 848 : /* fall through */ + case 847 : + if ((entire_insn & 0xfc00000f) == 0xd0000000) + { itype = SH64_MEDIA_INSN_ADDI; goto extract_sfmt_addi; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 848 : /* fall through */ case 849 : /* fall through */ case 850 : /* fall through */ case 851 : /* fall through */ @@ -633,7 +1393,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 860 : /* fall through */ case 861 : /* fall through */ case 862 : /* fall through */ - case 863 : itype = SH64_MEDIA_INSN_ADDIL; goto extract_sfmt_addi; case 864 : /* fall through */ + case 863 : + if ((entire_insn & 0xfc00000f) == 0xd4000000) + { itype = SH64_MEDIA_INSN_ADDIL; goto extract_sfmt_addi; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 864 : /* fall through */ case 865 : /* fall through */ case 866 : /* fall through */ case 867 : /* fall through */ @@ -648,7 +1412,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 876 : /* fall through */ case 877 : /* fall through */ case 878 : /* fall through */ - case 879 : itype = SH64_MEDIA_INSN_ANDI; goto extract_sfmt_addi; case 880 : /* fall through */ + case 879 : + if ((entire_insn & 0xfc00000f) == 0xd8000000) + { itype = SH64_MEDIA_INSN_ANDI; goto extract_sfmt_addi; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 880 : /* fall through */ case 881 : /* fall through */ case 882 : /* fall through */ case 883 : /* fall through */ @@ -663,7 +1431,63 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 892 : /* fall through */ case 893 : /* fall through */ case 894 : /* fall through */ - case 895 : itype = SH64_MEDIA_INSN_ORI; goto extract_sfmt_ori; case 897 : itype = SH64_MEDIA_INSN_PREFI; goto extract_sfmt_alloco; case 898 : itype = SH64_MEDIA_INSN_STLOL; goto extract_sfmt_alloco; case 899 : itype = SH64_MEDIA_INSN_STLOQ; goto extract_sfmt_alloco; case 900 : itype = SH64_MEDIA_INSN_ALLOCO; goto extract_sfmt_alloco; case 901 : itype = SH64_MEDIA_INSN_ICBI; goto extract_sfmt_alloco; case 902 : itype = SH64_MEDIA_INSN_STHIL; goto extract_sfmt_sthil; case 903 : itype = SH64_MEDIA_INSN_STHIQ; goto extract_sfmt_sthil; case 904 : itype = SH64_MEDIA_INSN_OCBP; goto extract_sfmt_alloco; case 905 : itype = SH64_MEDIA_INSN_OCBI; goto extract_sfmt_alloco; case 908 : itype = SH64_MEDIA_INSN_OCBWB; goto extract_sfmt_alloco; case 911 : itype = SH64_MEDIA_INSN_PUTCFG; goto extract_sfmt_alloco; case 913 : itype = SH64_MEDIA_INSN_BEQI; goto extract_sfmt_beqi; case 917 : itype = SH64_MEDIA_INSN_BNEI; goto extract_sfmt_beqi; case 928 : /* fall through */ + case 895 : + if ((entire_insn & 0xfc00000f) == 0xdc000000) + { itype = SH64_MEDIA_INSN_ORI; goto extract_sfmt_ori; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 897 : + if ((entire_insn & 0xfc0ffc0f) == 0xe001fc00) + { itype = SH64_MEDIA_INSN_PREFI; goto extract_sfmt_alloco; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 898 : + if ((entire_insn & 0xfc0f000f) == 0xe0020000) + { itype = SH64_MEDIA_INSN_STLOL; goto extract_sfmt_stlol; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 899 : + if ((entire_insn & 0xfc0f000f) == 0xe0030000) + { itype = SH64_MEDIA_INSN_STLOQ; goto extract_sfmt_stloq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 900 : + if ((entire_insn & 0xfc0f03ff) == 0xe00403f0) + { itype = SH64_MEDIA_INSN_ALLOCO; goto extract_sfmt_alloco; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 901 : + if ((entire_insn & 0xfc0f03ff) == 0xe00503f0) + { itype = SH64_MEDIA_INSN_ICBI; goto extract_sfmt_alloco; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 902 : + if ((entire_insn & 0xfc0f000f) == 0xe0060000) + { itype = SH64_MEDIA_INSN_STHIL; goto extract_sfmt_sthil; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 903 : + if ((entire_insn & 0xfc0f000f) == 0xe0070000) + { itype = SH64_MEDIA_INSN_STHIQ; goto extract_sfmt_sthiq; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 904 : + if ((entire_insn & 0xfc0f03ff) == 0xe00803f0) + { itype = SH64_MEDIA_INSN_OCBP; goto extract_sfmt_alloco; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 905 : + if ((entire_insn & 0xfc0f03ff) == 0xe00903f0) + { itype = SH64_MEDIA_INSN_OCBI; goto extract_sfmt_alloco; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 908 : + if ((entire_insn & 0xfc0f03ff) == 0xe00c03f0) + { itype = SH64_MEDIA_INSN_OCBWB; goto extract_sfmt_alloco; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 911 : + if ((entire_insn & 0xfc0f000f) == 0xe00f0000) + { itype = SH64_MEDIA_INSN_PUTCFG; goto extract_sfmt_putcfg; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 913 : + if ((entire_insn & 0xfc0f018f) == 0xe4010000) + { itype = SH64_MEDIA_INSN_BEQI; goto extract_sfmt_beqi; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 917 : + if ((entire_insn & 0xfc0f018f) == 0xe4050000) + { itype = SH64_MEDIA_INSN_BNEI; goto extract_sfmt_beqi; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 928 : /* fall through */ case 929 : /* fall through */ case 930 : /* fall through */ case 931 : /* fall through */ @@ -678,7 +1502,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 940 : /* fall through */ case 941 : /* fall through */ case 942 : /* fall through */ - case 943 : itype = SH64_MEDIA_INSN_PTA; goto extract_sfmt_pta; case 944 : /* fall through */ + case 943 : + if ((entire_insn & 0xfc00018f) == 0xe8000000) + { itype = SH64_MEDIA_INSN_PTA; goto extract_sfmt_pta; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 944 : /* fall through */ case 945 : /* fall through */ case 946 : /* fall through */ case 947 : /* fall through */ @@ -693,7 +1521,11 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, case 956 : /* fall through */ case 957 : /* fall through */ case 958 : /* fall through */ - case 959 : itype = SH64_MEDIA_INSN_PTB; goto extract_sfmt_pta; default : itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + case 959 : + if ((entire_insn & 0xfc00018f) == 0xec000000) + { itype = SH64_MEDIA_INSN_PTB; goto extract_sfmt_pta; } + itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; + default : itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty; } } } @@ -722,9 +1554,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; @@ -732,6 +1564,15 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -745,9 +1586,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, INT f_disp10; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10 = EXTRACT_LSB0_INT (insn, 32, 19, 10); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp10 = EXTRACT_MSB0_INT (insn, 32, 12, 10); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp10) = f_disp10; @@ -755,6 +1596,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_disp10 0x%x", 'x', f_disp10, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -762,12 +1611,24 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, extract_sfmt_alloco: { const IDESC *idesc = &sh64_media_insn_data[itype]; -#define FLD(f) abuf->fields.fmt_empty.f + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_xori.f + UINT f_left; + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); /* Record the fields for the semantic handler. */ - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_alloco", (char *) 0)); + FLD (f_left) = f_left; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_alloco", "f_left 0x%x", 'x', f_left, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rm) = f_left; + } +#endif #undef FLD return idesc; } @@ -781,9 +1642,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_tra; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; @@ -791,6 +1652,15 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_tra) = f_tra; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_tra 0x%x", 'x', f_tra, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (in_tra) = f_tra; + } +#endif #undef FLD return idesc; } @@ -804,9 +1674,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, INT f_imm6; UINT f_tra; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_imm6 = EXTRACT_LSB0_INT (insn, 32, 15, 6); - f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_imm6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); + f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); /* Record the fields for the semantic handler. */ FLD (f_imm6) = f_imm6; @@ -814,6 +1684,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_tra) = f_tra; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqi", "f_imm6 0x%x", 'x', f_imm6, "f_left 0x%x", 'x', f_left, "f_tra 0x%x", 'x', f_tra, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (in_tra) = f_tra; + } +#endif #undef FLD return idesc; } @@ -826,14 +1704,22 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_trb; UINT f_dest; - f_trb = EXTRACT_LSB0_UINT (insn, 32, 22, 3); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_trb = EXTRACT_MSB0_UINT (insn, 32, 9, 3); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ - FLD (f_trb) = f_trb; FLD (f_dest) = f_dest; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_blink", "f_trb 0x%x", 'x', f_trb, "f_dest 0x%x", 'x', f_dest, (char *) 0)); + FLD (f_trb) = f_trb; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_blink", "f_dest 0x%x", 'x', f_dest, "f_trb 0x%x", 'x', f_trb, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_trb) = f_trb; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -847,6 +1733,12 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, /* Record the fields for the semantic handler. */ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brk", (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif #undef FLD return idesc; } @@ -859,14 +1751,22 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_left; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_byterev", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -880,9 +1780,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; @@ -890,6 +1790,15 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmveq", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -904,9 +1813,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_dest; UINT f_left_right; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); f_left_right = f_left; /* Record the fields for the semantic handler. */ @@ -914,6 +1823,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fabsd", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_drgh) = f_left_right; + FLD (out_drf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -928,9 +1845,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_dest; UINT f_left_right; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); f_left_right = f_left; /* Record the fields for the semantic handler. */ @@ -938,6 +1855,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fabss", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_frgh) = f_left_right; + FLD (out_frf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -951,9 +1876,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; @@ -961,6 +1886,15 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_faddd", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_drg) = f_left; + FLD (in_drh) = f_right; + FLD (out_drf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -974,9 +1908,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; @@ -984,6 +1918,15 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fadds", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_frg) = f_left; + FLD (in_frh) = f_right; + FLD (out_frf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -997,9 +1940,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; @@ -1007,6 +1950,15 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcmpeqd", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_drg) = f_left; + FLD (in_drh) = f_right; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1020,9 +1972,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; @@ -1030,6 +1982,15 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcmpeqs", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_frg) = f_left; + FLD (in_frh) = f_right; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1044,9 +2005,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_dest; UINT f_left_right; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); f_left_right = f_left; /* Record the fields for the semantic handler. */ @@ -1054,6 +2015,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcnvds", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_drgh) = f_left_right; + FLD (out_frf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1068,9 +2037,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_dest; UINT f_left_right; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); f_left_right = f_left; /* Record the fields for the semantic handler. */ @@ -1078,6 +2047,38 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcnvsd", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_frgh) = f_left_right; + FLD (out_drf) = f_dest; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_fgetscr: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_shori.f + UINT f_dest; + + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_dest) = f_dest; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fgetscr", "f_dest 0x%x", 'x', f_dest, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_frf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1091,9 +2092,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; @@ -1101,6 +2102,17 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fiprs", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fvg) = f_left; + FLD (in_fvh) = f_right; + FLD (out_frf) = f_dest; + FLD (out_fvg) = f_left; + FLD (out_fvh) = f_right; + } +#endif #undef FLD return idesc; } @@ -1114,9 +2126,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, SI f_disp10x8; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp10x8 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (3)); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp10x8) = f_disp10x8; @@ -1124,6 +2136,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldd", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_drf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1137,9 +2157,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, SI f_disp10x8; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp10x8 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (3)); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp10x8) = f_disp10x8; @@ -1147,6 +2167,15 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_left) = f_left; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldp", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fpf) = f_dest; + FLD (in_rm) = f_left; + FLD (out_fpf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1160,9 +2189,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, SI f_disp10x4; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2)); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp10x4 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (2)); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp10x4) = f_disp10x4; @@ -1170,6 +2199,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flds", "f_disp10x4 0x%x", 'x', f_disp10x4, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_frf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1183,9 +2220,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; @@ -1193,6 +2230,15 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldxd", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (out_drf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1206,9 +2252,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_dest) = f_dest; @@ -1216,6 +2262,16 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_right) = f_right; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldxp", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fpf) = f_dest; + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (out_fpf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1229,9 +2285,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; @@ -1239,6 +2295,15 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldxs", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (out_frf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1252,9 +2317,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_dest) = f_dest; @@ -1262,6 +2327,16 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_right) = f_right; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmacs", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_frf) = f_dest; + FLD (in_frg) = f_left; + FLD (in_frh) = f_right; + FLD (out_frf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1276,9 +2351,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_dest; UINT f_left_right; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); f_left_right = f_left; /* Record the fields for the semantic handler. */ @@ -1286,6 +2361,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovdq", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_drgh) = f_left_right; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1298,14 +2381,22 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_left; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovls", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_frf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1318,14 +2409,22 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_left; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovqd", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_drf) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1340,9 +2439,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_dest; UINT f_left_right; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); f_left_right = f_left; /* Record the fields for the semantic handler. */ @@ -1350,34 +2449,47 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovsl", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_frgh) = f_left_right; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } - extract_sfmt_fstd: + extract_sfmt_fputscr: { const IDESC *idesc = &sh64_media_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_fldd.f +#define FLD(f) abuf->fields.sfmt_fabsd.f UINT f_left; - SI f_disp10x8; - UINT f_dest; + UINT f_right; + UINT f_left_right; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_left_right = f_left; /* Record the fields for the semantic handler. */ - FLD (f_disp10x8) = f_disp10x8; - FLD (f_dest) = f_dest; - FLD (f_left) = f_left; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstd", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0)); + FLD (f_left_right) = f_left_right; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fputscr", "f_left_right 0x%x", 'x', f_left_right, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_frgh) = f_left_right; + } +#endif #undef FLD return idesc; } - extract_sfmt_fstp: + extract_sfmt_fstd: { const IDESC *idesc = &sh64_media_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; @@ -1386,16 +2498,24 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, SI f_disp10x8; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp10x8 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (3)); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp10x8) = f_disp10x8; FLD (f_dest) = f_dest; FLD (f_left) = f_left; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstp", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstd", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_drf) = f_dest; + FLD (in_rm) = f_left; + } +#endif #undef FLD return idesc; } @@ -1409,9 +2529,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, SI f_disp10x4; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2)); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp10x4 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (2)); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp10x4) = f_disp10x4; @@ -1419,6 +2539,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_left) = f_left; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fsts", "f_disp10x4 0x%x", 'x', f_disp10x4, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_frf) = f_dest; + FLD (in_rm) = f_left; + } +#endif #undef FLD return idesc; } @@ -1432,9 +2560,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_dest) = f_dest; @@ -1442,11 +2570,20 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_right) = f_right; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstxd", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_drf) = f_dest; + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + } +#endif #undef FLD return idesc; } - extract_sfmt_fstxp: + extract_sfmt_fstxs: { const IDESC *idesc = &sh64_media_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; @@ -1455,21 +2592,30 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_dest) = f_dest; FLD (f_left) = f_left; FLD (f_right) = f_right; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstxp", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstxs", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_frf) = f_dest; + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + } +#endif #undef FLD return idesc; } - extract_sfmt_fstxs: + extract_sfmt_ftrvs: { const IDESC *idesc = &sh64_media_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; @@ -1478,39 +2624,59 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_dest) = f_dest; FLD (f_left) = f_left; FLD (f_right) = f_right; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstxs", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ftrvs", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_fvf) = f_dest; + FLD (in_fvh) = f_right; + FLD (in_mtrxg) = f_left; + FLD (out_fvf) = f_dest; + FLD (out_fvh) = f_right; + FLD (out_mtrxg) = f_left; + } +#endif #undef FLD return idesc; } - extract_sfmt_ftrvs: + extract_sfmt_getcfg: { const IDESC *idesc = &sh64_media_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_add.f +#define FLD(f) abuf->fields.sfmt_getcfg.f UINT f_left; - UINT f_right; + INT f_disp6; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ - FLD (f_dest) = f_dest; + FLD (f_disp6) = f_disp6; FLD (f_left) = f_left; - FLD (f_right) = f_right; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ftrvs", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0)); + FLD (f_dest) = f_dest; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_getcfg", "f_disp6 0x%x", 'x', f_disp6, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1523,14 +2689,21 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_left; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_getcon", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1543,14 +2716,22 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_trb; UINT f_dest; - f_trb = EXTRACT_LSB0_UINT (insn, 32, 22, 3); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_trb = EXTRACT_MSB0_UINT (insn, 32, 9, 3); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_trb) = f_trb; FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_gettr", "f_trb 0x%x", 'x', f_trb, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_trb) = f_trb; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1564,9 +2745,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, INT f_disp10; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10 = EXTRACT_LSB0_INT (insn, 32, 19, 10); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp10 = EXTRACT_MSB0_INT (insn, 32, 12, 10); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp10) = f_disp10; @@ -1574,6 +2755,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_disp10 0x%x", 'x', f_disp10, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1587,9 +2776,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, SI f_disp10x4; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2)); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp10x4 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (2)); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp10x4) = f_disp10x4; @@ -1597,6 +2786,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldl", "f_disp10x4 0x%x", 'x', f_disp10x4, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1610,9 +2807,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, SI f_disp10x8; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp10x8 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (3)); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp10x8) = f_disp10x8; @@ -1620,6 +2817,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldq", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1633,9 +2838,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, SI f_disp10x2; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10x2 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (1)); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp10x2 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (1)); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp10x2) = f_disp10x2; @@ -1643,6 +2848,138 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lduw", "f_disp10x2 0x%x", 'x', f_disp10x2, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldhil: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_getcfg.f + UINT f_left; + INT f_disp6; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_disp6) = f_disp6; + FLD (f_left) = f_left; + FLD (f_dest) = f_dest; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldhil", "f_disp6 0x%x", 'x', f_disp6, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldhiq: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_getcfg.f + UINT f_left; + INT f_disp6; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_disp6) = f_disp6; + FLD (f_left) = f_left; + FLD (f_dest) = f_dest; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldhiq", "f_disp6 0x%x", 'x', f_disp6, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldlol: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_getcfg.f + UINT f_left; + INT f_disp6; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_disp6) = f_disp6; + FLD (f_left) = f_left; + FLD (f_dest) = f_dest; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldlol", "f_disp6 0x%x", 'x', f_disp6, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldloq: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_getcfg.f + UINT f_left; + INT f_disp6; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_disp6) = f_disp6; + FLD (f_left) = f_left; + FLD (f_dest) = f_dest; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldloq", "f_disp6 0x%x", 'x', f_disp6, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1656,9 +2993,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; @@ -1666,6 +3003,175 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxb", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (out_rd) = f_dest; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldxl: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_left; + UINT f_right; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_left) = f_left; + FLD (f_right) = f_right; + FLD (f_dest) = f_dest; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxl", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (out_rd) = f_dest; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldxq: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_left; + UINT f_right; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_left) = f_left; + FLD (f_right) = f_right; + FLD (f_dest) = f_dest; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxq", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (out_rd) = f_dest; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldxub: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_left; + UINT f_right; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_left) = f_left; + FLD (f_right) = f_right; + FLD (f_dest) = f_dest; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxub", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (out_rd) = f_dest; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldxuw: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_left; + UINT f_right; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_left) = f_left; + FLD (f_right) = f_right; + FLD (f_dest) = f_dest; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxuw", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (out_rd) = f_dest; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_ldxw: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_left; + UINT f_right; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_left) = f_left; + FLD (f_right) = f_right; + FLD (f_dest) = f_dest; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxw", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1679,9 +3185,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_dest) = f_dest; @@ -1689,6 +3195,16 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_right) = f_right; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcmv", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1701,14 +3217,21 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, INT f_imm16; UINT f_dest; - f_imm16 = EXTRACT_LSB0_INT (insn, 32, 25, 16); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_imm16 = EXTRACT_MSB0_INT (insn, 32, 6, 16); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_imm16) = f_imm16; FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movi", "f_imm16 0x%x", 'x', f_imm16, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1722,9 +3245,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; @@ -1732,6 +3255,28 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpermw", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (out_rd) = f_dest; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_nop: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; +#define FLD(f) abuf->fields.fmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0)); + #undef FLD return idesc; } @@ -1745,9 +3290,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, INT f_imm10; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_imm10 = EXTRACT_LSB0_INT (insn, 32, 19, 10); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_imm10 = EXTRACT_MSB0_INT (insn, 32, 12, 10); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_imm10) = f_imm10; @@ -1755,6 +3300,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ori", "f_imm10 0x%x", 'x', f_imm10, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1767,14 +3320,21 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, DI f_disp16; UINT f_tra; - f_disp16 = ((((EXTRACT_LSB0_INT (insn, 32, 25, 16)) << (2))) + (pc)); - f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); + f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 6, 16)) << (2))) + (pc)); + f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); /* Record the fields for the semantic handler. */ FLD (f_disp16) = f_disp16; FLD (f_tra) = f_tra; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_pta", "f_disp16 0x%x", 'x', f_disp16, "f_tra 0x%x", 'x', f_tra, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (out_tra) = f_tra; + } +#endif #undef FLD return idesc; } @@ -1787,14 +3347,22 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_tra; - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); /* Record the fields for the semantic handler. */ FLD (f_right) = f_right; FLD (f_tra) = f_tra; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ptabs", "f_right 0x%x", 'x', f_right, "f_tra 0x%x", 'x', f_tra, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_right; + FLD (out_tra) = f_tra; + } +#endif #undef FLD return idesc; } @@ -1807,14 +3375,53 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_tra; - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); /* Record the fields for the semantic handler. */ FLD (f_right) = f_right; FLD (f_tra) = f_tra; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ptrel", "f_right 0x%x", 'x', f_right, "f_tra 0x%x", 'x', f_tra, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rn) = f_right; + FLD (out_tra) = f_tra; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_putcfg: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_getcfg.f + UINT f_left; + INT f_disp6; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_disp6) = f_disp6; + FLD (f_dest) = f_dest; + FLD (f_left) = f_left; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_putcfg", "f_disp6 0x%x", 'x', f_disp6, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + } +#endif #undef FLD return idesc; } @@ -1827,14 +3434,21 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_left; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_putcon", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + } +#endif #undef FLD return idesc; } @@ -1848,9 +3462,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_uimm6; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_uimm6 = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_uimm6 = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; @@ -1858,6 +3472,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shari", "f_left 0x%x", 'x', f_left, "f_uimm6 0x%x", 'x', f_uimm6, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1871,9 +3493,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_uimm6; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_uimm6 = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_uimm6 = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; @@ -1881,6 +3503,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sharil", "f_left 0x%x", 'x', f_left, "f_uimm6 0x%x", 'x', f_uimm6, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1893,14 +3523,22 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_uimm16; UINT f_dest; - f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 25, 16); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 6, 16); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_dest) = f_dest; FLD (f_uimm16) = f_uimm16; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shori", "f_dest 0x%x", 'x', f_dest, "f_uimm16 0x%x", 'x', f_uimm16, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -1914,9 +3552,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, INT f_disp10; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10 = EXTRACT_LSB0_INT (insn, 32, 19, 10); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp10 = EXTRACT_MSB0_INT (insn, 32, 12, 10); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp10) = f_disp10; @@ -1924,6 +3562,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_left) = f_left; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_disp10 0x%x", 'x', f_disp10, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + } +#endif #undef FLD return idesc; } @@ -1937,9 +3583,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, SI f_disp10x4; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2)); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp10x4 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (2)); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp10x4) = f_disp10x4; @@ -1947,6 +3593,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_left) = f_left; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stl", "f_disp10x4 0x%x", 'x', f_disp10x4, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + } +#endif #undef FLD return idesc; } @@ -1960,9 +3614,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, SI f_disp10x8; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp10x8 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (3)); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp10x8) = f_disp10x8; @@ -1970,6 +3624,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_left) = f_left; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stq", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + } +#endif #undef FLD return idesc; } @@ -1983,9 +3645,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, SI f_disp10x2; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp10x2 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (1)); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp10x2 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (1)); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp10x2) = f_disp10x2; @@ -1993,6 +3655,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_left) = f_left; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stw", "f_disp10x2 0x%x", 'x', f_disp10x2, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + } +#endif #undef FLD return idesc; } @@ -2001,14 +3671,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, { const IDESC *idesc = &sh64_media_insn_data[itype]; CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_sthil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f UINT f_left; INT f_disp6; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_disp6 = EXTRACT_LSB0_INT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_disp6) = f_disp6; @@ -2016,6 +3686,107 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_left) = f_left; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sthil", "f_disp6 0x%x", 'x', f_disp6, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_sthiq: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_getcfg.f + UINT f_left; + INT f_disp6; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_disp6) = f_disp6; + FLD (f_dest) = f_dest; + FLD (f_left) = f_left; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sthiq", "f_disp6 0x%x", 'x', f_disp6, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stlol: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_getcfg.f + UINT f_left; + INT f_disp6; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_disp6) = f_disp6; + FLD (f_dest) = f_dest; + FLD (f_left) = f_left; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stlol", "f_disp6 0x%x", 'x', f_disp6, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stloq: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_getcfg.f + UINT f_left; + INT f_disp6; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_disp6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_disp6) = f_disp6; + FLD (f_dest) = f_dest; + FLD (f_left) = f_left; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stloq", "f_disp6 0x%x", 'x', f_disp6, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + } +#endif #undef FLD return idesc; } @@ -2029,9 +3800,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_dest) = f_dest; @@ -2039,6 +3810,111 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_right) = f_right; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxb", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stxl: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_left; + UINT f_right; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_dest) = f_dest; + FLD (f_left) = f_left; + FLD (f_right) = f_right; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxl", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stxq: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_left; + UINT f_right; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_dest) = f_dest; + FLD (f_left) = f_left; + FLD (f_right) = f_right; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxq", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_stxw: + { + const IDESC *idesc = &sh64_media_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_add.f + UINT f_left; + UINT f_right; + UINT f_dest; + + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_dest) = f_dest; + FLD (f_left) = f_left; + FLD (f_right) = f_right; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxw", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + } +#endif #undef FLD return idesc; } @@ -2052,9 +3928,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, UINT f_right; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_dest) = f_dest; @@ -2062,6 +3938,16 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_right) = f_right; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swapq", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rd) = f_dest; + FLD (in_rm) = f_left; + FLD (in_rn) = f_right; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } @@ -2073,12 +3959,19 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, #define FLD(f) abuf->fields.sfmt_xori.f UINT f_left; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); /* Record the fields for the semantic handler. */ FLD (f_left) = f_left; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trapa", "f_left 0x%x", 'x', f_left, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + } +#endif #undef FLD return idesc; } @@ -2092,9 +3985,9 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, INT f_imm6; UINT f_dest; - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); - f_imm6 = EXTRACT_LSB0_INT (insn, 32, 15, 6); - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); + f_imm6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); /* Record the fields for the semantic handler. */ FLD (f_imm6) = f_imm6; @@ -2102,6 +3995,14 @@ sh64_media_decode (SIM_CPU *current_cpu, IADDR pc, FLD (f_dest) = f_dest; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xori", "f_imm6 0x%x", 'x', f_imm6, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0)); +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_rm) = f_left; + FLD (out_rd) = f_dest; + } +#endif #undef FLD return idesc; } diff --git a/sim/sh64/decode-media.h b/sim/sh64/decode-media.h index 8a84d4e..bb69f89 100644 --- a/sim/sh64/decode-media.h +++ b/sim/sh64/decode-media.h @@ -2,9 +2,9 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -87,7 +87,7 @@ typedef enum sh64_media_insn_type { , SH64_MEDIA_INSN_STLOL, SH64_MEDIA_INSN_STLOQ, SH64_MEDIA_INSN_STXB, SH64_MEDIA_INSN_STXL , SH64_MEDIA_INSN_STXQ, SH64_MEDIA_INSN_STXW, SH64_MEDIA_INSN_SUB, SH64_MEDIA_INSN_SUBL , SH64_MEDIA_INSN_SWAPQ, SH64_MEDIA_INSN_SYNCI, SH64_MEDIA_INSN_SYNCO, SH64_MEDIA_INSN_TRAPA - , SH64_MEDIA_INSN_XOR, SH64_MEDIA_INSN_XORI, SH64_MEDIA_INSN_MAX + , SH64_MEDIA_INSN_XOR, SH64_MEDIA_INSN_XORI, SH64_MEDIA_INSN__MAX } SH64_MEDIA_INSN_TYPE; /* Enum declaration for semantic formats in cpu family sh64. */ @@ -96,23 +96,170 @@ typedef enum sh64_media_sfmt_type { , SH64_MEDIA_SFMT_BEQ, SH64_MEDIA_SFMT_BEQI, SH64_MEDIA_SFMT_BLINK, SH64_MEDIA_SFMT_BRK , SH64_MEDIA_SFMT_BYTEREV, SH64_MEDIA_SFMT_CMVEQ, SH64_MEDIA_SFMT_FABSD, SH64_MEDIA_SFMT_FABSS , SH64_MEDIA_SFMT_FADDD, SH64_MEDIA_SFMT_FADDS, SH64_MEDIA_SFMT_FCMPEQD, SH64_MEDIA_SFMT_FCMPEQS - , SH64_MEDIA_SFMT_FCNVDS, SH64_MEDIA_SFMT_FCNVSD, SH64_MEDIA_SFMT_FIPRS, SH64_MEDIA_SFMT_FLDD - , SH64_MEDIA_SFMT_FLDP, SH64_MEDIA_SFMT_FLDS, SH64_MEDIA_SFMT_FLDXD, SH64_MEDIA_SFMT_FLDXP - , SH64_MEDIA_SFMT_FLDXS, SH64_MEDIA_SFMT_FMACS, SH64_MEDIA_SFMT_FMOVDQ, SH64_MEDIA_SFMT_FMOVLS - , SH64_MEDIA_SFMT_FMOVQD, SH64_MEDIA_SFMT_FMOVSL, SH64_MEDIA_SFMT_FSTD, SH64_MEDIA_SFMT_FSTP - , SH64_MEDIA_SFMT_FSTS, SH64_MEDIA_SFMT_FSTXD, SH64_MEDIA_SFMT_FSTXP, SH64_MEDIA_SFMT_FSTXS - , SH64_MEDIA_SFMT_FTRVS, SH64_MEDIA_SFMT_GETCON, SH64_MEDIA_SFMT_GETTR, SH64_MEDIA_SFMT_LDB - , SH64_MEDIA_SFMT_LDL, SH64_MEDIA_SFMT_LDQ, SH64_MEDIA_SFMT_LDUW, SH64_MEDIA_SFMT_LDXB - , SH64_MEDIA_SFMT_MCMV, SH64_MEDIA_SFMT_MOVI, SH64_MEDIA_SFMT_MPERMW, SH64_MEDIA_SFMT_ORI - , SH64_MEDIA_SFMT_PTA, SH64_MEDIA_SFMT_PTABS, SH64_MEDIA_SFMT_PTREL, SH64_MEDIA_SFMT_PUTCON + , SH64_MEDIA_SFMT_FCNVDS, SH64_MEDIA_SFMT_FCNVSD, SH64_MEDIA_SFMT_FGETSCR, SH64_MEDIA_SFMT_FIPRS + , SH64_MEDIA_SFMT_FLDD, SH64_MEDIA_SFMT_FLDP, SH64_MEDIA_SFMT_FLDS, SH64_MEDIA_SFMT_FLDXD + , SH64_MEDIA_SFMT_FLDXP, SH64_MEDIA_SFMT_FLDXS, SH64_MEDIA_SFMT_FMACS, SH64_MEDIA_SFMT_FMOVDQ + , SH64_MEDIA_SFMT_FMOVLS, SH64_MEDIA_SFMT_FMOVQD, SH64_MEDIA_SFMT_FMOVSL, SH64_MEDIA_SFMT_FPUTSCR + , SH64_MEDIA_SFMT_FSTD, SH64_MEDIA_SFMT_FSTS, SH64_MEDIA_SFMT_FSTXD, SH64_MEDIA_SFMT_FSTXS + , SH64_MEDIA_SFMT_FTRVS, SH64_MEDIA_SFMT_GETCFG, SH64_MEDIA_SFMT_GETCON, SH64_MEDIA_SFMT_GETTR + , SH64_MEDIA_SFMT_LDB, SH64_MEDIA_SFMT_LDL, SH64_MEDIA_SFMT_LDQ, SH64_MEDIA_SFMT_LDUW + , SH64_MEDIA_SFMT_LDHIL, SH64_MEDIA_SFMT_LDHIQ, SH64_MEDIA_SFMT_LDLOL, SH64_MEDIA_SFMT_LDLOQ + , SH64_MEDIA_SFMT_LDXB, SH64_MEDIA_SFMT_LDXL, SH64_MEDIA_SFMT_LDXQ, SH64_MEDIA_SFMT_LDXUB + , SH64_MEDIA_SFMT_LDXUW, SH64_MEDIA_SFMT_LDXW, SH64_MEDIA_SFMT_MCMV, SH64_MEDIA_SFMT_MOVI + , SH64_MEDIA_SFMT_MPERMW, SH64_MEDIA_SFMT_NOP, SH64_MEDIA_SFMT_ORI, SH64_MEDIA_SFMT_PTA + , SH64_MEDIA_SFMT_PTABS, SH64_MEDIA_SFMT_PTREL, SH64_MEDIA_SFMT_PUTCFG, SH64_MEDIA_SFMT_PUTCON , SH64_MEDIA_SFMT_SHARI, SH64_MEDIA_SFMT_SHARIL, SH64_MEDIA_SFMT_SHORI, SH64_MEDIA_SFMT_STB , SH64_MEDIA_SFMT_STL, SH64_MEDIA_SFMT_STQ, SH64_MEDIA_SFMT_STW, SH64_MEDIA_SFMT_STHIL - , SH64_MEDIA_SFMT_STXB, SH64_MEDIA_SFMT_SWAPQ, SH64_MEDIA_SFMT_TRAPA, SH64_MEDIA_SFMT_XORI + , SH64_MEDIA_SFMT_STHIQ, SH64_MEDIA_SFMT_STLOL, SH64_MEDIA_SFMT_STLOQ, SH64_MEDIA_SFMT_STXB + , SH64_MEDIA_SFMT_STXL, SH64_MEDIA_SFMT_STXQ, SH64_MEDIA_SFMT_STXW, SH64_MEDIA_SFMT_SWAPQ + , SH64_MEDIA_SFMT_TRAPA, SH64_MEDIA_SFMT_XORI } SH64_MEDIA_SFMT_TYPE; /* Function unit handlers (user written). */ +extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/); +extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/); +extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_fcnv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_fcmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_fsqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_fdiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_fpu_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_use_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_ldsl_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_lds_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_use_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_flds_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_load_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_set_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_fpu_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_use_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_u_set_fr_0 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_set_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_load_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_maybe_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_write_back (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_use_multiply_result (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_shift (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_tas (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_mulsw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_mull (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_dmul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_macl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_macw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_set_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_load_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_load_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_load_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_use_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_u_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_u_stc_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_ldcl_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_ldcl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_use_tbit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_ldc_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_ldc_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_set_sr_bit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_use_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_load_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_sts_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_lds_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_logic_b (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_jsr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_jmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_u_sx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); extern int sh64_model_sh5_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_putcfg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_getcfg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_pt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/); +extern int sh64_model_sh5_media_u_ftrvs (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_fsqrtd (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_fdivd (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_cond_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/); +extern int sh64_model_sh5_media_u_blink (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/); +extern int sh64_model_sh5_media_u_use_tr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_media_u_use_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_media_u_use_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_media_u_use_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_media_u_load_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_load_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_load_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_set_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_set_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_set_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_set_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/); +extern int sh64_model_sh5_media_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/); +extern int sh64_model_sh5_media_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_media_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_fcnv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_fcmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_fsqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_fdiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_fpu_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_use_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_ldsl_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_lds_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_use_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_flds_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_load_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_set_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_fpu_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_use_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_media_u_set_fr_0 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_set_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_load_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_maybe_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_write_back (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_use_multiply_result (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_shift (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_tas (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_mulsw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_mull (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_dmul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_macl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_macw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_set_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_load_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_load_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_load_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_use_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/); +extern int sh64_model_sh5_media_u_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/); +extern int sh64_model_sh5_media_u_stc_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_ldcl_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_ldcl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_use_tbit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_ldc_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_ldc_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_set_sr_bit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_use_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_load_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_sts_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_lds_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_logic_b (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_jsr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_jmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_sx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int sh64_model_sh5_media_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); /* Profiling before/after handlers (user written) */ diff --git a/sim/sh64/defs-compact.h b/sim/sh64/defs-compact.h index fb0b7e4..5ae3afa 100644 --- a/sim/sh64/defs-compact.h +++ b/sim/sh64/defs-compact.h @@ -2,9 +2,9 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -32,25 +32,18 @@ union sem_fields { int empty; } fmt_empty; struct { /* */ - SI f_dn; - } sfmt_fcnvds_compact; - struct { /* */ IADDR i_disp12; } sfmt_bra_compact; struct { /* */ IADDR i_disp8; } sfmt_bf_compact; struct { /* */ - SI f_imm4x2; - UINT f_rm; - } sfmt_movw11_compact; - struct { /* */ SI f_imm8x2; UINT f_rn; } sfmt_movw10_compact; struct { /* */ SI f_imm4x2; - UINT f_rn; + UINT f_rm; } sfmt_movw5_compact; struct { /* */ SI f_imm8x4; @@ -61,6 +54,10 @@ union sem_fields { UINT f_rm; } sfmt_movb5_compact; struct { /* */ + INT f_imm20; + UINT f_rn; + } sfmt_movi20_compact; + struct { /* */ SI f_vm; SI f_vn; } sfmt_fipr_compact; @@ -69,10 +66,25 @@ union sem_fields { UINT f_rn; } sfmt_addi_compact; struct { /* */ + SI f_imm12x4; + UINT f_rm; + UINT f_rn; + } sfmt_movl12_compact; + struct { /* */ SI f_imm4x4; UINT f_rm; UINT f_rn; } sfmt_movl5_compact; + struct { /* */ + SI f_dm; + SI f_imm12x8; + UINT f_rn; + } sfmt_fmov9_compact; + struct { /* */ + SI f_dn; + SI f_imm12x8; + UINT f_rm; + } sfmt_fmov8_compact; #if WITH_SCACHE_PBB /* Writeback handler. */ struct { @@ -141,10 +153,10 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_ADD_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \ - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \ - f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_ADDI_COMPACT_VARS \ UINT f_op4; \ @@ -153,9 +165,9 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_ADDI_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \ - f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_AND_COMPACT_VARS \ UINT f_op4; \ @@ -165,10 +177,10 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_AND_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \ - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \ - f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_ANDI_COMPACT_VARS \ UINT f_op8; \ @@ -176,8 +188,8 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_ANDI_COMPACT_CODE \ length = 2; \ - f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \ - f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \ + f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \ + f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_ANDB_COMPACT_VARS \ UINT f_op8; \ @@ -185,8 +197,8 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_ANDB_COMPACT_CODE \ length = 2; \ - f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \ - f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \ + f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \ + f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_BF_COMPACT_VARS \ UINT f_op8; \ @@ -194,8 +206,8 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_BF_COMPACT_CODE \ length = 2; \ - f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \ - f_disp8 = ((((EXTRACT_LSB0_INT (insn, 16, 7, 8)) << (1))) + (((pc) + (4)))); \ + f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \ + f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (4)))); \ #define EXTRACT_IFMT_BRA_COMPACT_VARS \ UINT f_op4; \ @@ -203,8 +215,8 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_BRA_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_disp12 = ((((EXTRACT_LSB0_INT (insn, 16, 11, 12)) << (1))) + (((pc) + (4)))); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_disp12 = ((((EXTRACT_MSB0_INT (insn, 16, 4, 12)) << (1))) + (((pc) + (4)))); \ #define EXTRACT_IFMT_BRAF_COMPACT_VARS \ UINT f_op4; \ @@ -213,16 +225,16 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_BRAF_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \ - f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_BRK_COMPACT_VARS \ UINT f_op16; \ unsigned int length; #define EXTRACT_IFMT_BRK_COMPACT_CODE \ length = 2; \ - f_op16 = EXTRACT_LSB0_UINT (insn, 16, 15, 16); \ + f_op16 = EXTRACT_MSB0_UINT (insn, 16, 0, 16); \ #define EXTRACT_IFMT_FABS_COMPACT_VARS \ UINT f_op4; \ @@ -231,9 +243,9 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FABS_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \ - f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_FADD_COMPACT_VARS \ UINT f_op4; \ @@ -243,23 +255,23 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FADD_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \ - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \ - f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_FCNVDS_COMPACT_VARS \ UINT f_op4; \ SI f_dn; \ - UINT f_8_1; \ + UINT f_7_1; \ UINT f_sub8; \ unsigned int length; #define EXTRACT_IFMT_FCNVDS_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_dn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 3)) << (1)); \ - f_8_1 = EXTRACT_LSB0_UINT (insn, 16, 8, 1); \ - f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_dn = ((EXTRACT_MSB0_UINT (insn, 16, 4, 3)) << (1)); \ + f_7_1 = EXTRACT_MSB0_UINT (insn, 16, 7, 1); \ + f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_FIPR_COMPACT_VARS \ UINT f_op4; \ @@ -269,10 +281,10 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FIPR_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_vn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 2)) << (2)); \ - f_vm = ((EXTRACT_LSB0_UINT (insn, 16, 9, 2)) << (2)); \ - f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_vn = ((EXTRACT_MSB0_UINT (insn, 16, 4, 2)) << (2)); \ + f_vm = ((EXTRACT_MSB0_UINT (insn, 16, 6, 2)) << (2)); \ + f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_FLDS_COMPACT_VARS \ UINT f_op4; \ @@ -281,9 +293,9 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FLDS_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \ - f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \ #define EXTRACT_IFMT_FMAC_COMPACT_VARS \ UINT f_op4; \ @@ -293,10 +305,23 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FMAC_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \ - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \ - f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ + +#define EXTRACT_IFMT_FMOV1_COMPACT_VARS \ + UINT f_op4; \ + UINT f_rn; \ + UINT f_rm; \ + UINT f_sub4; \ + unsigned int length; +#define EXTRACT_IFMT_FMOV1_COMPACT_CODE \ + length = 2; \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_FMOV2_COMPACT_VARS \ UINT f_op4; \ @@ -306,10 +331,10 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FMOV2_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \ - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \ - f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_FMOV5_COMPACT_VARS \ UINT f_op4; \ @@ -319,10 +344,48 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FMOV5_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \ - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \ - f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ + +#define EXTRACT_IFMT_FMOV8_COMPACT_VARS \ + UINT f_op4; \ + SI f_dn; \ + UINT f_7_1; \ + UINT f_rm; \ + UINT f_sub4; \ + UINT f_16_4; \ + SI f_imm12x8; \ + unsigned int length; +#define EXTRACT_IFMT_FMOV8_COMPACT_CODE \ + length = 4; \ + f_op4 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_dn = ((EXTRACT_MSB0_UINT (insn, 32, 4, 3)) << (1)); \ + f_7_1 = EXTRACT_MSB0_UINT (insn, 32, 7, 1); \ + f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_sub4 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_16_4 = EXTRACT_MSB0_UINT (insn, 32, 16, 4); \ + f_imm12x8 = ((EXTRACT_MSB0_INT (insn, 32, 20, 12)) << (3)); \ + +#define EXTRACT_IFMT_FMOV9_COMPACT_VARS \ + UINT f_op4; \ + UINT f_rn; \ + SI f_dm; \ + UINT f_11_1; \ + UINT f_sub4; \ + UINT f_16_4; \ + SI f_imm12x8; \ + unsigned int length; +#define EXTRACT_IFMT_FMOV9_COMPACT_CODE \ + length = 4; \ + f_op4 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_dm = ((EXTRACT_MSB0_UINT (insn, 32, 8, 3)) << (1)); \ + f_11_1 = EXTRACT_MSB0_UINT (insn, 32, 11, 1); \ + f_sub4 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_16_4 = EXTRACT_MSB0_UINT (insn, 32, 16, 4); \ + f_imm12x8 = ((EXTRACT_MSB0_INT (insn, 32, 20, 12)) << (3)); \ #define EXTRACT_IFMT_FTRV_COMPACT_VARS \ UINT f_op4; \ @@ -331,9 +394,26 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FTRV_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_vn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 2)) << (2)); \ - f_sub10 = EXTRACT_LSB0_UINT (insn, 16, 9, 10); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_vn = ((EXTRACT_MSB0_UINT (insn, 16, 4, 2)) << (2)); \ + f_sub10 = EXTRACT_MSB0_UINT (insn, 16, 6, 10); \ + +#define EXTRACT_IFMT_MOVI20_COMPACT_VARS \ + UINT f_op4; \ + UINT f_rn; \ + INT f_imm20_hi; \ + UINT f_imm20_lo; \ + INT f_imm20; \ + UINT f_sub4; \ + unsigned int length; +#define EXTRACT_IFMT_MOVI20_COMPACT_CODE \ + length = 4; \ + f_op4 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_imm20_hi = EXTRACT_MSB0_INT (insn, 32, 8, 4); \ + f_imm20_lo = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \ + f_imm20 = ((((f_imm20_hi) << (16))) | (f_imm20_lo));\ + f_sub4 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ #define EXTRACT_IFMT_MOVB5_COMPACT_VARS \ UINT f_op8; \ @@ -342,9 +422,9 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MOVB5_COMPACT_CODE \ length = 2; \ - f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \ - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \ - f_imm4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ + f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \ + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_imm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \ #define EXTRACT_IFMT_MOVL4_COMPACT_VARS \ UINT f_op8; \ @@ -352,8 +432,8 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MOVL4_COMPACT_CODE \ length = 2; \ - f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \ - f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2)); \ + f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \ + f_imm8x4 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \ #define EXTRACT_IFMT_MOVL5_COMPACT_VARS \ UINT f_op4; \ @@ -363,10 +443,10 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MOVL5_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \ - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \ - f_imm4x4 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (2)); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_imm4x4 = ((EXTRACT_MSB0_UINT (insn, 16, 12, 4)) << (2)); \ #define EXTRACT_IFMT_MOVL10_COMPACT_VARS \ UINT f_op4; \ @@ -375,9 +455,26 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MOVL10_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \ - f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2)); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_imm8x4 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \ + +#define EXTRACT_IFMT_MOVL12_COMPACT_VARS \ + UINT f_op4; \ + UINT f_rn; \ + UINT f_rm; \ + UINT f_sub4; \ + UINT f_16_4; \ + SI f_imm12x4; \ + unsigned int length; +#define EXTRACT_IFMT_MOVL12_COMPACT_CODE \ + length = 4; \ + f_op4 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \ + f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \ + f_sub4 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_16_4 = EXTRACT_MSB0_UINT (insn, 32, 16, 4); \ + f_imm12x4 = ((EXTRACT_MSB0_INT (insn, 32, 20, 12)) << (2)); \ #define EXTRACT_IFMT_MOVW4_COMPACT_VARS \ UINT f_op8; \ @@ -385,19 +482,19 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MOVW4_COMPACT_CODE \ length = 2; \ - f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \ - f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1)); \ + f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \ + f_imm8x2 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); \ #define EXTRACT_IFMT_MOVW5_COMPACT_VARS \ UINT f_op8; \ - UINT f_rn; \ + UINT f_rm; \ SI f_imm4x2; \ unsigned int length; #define EXTRACT_IFMT_MOVW5_COMPACT_CODE \ length = 2; \ - f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \ - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \ - f_imm4x2 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)); \ + f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \ + f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \ + f_imm4x2 = ((EXTRACT_MSB0_UINT (insn, 16, 12, 4)) << (1)); \ #define EXTRACT_IFMT_MOVW10_COMPACT_VARS \ UINT f_op4; \ @@ -406,19 +503,8 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MOVW10_COMPACT_CODE \ length = 2; \ - f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ - f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \ - f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1)); \ - -#define EXTRACT_IFMT_MOVW11_COMPACT_VARS \ - UINT f_op8; \ - UINT f_rm; \ - SI f_imm4x2; \ - unsigned int length; -#define EXTRACT_IFMT_MOVW11_COMPACT_CODE \ - length = 2; \ - f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \ - f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \ - f_imm4x2 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)); \ + f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \ + f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \ + f_imm8x2 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); \ #endif /* DEFS_SH64_COMPACT_H */ diff --git a/sim/sh64/defs-media.h b/sim/sh64/defs-media.h index 7e749f9..b3f6c59 100644 --- a/sim/sh64/defs-media.h +++ b/sim/sh64/defs-media.h @@ -2,9 +2,9 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -57,11 +57,6 @@ union sem_fields { UINT f_left; } sfmt_xori; struct { /* */ - INT f_disp6; - UINT f_dest; - UINT f_left; - } sfmt_sthil; - struct { /* */ UINT f_dest; UINT f_left; UINT f_uimm6; @@ -77,6 +72,11 @@ union sem_fields { UINT f_left; } sfmt_lduw; struct { /* */ + INT f_disp6; + UINT f_dest; + UINT f_left; + } sfmt_getcfg; + struct { /* */ SI f_disp10x4; UINT f_dest; UINT f_left; @@ -106,11 +106,6 @@ union sem_fields { UINT f_left; UINT f_right; } sfmt_add; - struct { - INT f_disp6; - UINT f_dest; - UINT f_left; - } sfmt_ldhil; #if WITH_SCACHE_PBB /* Writeback handler. */ struct { @@ -181,12 +176,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_ADD_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_ADDI_VARS \ UINT f_op; \ @@ -197,11 +192,11 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_ADDI_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_disp10 = EXTRACT_LSB0_INT (insn, 32, 19, 10); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_disp10 = EXTRACT_MSB0_INT (insn, 32, 12, 10); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_ALLOCO_VARS \ UINT f_op; \ @@ -213,12 +208,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_ALLOCO_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_disp6x32 = ((EXTRACT_LSB0_INT (insn, 32, 15, 6)) << (5)); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_disp6x32 = ((EXTRACT_MSB0_INT (insn, 32, 16, 6)) << (5)); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_BEQ_VARS \ UINT f_op; \ @@ -226,20 +221,20 @@ struct scache { UINT f_ext; \ UINT f_right; \ UINT f_likely; \ - UINT f_8_2; \ + UINT f_23_2; \ UINT f_tra; \ UINT f_rsvd; \ unsigned int length; #define EXTRACT_IFMT_BEQ_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \ - f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \ - f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_likely = EXTRACT_MSB0_UINT (insn, 32, 22, 1); \ + f_23_2 = EXTRACT_MSB0_UINT (insn, 32, 23, 2); \ + f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_BEQI_VARS \ UINT f_op; \ @@ -247,24 +242,24 @@ struct scache { UINT f_ext; \ INT f_imm6; \ UINT f_likely; \ - UINT f_8_2; \ + UINT f_23_2; \ UINT f_tra; \ UINT f_rsvd; \ unsigned int length; #define EXTRACT_IFMT_BEQI_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_imm6 = EXTRACT_LSB0_INT (insn, 32, 15, 6); \ - f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \ - f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \ - f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_imm6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); \ + f_likely = EXTRACT_MSB0_UINT (insn, 32, 22, 1); \ + f_23_2 = EXTRACT_MSB0_UINT (insn, 32, 23, 2); \ + f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_BLINK_VARS \ UINT f_op; \ - UINT f_25; \ + UINT f_6_3; \ UINT f_trb; \ UINT f_ext; \ UINT f_right; \ @@ -273,13 +268,13 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_BLINK_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_25 = EXTRACT_LSB0_UINT (insn, 32, 25, 3); \ - f_trb = EXTRACT_LSB0_UINT (insn, 32, 22, 3); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_6_3 = EXTRACT_MSB0_UINT (insn, 32, 6, 3); \ + f_trb = EXTRACT_MSB0_UINT (insn, 32, 9, 3); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_BRK_VARS \ UINT f_op; \ @@ -291,12 +286,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_BRK_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_BYTEREV_VARS \ UINT f_op; \ @@ -308,50 +303,50 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_BYTEREV_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FABSD_VARS \ UINT f_op; \ - UINT f_ext; \ UINT f_left; \ UINT f_right; \ UINT f_left_right; \ + UINT f_ext; \ UINT f_dest; \ UINT f_rsvd; \ unsigned int length; #define EXTRACT_IFMT_FABSD_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ f_left_right = f_left;\ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FABSS_VARS \ UINT f_op; \ - UINT f_ext; \ UINT f_left; \ UINT f_right; \ UINT f_left_right; \ + UINT f_ext; \ UINT f_dest; \ UINT f_rsvd; \ unsigned int length; #define EXTRACT_IFMT_FABSS_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ f_left_right = f_left;\ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FADDD_VARS \ UINT f_op; \ @@ -363,12 +358,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FADDD_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FADDS_VARS \ UINT f_op; \ @@ -380,12 +375,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FADDS_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FCMPEQD_VARS \ UINT f_op; \ @@ -397,12 +392,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FCMPEQD_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FCMPEQS_VARS \ UINT f_op; \ @@ -414,50 +409,50 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FCMPEQS_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FCNVDS_VARS \ UINT f_op; \ - UINT f_ext; \ UINT f_left; \ UINT f_right; \ UINT f_left_right; \ + UINT f_ext; \ UINT f_dest; \ UINT f_rsvd; \ unsigned int length; #define EXTRACT_IFMT_FCNVDS_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ f_left_right = f_left;\ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FCNVSD_VARS \ UINT f_op; \ - UINT f_ext; \ UINT f_left; \ UINT f_right; \ UINT f_left_right; \ + UINT f_ext; \ UINT f_dest; \ UINT f_rsvd; \ unsigned int length; #define EXTRACT_IFMT_FCNVSD_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ f_left_right = f_left;\ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FGETSCR_VARS \ UINT f_op; \ @@ -469,12 +464,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FGETSCR_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FIPRS_VARS \ UINT f_op; \ @@ -486,12 +481,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FIPRS_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FLDD_VARS \ UINT f_op; \ @@ -502,11 +497,11 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FLDD_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_disp10x8 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (3)); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FLDP_VARS \ UINT f_op; \ @@ -517,11 +512,11 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FLDP_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_disp10x8 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (3)); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FLDS_VARS \ UINT f_op; \ @@ -532,11 +527,11 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FLDS_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2)); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_disp10x4 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (2)); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FLDXD_VARS \ UINT f_op; \ @@ -548,12 +543,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FLDXD_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FLDXP_VARS \ UINT f_op; \ @@ -565,31 +560,31 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FLDXP_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FMOVDQ_VARS \ UINT f_op; \ - UINT f_ext; \ UINT f_left; \ UINT f_right; \ UINT f_left_right; \ + UINT f_ext; \ UINT f_dest; \ UINT f_rsvd; \ unsigned int length; #define EXTRACT_IFMT_FMOVDQ_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ f_left_right = f_left;\ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FMOVLS_VARS \ UINT f_op; \ @@ -601,50 +596,50 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FMOVLS_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FMOVSL_VARS \ UINT f_op; \ - UINT f_ext; \ UINT f_left; \ UINT f_right; \ UINT f_left_right; \ + UINT f_ext; \ UINT f_dest; \ UINT f_rsvd; \ unsigned int length; #define EXTRACT_IFMT_FMOVSL_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ f_left_right = f_left;\ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FPUTSCR_VARS \ UINT f_op; \ - UINT f_ext; \ UINT f_left; \ UINT f_right; \ UINT f_left_right; \ + UINT f_ext; \ UINT f_dest; \ UINT f_rsvd; \ unsigned int length; #define EXTRACT_IFMT_FPUTSCR_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ f_left_right = f_left;\ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FSTXD_VARS \ UINT f_op; \ @@ -656,12 +651,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FSTXD_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_FTRVS_VARS \ UINT f_op; \ @@ -673,12 +668,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_FTRVS_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_GETCFG_VARS \ UINT f_op; \ @@ -690,12 +685,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_GETCFG_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_disp6 = EXTRACT_LSB0_INT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_disp6 = EXTRACT_MSB0_INT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_GETCON_VARS \ UINT f_op; \ @@ -707,12 +702,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_GETCON_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_LDL_VARS \ UINT f_op; \ @@ -723,11 +718,11 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_LDL_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2)); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_disp10x4 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (2)); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_LDQ_VARS \ UINT f_op; \ @@ -738,11 +733,11 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_LDQ_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_disp10x8 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (3)); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_MMACNFX_WL_VARS \ UINT f_op; \ @@ -754,12 +749,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MMACNFX_WL_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_MOVI_VARS \ UINT f_op; \ @@ -769,10 +764,10 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_MOVI_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_imm16 = EXTRACT_LSB0_INT (insn, 32, 25, 16); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_imm16 = EXTRACT_MSB0_INT (insn, 32, 6, 16); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_ORI_VARS \ UINT f_op; \ @@ -783,11 +778,11 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_ORI_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_imm10 = EXTRACT_LSB0_INT (insn, 32, 19, 10); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_imm10 = EXTRACT_MSB0_INT (insn, 32, 12, 10); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_PREFI_VARS \ UINT f_op; \ @@ -799,29 +794,29 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_PREFI_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_disp6x32 = ((EXTRACT_LSB0_INT (insn, 32, 15, 6)) << (5)); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_disp6x32 = ((EXTRACT_MSB0_INT (insn, 32, 16, 6)) << (5)); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_PTA_VARS \ UINT f_op; \ DI f_disp16; \ UINT f_likely; \ - UINT f_8_2; \ + UINT f_23_2; \ UINT f_tra; \ UINT f_rsvd; \ unsigned int length; #define EXTRACT_IFMT_PTA_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_disp16 = ((((EXTRACT_LSB0_INT (insn, 32, 25, 16)) << (2))) + (pc)); \ - f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \ - f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \ - f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 6, 16)) << (2))) + (pc)); \ + f_likely = EXTRACT_MSB0_UINT (insn, 32, 22, 1); \ + f_23_2 = EXTRACT_MSB0_UINT (insn, 32, 23, 2); \ + f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_PTABS_VARS \ UINT f_op; \ @@ -829,20 +824,20 @@ struct scache { UINT f_ext; \ UINT f_right; \ UINT f_likely; \ - UINT f_8_2; \ + UINT f_23_2; \ UINT f_tra; \ UINT f_rsvd; \ unsigned int length; #define EXTRACT_IFMT_PTABS_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \ - f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \ - f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_likely = EXTRACT_MSB0_UINT (insn, 32, 22, 1); \ + f_23_2 = EXTRACT_MSB0_UINT (insn, 32, 23, 2); \ + f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_PUTCON_VARS \ UINT f_op; \ @@ -854,12 +849,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_PUTCON_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_SHARI_VARS \ UINT f_op; \ @@ -871,12 +866,12 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_SHARI_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_uimm6 = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_uimm6 = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_SHORI_VARS \ UINT f_op; \ @@ -886,10 +881,10 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_SHORI_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 25, 16); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 6, 16); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_STW_VARS \ UINT f_op; \ @@ -900,11 +895,11 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_STW_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_disp10x2 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (1)); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_disp10x2 = ((EXTRACT_MSB0_INT (insn, 32, 12, 10)) << (1)); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #define EXTRACT_IFMT_TRAPA_VARS \ UINT f_op; \ @@ -916,11 +911,11 @@ struct scache { unsigned int length; #define EXTRACT_IFMT_TRAPA_CODE \ length = 4; \ - f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ - f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \ - f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \ - f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \ - f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \ - f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \ + f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \ + f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \ + f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \ + f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \ + f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \ #endif /* DEFS_SH64_MEDIA_H */ diff --git a/sim/sh64/sem-compact-switch.c b/sim/sh64/sem-compact-switch.c index 59270e8..34f952a 100644 --- a/sim/sh64/sem-compact-switch.c +++ b/sim/sh64/sem-compact-switch.c @@ -2,9 +2,9 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -69,6 +69,8 @@ with this program; if not, write to the Free Software Foundation, Inc., { SH64_COMPACT_INSN_DIV0S_COMPACT, && case_sem_INSN_DIV0S_COMPACT }, { SH64_COMPACT_INSN_DIV0U_COMPACT, && case_sem_INSN_DIV0U_COMPACT }, { SH64_COMPACT_INSN_DIV1_COMPACT, && case_sem_INSN_DIV1_COMPACT }, + { SH64_COMPACT_INSN_DIVU_COMPACT, && case_sem_INSN_DIVU_COMPACT }, + { SH64_COMPACT_INSN_MULR_COMPACT, && case_sem_INSN_MULR_COMPACT }, { SH64_COMPACT_INSN_DMULSL_COMPACT, && case_sem_INSN_DMULSL_COMPACT }, { SH64_COMPACT_INSN_DMULUL_COMPACT, && case_sem_INSN_DMULUL_COMPACT }, { SH64_COMPACT_INSN_DT_COMPACT, && case_sem_INSN_DT_COMPACT }, @@ -96,6 +98,8 @@ with this program; if not, write to the Free Software Foundation, Inc., { SH64_COMPACT_INSN_FMOV5_COMPACT, && case_sem_INSN_FMOV5_COMPACT }, { SH64_COMPACT_INSN_FMOV6_COMPACT, && case_sem_INSN_FMOV6_COMPACT }, { SH64_COMPACT_INSN_FMOV7_COMPACT, && case_sem_INSN_FMOV7_COMPACT }, + { SH64_COMPACT_INSN_FMOV8_COMPACT, && case_sem_INSN_FMOV8_COMPACT }, + { SH64_COMPACT_INSN_FMOV9_COMPACT, && case_sem_INSN_FMOV9_COMPACT }, { SH64_COMPACT_INSN_FMUL_COMPACT, && case_sem_INSN_FMUL_COMPACT }, { SH64_COMPACT_INSN_FNEG_COMPACT, && case_sem_INSN_FNEG_COMPACT }, { SH64_COMPACT_INSN_FRCHG_COMPACT, && case_sem_INSN_FRCHG_COMPACT }, @@ -107,8 +111,11 @@ with this program; if not, write to the Free Software Foundation, Inc., { SH64_COMPACT_INSN_FTRV_COMPACT, && case_sem_INSN_FTRV_COMPACT }, { SH64_COMPACT_INSN_JMP_COMPACT, && case_sem_INSN_JMP_COMPACT }, { SH64_COMPACT_INSN_JSR_COMPACT, && case_sem_INSN_JSR_COMPACT }, - { SH64_COMPACT_INSN_LDC_COMPACT, && case_sem_INSN_LDC_COMPACT }, - { SH64_COMPACT_INSN_LDCL_COMPACT, && case_sem_INSN_LDCL_COMPACT }, + { SH64_COMPACT_INSN_LDC_GBR_COMPACT, && case_sem_INSN_LDC_GBR_COMPACT }, + { SH64_COMPACT_INSN_LDC_VBR_COMPACT, && case_sem_INSN_LDC_VBR_COMPACT }, + { SH64_COMPACT_INSN_LDC_SR_COMPACT, && case_sem_INSN_LDC_SR_COMPACT }, + { SH64_COMPACT_INSN_LDCL_GBR_COMPACT, && case_sem_INSN_LDCL_GBR_COMPACT }, + { SH64_COMPACT_INSN_LDCL_VBR_COMPACT, && case_sem_INSN_LDCL_VBR_COMPACT }, { SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, && case_sem_INSN_LDS_FPSCR_COMPACT }, { SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, && case_sem_INSN_LDSL_FPSCR_COMPACT }, { SH64_COMPACT_INSN_LDS_FPUL_COMPACT, && case_sem_INSN_LDS_FPUL_COMPACT }, @@ -123,6 +130,7 @@ with this program; if not, write to the Free Software Foundation, Inc., { SH64_COMPACT_INSN_MACW_COMPACT, && case_sem_INSN_MACW_COMPACT }, { SH64_COMPACT_INSN_MOV_COMPACT, && case_sem_INSN_MOV_COMPACT }, { SH64_COMPACT_INSN_MOVI_COMPACT, && case_sem_INSN_MOVI_COMPACT }, + { SH64_COMPACT_INSN_MOVI20_COMPACT, && case_sem_INSN_MOVI20_COMPACT }, { SH64_COMPACT_INSN_MOVB1_COMPACT, && case_sem_INSN_MOVB1_COMPACT }, { SH64_COMPACT_INSN_MOVB2_COMPACT, && case_sem_INSN_MOVB2_COMPACT }, { SH64_COMPACT_INSN_MOVB3_COMPACT, && case_sem_INSN_MOVB3_COMPACT }, @@ -144,6 +152,8 @@ with this program; if not, write to the Free Software Foundation, Inc., { SH64_COMPACT_INSN_MOVL9_COMPACT, && case_sem_INSN_MOVL9_COMPACT }, { SH64_COMPACT_INSN_MOVL10_COMPACT, && case_sem_INSN_MOVL10_COMPACT }, { SH64_COMPACT_INSN_MOVL11_COMPACT, && case_sem_INSN_MOVL11_COMPACT }, + { SH64_COMPACT_INSN_MOVL12_COMPACT, && case_sem_INSN_MOVL12_COMPACT }, + { SH64_COMPACT_INSN_MOVL13_COMPACT, && case_sem_INSN_MOVL13_COMPACT }, { SH64_COMPACT_INSN_MOVW1_COMPACT, && case_sem_INSN_MOVW1_COMPACT }, { SH64_COMPACT_INSN_MOVW2_COMPACT, && case_sem_INSN_MOVW2_COMPACT }, { SH64_COMPACT_INSN_MOVW3_COMPACT, && case_sem_INSN_MOVW3_COMPACT }, @@ -157,7 +167,10 @@ with this program; if not, write to the Free Software Foundation, Inc., { SH64_COMPACT_INSN_MOVW11_COMPACT, && case_sem_INSN_MOVW11_COMPACT }, { SH64_COMPACT_INSN_MOVA_COMPACT, && case_sem_INSN_MOVA_COMPACT }, { SH64_COMPACT_INSN_MOVCAL_COMPACT, && case_sem_INSN_MOVCAL_COMPACT }, + { SH64_COMPACT_INSN_MOVCOL_COMPACT, && case_sem_INSN_MOVCOL_COMPACT }, { SH64_COMPACT_INSN_MOVT_COMPACT, && case_sem_INSN_MOVT_COMPACT }, + { SH64_COMPACT_INSN_MOVUAL_COMPACT, && case_sem_INSN_MOVUAL_COMPACT }, + { SH64_COMPACT_INSN_MOVUAL2_COMPACT, && case_sem_INSN_MOVUAL2_COMPACT }, { SH64_COMPACT_INSN_MULL_COMPACT, && case_sem_INSN_MULL_COMPACT }, { SH64_COMPACT_INSN_MULSW_COMPACT, && case_sem_INSN_MULSW_COMPACT }, { SH64_COMPACT_INSN_MULUW_COMPACT, && case_sem_INSN_MULUW_COMPACT }, @@ -192,7 +205,9 @@ with this program; if not, write to the Free Software Foundation, Inc., { SH64_COMPACT_INSN_SHLR8_COMPACT, && case_sem_INSN_SHLR8_COMPACT }, { SH64_COMPACT_INSN_SHLR16_COMPACT, && case_sem_INSN_SHLR16_COMPACT }, { SH64_COMPACT_INSN_STC_GBR_COMPACT, && case_sem_INSN_STC_GBR_COMPACT }, + { SH64_COMPACT_INSN_STC_VBR_COMPACT, && case_sem_INSN_STC_VBR_COMPACT }, { SH64_COMPACT_INSN_STCL_GBR_COMPACT, && case_sem_INSN_STCL_GBR_COMPACT }, + { SH64_COMPACT_INSN_STCL_VBR_COMPACT, && case_sem_INSN_STCL_VBR_COMPACT }, { SH64_COMPACT_INSN_STS_FPSCR_COMPACT, && case_sem_INSN_STS_FPSCR_COMPACT }, { SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, && case_sem_INSN_STSL_FPSCR_COMPACT }, { SH64_COMPACT_INSN_STS_FPUL_COMPACT, && case_sem_INSN_STS_FPUL_COMPACT }, @@ -424,7 +439,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -432,7 +447,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -451,7 +466,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), EXTQISI (ANDQI (FLD (f_imm8), 255))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -462,7 +477,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -473,7 +488,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SI opval = ADDCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = tmp_flag; @@ -490,7 +505,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -501,7 +516,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = tmp_t; @@ -518,7 +533,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -526,7 +541,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { DI opval = ANDDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn))); SET_H_GR (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); } #undef FLD @@ -545,7 +560,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SI opval = ANDSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8))); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -615,13 +630,22 @@ if (NOTBI (GET_H_TBIT ())) { if (NOTBI (GET_H_TBIT ())) { { { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ + { UDI opval = FLD (i_disp8); SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); - written |= (1 << 2); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -641,11 +665,19 @@ if (NOTBI (GET_H_TBIT ())) { { { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ + { UDI opval = FLD (i_disp12); SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -664,11 +696,19 @@ if (NOTBI (GET_H_TBIT ())) { { { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ + { UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -707,6 +747,14 @@ sh64_break (current_cpu, pc); SET_H_PR (opval); TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); } +} + { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ { UDI opval = FLD (i_disp12); SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); @@ -737,6 +785,14 @@ sh64_break (current_cpu, pc); SET_H_PR (opval); TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); } +} + { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ { UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); @@ -788,13 +844,22 @@ if (GET_H_TBIT ()) { if (GET_H_TBIT ()) { { { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ + { UDI opval = FLD (i_disp8); SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); - written |= (1 << 2); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -870,7 +935,7 @@ if (GET_H_TBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -908,7 +973,7 @@ if (GET_H_TBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -927,7 +992,7 @@ if (GET_H_TBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -946,7 +1011,7 @@ if (GET_H_TBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -965,7 +1030,7 @@ if (GET_H_TBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1022,7 +1087,7 @@ if (GET_H_TBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1050,7 +1115,7 @@ if (GET_H_TBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1112,7 +1177,7 @@ if (GET_H_TBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1130,7 +1195,7 @@ if (GET_H_TBIT ()) { { SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), ZEXTBISI (GET_H_TBIT ())); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } if (NOTBI (tmp_oldq)) { if (NOTBI (GET_H_MBIT ())) { @@ -1139,7 +1204,7 @@ if (NOTBI (GET_H_MBIT ())) { { SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); if (NOTBI (GET_H_QBIT ())) { @@ -1162,7 +1227,7 @@ if (NOTBI (GET_H_QBIT ())) { { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); if (NOTBI (GET_H_QBIT ())) { @@ -1187,7 +1252,7 @@ if (NOTBI (GET_H_MBIT ())) { { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); if (NOTBI (GET_H_QBIT ())) { @@ -1210,7 +1275,7 @@ if (NOTBI (GET_H_QBIT ())) { { SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); if (NOTBI (GET_H_QBIT ())) { @@ -1240,11 +1305,49 @@ if (NOTBI (GET_H_QBIT ())) { } NEXT (vpc); + CASE (sem, INSN_DIVU_COMPACT) : /* divu r0, $rn */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = UDIVSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (((UINT) 0))); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MULR_COMPACT) : /* mulr r0, $rn */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = MULSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (((UINT) 0))); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + CASE (sem, INSN_DMULSL_COMPACT) : /* dmuls.l $rm, $rn */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1272,7 +1375,7 @@ if (NOTBI (GET_H_QBIT ())) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1309,7 +1412,7 @@ if (NOTBI (GET_H_QBIT ())) { { SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 1); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = EQSI (GET_H_GRC (FLD (f_rn)), 0); @@ -1326,7 +1429,7 @@ if (NOTBI (GET_H_QBIT ())) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1334,7 +1437,7 @@ if (NOTBI (GET_H_QBIT ())) { { SI opval = EXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -1345,7 +1448,7 @@ if (NOTBI (GET_H_QBIT ())) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1353,7 +1456,7 @@ if (NOTBI (GET_H_QBIT ())) { { SI opval = EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -1364,7 +1467,7 @@ if (NOTBI (GET_H_QBIT ())) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1372,7 +1475,7 @@ if (NOTBI (GET_H_QBIT ())) { { SI opval = ZEXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -1383,7 +1486,7 @@ if (NOTBI (GET_H_QBIT ())) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1391,7 +1494,7 @@ if (NOTBI (GET_H_QBIT ())) { { SI opval = ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -1409,17 +1512,17 @@ if (NOTBI (GET_H_QBIT ())) { if (GET_H_PRBIT ()) { { - DF opval = sh64_fabsd (current_cpu, GET_H_DR (FLD (f_rn))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + DF opval = sh64_fabsd (current_cpu, GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_fabss (current_cpu, GET_H_FRC (FLD (f_rn))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_fabss (current_cpu, GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -1432,24 +1535,24 @@ if (GET_H_PRBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (GET_H_PRBIT ()) { { - DF opval = sh64_faddd (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + DF opval = sh64_faddd (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_fadds (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_fadds (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -1462,23 +1565,23 @@ if (GET_H_PRBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (GET_H_PRBIT ()) { { - BI opval = sh64_fcmpeqd (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn))); + BI opval = sh64_fcmpeqd (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); SET_H_TBIT (opval); - written |= (1 << 7); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); } } else { { - BI opval = sh64_fcmpeqs (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn))); + BI opval = sh64_fcmpeqs (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); SET_H_TBIT (opval); - written |= (1 << 7); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); } } @@ -1492,23 +1595,23 @@ if (GET_H_PRBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (GET_H_PRBIT ()) { { - BI opval = sh64_fcmpgtd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm))); + BI opval = sh64_fcmpgtd (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); SET_H_TBIT (opval); - written |= (1 << 7); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); } } else { { - BI opval = sh64_fcmpgts (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm))); + BI opval = sh64_fcmpgts (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); SET_H_TBIT (opval); - written |= (1 << 7); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); } } @@ -1522,7 +1625,7 @@ if (GET_H_PRBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f +#define FLD(f) abuf->fields.sfmt_fmov8_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1530,7 +1633,7 @@ if (GET_H_PRBIT ()) { { SF opval = sh64_fcnvds (current_cpu, GET_H_DRC (FLD (f_dn))); CPU (h_fr[((UINT) 32)]) = opval; - TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); } #undef FLD @@ -1541,7 +1644,7 @@ if (GET_H_PRBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f +#define FLD(f) abuf->fields.sfmt_fmov8_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1549,7 +1652,7 @@ if (GET_H_PRBIT ()) { { DF opval = sh64_fcnvsd (current_cpu, CPU (h_fr[((UINT) 32)])); SET_H_DRC (FLD (f_dn), opval); - TRACE_RESULT (current_cpu, abuf, "drn", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "drc", 'f', opval); } #undef FLD @@ -1560,24 +1663,24 @@ if (GET_H_PRBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (GET_H_PRBIT ()) { { - DF opval = sh64_fdivd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + DF opval = sh64_fdivd (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_fdivs (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_fdivs (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -1595,28 +1698,13 @@ if (GET_H_PRBIT ()) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -{ - QI tmp_m; - QI tmp_n; - SF tmp_res; - tmp_m = FLD (f_vm); - tmp_n = FLD (f_vn); - tmp_res = sh64_fmuls (current_cpu, GET_H_FVC (FLD (f_vm)), GET_H_FVC (FLD (f_vn))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 1)), GET_H_FRC (ADDQI (tmp_n, 1)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 2)), GET_H_FRC (ADDQI (tmp_n, 2)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 3)), GET_H_FRC (ADDQI (tmp_n, 3)))); - { - SF opval = tmp_res; - SET_H_FRC (ADDQI (tmp_n, 3), opval); - TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-3", 'f', opval); - } -} +sh64_fipr (current_cpu, FLD (f_vm), FLD (f_vn)); #undef FLD } NEXT (vpc); - CASE (sem, INSN_FLDS_COMPACT) : /* flds $frn */ + CASE (sem, INSN_FLDS_COMPACT) : /* flds $frn, fpul */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); @@ -1628,7 +1716,7 @@ if (GET_H_PRBIT ()) { { SF opval = GET_H_FRC (FLD (f_rn)); CPU (h_fr[((UINT) 32)]) = opval; - TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); } #undef FLD @@ -1647,7 +1735,7 @@ if (GET_H_PRBIT ()) { { SF opval = sh64_fldi0 (current_cpu); SET_H_FRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "frc", 'f', opval); } #undef FLD @@ -1666,7 +1754,7 @@ if (GET_H_PRBIT ()) { { SF opval = sh64_fldi1 (current_cpu); SET_H_FRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "frc", 'f', opval); } #undef FLD @@ -1685,16 +1773,16 @@ if (GET_H_PRBIT ()) { if (GET_H_PRBIT ()) { { DF opval = sh64_floatld (current_cpu, CPU (h_fr[((UINT) 32)])); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_floatls (current_cpu, CPU (h_fr[((UINT) 32)])); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_floatls (current_cpu, CPU (h_fr[((UINT) 32)])); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -1707,7 +1795,7 @@ if (GET_H_PRBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1715,114 +1803,67 @@ if (GET_H_PRBIT ()) { { SF opval = sh64_fmacs (current_cpu, GET_H_FRC (((UINT) 0)), GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn))); SET_H_FRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "frc", 'f', opval); } #undef FLD } NEXT (vpc); - CASE (sem, INSN_FMOV1_COMPACT) : /* fmov $frm, $frn */ + CASE (sem, INSN_FMOV1_COMPACT) : /* fmov $fmovm, $fmovn */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -if (NOTBI (GET_H_SZBIT ())) { - { - SF opval = GET_H_FRC (FLD (f_rm)); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); - } -} else { -if (EQSI (ANDSI (FLD (f_rm), 1), 1)) { -if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { - { - DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); - SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); - } -} else { - { - DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); - } -} -} else { -if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { { - DF opval = GET_H_DR (FLD (f_rm)); - SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); + DF opval = GET_H_FMOV (FLD (f_rm)); + SET_H_FMOV (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); } -} else { - { - DF opval = GET_H_DR (FLD (f_rm)); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); - } -} -} -} - abuf->written = written; #undef FLD } NEXT (vpc); - CASE (sem, INSN_FMOV2_COMPACT) : /* fmov @$rm, $frn */ + CASE (sem, INSN_FMOV2_COMPACT) : /* fmov @$rm, $fmovn */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (NOTBI (GET_H_SZBIT ())) { { - SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); - } -} else { -if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { - { - DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); - SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); + DF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); + SET_H_FMOV (FLD (f_rn), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); } } else { { DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); + SET_H_FMOV (FLD (f_rn), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); } } -} abuf->written = written; #undef FLD } NEXT (vpc); - CASE (sem, INSN_FMOV3_COMPACT) : /* fmov @${rm}+, frn */ + CASE (sem, INSN_FMOV3_COMPACT) : /* fmov @${rm}+, fmovn */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1830,40 +1871,31 @@ if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { if (NOTBI (GET_H_SZBIT ())) { { { - SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); + DF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); + SET_H_FMOV (FLD (f_rn), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); } { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); SET_H_GRC (FLD (f_rm), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } } else { { -if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { { DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); - SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); + SET_H_FMOV (FLD (f_rn), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); } -} else { - { - DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); - } -} { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 8); SET_H_GRC (FLD (f_rm), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } } @@ -1873,89 +1905,71 @@ if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { } NEXT (vpc); - CASE (sem, INSN_FMOV4_COMPACT) : /* fmov @(r0, $rm), $frn */ + CASE (sem, INSN_FMOV4_COMPACT) : /* fmov @(r0, $rm), $fmovn */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (NOTBI (GET_H_SZBIT ())) { { - SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); - } -} else { -if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { - { - DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); - SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); + DF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); + SET_H_FMOV (FLD (f_rn), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); } } else { { DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); + SET_H_FMOV (FLD (f_rn), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); } } -} abuf->written = written; #undef FLD } NEXT (vpc); - CASE (sem, INSN_FMOV5_COMPACT) : /* fmov $frm, @$rn */ + CASE (sem, INSN_FMOV5_COMPACT) : /* fmov $fmovm, @$rn */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (NOTBI (GET_H_SZBIT ())) { { - SF opval = GET_H_FRC (FLD (f_rm)); + SF opval = GET_H_FMOV (FLD (f_rm)); SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); - } -} else { -if (EQSI (ANDSI (FLD (f_rm), 1), 1)) { - { - DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); - SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); - written |= (1 << 7); + written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); } } else { { - DF opval = GET_H_DR (FLD (f_rm)); + DF opval = GET_H_FMOV (FLD (f_rm)); SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); - written |= (1 << 7); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); } } -} abuf->written = written; #undef FLD } NEXT (vpc); - CASE (sem, INSN_FMOV6_COMPACT) : /* fmov $frm, @-$rn */ + CASE (sem, INSN_FMOV6_COMPACT) : /* fmov $fmovm, @-$rn */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1965,13 +1979,13 @@ if (NOTBI (GET_H_SZBIT ())) { { SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { - SF opval = GET_H_FRC (FLD (f_rm)); + SF opval = GET_H_FMOV (FLD (f_rm)); SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); - written |= (1 << 6); + written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); } } @@ -1980,67 +1994,87 @@ if (NOTBI (GET_H_SZBIT ())) { { SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 8); SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); - } -if (EQSI (ANDSI (FLD (f_rm), 1), 1)) { - { - DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); - SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } -} else { { - DF opval = GET_H_DR (FLD (f_rm)); + DF opval = GET_H_FMOV (FLD (f_rm)); SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); - written |= (1 << 7); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); } } } -} abuf->written = written; #undef FLD } NEXT (vpc); - CASE (sem, INSN_FMOV7_COMPACT) : /* fmov $frm, @(r0, $rn) */ + CASE (sem, INSN_FMOV7_COMPACT) : /* fmov $fmovm, @(r0, $rn) */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (NOTBI (GET_H_SZBIT ())) { { - SF opval = GET_H_FRC (FLD (f_rm)); + SF opval = GET_H_FMOV (FLD (f_rm)); SETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); - written |= (1 << 7); + written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); } } else { -if (EQSI (ANDSI (FLD (f_rm), 1), 1)) { { - DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); + DF opval = GET_H_FMOV (FLD (f_rm)); SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); - written |= (1 << 8); + written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); } -} else { +} + + abuf->written = written; +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_FMOV8_COMPACT) : /* fmov.d @($imm12x8, $rm), $drn */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_fmov8_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + { - DF opval = GET_H_DR (FLD (f_rm)); - SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); + DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm12x8))); + SET_H_DRC (FLD (f_dn), opval); + TRACE_RESULT (current_cpu, abuf, "drc", 'f', opval); } + +#undef FLD } -} + NEXT (vpc); + + CASE (sem, INSN_FMOV9_COMPACT) : /* mov.l $drm, @($imm12x8, $rn) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_fmov9_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DF opval = GET_H_DRC (FLD (f_dm)); + SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm12x8)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); + } - abuf->written = written; #undef FLD } NEXT (vpc); @@ -2049,24 +2083,24 @@ if (EQSI (ANDSI (FLD (f_rm), 1), 1)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (GET_H_PRBIT ()) { { - DF opval = sh64_fmuld (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + DF opval = sh64_fmuld (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_fmuls (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_fmuls (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -2086,17 +2120,17 @@ if (GET_H_PRBIT ()) { if (GET_H_PRBIT ()) { { - DF opval = sh64_fnegd (current_cpu, GET_H_DR (FLD (f_rn))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + DF opval = sh64_fnegd (current_cpu, GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_fnegs (current_cpu, GET_H_FRC (FLD (f_rn))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_fnegs (current_cpu, GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -2154,17 +2188,17 @@ if (GET_H_PRBIT ()) { if (GET_H_PRBIT ()) { { - DF opval = sh64_fsqrtd (current_cpu, GET_H_DR (FLD (f_rn))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + DF opval = sh64_fsqrtd (current_cpu, GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_fsqrts (current_cpu, GET_H_FRC (FLD (f_rn))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_fsqrts (current_cpu, GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -2185,7 +2219,7 @@ if (GET_H_PRBIT ()) { { SF opval = CPU (h_fr[((UINT) 32)]); SET_H_FRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "frc", 'f', opval); } #undef FLD @@ -2196,24 +2230,24 @@ if (GET_H_PRBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (GET_H_PRBIT ()) { { - DF opval = sh64_fsubd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + DF opval = sh64_fsubd (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_fsubs (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_fsubs (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -2232,9 +2266,9 @@ if (GET_H_PRBIT ()) { vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - SF opval = ((GET_H_PRBIT ()) ? (sh64_ftrcdl (current_cpu, GET_H_DR (FLD (f_rn)))) : (sh64_ftrcsl (current_cpu, GET_H_FRC (FLD (f_rn))))); + SF opval = ((GET_H_PRBIT ()) ? (sh64_ftrcdl (current_cpu, GET_H_FSD (FLD (f_rn)))) : (sh64_ftrcsl (current_cpu, GET_H_FSD (FLD (f_rn))))); CPU (h_fr[((UINT) 32)]) = opval; - TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); } #undef FLD @@ -2250,47 +2284,7 @@ if (GET_H_PRBIT ()) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -{ - QI tmp_n; - SF tmp_res; - tmp_n = FLD (f_vn); - tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 0)), GET_H_FRC (tmp_n)); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 4)), GET_H_FRC (ADDQI (tmp_n, 1)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 8)), GET_H_FRC (ADDQI (tmp_n, 2)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 12)), GET_H_FRC (ADDQI (tmp_n, 3)))); - { - SF opval = tmp_res; - SET_H_FRC (tmp_n, opval); - TRACE_RESULT (current_cpu, abuf, "frc-n", 'f', opval); - } - tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 1)), GET_H_FRC (tmp_n)); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 5)), GET_H_FRC (ADDQI (tmp_n, 1)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 9)), GET_H_FRC (ADDQI (tmp_n, 2)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 13)), GET_H_FRC (ADDQI (tmp_n, 3)))); - { - SF opval = tmp_res; - SET_H_FRC (ADDQI (tmp_n, 1), opval); - TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-1", 'f', opval); - } - tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 2)), GET_H_FRC (tmp_n)); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 6)), GET_H_FRC (ADDQI (tmp_n, 1)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 10)), GET_H_FRC (ADDQI (tmp_n, 2)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 14)), GET_H_FRC (ADDQI (tmp_n, 3)))); - { - SF opval = tmp_res; - SET_H_FRC (ADDQI (tmp_n, 2), opval); - TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-2", 'f', opval); - } - tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 3)), GET_H_FRC (tmp_n)); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 7)), GET_H_FRC (ADDQI (tmp_n, 1)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 11)), GET_H_FRC (ADDQI (tmp_n, 2)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 15)), GET_H_FRC (ADDQI (tmp_n, 3)))); - { - SF opval = tmp_res; - SET_H_FRC (ADDQI (tmp_n, 3), opval); - TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-3", 'f', opval); - } -} +sh64_ftrv (current_cpu, FLD (f_vn)); #undef FLD } @@ -2308,11 +2302,20 @@ if (GET_H_PRBIT ()) { { { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ + { UDI opval = GET_H_GRC (FLD (f_rn)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +((void) 0); /*nop*/ +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -2336,12 +2339,21 @@ if (GET_H_PRBIT ()) { SET_H_PR (opval); TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); } +} + { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ { UDI opval = GET_H_GRC (FLD (f_rn)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +((void) 0); /*nop*/ } SEM_BRANCH_FINI (vpc); @@ -2349,7 +2361,7 @@ if (GET_H_PRBIT ()) { } NEXT (vpc); - CASE (sem, INSN_LDC_COMPACT) : /* ldc $rn, gbr */ + CASE (sem, INSN_LDC_GBR_COMPACT) : /* ldc $rn, gbr */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); @@ -2368,7 +2380,45 @@ if (GET_H_PRBIT ()) { } NEXT (vpc); - CASE (sem, INSN_LDCL_COMPACT) : /* ldc.l @${rn}+, gbr */ + CASE (sem, INSN_LDC_VBR_COMPACT) : /* ldc $rn, vbr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = GET_H_GRC (FLD (f_rn)); + SET_H_VBR (opval); + TRACE_RESULT (current_cpu, abuf, "vbr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LDC_SR_COMPACT) : /* ldc $rn, sr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = GET_H_GRC (FLD (f_rn)); + CPU (h_sr) = opval; + TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LDCL_GBR_COMPACT) : /* ldc.l @${rn}+, gbr */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); @@ -2386,7 +2436,33 @@ if (GET_H_PRBIT ()) { { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_LDCL_VBR_COMPACT) : /* ldc.l @${rn}+, vbr */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + { + SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); + SET_H_VBR (opval); + TRACE_RESULT (current_cpu, abuf, "vbr", 'x', opval); + } + { + SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2405,7 +2481,7 @@ if (GET_H_PRBIT ()) { { SI opval = GET_H_GRC (FLD (f_rn)); - SET_H_FPCCR (opval); + CPU (h_fpscr) = opval; TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval); } @@ -2425,13 +2501,13 @@ if (GET_H_PRBIT ()) { { { SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); - SET_H_FPCCR (opval); + CPU (h_fpscr) = opval; TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval); } { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2451,7 +2527,7 @@ if (GET_H_PRBIT ()) { { SF opval = SUBWORDSISF (GET_H_GRC (FLD (f_rn))); CPU (h_fr[((UINT) 32)]) = opval; - TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); } #undef FLD @@ -2471,12 +2547,12 @@ if (GET_H_PRBIT ()) { { SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn))); CPU (h_fr[((UINT) 32)]) = opval; - TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); } { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2521,7 +2597,7 @@ if (GET_H_PRBIT ()) { { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2566,7 +2642,7 @@ if (GET_H_PRBIT ()) { { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2611,7 +2687,7 @@ if (GET_H_PRBIT ()) { { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2623,7 +2699,7 @@ if (GET_H_PRBIT ()) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2638,20 +2714,20 @@ if (GET_H_PRBIT ()) { { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } if (EQSI (FLD (f_rn), FLD (f_rm))) { { { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 11); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } } @@ -2660,7 +2736,7 @@ if (EQSI (FLD (f_rn), FLD (f_rm))) { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 11); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } tmp_tmpry = MULDI (ZEXTSIDI (tmp_x), ZEXTSIDI (tmp_y)); tmp_mac = ORDI (SLLDI (ZEXTSIDI (GET_H_MACH ()), 32), ZEXTSIDI (GET_H_MACL ())); @@ -2703,7 +2779,7 @@ if (LTDI (tmp_result, tmp_min)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2718,20 +2794,20 @@ if (LTDI (tmp_result, tmp_min)) { { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } if (EQSI (FLD (f_rn), FLD (f_rm))) { { { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 11); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } } @@ -2740,7 +2816,7 @@ if (EQSI (FLD (f_rn), FLD (f_rm))) { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 11); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } tmp_tmpry = MULSI (ZEXTHISI (tmp_x), ZEXTHISI (tmp_y)); if (GET_H_SBIT ()) { @@ -2789,7 +2865,7 @@ if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2797,7 +2873,7 @@ if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) { { DI opval = GET_H_GR (FLD (f_rm)); SET_H_GR (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); } #undef FLD @@ -2816,7 +2892,26 @@ if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) { { SI opval = EXTQIDI (ANDQI (FLD (f_imm8), 255)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MOVI20_COMPACT) : /* movi20 #$imm20, $rn */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_movi20_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = FLD (f_imm20); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -2827,7 +2922,7 @@ if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2846,7 +2941,7 @@ if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2862,7 +2957,7 @@ if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) { { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2874,7 +2969,7 @@ if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2939,7 +3034,7 @@ if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2947,7 +3042,7 @@ if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) { { SI opval = EXTQISI (GETMEMQI (current_cpu, pc, GET_H_GRC (FLD (f_rm)))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -2958,7 +3053,7 @@ if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -2971,20 +3066,20 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { SI opval = EXTQISI (tmp_data); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 1); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } { SI opval = EXTQISI (tmp_data); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2997,7 +3092,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3005,7 +3100,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3024,7 +3119,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8)))); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3043,7 +3138,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4)))); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3054,7 +3149,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3073,7 +3168,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3089,7 +3184,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -3101,7 +3196,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3158,7 +3253,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3166,7 +3261,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3177,7 +3272,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3186,21 +3281,21 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = GET_H_GRC (FLD (f_rn)); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } } @@ -3214,7 +3309,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3222,7 +3317,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3241,7 +3336,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x4))); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3260,7 +3355,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_imm8x4), ANDDI (ADDDI (pc, 4), INVSI (3)))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3279,7 +3374,45 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x4))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MOVL12_COMPACT) : /* mov.l @($imm12x4, $rm), $rn */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm12x4))); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MOVL13_COMPACT) : /* mov.l $rm, @($imm12x4, $rn) */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = GET_H_GRC (FLD (f_rm)); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm12x4)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } #undef FLD @@ -3290,7 +3423,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3309,7 +3442,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3325,7 +3458,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -3337,7 +3470,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3371,7 +3504,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { } NEXT (vpc); - CASE (sem, INSN_MOVW5_COMPACT) : /* mov.w r0, @($imm4x2, $rn) */ + CASE (sem, INSN_MOVW5_COMPACT) : /* mov.w r0, @($imm4x2, $rm) */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); @@ -3382,7 +3515,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { HI opval = SUBWORDSIHI (GET_H_GRC (((UINT) 0)), 1); - SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm4x2)), opval); + SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x2)), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } @@ -3394,7 +3527,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3402,7 +3535,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = EXTHISI (GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm)))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3413,7 +3546,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3426,20 +3559,20 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { SI opval = EXTHISI (tmp_data); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } { SI opval = EXTHISI (tmp_data); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -3452,7 +3585,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3460,7 +3593,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3479,7 +3612,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x2)))); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3498,7 +3631,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDDI (ADDDI (pc, 4), FLD (f_imm8x2)))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3509,7 +3642,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movw11_compact.f +#define FLD(f) abuf->fields.sfmt_movw5_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3517,7 +3650,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x2)))); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3536,7 +3669,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = ADDDI (ANDDI (ADDDI (pc, 4), INVSI (3)), FLD (f_imm8x4)); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3562,6 +3695,25 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { } NEXT (vpc); + CASE (sem, INSN_MOVCOL_COMPACT) : /* movco.l r0, @$rn */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = GET_H_GRC (FLD (f_rn)); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + CASE (sem, INSN_MOVT_COMPACT) : /* movt $rn */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); @@ -3574,18 +3726,63 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = ZEXTBISI (GET_H_TBIT ()); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD } NEXT (vpc); + CASE (sem, INSN_MOVUAL_COMPACT) : /* movua.l @$rn, r0 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = sh64_movua (current_cpu, pc, GET_H_GRC (FLD (f_rn))); + SET_H_GRC (((UINT) 0), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_MOVUAL2_COMPACT) : /* movua.l @$rn+, r0 */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + { + SI opval = sh64_movua (current_cpu, pc, GET_H_GRC (FLD (f_rn))); + SET_H_GRC (((UINT) 0), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + { + SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + CASE (sem, INSN_MULL_COMPACT) : /* mul.l $rm, $rn */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3604,7 +3801,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3623,7 +3820,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3642,7 +3839,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3650,7 +3847,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = NEGSI (GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3661,7 +3858,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3672,7 +3869,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = SUBCSI (0, GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = tmp_flag; @@ -3704,7 +3901,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3712,7 +3909,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { DI opval = INVDI (GET_H_GR (FLD (f_rm))); SET_H_GR (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); } #undef FLD @@ -3723,12 +3920,19 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_movw10_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); +{ + { + SI opval = GET_H_GRC (FLD (f_rn)); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } ((void) 0); /*nop*/ +} #undef FLD } @@ -3738,12 +3942,19 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_movw10_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); +{ + { + SI opval = GET_H_GRC (FLD (f_rn)); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } ((void) 0); /*nop*/ +} #undef FLD } @@ -3753,12 +3964,19 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_movw10_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); +{ + { + SI opval = GET_H_GRC (FLD (f_rn)); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } ((void) 0); /*nop*/ +} #undef FLD } @@ -3768,7 +3986,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3776,7 +3994,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { DI opval = ORDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn))); SET_H_GR (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); } #undef FLD @@ -3795,7 +4013,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = ORSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8))); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -3831,12 +4049,12 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_movw10_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -((void) 0); /*nop*/ +sh64_pref (current_cpu, GET_H_GRC (FLD (f_rn))); #undef FLD } @@ -3857,7 +4075,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), GET_H_TBIT ()); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_temp) ? (1) : (0)); @@ -3887,7 +4105,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_lsbit) ? (1) : (0)); @@ -3915,7 +4133,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), tmp_temp); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_temp) ? (1) : (0)); @@ -3945,7 +4163,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_lsbit) ? (1) : (0)); @@ -3970,11 +4188,20 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ + { UDI opval = GET_H_PR (); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +((void) 0); /*nop*/ +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -4023,43 +4250,43 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - QI tmp_shamt; - tmp_shamt = ANDQI (GET_H_GRC (FLD (f_rm)), 31); + SI tmp_shamt; + tmp_shamt = ANDSI (GET_H_GRC (FLD (f_rm)), 31); if (GESI (GET_H_GRC (FLD (f_rm)), 0)) { { SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt); SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { -if (NEQI (tmp_shamt, 0)) { +if (NESI (tmp_shamt, 0)) { { SI opval = SRASI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt)); SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { if (LTSI (GET_H_GRC (FLD (f_rn)), 0)) { { SI opval = NEGSI (1); SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { { SI opval = 0; SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } } @@ -4086,7 +4313,7 @@ if (LTSI (GET_H_GRC (FLD (f_rn)), 0)) { { SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_t) ? (1) : (0)); @@ -4114,7 +4341,7 @@ if (LTSI (GET_H_GRC (FLD (f_rn)), 0)) { { SI opval = SRASI (GET_H_GRC (FLD (f_rn)), 1); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_t) ? (1) : (0)); @@ -4131,35 +4358,35 @@ if (LTSI (GET_H_GRC (FLD (f_rn)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - QI tmp_shamt; - tmp_shamt = ANDQI (GET_H_GRC (FLD (f_rm)), 31); + SI tmp_shamt; + tmp_shamt = ANDSI (GET_H_GRC (FLD (f_rm)), 31); if (GESI (GET_H_GRC (FLD (f_rm)), 0)) { { SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt); SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { -if (NEQI (tmp_shamt, 0)) { +if (NESI (tmp_shamt, 0)) { { SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt)); SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { { SI opval = 0; SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } } @@ -4185,7 +4412,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_t) ? (1) : (0)); @@ -4210,7 +4437,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 2); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4229,7 +4456,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 8); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4248,7 +4475,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 16); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4270,7 +4497,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 1); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_t) ? (1) : (0)); @@ -4295,7 +4522,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 2); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4314,7 +4541,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 8); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4333,7 +4560,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 16); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4352,7 +4579,26 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = GET_H_GBR (); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_STC_VBR_COMPACT) : /* stc vbr, $rn */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = GET_H_VBR (); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4379,7 +4625,35 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } +} + +#undef FLD +} + NEXT (vpc); + + CASE (sem, INSN_STCL_VBR_COMPACT) : /* stc.l vbr, @-$rn */ +{ + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); + ARGBUF *abuf = SEM_ARGBUF (sem_arg); +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + DI tmp_addr; + tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); + { + SI opval = GET_H_VBR (); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + { + SI opval = tmp_addr; + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -4397,9 +4671,9 @@ if (NEQI (tmp_shamt, 0)) { vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - SI opval = GET_H_FPCCR (); + SI opval = CPU (h_fpscr); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4419,14 +4693,14 @@ if (NEQI (tmp_shamt, 0)) { DI tmp_addr; tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); { - SI opval = GET_H_FPCCR (); + SI opval = CPU (h_fpscr); SETMEMSI (current_cpu, pc, tmp_addr, opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -4446,7 +4720,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = SUBWORDSFSI (CPU (h_fr[((UINT) 32)])); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4473,7 +4747,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -4493,7 +4767,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = GET_H_MACH (); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4520,7 +4794,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -4540,7 +4814,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = GET_H_MACL (); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4567,7 +4841,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -4587,7 +4861,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = GET_H_PR (); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4614,7 +4888,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -4626,7 +4900,7 @@ if (NEQI (tmp_shamt, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4634,7 +4908,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4645,7 +4919,7 @@ if (NEQI (tmp_shamt, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4656,7 +4930,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = SUBCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = tmp_flag; @@ -4673,7 +4947,7 @@ if (NEQI (tmp_shamt, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4684,7 +4958,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_t) ? (1) : (0)); @@ -4701,7 +4975,7 @@ if (NEQI (tmp_shamt, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4716,7 +4990,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = ORSI (SLLSI (tmp_top_half, 16), ORSI (SLLSI (tmp_byte0, 8), tmp_byte1)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -4728,7 +5002,7 @@ if (NEQI (tmp_shamt, 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4736,7 +5010,7 @@ if (NEQI (tmp_shamt, 0)) { { SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rm)), 16), SLLSI (GET_H_GRC (FLD (f_rm)), 16)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4791,7 +5065,7 @@ sh64_compact_trapa (current_cpu, FLD (f_imm8), pc); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4852,7 +5126,7 @@ sh64_compact_trapa (current_cpu, FLD (f_imm8), pc); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4860,7 +5134,7 @@ sh64_compact_trapa (current_cpu, FLD (f_imm8), pc); { DI opval = XORDI (GET_H_GR (FLD (f_rn)), GET_H_GR (FLD (f_rm))); SET_H_GR (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); } #undef FLD @@ -4877,9 +5151,9 @@ sh64_compact_trapa (current_cpu, FLD (f_imm8), pc); vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = XORDI (GET_H_GR (((UINT) 0)), ZEXTSIDI (FLD (f_imm8))); - SET_H_GR (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "gr-0", 'D', opval); + SI opval = XORSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8))); + SET_H_GRC (((UINT) 0), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD @@ -4915,7 +5189,7 @@ sh64_compact_trapa (current_cpu, FLD (f_imm8), pc); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -4923,7 +5197,7 @@ sh64_compact_trapa (current_cpu, FLD (f_imm8), pc); { SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rm)), 16), SRLSI (GET_H_GRC (FLD (f_rn)), 16)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } #undef FLD diff --git a/sim/sh64/sem-compact.c b/sim/sh64/sem-compact.c index fae6877..3774cf5 100644 --- a/sim/sh64/sem-compact.c +++ b/sim/sh64/sem-compact.c @@ -2,9 +2,9 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. -This file is part of the GNU Simulators. +This file is part of the GNU simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -206,7 +206,7 @@ SEM_FN_NAME (sh64_compact,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,add_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -215,7 +215,7 @@ SEM_FN_NAME (sh64_compact,add_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -236,7 +236,7 @@ SEM_FN_NAME (sh64_compact,addi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), EXTQISI (ANDQI (FLD (f_imm8), 255))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -248,7 +248,7 @@ SEM_FN_NAME (sh64_compact,addi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,addc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -260,7 +260,7 @@ SEM_FN_NAME (sh64_compact,addc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ADDCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = tmp_flag; @@ -278,7 +278,7 @@ SEM_FN_NAME (sh64_compact,addc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,addv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -290,7 +290,7 @@ SEM_FN_NAME (sh64_compact,addv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = tmp_t; @@ -308,7 +308,7 @@ SEM_FN_NAME (sh64_compact,addv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,and_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -317,7 +317,7 @@ SEM_FN_NAME (sh64_compact,and_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { DI opval = ANDDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn))); SET_H_GR (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); } return vpc; @@ -338,7 +338,7 @@ SEM_FN_NAME (sh64_compact,andi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ANDSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8))); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -414,13 +414,22 @@ SEM_FN_NAME (sh64_compact,bfs_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (GET_H_TBIT ())) { { { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ + { UDI opval = FLD (i_disp8); SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); - written |= (1 << 2); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -442,11 +451,19 @@ SEM_FN_NAME (sh64_compact,bra_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ + { UDI opval = FLD (i_disp12); SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} SEM_BRANCH_FINI (vpc); return vpc; @@ -467,11 +484,19 @@ SEM_FN_NAME (sh64_compact,braf_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ + { UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} SEM_BRANCH_FINI (vpc); return vpc; @@ -514,6 +539,14 @@ SEM_FN_NAME (sh64_compact,bsr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SET_H_PR (opval); TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); } +} + { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ { UDI opval = FLD (i_disp12); SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); @@ -546,6 +579,14 @@ SEM_FN_NAME (sh64_compact,bsrf_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SET_H_PR (opval); TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); } +} + { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ { UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); @@ -601,13 +642,22 @@ SEM_FN_NAME (sh64_compact,bts_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GET_H_TBIT ()) { { { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ + { UDI opval = FLD (i_disp8); SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); - written |= (1 << 2); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -690,7 +740,7 @@ SEM_FN_NAME (sh64_compact,clrt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,cmpeq_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -732,7 +782,7 @@ SEM_FN_NAME (sh64_compact,cmpeqi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg static SEM_PC SEM_FN_NAME (sh64_compact,cmpge_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -753,7 +803,7 @@ SEM_FN_NAME (sh64_compact,cmpge_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,cmpgt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -774,7 +824,7 @@ SEM_FN_NAME (sh64_compact,cmpgt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,cmphi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -795,7 +845,7 @@ SEM_FN_NAME (sh64_compact,cmphi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,cmphs_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -858,7 +908,7 @@ SEM_FN_NAME (sh64_compact,cmppz_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,cmpstr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -888,7 +938,7 @@ SEM_FN_NAME (sh64_compact,cmpstr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg static SEM_PC SEM_FN_NAME (sh64_compact,div0s_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -954,7 +1004,7 @@ SEM_FN_NAME (sh64_compact,div0u_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,div1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -973,7 +1023,7 @@ SEM_FN_NAME (sh64_compact,div1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), ZEXTBISI (GET_H_TBIT ())); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } if (NOTBI (tmp_oldq)) { if (NOTBI (GET_H_MBIT ())) { @@ -982,7 +1032,7 @@ if (NOTBI (GET_H_MBIT ())) { { SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); if (NOTBI (GET_H_QBIT ())) { @@ -1005,7 +1055,7 @@ if (NOTBI (GET_H_QBIT ())) { { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); if (NOTBI (GET_H_QBIT ())) { @@ -1030,7 +1080,7 @@ if (NOTBI (GET_H_MBIT ())) { { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); if (NOTBI (GET_H_QBIT ())) { @@ -1053,7 +1103,7 @@ if (NOTBI (GET_H_QBIT ())) { { SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0); if (NOTBI (GET_H_QBIT ())) { @@ -1083,12 +1133,54 @@ if (NOTBI (GET_H_QBIT ())) { #undef FLD } +/* divu-compact: divu r0, $rn */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,divu_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = UDIVSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (((UINT) 0))); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mulr-compact: mulr r0, $rn */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,mulr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = MULSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (((UINT) 0))); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + + return vpc; +#undef FLD +} + /* dmulsl-compact: dmuls.l $rm, $rn */ static SEM_PC SEM_FN_NAME (sh64_compact,dmulsl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1118,7 +1210,7 @@ SEM_FN_NAME (sh64_compact,dmulsl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg static SEM_PC SEM_FN_NAME (sh64_compact,dmulul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1158,7 +1250,7 @@ SEM_FN_NAME (sh64_compact,dt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 1); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = EQSI (GET_H_GRC (FLD (f_rn)), 0); @@ -1176,7 +1268,7 @@ SEM_FN_NAME (sh64_compact,dt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,extsb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1185,7 +1277,7 @@ SEM_FN_NAME (sh64_compact,extsb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = EXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -1197,7 +1289,7 @@ SEM_FN_NAME (sh64_compact,extsb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,extsw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1206,7 +1298,7 @@ SEM_FN_NAME (sh64_compact,extsw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -1218,7 +1310,7 @@ SEM_FN_NAME (sh64_compact,extsw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,extub_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1227,7 +1319,7 @@ SEM_FN_NAME (sh64_compact,extub_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ZEXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -1239,7 +1331,7 @@ SEM_FN_NAME (sh64_compact,extub_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,extuw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1248,7 +1340,7 @@ SEM_FN_NAME (sh64_compact,extuw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -1268,17 +1360,17 @@ SEM_FN_NAME (sh64_compact,fabs_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GET_H_PRBIT ()) { { - DF opval = sh64_fabsd (current_cpu, GET_H_DR (FLD (f_rn))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + DF opval = sh64_fabsd (current_cpu, GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_fabss (current_cpu, GET_H_FRC (FLD (f_rn))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_fabss (current_cpu, GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -1292,7 +1384,7 @@ if (GET_H_PRBIT ()) { static SEM_PC SEM_FN_NAME (sh64_compact,fadd_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1300,17 +1392,17 @@ SEM_FN_NAME (sh64_compact,fadd_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GET_H_PRBIT ()) { { - DF opval = sh64_faddd (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + DF opval = sh64_faddd (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_fadds (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_fadds (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -1324,7 +1416,7 @@ if (GET_H_PRBIT ()) { static SEM_PC SEM_FN_NAME (sh64_compact,fcmpeq_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1332,16 +1424,16 @@ SEM_FN_NAME (sh64_compact,fcmpeq_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg if (GET_H_PRBIT ()) { { - BI opval = sh64_fcmpeqd (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn))); + BI opval = sh64_fcmpeqd (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); SET_H_TBIT (opval); - written |= (1 << 7); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); } } else { { - BI opval = sh64_fcmpeqs (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn))); + BI opval = sh64_fcmpeqs (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); SET_H_TBIT (opval); - written |= (1 << 7); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); } } @@ -1356,7 +1448,7 @@ if (GET_H_PRBIT ()) { static SEM_PC SEM_FN_NAME (sh64_compact,fcmpgt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1364,16 +1456,16 @@ SEM_FN_NAME (sh64_compact,fcmpgt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg if (GET_H_PRBIT ()) { { - BI opval = sh64_fcmpgtd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm))); + BI opval = sh64_fcmpgtd (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); SET_H_TBIT (opval); - written |= (1 << 7); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); } } else { { - BI opval = sh64_fcmpgts (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm))); + BI opval = sh64_fcmpgts (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); SET_H_TBIT (opval); - written |= (1 << 7); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval); } } @@ -1388,7 +1480,7 @@ if (GET_H_PRBIT ()) { static SEM_PC SEM_FN_NAME (sh64_compact,fcnvds_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f +#define FLD(f) abuf->fields.sfmt_fmov8_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1397,7 +1489,7 @@ SEM_FN_NAME (sh64_compact,fcnvds_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg { SF opval = sh64_fcnvds (current_cpu, GET_H_DRC (FLD (f_dn))); CPU (h_fr[((UINT) 32)]) = opval; - TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); } return vpc; @@ -1409,7 +1501,7 @@ SEM_FN_NAME (sh64_compact,fcnvds_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg static SEM_PC SEM_FN_NAME (sh64_compact,fcnvsd_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f +#define FLD(f) abuf->fields.sfmt_fmov8_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1418,7 +1510,7 @@ SEM_FN_NAME (sh64_compact,fcnvsd_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg { DF opval = sh64_fcnvsd (current_cpu, CPU (h_fr[((UINT) 32)])); SET_H_DRC (FLD (f_dn), opval); - TRACE_RESULT (current_cpu, abuf, "drn", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "drc", 'f', opval); } return vpc; @@ -1430,7 +1522,7 @@ SEM_FN_NAME (sh64_compact,fcnvsd_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg static SEM_PC SEM_FN_NAME (sh64_compact,fdiv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1438,17 +1530,17 @@ SEM_FN_NAME (sh64_compact,fdiv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GET_H_PRBIT ()) { { - DF opval = sh64_fdivd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + DF opval = sh64_fdivd (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_fdivs (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_fdivs (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -1468,28 +1560,13 @@ SEM_FN_NAME (sh64_compact,fipr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -{ - QI tmp_m; - QI tmp_n; - SF tmp_res; - tmp_m = FLD (f_vm); - tmp_n = FLD (f_vn); - tmp_res = sh64_fmuls (current_cpu, GET_H_FVC (FLD (f_vm)), GET_H_FVC (FLD (f_vn))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 1)), GET_H_FRC (ADDQI (tmp_n, 1)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 2)), GET_H_FRC (ADDQI (tmp_n, 2)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 3)), GET_H_FRC (ADDQI (tmp_n, 3)))); - { - SF opval = tmp_res; - SET_H_FRC (ADDQI (tmp_n, 3), opval); - TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-3", 'f', opval); - } -} +sh64_fipr (current_cpu, FLD (f_vm), FLD (f_vn)); return vpc; #undef FLD } -/* flds-compact: flds $frn */ +/* flds-compact: flds $frn, fpul */ static SEM_PC SEM_FN_NAME (sh64_compact,flds_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) @@ -1503,7 +1580,7 @@ SEM_FN_NAME (sh64_compact,flds_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SF opval = GET_H_FRC (FLD (f_rn)); CPU (h_fr[((UINT) 32)]) = opval; - TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); } return vpc; @@ -1524,7 +1601,7 @@ SEM_FN_NAME (sh64_compact,fldi0_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SF opval = sh64_fldi0 (current_cpu); SET_H_FRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "frc", 'f', opval); } return vpc; @@ -1545,7 +1622,7 @@ SEM_FN_NAME (sh64_compact,fldi1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SF opval = sh64_fldi1 (current_cpu); SET_H_FRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "frc", 'f', opval); } return vpc; @@ -1566,16 +1643,16 @@ SEM_FN_NAME (sh64_compact,float_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GET_H_PRBIT ()) { { DF opval = sh64_floatld (current_cpu, CPU (h_fr[((UINT) 32)])); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_floatls (current_cpu, CPU (h_fr[((UINT) 32)])); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_floatls (current_cpu, CPU (h_fr[((UINT) 32)])); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -1589,7 +1666,7 @@ if (GET_H_PRBIT ()) { static SEM_PC SEM_FN_NAME (sh64_compact,fmac_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1598,78 +1675,40 @@ SEM_FN_NAME (sh64_compact,fmac_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SF opval = sh64_fmacs (current_cpu, GET_H_FRC (((UINT) 0)), GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn))); SET_H_FRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "frc", 'f', opval); } return vpc; #undef FLD } -/* fmov1-compact: fmov $frm, $frn */ +/* fmov1-compact: fmov $fmovm, $fmovn */ static SEM_PC SEM_FN_NAME (sh64_compact,fmov1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -if (NOTBI (GET_H_SZBIT ())) { - { - SF opval = GET_H_FRC (FLD (f_rm)); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); - } -} else { -if (EQSI (ANDSI (FLD (f_rm), 1), 1)) { -if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { { - DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); - SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); + DF opval = GET_H_FMOV (FLD (f_rm)); + SET_H_FMOV (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); } -} else { - { - DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); - } -} -} else { -if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { - { - DF opval = GET_H_DR (FLD (f_rm)); - SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); - } -} else { - { - DF opval = GET_H_DR (FLD (f_rm)); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); - } -} -} -} - abuf->written = written; return vpc; #undef FLD } -/* fmov2-compact: fmov @$rm, $frn */ +/* fmov2-compact: fmov @$rm, $fmovn */ static SEM_PC SEM_FN_NAME (sh64_compact,fmov2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1677,40 +1716,31 @@ SEM_FN_NAME (sh64_compact,fmov2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (GET_H_SZBIT ())) { { - SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); - } -} else { -if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { - { - DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); - SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); + DF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); + SET_H_FMOV (FLD (f_rn), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); } } else { { DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); + SET_H_FMOV (FLD (f_rn), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); } } -} abuf->written = written; return vpc; #undef FLD } -/* fmov3-compact: fmov @${rm}+, frn */ +/* fmov3-compact: fmov @${rm}+, fmovn */ static SEM_PC SEM_FN_NAME (sh64_compact,fmov3_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1719,40 +1749,31 @@ SEM_FN_NAME (sh64_compact,fmov3_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (GET_H_SZBIT ())) { { { - SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); + DF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); + SET_H_FMOV (FLD (f_rn), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); } { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); SET_H_GRC (FLD (f_rm), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } } else { { -if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { { DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); - SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); - } -} else { - { - DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); + SET_H_FMOV (FLD (f_rn), opval); + written |= (1 << 4); + TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); } -} { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 8); SET_H_GRC (FLD (f_rm), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } } @@ -1762,12 +1783,12 @@ if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { #undef FLD } -/* fmov4-compact: fmov @(r0, $rm), $frn */ +/* fmov4-compact: fmov @(r0, $rm), $fmovn */ static SEM_PC SEM_FN_NAME (sh64_compact,fmov4_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1775,40 +1796,31 @@ SEM_FN_NAME (sh64_compact,fmov4_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (GET_H_SZBIT ())) { { - SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); - } -} else { -if (EQSI (ANDSI (FLD (f_rn), 1), 1)) { - { - DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); - SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval); + DF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); + SET_H_FMOV (FLD (f_rn), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); } } else { { DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval); + SET_H_FMOV (FLD (f_rn), opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "fmov", 'f', opval); } } -} abuf->written = written; return vpc; #undef FLD } -/* fmov5-compact: fmov $frm, @$rn */ +/* fmov5-compact: fmov $fmovm, @$rn */ static SEM_PC SEM_FN_NAME (sh64_compact,fmov5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1816,40 +1828,31 @@ SEM_FN_NAME (sh64_compact,fmov5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (GET_H_SZBIT ())) { { - SF opval = GET_H_FRC (FLD (f_rm)); + SF opval = GET_H_FMOV (FLD (f_rm)); SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); - written |= (1 << 6); - TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); - } -} else { -if (EQSI (ANDSI (FLD (f_rm), 1), 1)) { - { - DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); - SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); - written |= (1 << 7); + written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); } } else { { - DF opval = GET_H_DR (FLD (f_rm)); + DF opval = GET_H_FMOV (FLD (f_rm)); SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); - written |= (1 << 7); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); } } -} abuf->written = written; return vpc; #undef FLD } -/* fmov6-compact: fmov $frm, @-$rn */ +/* fmov6-compact: fmov $fmovm, @-$rn */ static SEM_PC SEM_FN_NAME (sh64_compact,fmov6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1860,13 +1863,13 @@ if (NOTBI (GET_H_SZBIT ())) { { SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { - SF opval = GET_H_FRC (FLD (f_rm)); + SF opval = GET_H_FMOV (FLD (f_rm)); SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); - written |= (1 << 6); + written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); } } @@ -1875,38 +1878,29 @@ if (NOTBI (GET_H_SZBIT ())) { { SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 8); SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); - } -if (EQSI (ANDSI (FLD (f_rm), 1), 1)) { - { - DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); - SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); + written |= (1 << 5); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } -} else { { - DF opval = GET_H_DR (FLD (f_rm)); + DF opval = GET_H_FMOV (FLD (f_rm)); SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval); - written |= (1 << 7); + written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); } } } -} abuf->written = written; return vpc; #undef FLD } -/* fmov7-compact: fmov $frm, @(r0, $rn) */ +/* fmov7-compact: fmov $fmovm, @(r0, $rn) */ static SEM_PC SEM_FN_NAME (sh64_compact,fmov7_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1914,30 +1908,63 @@ SEM_FN_NAME (sh64_compact,fmov7_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (NOTBI (GET_H_SZBIT ())) { { - SF opval = GET_H_FRC (FLD (f_rm)); + SF opval = GET_H_FMOV (FLD (f_rm)); SETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); - written |= (1 << 7); + written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); } } else { -if (EQSI (ANDSI (FLD (f_rm), 1), 1)) { { - DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1)))); + DF opval = GET_H_FMOV (FLD (f_rm)); SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); - written |= (1 << 8); + written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); } -} else { +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* fmov8-compact: fmov.d @($imm12x8, $rm), $drn */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,fmov8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmov8_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + { - DF opval = GET_H_DR (FLD (f_rm)); - SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); + DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm12x8))); + SET_H_DRC (FLD (f_dn), opval); + TRACE_RESULT (current_cpu, abuf, "drc", 'f', opval); } -} + + return vpc; +#undef FLD } - abuf->written = written; +/* fmov9-compact: mov.l $drm, @($imm12x8, $rn) */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,fmov9_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmov9_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + DF opval = GET_H_DRC (FLD (f_dm)); + SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm12x8)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); + } + return vpc; #undef FLD } @@ -1947,7 +1974,7 @@ if (EQSI (ANDSI (FLD (f_rm), 1), 1)) { static SEM_PC SEM_FN_NAME (sh64_compact,fmul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -1955,17 +1982,17 @@ SEM_FN_NAME (sh64_compact,fmul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GET_H_PRBIT ()) { { - DF opval = sh64_fmuld (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + DF opval = sh64_fmuld (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_fmuls (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_fmuls (current_cpu, GET_H_FSD (FLD (f_rm)), GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -1987,17 +2014,17 @@ SEM_FN_NAME (sh64_compact,fneg_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GET_H_PRBIT ()) { { - DF opval = sh64_fnegd (current_cpu, GET_H_DR (FLD (f_rn))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + DF opval = sh64_fnegd (current_cpu, GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_fnegs (current_cpu, GET_H_FRC (FLD (f_rn))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_fnegs (current_cpu, GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -2061,17 +2088,17 @@ SEM_FN_NAME (sh64_compact,fsqrt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GET_H_PRBIT ()) { { - DF opval = sh64_fsqrtd (current_cpu, GET_H_DR (FLD (f_rn))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + DF opval = sh64_fsqrtd (current_cpu, GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_fsqrts (current_cpu, GET_H_FRC (FLD (f_rn))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_fsqrts (current_cpu, GET_H_FSD (FLD (f_rn))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -2094,7 +2121,7 @@ SEM_FN_NAME (sh64_compact,fsts_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SF opval = CPU (h_fr[((UINT) 32)]); SET_H_FRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "frc", 'f', opval); } return vpc; @@ -2106,7 +2133,7 @@ SEM_FN_NAME (sh64_compact,fsts_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,fsub_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2114,17 +2141,17 @@ SEM_FN_NAME (sh64_compact,fsub_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (GET_H_PRBIT ()) { { - DF opval = sh64_fsubd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm))); - SET_H_DR (FLD (f_rn), opval); - written |= (1 << 8); - TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval); + DF opval = sh64_fsubd (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } else { { - SF opval = sh64_fsubs (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm))); - SET_H_FRC (FLD (f_rn), opval); - written |= (1 << 7); - TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval); + DF opval = sh64_fsubs (current_cpu, GET_H_FSD (FLD (f_rn)), GET_H_FSD (FLD (f_rm))); + SET_H_FSD (FLD (f_rn), opval); + written |= (1 << 3); + TRACE_RESULT (current_cpu, abuf, "fsd", 'f', opval); } } @@ -2145,9 +2172,9 @@ SEM_FN_NAME (sh64_compact,ftrc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - SF opval = ((GET_H_PRBIT ()) ? (sh64_ftrcdl (current_cpu, GET_H_DR (FLD (f_rn)))) : (sh64_ftrcsl (current_cpu, GET_H_FRC (FLD (f_rn))))); + SF opval = ((GET_H_PRBIT ()) ? (sh64_ftrcdl (current_cpu, GET_H_FSD (FLD (f_rn)))) : (sh64_ftrcsl (current_cpu, GET_H_FSD (FLD (f_rn))))); CPU (h_fr[((UINT) 32)]) = opval; - TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); } return vpc; @@ -2165,47 +2192,7 @@ SEM_FN_NAME (sh64_compact,ftrv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -{ - QI tmp_n; - SF tmp_res; - tmp_n = FLD (f_vn); - tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 0)), GET_H_FRC (tmp_n)); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 4)), GET_H_FRC (ADDQI (tmp_n, 1)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 8)), GET_H_FRC (ADDQI (tmp_n, 2)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 12)), GET_H_FRC (ADDQI (tmp_n, 3)))); - { - SF opval = tmp_res; - SET_H_FRC (tmp_n, opval); - TRACE_RESULT (current_cpu, abuf, "frc-n", 'f', opval); - } - tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 1)), GET_H_FRC (tmp_n)); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 5)), GET_H_FRC (ADDQI (tmp_n, 1)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 9)), GET_H_FRC (ADDQI (tmp_n, 2)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 13)), GET_H_FRC (ADDQI (tmp_n, 3)))); - { - SF opval = tmp_res; - SET_H_FRC (ADDQI (tmp_n, 1), opval); - TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-1", 'f', opval); - } - tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 2)), GET_H_FRC (tmp_n)); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 6)), GET_H_FRC (ADDQI (tmp_n, 1)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 10)), GET_H_FRC (ADDQI (tmp_n, 2)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 14)), GET_H_FRC (ADDQI (tmp_n, 3)))); - { - SF opval = tmp_res; - SET_H_FRC (ADDQI (tmp_n, 2), opval); - TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-2", 'f', opval); - } - tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 3)), GET_H_FRC (tmp_n)); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 7)), GET_H_FRC (ADDQI (tmp_n, 1)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 11)), GET_H_FRC (ADDQI (tmp_n, 2)))); - tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 15)), GET_H_FRC (ADDQI (tmp_n, 3)))); - { - SF opval = tmp_res; - SET_H_FRC (ADDQI (tmp_n, 3), opval); - TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-3", 'f', opval); - } -} +sh64_ftrv (current_cpu, FLD (f_vn)); return vpc; #undef FLD @@ -2225,11 +2212,20 @@ SEM_FN_NAME (sh64_compact,jmp_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ + { UDI opval = GET_H_GRC (FLD (f_rn)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +((void) 0); /*nop*/ +} SEM_BRANCH_FINI (vpc); return vpc; @@ -2255,12 +2251,21 @@ SEM_FN_NAME (sh64_compact,jsr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SET_H_PR (opval); TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval); } +} + { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ { UDI opval = GET_H_GRC (FLD (f_rn)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +((void) 0); /*nop*/ } SEM_BRANCH_FINI (vpc); @@ -2268,10 +2273,10 @@ SEM_FN_NAME (sh64_compact,jsr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) #undef FLD } -/* ldc-compact: ldc $rn, gbr */ +/* ldc-gbr-compact: ldc $rn, gbr */ static SEM_PC -SEM_FN_NAME (sh64_compact,ldc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +SEM_FN_NAME (sh64_compact,ldc_gbr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.sfmt_movw10_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); @@ -2289,10 +2294,52 @@ SEM_FN_NAME (sh64_compact,ldc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) #undef FLD } -/* ldcl-compact: ldc.l @${rn}+, gbr */ +/* ldc-vbr-compact: ldc $rn, vbr */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,ldc_vbr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = GET_H_GRC (FLD (f_rn)); + SET_H_VBR (opval); + TRACE_RESULT (current_cpu, abuf, "vbr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldc-sr-compact: ldc $rn, sr */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,ldc_sr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = GET_H_GRC (FLD (f_rn)); + CPU (h_sr) = opval; + TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldcl-gbr-compact: ldc.l @${rn}+, gbr */ static SEM_PC -SEM_FN_NAME (sh64_compact,ldcl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +SEM_FN_NAME (sh64_compact,ldcl_gbr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.sfmt_movw10_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); @@ -2309,7 +2356,35 @@ SEM_FN_NAME (sh64_compact,ldcl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* ldcl-vbr-compact: ldc.l @${rn}+, vbr */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,ldcl_vbr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + { + SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); + SET_H_VBR (opval); + TRACE_RESULT (current_cpu, abuf, "vbr", 'x', opval); + } + { + SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2330,7 +2405,7 @@ SEM_FN_NAME (sh64_compact,lds_fpscr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_ { SI opval = GET_H_GRC (FLD (f_rn)); - SET_H_FPCCR (opval); + CPU (h_fpscr) = opval; TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval); } @@ -2352,13 +2427,13 @@ SEM_FN_NAME (sh64_compact,ldsl_fpscr_compact) (SIM_CPU *current_cpu, SEM_ARG sem { { SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn))); - SET_H_FPCCR (opval); + CPU (h_fpscr) = opval; TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval); } { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2380,7 +2455,7 @@ SEM_FN_NAME (sh64_compact,lds_fpul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_a { SF opval = SUBWORDSISF (GET_H_GRC (FLD (f_rn))); CPU (h_fr[((UINT) 32)]) = opval; - TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); } return vpc; @@ -2402,12 +2477,12 @@ SEM_FN_NAME (sh64_compact,ldsl_fpul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_ { SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn))); CPU (h_fr[((UINT) 32)]) = opval; - TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval); + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); } { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2456,7 +2531,7 @@ SEM_FN_NAME (sh64_compact,ldsl_mach_compact) (SIM_CPU *current_cpu, SEM_ARG sem_ { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2505,7 +2580,7 @@ SEM_FN_NAME (sh64_compact,ldsl_macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_ { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2554,7 +2629,7 @@ SEM_FN_NAME (sh64_compact,ldsl_pr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_ar { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2567,7 +2642,7 @@ SEM_FN_NAME (sh64_compact,ldsl_pr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_ar static SEM_PC SEM_FN_NAME (sh64_compact,macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2583,20 +2658,20 @@ SEM_FN_NAME (sh64_compact,macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } if (EQSI (FLD (f_rn), FLD (f_rm))) { { { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 11); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } } @@ -2605,7 +2680,7 @@ if (EQSI (FLD (f_rn), FLD (f_rm))) { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 11); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } tmp_tmpry = MULDI (ZEXTSIDI (tmp_x), ZEXTSIDI (tmp_y)); tmp_mac = ORDI (SLLDI (ZEXTSIDI (GET_H_MACH ()), 32), ZEXTSIDI (GET_H_MACL ())); @@ -2649,7 +2724,7 @@ if (LTDI (tmp_result, tmp_min)) { static SEM_PC SEM_FN_NAME (sh64_compact,macw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2665,20 +2740,20 @@ SEM_FN_NAME (sh64_compact,macw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } if (EQSI (FLD (f_rn), FLD (f_rm))) { { { SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 11); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } } @@ -2687,7 +2762,7 @@ if (EQSI (FLD (f_rn), FLD (f_rm))) { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 11); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } tmp_tmpry = MULSI (ZEXTHISI (tmp_x), ZEXTHISI (tmp_y)); if (GET_H_SBIT ()) { @@ -2737,7 +2812,7 @@ if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) { static SEM_PC SEM_FN_NAME (sh64_compact,mov_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2746,7 +2821,7 @@ SEM_FN_NAME (sh64_compact,mov_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { DI opval = GET_H_GR (FLD (f_rm)); SET_H_GR (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); } return vpc; @@ -2767,7 +2842,28 @@ SEM_FN_NAME (sh64_compact,movi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = EXTQIDI (ANDQI (FLD (f_imm8), 255)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* movi20-compact: movi20 #$imm20, $rn */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,movi20_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movi20_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = FLD (f_imm20); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -2779,7 +2875,7 @@ SEM_FN_NAME (sh64_compact,movi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,movb1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2800,7 +2896,7 @@ SEM_FN_NAME (sh64_compact,movb1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,movb2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2817,7 +2913,7 @@ SEM_FN_NAME (sh64_compact,movb2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2830,7 +2926,7 @@ SEM_FN_NAME (sh64_compact,movb2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,movb3_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2901,7 +2997,7 @@ SEM_FN_NAME (sh64_compact,movb5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,movb6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2910,7 +3006,7 @@ SEM_FN_NAME (sh64_compact,movb6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = EXTQISI (GETMEMQI (current_cpu, pc, GET_H_GRC (FLD (f_rm)))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -2922,7 +3018,7 @@ SEM_FN_NAME (sh64_compact,movb6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,movb7_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2936,20 +3032,20 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { SI opval = EXTQISI (tmp_data); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 1); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } { SI opval = EXTQISI (tmp_data); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -2963,7 +3059,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { static SEM_PC SEM_FN_NAME (sh64_compact,movb8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2972,7 +3068,7 @@ SEM_FN_NAME (sh64_compact,movb8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -2993,7 +3089,7 @@ SEM_FN_NAME (sh64_compact,movb9_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8)))); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -3014,7 +3110,7 @@ SEM_FN_NAME (sh64_compact,movb10_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg { SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4)))); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -3026,7 +3122,7 @@ SEM_FN_NAME (sh64_compact,movb10_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg static SEM_PC SEM_FN_NAME (sh64_compact,movl1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3047,7 +3143,7 @@ SEM_FN_NAME (sh64_compact,movl1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,movl2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3064,7 +3160,7 @@ SEM_FN_NAME (sh64_compact,movl2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -3077,7 +3173,7 @@ SEM_FN_NAME (sh64_compact,movl2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,movl3_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3140,7 +3236,7 @@ SEM_FN_NAME (sh64_compact,movl5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,movl6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3149,7 +3245,7 @@ SEM_FN_NAME (sh64_compact,movl6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -3161,7 +3257,7 @@ SEM_FN_NAME (sh64_compact,movl6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,movl7_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3171,21 +3267,21 @@ SEM_FN_NAME (sh64_compact,movl7_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } if (EQSI (FLD (f_rm), FLD (f_rn))) { { SI opval = GET_H_GRC (FLD (f_rn)); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 5); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } } @@ -3200,7 +3296,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { static SEM_PC SEM_FN_NAME (sh64_compact,movl8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3209,7 +3305,7 @@ SEM_FN_NAME (sh64_compact,movl8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -3230,7 +3326,7 @@ SEM_FN_NAME (sh64_compact,movl9_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x4))); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -3251,7 +3347,7 @@ SEM_FN_NAME (sh64_compact,movl10_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg { SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_imm8x4), ANDDI (ADDDI (pc, 4), INVSI (3)))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -3272,7 +3368,49 @@ SEM_FN_NAME (sh64_compact,movl11_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg { SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x4))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* movl12-compact: mov.l @($imm12x4, $rm), $rn */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,movl12_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm12x4))); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* movl13-compact: mov.l $rm, @($imm12x4, $rn) */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,movl13_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movl12_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + + { + SI opval = GET_H_GRC (FLD (f_rm)); + SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm12x4)), opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } return vpc; @@ -3284,7 +3422,7 @@ SEM_FN_NAME (sh64_compact,movl11_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg static SEM_PC SEM_FN_NAME (sh64_compact,movw1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3305,7 +3443,7 @@ SEM_FN_NAME (sh64_compact,movw1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,movw2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3322,7 +3460,7 @@ SEM_FN_NAME (sh64_compact,movw2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -3335,7 +3473,7 @@ SEM_FN_NAME (sh64_compact,movw2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,movw3_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3372,7 +3510,7 @@ SEM_FN_NAME (sh64_compact,movw4_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) #undef FLD } -/* movw5-compact: mov.w r0, @($imm4x2, $rn) */ +/* movw5-compact: mov.w r0, @($imm4x2, $rm) */ static SEM_PC SEM_FN_NAME (sh64_compact,movw5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) @@ -3385,7 +3523,7 @@ SEM_FN_NAME (sh64_compact,movw5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { HI opval = SUBWORDSIHI (GET_H_GRC (((UINT) 0)), 1); - SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm4x2)), opval); + SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x2)), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } @@ -3398,7 +3536,7 @@ SEM_FN_NAME (sh64_compact,movw5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,movw6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3407,7 +3545,7 @@ SEM_FN_NAME (sh64_compact,movw6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = EXTHISI (GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm)))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -3419,7 +3557,7 @@ SEM_FN_NAME (sh64_compact,movw6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,movw7_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3433,20 +3571,20 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { SI opval = EXTHISI (tmp_data); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { { SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2); SET_H_GRC (FLD (f_rm), opval); written |= (1 << 4); - TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } { SI opval = EXTHISI (tmp_data); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -3460,7 +3598,7 @@ if (EQSI (FLD (f_rm), FLD (f_rn))) { static SEM_PC SEM_FN_NAME (sh64_compact,movw8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3469,7 +3607,7 @@ SEM_FN_NAME (sh64_compact,movw8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -3490,7 +3628,7 @@ SEM_FN_NAME (sh64_compact,movw9_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x2)))); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -3511,7 +3649,7 @@ SEM_FN_NAME (sh64_compact,movw10_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg { SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDDI (ADDDI (pc, 4), FLD (f_imm8x2)))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -3523,7 +3661,7 @@ SEM_FN_NAME (sh64_compact,movw10_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg static SEM_PC SEM_FN_NAME (sh64_compact,movw11_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movw11_compact.f +#define FLD(f) abuf->fields.sfmt_movw5_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3532,7 +3670,7 @@ SEM_FN_NAME (sh64_compact,movw11_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg { SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x2)))); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -3553,7 +3691,7 @@ SEM_FN_NAME (sh64_compact,mova_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ADDDI (ANDDI (ADDDI (pc, 4), INVSI (3)), FLD (f_imm8x4)); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -3581,6 +3719,27 @@ SEM_FN_NAME (sh64_compact,movcal_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg #undef FLD } +/* movcol-compact: movco.l r0, @$rn */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,movcol_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = GET_H_GRC (FLD (f_rn)); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + + return vpc; +#undef FLD +} + /* movt-compact: movt $rn */ static SEM_PC @@ -3595,19 +3754,68 @@ SEM_FN_NAME (sh64_compact,movt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ZEXTBISI (GET_H_TBIT ()); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; #undef FLD } +/* movual-compact: movua.l @$rn, r0 */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,movual_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = sh64_movua (current_cpu, pc, GET_H_GRC (FLD (f_rn))); + SET_H_GRC (((UINT) 0), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* movual2-compact: movua.l @$rn+, r0 */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,movual2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + { + SI opval = sh64_movua (current_cpu, pc, GET_H_GRC (FLD (f_rn))); + SET_H_GRC (((UINT) 0), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + { + SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } +} + + return vpc; +#undef FLD +} + /* mull-compact: mul.l $rm, $rn */ static SEM_PC SEM_FN_NAME (sh64_compact,mull_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3628,7 +3836,7 @@ SEM_FN_NAME (sh64_compact,mull_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,mulsw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3649,7 +3857,7 @@ SEM_FN_NAME (sh64_compact,mulsw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,muluw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3670,7 +3878,7 @@ SEM_FN_NAME (sh64_compact,muluw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,neg_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3679,7 +3887,7 @@ SEM_FN_NAME (sh64_compact,neg_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = NEGSI (GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -3691,7 +3899,7 @@ SEM_FN_NAME (sh64_compact,neg_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,negc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3703,7 +3911,7 @@ SEM_FN_NAME (sh64_compact,negc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = SUBCSI (0, GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = tmp_flag; @@ -3738,7 +3946,7 @@ SEM_FN_NAME (sh64_compact,nop_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,not_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3747,7 +3955,7 @@ SEM_FN_NAME (sh64_compact,not_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { DI opval = INVDI (GET_H_GR (FLD (f_rm))); SET_H_GR (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); } return vpc; @@ -3759,13 +3967,20 @@ SEM_FN_NAME (sh64_compact,not_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,ocbi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_movw10_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); +{ + { + SI opval = GET_H_GRC (FLD (f_rn)); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } ((void) 0); /*nop*/ +} return vpc; #undef FLD @@ -3776,13 +3991,20 @@ SEM_FN_NAME (sh64_compact,ocbi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,ocbp_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_movw10_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); +{ + { + SI opval = GET_H_GRC (FLD (f_rn)); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } ((void) 0); /*nop*/ +} return vpc; #undef FLD @@ -3793,13 +4015,20 @@ SEM_FN_NAME (sh64_compact,ocbp_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,ocbwb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_movw10_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); +{ + { + SI opval = GET_H_GRC (FLD (f_rn)); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } ((void) 0); /*nop*/ +} return vpc; #undef FLD @@ -3810,7 +4039,7 @@ SEM_FN_NAME (sh64_compact,ocbwb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,or_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -3819,7 +4048,7 @@ SEM_FN_NAME (sh64_compact,or_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { DI opval = ORDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn))); SET_H_GR (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); } return vpc; @@ -3840,7 +4069,7 @@ SEM_FN_NAME (sh64_compact,ori_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ORSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8))); SET_H_GRC (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -3879,13 +4108,13 @@ SEM_FN_NAME (sh64_compact,orb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,pref_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_movw10_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -((void) 0); /*nop*/ +sh64_pref (current_cpu, GET_H_GRC (FLD (f_rn))); return vpc; #undef FLD @@ -3908,7 +4137,7 @@ SEM_FN_NAME (sh64_compact,rotcl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), GET_H_TBIT ()); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_temp) ? (1) : (0)); @@ -3940,7 +4169,7 @@ SEM_FN_NAME (sh64_compact,rotcr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_lsbit) ? (1) : (0)); @@ -3970,7 +4199,7 @@ SEM_FN_NAME (sh64_compact,rotl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), tmp_temp); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_temp) ? (1) : (0)); @@ -4002,7 +4231,7 @@ SEM_FN_NAME (sh64_compact,rotr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_lsbit) ? (1) : (0)); @@ -4029,11 +4258,20 @@ SEM_FN_NAME (sh64_compact,rts_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { { + UDI opval = ADDDI (pc, 2); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +((void) 0); /*nop*/ +{ + { UDI opval = GET_H_PR (); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +((void) 0); /*nop*/ +} SEM_BRANCH_FINI (vpc); return vpc; @@ -4087,44 +4325,44 @@ SEM_FN_NAME (sh64_compact,sett_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,shad_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - QI tmp_shamt; - tmp_shamt = ANDQI (GET_H_GRC (FLD (f_rm)), 31); + SI tmp_shamt; + tmp_shamt = ANDSI (GET_H_GRC (FLD (f_rm)), 31); if (GESI (GET_H_GRC (FLD (f_rm)), 0)) { { SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt); SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { -if (NEQI (tmp_shamt, 0)) { +if (NESI (tmp_shamt, 0)) { { SI opval = SRASI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt)); SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { if (LTSI (GET_H_GRC (FLD (f_rn)), 0)) { { SI opval = NEGSI (1); SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { { SI opval = 0; SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } } @@ -4153,7 +4391,7 @@ SEM_FN_NAME (sh64_compact,shal_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_t) ? (1) : (0)); @@ -4183,7 +4421,7 @@ SEM_FN_NAME (sh64_compact,shar_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = SRASI (GET_H_GRC (FLD (f_rn)), 1); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_t) ? (1) : (0)); @@ -4201,36 +4439,36 @@ SEM_FN_NAME (sh64_compact,shar_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,shld_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - QI tmp_shamt; - tmp_shamt = ANDQI (GET_H_GRC (FLD (f_rm)), 31); + SI tmp_shamt; + tmp_shamt = ANDSI (GET_H_GRC (FLD (f_rm)), 31); if (GESI (GET_H_GRC (FLD (f_rm)), 0)) { { SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt); SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { -if (NEQI (tmp_shamt, 0)) { +if (NESI (tmp_shamt, 0)) { { SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt)); SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } else { { SI opval = 0; SET_H_GRC (FLD (f_rn), opval); - written |= (1 << 3); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + written |= (1 << 2); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } } @@ -4258,7 +4496,7 @@ SEM_FN_NAME (sh64_compact,shll_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_t) ? (1) : (0)); @@ -4285,7 +4523,7 @@ SEM_FN_NAME (sh64_compact,shll2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 2); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -4306,7 +4544,7 @@ SEM_FN_NAME (sh64_compact,shll8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 8); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -4327,7 +4565,7 @@ SEM_FN_NAME (sh64_compact,shll16_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg { SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 16); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -4351,7 +4589,7 @@ SEM_FN_NAME (sh64_compact,shlr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 1); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_t) ? (1) : (0)); @@ -4378,7 +4616,7 @@ SEM_FN_NAME (sh64_compact,shlr2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 2); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -4399,7 +4637,7 @@ SEM_FN_NAME (sh64_compact,shlr8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 8); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -4420,7 +4658,7 @@ SEM_FN_NAME (sh64_compact,shlr16_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg { SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 16); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -4441,7 +4679,28 @@ SEM_FN_NAME (sh64_compact,stc_gbr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_ar { SI opval = GET_H_GBR (); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* stc-vbr-compact: stc vbr, $rn */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,stc_vbr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + + { + SI opval = GET_H_VBR (); + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -4470,7 +4729,37 @@ SEM_FN_NAME (sh64_compact,stcl_gbr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_a { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* stcl-vbr-compact: stc.l vbr, @-$rn */ + +static SEM_PC +SEM_FN_NAME (sh64_compact,stcl_vbr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movw10_compact.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); + +{ + DI tmp_addr; + tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); + { + SI opval = GET_H_VBR (); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + { + SI opval = tmp_addr; + SET_H_GRC (FLD (f_rn), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -4490,9 +4779,9 @@ SEM_FN_NAME (sh64_compact,sts_fpscr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - SI opval = GET_H_FPCCR (); + SI opval = CPU (h_fpscr); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -4514,14 +4803,14 @@ SEM_FN_NAME (sh64_compact,stsl_fpscr_compact) (SIM_CPU *current_cpu, SEM_ARG sem DI tmp_addr; tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4); { - SI opval = GET_H_FPCCR (); + SI opval = CPU (h_fpscr); SETMEMSI (current_cpu, pc, tmp_addr, opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -4543,7 +4832,7 @@ SEM_FN_NAME (sh64_compact,sts_fpul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_a { SI opval = SUBWORDSFSI (CPU (h_fr[((UINT) 32)])); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -4572,7 +4861,7 @@ SEM_FN_NAME (sh64_compact,stsl_fpul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_ { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -4594,7 +4883,7 @@ SEM_FN_NAME (sh64_compact,sts_mach_compact) (SIM_CPU *current_cpu, SEM_ARG sem_a { SI opval = GET_H_MACH (); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -4623,7 +4912,7 @@ SEM_FN_NAME (sh64_compact,stsl_mach_compact) (SIM_CPU *current_cpu, SEM_ARG sem_ { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -4645,7 +4934,7 @@ SEM_FN_NAME (sh64_compact,sts_macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_a { SI opval = GET_H_MACL (); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -4674,7 +4963,7 @@ SEM_FN_NAME (sh64_compact,stsl_macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_ { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -4696,7 +4985,7 @@ SEM_FN_NAME (sh64_compact,sts_pr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg { SI opval = GET_H_PR (); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -4725,7 +5014,7 @@ SEM_FN_NAME (sh64_compact,stsl_pr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_ar { SI opval = tmp_addr; SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -4738,7 +5027,7 @@ SEM_FN_NAME (sh64_compact,stsl_pr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_ar static SEM_PC SEM_FN_NAME (sh64_compact,sub_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4747,7 +5036,7 @@ SEM_FN_NAME (sh64_compact,sub_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -4759,7 +5048,7 @@ SEM_FN_NAME (sh64_compact,sub_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,subc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4771,7 +5060,7 @@ SEM_FN_NAME (sh64_compact,subc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = SUBCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ()); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = tmp_flag; @@ -4789,7 +5078,7 @@ SEM_FN_NAME (sh64_compact,subc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,subv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4801,7 +5090,7 @@ SEM_FN_NAME (sh64_compact,subv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm))); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } { BI opval = ((tmp_t) ? (1) : (0)); @@ -4819,7 +5108,7 @@ SEM_FN_NAME (sh64_compact,subv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,swapb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4835,7 +5124,7 @@ SEM_FN_NAME (sh64_compact,swapb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ORSI (SLLSI (tmp_top_half, 16), ORSI (SLLSI (tmp_byte0, 8), tmp_byte1)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } } @@ -4848,7 +5137,7 @@ SEM_FN_NAME (sh64_compact,swapb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,swapw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4857,7 +5146,7 @@ SEM_FN_NAME (sh64_compact,swapw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rm)), 16), SLLSI (GET_H_GRC (FLD (f_rm)), 16)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -4917,7 +5206,7 @@ sh64_compact_trapa (current_cpu, FLD (f_imm8), pc); static SEM_PC SEM_FN_NAME (sh64_compact,tst_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4984,7 +5273,7 @@ SEM_FN_NAME (sh64_compact,tstb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,xor_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4993,7 +5282,7 @@ SEM_FN_NAME (sh64_compact,xor_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { DI opval = XORDI (GET_H_GR (FLD (f_rn)), GET_H_GR (FLD (f_rm))); SET_H_GR (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); } return vpc; @@ -5012,9 +5301,9 @@ SEM_FN_NAME (sh64_compact,xori_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = XORDI (GET_H_GR (((UINT) 0)), ZEXTSIDI (FLD (f_imm8))); - SET_H_GR (((UINT) 0), opval); - TRACE_RESULT (current_cpu, abuf, "gr-0", 'D', opval); + SI opval = XORSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8))); + SET_H_GRC (((UINT) 0), opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -5053,7 +5342,7 @@ SEM_FN_NAME (sh64_compact,xorb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_compact,xtrct_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_movl5_compact.f +#define FLD(f) abuf->fields.sfmt_movl12_compact.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5062,7 +5351,7 @@ SEM_FN_NAME (sh64_compact,xtrct_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rm)), 16), SRLSI (GET_H_GRC (FLD (f_rn)), 16)); SET_H_GRC (FLD (f_rn), opval); - TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval); + TRACE_RESULT (current_cpu, abuf, "grc", 'x', opval); } return vpc; @@ -5109,6 +5398,8 @@ static const struct sem_fn_desc sem_fns[] = { { SH64_COMPACT_INSN_DIV0S_COMPACT, SEM_FN_NAME (sh64_compact,div0s_compact) }, { SH64_COMPACT_INSN_DIV0U_COMPACT, SEM_FN_NAME (sh64_compact,div0u_compact) }, { SH64_COMPACT_INSN_DIV1_COMPACT, SEM_FN_NAME (sh64_compact,div1_compact) }, + { SH64_COMPACT_INSN_DIVU_COMPACT, SEM_FN_NAME (sh64_compact,divu_compact) }, + { SH64_COMPACT_INSN_MULR_COMPACT, SEM_FN_NAME (sh64_compact,mulr_compact) }, { SH64_COMPACT_INSN_DMULSL_COMPACT, SEM_FN_NAME (sh64_compact,dmulsl_compact) }, { SH64_COMPACT_INSN_DMULUL_COMPACT, SEM_FN_NAME (sh64_compact,dmulul_compact) }, { SH64_COMPACT_INSN_DT_COMPACT, SEM_FN_NAME (sh64_compact,dt_compact) }, @@ -5136,6 +5427,8 @@ static const struct sem_fn_desc sem_fns[] = { { SH64_COMPACT_INSN_FMOV5_COMPACT, SEM_FN_NAME (sh64_compact,fmov5_compact) }, { SH64_COMPACT_INSN_FMOV6_COMPACT, SEM_FN_NAME (sh64_compact,fmov6_compact) }, { SH64_COMPACT_INSN_FMOV7_COMPACT, SEM_FN_NAME (sh64_compact,fmov7_compact) }, + { SH64_COMPACT_INSN_FMOV8_COMPACT, SEM_FN_NAME (sh64_compact,fmov8_compact) }, + { SH64_COMPACT_INSN_FMOV9_COMPACT, SEM_FN_NAME (sh64_compact,fmov9_compact) }, { SH64_COMPACT_INSN_FMUL_COMPACT, SEM_FN_NAME (sh64_compact,fmul_compact) }, { SH64_COMPACT_INSN_FNEG_COMPACT, SEM_FN_NAME (sh64_compact,fneg_compact) }, { SH64_COMPACT_INSN_FRCHG_COMPACT, SEM_FN_NAME (sh64_compact,frchg_compact) }, @@ -5147,8 +5440,11 @@ static const struct sem_fn_desc sem_fns[] = { { SH64_COMPACT_INSN_FTRV_COMPACT, SEM_FN_NAME (sh64_compact,ftrv_compact) }, { SH64_COMPACT_INSN_JMP_COMPACT, SEM_FN_NAME (sh64_compact,jmp_compact) }, { SH64_COMPACT_INSN_JSR_COMPACT, SEM_FN_NAME (sh64_compact,jsr_compact) }, - { SH64_COMPACT_INSN_LDC_COMPACT, SEM_FN_NAME (sh64_compact,ldc_compact) }, - { SH64_COMPACT_INSN_LDCL_COMPACT, SEM_FN_NAME (sh64_compact,ldcl_compact) }, + { SH64_COMPACT_INSN_LDC_GBR_COMPACT, SEM_FN_NAME (sh64_compact,ldc_gbr_compact) }, + { SH64_COMPACT_INSN_LDC_VBR_COMPACT, SEM_FN_NAME (sh64_compact,ldc_vbr_compact) }, + { SH64_COMPACT_INSN_LDC_SR_COMPACT, SEM_FN_NAME (sh64_compact,ldc_sr_compact) }, + { SH64_COMPACT_INSN_LDCL_GBR_COMPACT, SEM_FN_NAME (sh64_compact,ldcl_gbr_compact) }, + { SH64_COMPACT_INSN_LDCL_VBR_COMPACT, SEM_FN_NAME (sh64_compact,ldcl_vbr_compact) }, { SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, SEM_FN_NAME (sh64_compact,lds_fpscr_compact) }, { SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, SEM_FN_NAME (sh64_compact,ldsl_fpscr_compact) }, { SH64_COMPACT_INSN_LDS_FPUL_COMPACT, SEM_FN_NAME (sh64_compact,lds_fpul_compact) }, @@ -5163,6 +5459,7 @@ static const struct sem_fn_desc sem_fns[] = { { SH64_COMPACT_INSN_MACW_COMPACT, SEM_FN_NAME (sh64_compact,macw_compact) }, { SH64_COMPACT_INSN_MOV_COMPACT, SEM_FN_NAME (sh64_compact,mov_compact) }, { SH64_COMPACT_INSN_MOVI_COMPACT, SEM_FN_NAME (sh64_compact,movi_compact) }, + { SH64_COMPACT_INSN_MOVI20_COMPACT, SEM_FN_NAME (sh64_compact,movi20_compact) }, { SH64_COMPACT_INSN_MOVB1_COMPACT, SEM_FN_NAME (sh64_compact,movb1_compact) }, { SH64_COMPACT_INSN_MOVB2_COMPACT, SEM_FN_NAME (sh64_compact,movb2_compact) }, { SH64_COMPACT_INSN_MOVB3_COMPACT, SEM_FN_NAME (sh64_compact,movb3_compact) }, @@ -5184,6 +5481,8 @@ static const struct sem_fn_desc sem_fns[] = { { SH64_COMPACT_INSN_MOVL9_COMPACT, SEM_FN_NAME (sh64_compact,movl9_compact) }, { SH64_COMPACT_INSN_MOVL10_COMPACT, SEM_FN_NAME (sh64_compact,movl10_compact) }, { SH64_COMPACT_INSN_MOVL11_COMPACT, SEM_FN_NAME (sh64_compact,movl11_compact) }, + { SH64_COMPACT_INSN_MOVL12_COMPACT, SEM_FN_NAME (sh64_compact,movl12_compact) }, + { SH64_COMPACT_INSN_MOVL13_COMPACT, SEM_FN_NAME (sh64_compact,movl13_compact) }, { SH64_COMPACT_INSN_MOVW1_COMPACT, SEM_FN_NAME (sh64_compact,movw1_compact) }, { SH64_COMPACT_INSN_MOVW2_COMPACT, SEM_FN_NAME (sh64_compact,movw2_compact) }, { SH64_COMPACT_INSN_MOVW3_COMPACT, SEM_FN_NAME (sh64_compact,movw3_compact) }, @@ -5197,7 +5496,10 @@ static const struct sem_fn_desc sem_fns[] = { { SH64_COMPACT_INSN_MOVW11_COMPACT, SEM_FN_NAME (sh64_compact,movw11_compact) }, { SH64_COMPACT_INSN_MOVA_COMPACT, SEM_FN_NAME (sh64_compact,mova_compact) }, { SH64_COMPACT_INSN_MOVCAL_COMPACT, SEM_FN_NAME (sh64_compact,movcal_compact) }, + { SH64_COMPACT_INSN_MOVCOL_COMPACT, SEM_FN_NAME (sh64_compact,movcol_compact) }, { SH64_COMPACT_INSN_MOVT_COMPACT, SEM_FN_NAME (sh64_compact,movt_compact) }, + { SH64_COMPACT_INSN_MOVUAL_COMPACT, SEM_FN_NAME (sh64_compact,movual_compact) }, + { SH64_COMPACT_INSN_MOVUAL2_COMPACT, SEM_FN_NAME (sh64_compact,movual2_compact) }, { SH64_COMPACT_INSN_MULL_COMPACT, SEM_FN_NAME (sh64_compact,mull_compact) }, { SH64_COMPACT_INSN_MULSW_COMPACT, SEM_FN_NAME (sh64_compact,mulsw_compact) }, { SH64_COMPACT_INSN_MULUW_COMPACT, SEM_FN_NAME (sh64_compact,muluw_compact) }, @@ -5232,7 +5534,9 @@ static const struct sem_fn_desc sem_fns[] = { { SH64_COMPACT_INSN_SHLR8_COMPACT, SEM_FN_NAME (sh64_compact,shlr8_compact) }, { SH64_COMPACT_INSN_SHLR16_COMPACT, SEM_FN_NAME (sh64_compact,shlr16_compact) }, { SH64_COMPACT_INSN_STC_GBR_COMPACT, SEM_FN_NAME (sh64_compact,stc_gbr_compact) }, + { SH64_COMPACT_INSN_STC_VBR_COMPACT, SEM_FN_NAME (sh64_compact,stc_vbr_compact) }, { SH64_COMPACT_INSN_STCL_GBR_COMPACT, SEM_FN_NAME (sh64_compact,stcl_gbr_compact) }, + { SH64_COMPACT_INSN_STCL_VBR_COMPACT, SEM_FN_NAME (sh64_compact,stcl_vbr_compact) }, { SH64_COMPACT_INSN_STS_FPSCR_COMPACT, SEM_FN_NAME (sh64_compact,sts_fpscr_compact) }, { SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, SEM_FN_NAME (sh64_compact,stsl_fpscr_compact) }, { SH64_COMPACT_INSN_STS_FPUL_COMPACT, SEM_FN_NAME (sh64_compact,sts_fpul_compact) }, diff --git a/sim/sh64/sem-media-switch.c b/sim/sh64/sem-media-switch.c index 075738a..cbbf524 100644 --- a/sim/sh64/sem-media-switch.c +++ b/sim/sh64/sem-media-switch.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -548,12 +548,19 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_xori.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + { + DI opval = GET_H_GR (FLD (f_left)); + SET_H_GR (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); + } ((void) 0); /*nop*/ +} #undef FLD } @@ -626,6 +633,8 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -634,6 +643,7 @@ if (EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -651,6 +661,8 @@ if (EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (EQDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -659,6 +671,7 @@ if (EQDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -676,6 +689,8 @@ if (EQDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (GEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -684,6 +699,7 @@ if (GEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -701,6 +717,8 @@ if (GEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (GEUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -709,6 +727,7 @@ if (GEUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -726,6 +745,8 @@ if (GEUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -734,6 +755,7 @@ if (GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -751,6 +773,8 @@ if (GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -759,6 +783,7 @@ if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -787,6 +812,11 @@ if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } +if (EQSI (FLD (f_dest), 63)) { +((void) 0); /*nop*/ +} else { +((void) 0); /*nop*/ +} } SEM_BRANCH_FINI (vpc); @@ -804,6 +834,8 @@ if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (NEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -812,6 +844,7 @@ if (NEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -829,6 +862,8 @@ if (NEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (NEDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -837,6 +872,7 @@ if (NEDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -1327,12 +1363,16 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_shori.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -((void) 0); /*nop*/ + { + SF opval = SUBWORDSISF (CPU (h_fpscr)); + CPU (h_fr[FLD (f_dest)]) = opval; + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } #undef FLD } @@ -1348,17 +1388,18 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) { vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - UQI tmp_g; - UQI tmp_h; - SF tmp_temp; - tmp_g = FLD (f_left); - tmp_h = FLD (f_right); - tmp_temp = sh64_fmuls (current_cpu, CPU (h_fr[tmp_g]), CPU (h_fr[tmp_h])); - tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 1)]), CPU (h_fr[ADDQI (tmp_h, 1)]))); - tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 2)]), CPU (h_fr[ADDQI (tmp_h, 2)]))); - tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 3)]), CPU (h_fr[ADDQI (tmp_h, 3)]))); { - SF opval = tmp_temp; + SF opval = GET_H_FV (FLD (f_left)); + SET_H_FV (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval); + } + { + SF opval = GET_H_FV (FLD (f_right)); + SET_H_FV (FLD (f_right), opval); + TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval); + } + { + SF opval = sh64_fiprs (current_cpu, FLD (f_left), FLD (f_right)); CPU (h_fr[FLD (f_dest)]) = opval; TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); } @@ -1397,18 +1438,12 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) { vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - QI tmp_f; - tmp_f = FLD (f_dest); { - SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8))); - CPU (h_fr[tmp_f]) = opval; - TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); - } - { - SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4))); - CPU (h_fr[ADDQI (tmp_f, 1)]) = opval; - TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + SF opval = GET_H_FP (FLD (f_dest)); + SET_H_FP (FLD (f_dest), opval); + TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval); } +sh64_fldp (current_cpu, pc, GET_H_GR (FLD (f_left)), FLD (f_disp10x8), FLD (f_dest)); } #undef FLD @@ -1463,18 +1498,12 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) { vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - QI tmp_f; - tmp_f = FLD (f_dest); - { - SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))); - CPU (h_fr[tmp_f]) = opval; - TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); - } { - SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4))); - CPU (h_fr[ADDQI (tmp_f, 1)]) = opval; - TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + SF opval = GET_H_FP (FLD (f_dest)); + SET_H_FP (FLD (f_dest), opval); + TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval); } +sh64_fldp (current_cpu, pc, GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)), FLD (f_dest)); } #undef FLD @@ -1789,12 +1818,16 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_fabsd.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -((void) 0); /*nop*/ + { + SI opval = SUBWORDSFSI (CPU (h_fr[FLD (f_left_right)])); + CPU (h_fpscr) = opval; + TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval); + } #undef FLD } @@ -1867,18 +1900,12 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) { vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - QI tmp_f; - tmp_f = FLD (f_dest); - { - SF opval = CPU (h_fr[tmp_f]); - SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); - } { - SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]); - SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); + SF opval = GET_H_FP (FLD (f_dest)); + SET_H_FP (FLD (f_dest), opval); + TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval); } +sh64_fstp (current_cpu, pc, GET_H_GR (FLD (f_left)), FLD (f_disp10x8), FLD (f_dest)); } #undef FLD @@ -1933,18 +1960,12 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) { vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - QI tmp_f; - tmp_f = FLD (f_dest); { - SF opval = CPU (h_fr[tmp_f]); - SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); - } - { - SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]); - SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); + SF opval = GET_H_FP (FLD (f_dest)); + SET_H_FP (FLD (f_dest), opval); + TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval); } +sh64_fstp (current_cpu, pc, GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)), FLD (f_dest)); } #undef FLD @@ -2093,7 +2114,24 @@ if (NEDI (GET_H_GR (FLD (f_left)), 0)) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + { + SF opval = GET_H_FMTX (FLD (f_left)); + SET_H_FMTX (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "fmtx", 'f', opval); + } + { + SF opval = GET_H_FV (FLD (f_right)); + SET_H_FV (FLD (f_right), opval); + TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval); + } + { + SF opval = GET_H_FV (FLD (f_dest)); + SET_H_FV (FLD (f_dest), opval); + TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval); + } sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest)); +} #undef FLD } @@ -2103,12 +2141,21 @@ sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest)); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_getcfg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + SI tmp_address; + tmp_address = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6)); ((void) 0); /*nop*/ + { + DI opval = GETMEMSI (current_cpu, pc, tmp_address); + SET_H_GR (FLD (f_dest), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); + } +} #undef FLD } @@ -2156,12 +2203,19 @@ sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest)); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_xori.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + { + DI opval = GET_H_GR (FLD (f_left)); + SET_H_GR (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); + } ((void) 0); /*nop*/ +} #undef FLD } @@ -2285,7 +2339,7 @@ sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest)); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2348,7 +2402,7 @@ if (ANDQI (tmp_bytecount, 2)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2417,7 +2471,7 @@ if (ANDQI (tmp_bytecount, 4)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -2480,7 +2534,7 @@ if (ANDQI (tmp_bytecount, 1)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -4383,12 +4437,19 @@ if (ANDQI (tmp_bytecount, 1)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_xori.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + { + DI opval = GET_H_GR (FLD (f_left)); + SET_H_GR (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); + } ((void) 0); /*nop*/ +} #undef FLD } @@ -4398,12 +4459,19 @@ if (ANDQI (tmp_bytecount, 1)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_xori.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + { + DI opval = GET_H_GR (FLD (f_left)); + SET_H_GR (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); + } ((void) 0); /*nop*/ +} #undef FLD } @@ -4413,12 +4481,19 @@ if (ANDQI (tmp_bytecount, 1)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_xori.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + { + DI opval = GET_H_GR (FLD (f_left)); + SET_H_GR (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); + } ((void) 0); /*nop*/ +} #undef FLD } @@ -4466,12 +4541,19 @@ if (ANDQI (tmp_bytecount, 1)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_xori.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + { + DI opval = GET_H_GR (FLD (f_left)); + SET_H_GR (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); + } ((void) 0); /*nop*/ +} #undef FLD } @@ -4486,11 +4568,14 @@ if (ANDQI (tmp_bytecount, 1)) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ { DI opval = ADDSI (FLD (f_disp16), 1); CPU (h_tr[FLD (f_tra)]) = opval; TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval); } +} #undef FLD } @@ -4505,11 +4590,14 @@ if (ANDQI (tmp_bytecount, 1)) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ { DI opval = GET_H_GR (FLD (f_right)); CPU (h_tr[FLD (f_tra)]) = opval; TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval); } +} #undef FLD } @@ -4524,11 +4612,14 @@ if (ANDQI (tmp_bytecount, 1)) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ { DI opval = FLD (f_disp16); CPU (h_tr[FLD (f_tra)]) = opval; TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval); } +} #undef FLD } @@ -4543,11 +4634,14 @@ if (ANDQI (tmp_bytecount, 1)) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ { DI opval = ADDDI (pc, GET_H_GR (FLD (f_right))); CPU (h_tr[FLD (f_tra)]) = opval; TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval); } +} #undef FLD } @@ -4557,12 +4651,21 @@ if (ANDQI (tmp_bytecount, 1)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_getcfg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + SI tmp_address; + tmp_address = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6)); ((void) 0); /*nop*/ + { + SI opval = GET_H_GR (FLD (f_dest)); + SETMEMSI (current_cpu, pc, tmp_address, opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } +} #undef FLD } @@ -4944,7 +5047,7 @@ if (ANDQI (tmp_bytecount, 1)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -5028,7 +5131,7 @@ if (ANDQI (tmp_bytecount, 1)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -5134,7 +5237,7 @@ if (ANDQI (tmp_bytecount, 1)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -5218,7 +5321,7 @@ if (ANDQI (tmp_bytecount, 2)) { { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); diff --git a/sim/sh64/sem-media.c b/sim/sh64/sem-media.c index aee11cc..841153a 100644 --- a/sim/sh64/sem-media.c +++ b/sim/sh64/sem-media.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -18,7 +18,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -311,13 +311,20 @@ SEM_FN_NAME (sh64_media,addzl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_media,alloco) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_xori.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + { + DI opval = GET_H_GR (FLD (f_left)); + SET_H_GR (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); + } ((void) 0); /*nop*/ +} return vpc; #undef FLD @@ -398,6 +405,8 @@ SEM_FN_NAME (sh64_media,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -406,6 +415,7 @@ if (EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -425,6 +435,8 @@ SEM_FN_NAME (sh64_media,beqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (EQDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -433,6 +445,7 @@ if (EQDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -452,6 +465,8 @@ SEM_FN_NAME (sh64_media,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (GEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -460,6 +475,7 @@ if (GEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -479,6 +495,8 @@ SEM_FN_NAME (sh64_media,bgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (GEUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -487,6 +505,7 @@ if (GEUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -506,6 +525,8 @@ SEM_FN_NAME (sh64_media,bgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -514,6 +535,7 @@ if (GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -533,6 +555,8 @@ SEM_FN_NAME (sh64_media,bgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -541,6 +565,7 @@ if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -571,6 +596,11 @@ SEM_FN_NAME (sh64_media,blink) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } +if (EQSI (FLD (f_dest), 63)) { +((void) 0); /*nop*/ +} else { +((void) 0); /*nop*/ +} } SEM_BRANCH_FINI (vpc); @@ -590,6 +620,8 @@ SEM_FN_NAME (sh64_media,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (NEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -598,6 +630,7 @@ if (NEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -617,6 +650,8 @@ SEM_FN_NAME (sh64_media,bnei) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ if (NEDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) { { UDI opval = CPU (h_tr[FLD (f_tra)]); @@ -625,6 +660,7 @@ if (NEDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); } } +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -1162,13 +1198,17 @@ SEM_FN_NAME (sh64_media,fdivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_media,fgetscr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_shori.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -((void) 0); /*nop*/ + { + SF opval = SUBWORDSISF (CPU (h_fpscr)); + CPU (h_fr[FLD (f_dest)]) = opval; + TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + } return vpc; #undef FLD @@ -1186,17 +1226,18 @@ SEM_FN_NAME (sh64_media,fiprs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - UQI tmp_g; - UQI tmp_h; - SF tmp_temp; - tmp_g = FLD (f_left); - tmp_h = FLD (f_right); - tmp_temp = sh64_fmuls (current_cpu, CPU (h_fr[tmp_g]), CPU (h_fr[tmp_h])); - tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 1)]), CPU (h_fr[ADDQI (tmp_h, 1)]))); - tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 2)]), CPU (h_fr[ADDQI (tmp_h, 2)]))); - tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 3)]), CPU (h_fr[ADDQI (tmp_h, 3)]))); { - SF opval = tmp_temp; + SF opval = GET_H_FV (FLD (f_left)); + SET_H_FV (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval); + } + { + SF opval = GET_H_FV (FLD (f_right)); + SET_H_FV (FLD (f_right), opval); + TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval); + } + { + SF opval = sh64_fiprs (current_cpu, FLD (f_left), FLD (f_right)); CPU (h_fr[FLD (f_dest)]) = opval; TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); } @@ -1239,18 +1280,12 @@ SEM_FN_NAME (sh64_media,fldp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - QI tmp_f; - tmp_f = FLD (f_dest); { - SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8))); - CPU (h_fr[tmp_f]) = opval; - TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); - } - { - SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4))); - CPU (h_fr[ADDQI (tmp_f, 1)]) = opval; - TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + SF opval = GET_H_FP (FLD (f_dest)); + SET_H_FP (FLD (f_dest), opval); + TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval); } +sh64_fldp (current_cpu, pc, GET_H_GR (FLD (f_left)), FLD (f_disp10x8), FLD (f_dest)); } return vpc; @@ -1311,18 +1346,12 @@ SEM_FN_NAME (sh64_media,fldxp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - QI tmp_f; - tmp_f = FLD (f_dest); - { - SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))); - CPU (h_fr[tmp_f]) = opval; - TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); - } { - SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4))); - CPU (h_fr[ADDQI (tmp_f, 1)]) = opval; - TRACE_RESULT (current_cpu, abuf, "fr", 'f', opval); + SF opval = GET_H_FP (FLD (f_dest)); + SET_H_FP (FLD (f_dest), opval); + TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval); } +sh64_fldp (current_cpu, pc, GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)), FLD (f_dest)); } return vpc; @@ -1670,13 +1699,17 @@ SEM_FN_NAME (sh64_media,fnegs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_media,fputscr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_fabsd.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); -((void) 0); /*nop*/ + { + SI opval = SUBWORDSFSI (CPU (h_fr[FLD (f_left_right)])); + CPU (h_fpscr) = opval; + TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval); + } return vpc; #undef FLD @@ -1757,18 +1790,12 @@ SEM_FN_NAME (sh64_media,fstp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - QI tmp_f; - tmp_f = FLD (f_dest); - { - SF opval = CPU (h_fr[tmp_f]); - SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); - } { - SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]); - SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); + SF opval = GET_H_FP (FLD (f_dest)); + SET_H_FP (FLD (f_dest), opval); + TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval); } +sh64_fstp (current_cpu, pc, GET_H_GR (FLD (f_left)), FLD (f_disp10x8), FLD (f_dest)); } return vpc; @@ -1829,18 +1856,12 @@ SEM_FN_NAME (sh64_media,fstxp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { - QI tmp_f; - tmp_f = FLD (f_dest); { - SF opval = CPU (h_fr[tmp_f]); - SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); - } - { - SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]); - SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4)), opval); - TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval); + SF opval = GET_H_FP (FLD (f_dest)); + SET_H_FP (FLD (f_dest), opval); + TRACE_RESULT (current_cpu, abuf, "fp", 'f', opval); } +sh64_fstp (current_cpu, pc, GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)), FLD (f_dest)); } return vpc; @@ -2005,7 +2026,24 @@ SEM_FN_NAME (sh64_media,ftrvs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + { + SF opval = GET_H_FMTX (FLD (f_left)); + SET_H_FMTX (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "fmtx", 'f', opval); + } + { + SF opval = GET_H_FV (FLD (f_right)); + SET_H_FV (FLD (f_right), opval); + TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval); + } + { + SF opval = GET_H_FV (FLD (f_dest)); + SET_H_FV (FLD (f_dest), opval); + TRACE_RESULT (current_cpu, abuf, "fv", 'f', opval); + } sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest)); +} return vpc; #undef FLD @@ -2016,13 +2054,22 @@ sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest)); static SEM_PC SEM_FN_NAME (sh64_media,getcfg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_getcfg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + SI tmp_address; + tmp_address = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6)); ((void) 0); /*nop*/ + { + DI opval = GETMEMSI (current_cpu, pc, tmp_address); + SET_H_GR (FLD (f_dest), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); + } +} return vpc; #undef FLD @@ -2075,13 +2122,20 @@ SEM_FN_NAME (sh64_media,gettr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_media,icbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_xori.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + { + DI opval = GET_H_GR (FLD (f_left)); + SET_H_GR (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); + } ((void) 0); /*nop*/ +} return vpc; #undef FLD @@ -2218,7 +2272,7 @@ SEM_FN_NAME (sh64_media,ldw) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_media,ldhil) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2283,7 +2337,7 @@ if (ANDQI (tmp_bytecount, 2)) { static SEM_PC SEM_FN_NAME (sh64_media,ldhiq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2354,7 +2408,7 @@ if (ANDQI (tmp_bytecount, 4)) { static SEM_PC SEM_FN_NAME (sh64_media,ldlol) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -2419,7 +2473,7 @@ if (ANDQI (tmp_bytecount, 1)) { static SEM_PC SEM_FN_NAME (sh64_media,ldloq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -4458,13 +4512,20 @@ SEM_FN_NAME (sh64_media,nsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_media,ocbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_xori.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + { + DI opval = GET_H_GR (FLD (f_left)); + SET_H_GR (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); + } ((void) 0); /*nop*/ +} return vpc; #undef FLD @@ -4475,13 +4536,20 @@ SEM_FN_NAME (sh64_media,ocbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_media,ocbp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_xori.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + { + DI opval = GET_H_GR (FLD (f_left)); + SET_H_GR (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); + } ((void) 0); /*nop*/ +} return vpc; #undef FLD @@ -4492,13 +4560,20 @@ SEM_FN_NAME (sh64_media,ocbp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_media,ocbwb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_xori.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + { + DI opval = GET_H_GR (FLD (f_left)); + SET_H_GR (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); + } ((void) 0); /*nop*/ +} return vpc; #undef FLD @@ -4551,13 +4626,20 @@ SEM_FN_NAME (sh64_media,ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_media,prefi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_xori.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + { + DI opval = GET_H_GR (FLD (f_left)); + SET_H_GR (FLD (f_left), opval); + TRACE_RESULT (current_cpu, abuf, "gr", 'D', opval); + } ((void) 0); /*nop*/ +} return vpc; #undef FLD @@ -4574,11 +4656,14 @@ SEM_FN_NAME (sh64_media,pta) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ { DI opval = ADDSI (FLD (f_disp16), 1); CPU (h_tr[FLD (f_tra)]) = opval; TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval); } +} return vpc; #undef FLD @@ -4595,11 +4680,14 @@ SEM_FN_NAME (sh64_media,ptabs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ { DI opval = GET_H_GR (FLD (f_right)); CPU (h_tr[FLD (f_tra)]) = opval; TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval); } +} return vpc; #undef FLD @@ -4616,11 +4704,14 @@ SEM_FN_NAME (sh64_media,ptb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ { DI opval = FLD (f_disp16); CPU (h_tr[FLD (f_tra)]) = opval; TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval); } +} return vpc; #undef FLD @@ -4637,11 +4728,14 @@ SEM_FN_NAME (sh64_media,ptrel) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ +((void) 0); /*nop*/ { DI opval = ADDDI (pc, GET_H_GR (FLD (f_right))); CPU (h_tr[FLD (f_tra)]) = opval; TRACE_RESULT (current_cpu, abuf, "tr", 'D', opval); } +} return vpc; #undef FLD @@ -4652,13 +4746,22 @@ SEM_FN_NAME (sh64_media,ptrel) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_media,putcfg) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.fmt_empty.f +#define FLD(f) abuf->fields.sfmt_getcfg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); +{ + SI tmp_address; + tmp_address = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6)); ((void) 0); /*nop*/ + { + SI opval = GET_H_GR (FLD (f_dest)); + SETMEMSI (current_cpu, pc, tmp_address, opval); + TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } +} return vpc; #undef FLD @@ -5081,7 +5184,7 @@ SEM_FN_NAME (sh64_media,stw) (SIM_CPU *current_cpu, SEM_ARG sem_arg) static SEM_PC SEM_FN_NAME (sh64_media,sthil) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5167,7 +5270,7 @@ if (ANDQI (tmp_bytecount, 1)) { static SEM_PC SEM_FN_NAME (sh64_media,sthiq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5275,7 +5378,7 @@ if (ANDQI (tmp_bytecount, 1)) { static SEM_PC SEM_FN_NAME (sh64_media,stlol) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; @@ -5361,7 +5464,7 @@ if (ANDQI (tmp_bytecount, 2)) { static SEM_PC SEM_FN_NAME (sh64_media,stloq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { -#define FLD(f) abuf->fields.sfmt_ldhil.f +#define FLD(f) abuf->fields.sfmt_getcfg.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; diff --git a/sim/sh64/sh-desc.c b/sim/sh64/sh-desc.c index e95ab87..456a39a 100644 --- a/sim/sh64/sh-desc.c +++ b/sim/sh64/sh-desc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -18,12 +18,11 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #include "sysdep.h" -#include <ctype.h> #include <stdio.h> #include <stdarg.h> #include "ansidecl.h" @@ -33,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "sh-opc.h" #include "opintl.h" #include "libiberty.h" +#include "xregex.h" /* Attributes. */ @@ -43,19 +43,26 @@ static const CGEN_ATTR_ENTRY bool_attr[] = { 0, 0 } }; -static const CGEN_ATTR_ENTRY MACH_attr[] = +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = { { "base", MACH_BASE }, { "sh2", MACH_SH2 }, + { "sh2e", MACH_SH2E }, + { "sh2a_fpu", MACH_SH2A_FPU }, + { "sh2a_nofpu", MACH_SH2A_NOFPU }, { "sh3", MACH_SH3 }, { "sh3e", MACH_SH3E }, + { "sh4_nofpu", MACH_SH4_NOFPU }, { "sh4", MACH_SH4 }, + { "sh4a_nofpu", MACH_SH4A_NOFPU }, + { "sh4a", MACH_SH4A }, + { "sh4al", MACH_SH4AL }, { "sh5", MACH_SH5 }, { "max", MACH_MAX }, { 0, 0 } }; -static const CGEN_ATTR_ENTRY ISA_attr[] = +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = { { "compact", ISA_COMPACT }, { "media", ISA_MEDIA }, @@ -63,6 +70,32 @@ static const CGEN_ATTR_ENTRY ISA_attr[] = { 0, 0 } }; +static const CGEN_ATTR_ENTRY SH4_GROUP_attr[] ATTRIBUTE_UNUSED = +{ + { "NONE", SH4_GROUP_NONE }, + { "MT", SH4_GROUP_MT }, + { "EX", SH4_GROUP_EX }, + { "BR", SH4_GROUP_BR }, + { "LS", SH4_GROUP_LS }, + { "FE", SH4_GROUP_FE }, + { "CO", SH4_GROUP_CO }, + { "MAX", SH4_GROUP_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY SH4A_GROUP_attr[] ATTRIBUTE_UNUSED = +{ + { "NONE", SH4A_GROUP_NONE }, + { "MT", SH4A_GROUP_MT }, + { "EX", SH4A_GROUP_EX }, + { "BR", SH4A_GROUP_BR }, + { "LS", SH4A_GROUP_LS }, + { "FE", SH4A_GROUP_FE }, + { "CO", SH4A_GROUP_CO }, + { "MAX", SH4A_GROUP_MAX }, + { 0, 0 } +}; + const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[] = { { "MACH", & MACH_attr[0], & MACH_attr[0] }, @@ -79,6 +112,7 @@ const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[] = const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[] = { { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, { "PC", &bool_attr[0], &bool_attr[0] }, @@ -105,6 +139,8 @@ const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[] = { { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "SH4-GROUP", & SH4_GROUP_attr[0], & SH4_GROUP_attr[0] }, + { "SH4A-GROUP", & SH4A_GROUP_attr[0], & SH4A_GROUP_attr[0] }, { "ALIAS", &bool_attr[0], &bool_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, @@ -112,11 +148,12 @@ const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[] = { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, - { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, { "NO-DIS", &bool_attr[0], &bool_attr[0] }, { "PBB", &bool_attr[0], &bool_attr[0] }, { "ILLSLOT", &bool_attr[0], &bool_attr[0] }, { "FP-INSN", &bool_attr[0], &bool_attr[0] }, + { "32-BIT-INSN", &bool_attr[0], &bool_attr[0] }, { 0, 0, 0 } }; @@ -124,538 +161,567 @@ const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[] = static const CGEN_ISA sh_cgen_isa_table[] = { { "media", 32, 32, 32, 32 }, - { "compact", 16, 16, 16, 16 }, + { "compact", 32, 32, 16, 32 }, { 0, 0, 0, 0, 0 } }; /* Machine variants. */ static const CGEN_MACH sh_cgen_mach_table[] = { - { "sh2", "sh2", MACH_SH2 }, - { "sh3", "sh3", MACH_SH3 }, - { "sh3e", "sh3e", MACH_SH3E }, - { "sh4", "sh4", MACH_SH4 }, - { "sh5", "sh5", MACH_SH5 }, - { 0, 0, 0 } + { "sh2", "sh2", MACH_SH2, 0 }, + { "sh2e", "sh2e", MACH_SH2E, 0 }, + { "sh2a-fpu", "sh2a-fpu", MACH_SH2A_FPU, 0 }, + { "sh2a-nofpu", "sh2a-nofpu", MACH_SH2A_NOFPU, 0 }, + { "sh3", "sh3", MACH_SH3, 0 }, + { "sh3e", "sh3e", MACH_SH3E, 0 }, + { "sh4-nofpu", "sh4-nofpu", MACH_SH4_NOFPU, 0 }, + { "sh4", "sh4", MACH_SH4, 0 }, + { "sh4a-nofpu", "sh4a-nofpu", MACH_SH4A_NOFPU, 0 }, + { "sh4a", "sh4a", MACH_SH4A, 0 }, + { "sh4al", "sh4al", MACH_SH4AL, 0 }, + { "sh5", "sh5", MACH_SH5, 0 }, + { 0, 0, 0, 0 } }; static CGEN_KEYWORD_ENTRY sh_cgen_opval_frc_names_entries[] = { - { "fr0", 0, {0, {0}}, 0, 0 }, - { "fr1", 1, {0, {0}}, 0, 0 }, - { "fr2", 2, {0, {0}}, 0, 0 }, - { "fr3", 3, {0, {0}}, 0, 0 }, - { "fr4", 4, {0, {0}}, 0, 0 }, - { "fr5", 5, {0, {0}}, 0, 0 }, - { "fr6", 6, {0, {0}}, 0, 0 }, - { "fr7", 7, {0, {0}}, 0, 0 }, - { "fr8", 8, {0, {0}}, 0, 0 }, - { "fr9", 9, {0, {0}}, 0, 0 }, - { "fr10", 10, {0, {0}}, 0, 0 }, - { "fr11", 11, {0, {0}}, 0, 0 }, - { "fr12", 12, {0, {0}}, 0, 0 }, - { "fr13", 13, {0, {0}}, 0, 0 }, - { "fr14", 14, {0, {0}}, 0, 0 }, - { "fr15", 15, {0, {0}}, 0, 0 } + { "fr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "fr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "fr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "fr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "fr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "fr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "fr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "fr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "fr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "fr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "fr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "fr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "fr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "fr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "fr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "fr15", 15, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD sh_cgen_opval_frc_names = { & sh_cgen_opval_frc_names_entries[0], 16, - 0, 0, 0, 0 + 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY sh_cgen_opval_drc_names_entries[] = { - { "dr0", 0, {0, {0}}, 0, 0 }, - { "dr2", 2, {0, {0}}, 0, 0 }, - { "dr4", 4, {0, {0}}, 0, 0 }, - { "dr6", 6, {0, {0}}, 0, 0 }, - { "dr8", 8, {0, {0}}, 0, 0 }, - { "dr10", 10, {0, {0}}, 0, 0 }, - { "dr12", 12, {0, {0}}, 0, 0 }, - { "dr14", 14, {0, {0}}, 0, 0 } + { "dr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "dr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "dr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "dr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "dr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "dr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "dr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "dr14", 14, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD sh_cgen_opval_drc_names = { & sh_cgen_opval_drc_names_entries[0], 8, - 0, 0, 0, 0 + 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY sh_cgen_opval_xf_names_entries[] = { - { "xf0", 0, {0, {0}}, 0, 0 }, - { "xf1", 1, {0, {0}}, 0, 0 }, - { "xf2", 2, {0, {0}}, 0, 0 }, - { "xf3", 3, {0, {0}}, 0, 0 }, - { "xf4", 4, {0, {0}}, 0, 0 }, - { "xf5", 5, {0, {0}}, 0, 0 }, - { "xf6", 6, {0, {0}}, 0, 0 }, - { "xf7", 7, {0, {0}}, 0, 0 }, - { "xf8", 8, {0, {0}}, 0, 0 }, - { "xf9", 9, {0, {0}}, 0, 0 }, - { "xf10", 10, {0, {0}}, 0, 0 }, - { "xf11", 11, {0, {0}}, 0, 0 }, - { "xf12", 12, {0, {0}}, 0, 0 }, - { "xf13", 13, {0, {0}}, 0, 0 }, - { "xf14", 14, {0, {0}}, 0, 0 }, - { "xf15", 15, {0, {0}}, 0, 0 } + { "xf0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "xf1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "xf2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "xf3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "xf4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "xf5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "xf6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "xf7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "xf8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "xf9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "xf10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "xf11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "xf12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "xf13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "xf14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "xf15", 15, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD sh_cgen_opval_xf_names = { & sh_cgen_opval_xf_names_entries[0], 16, - 0, 0, 0, 0 + 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_gr_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 }, - { "r1", 1, {0, {0}}, 0, 0 }, - { "r2", 2, {0, {0}}, 0, 0 }, - { "r3", 3, {0, {0}}, 0, 0 }, - { "r4", 4, {0, {0}}, 0, 0 }, - { "r5", 5, {0, {0}}, 0, 0 }, - { "r6", 6, {0, {0}}, 0, 0 }, - { "r7", 7, {0, {0}}, 0, 0 }, - { "r8", 8, {0, {0}}, 0, 0 }, - { "r9", 9, {0, {0}}, 0, 0 }, - { "r10", 10, {0, {0}}, 0, 0 }, - { "r11", 11, {0, {0}}, 0, 0 }, - { "r12", 12, {0, {0}}, 0, 0 }, - { "r13", 13, {0, {0}}, 0, 0 }, - { "r14", 14, {0, {0}}, 0, 0 }, - { "r15", 15, {0, {0}}, 0, 0 }, - { "r16", 16, {0, {0}}, 0, 0 }, - { "r17", 17, {0, {0}}, 0, 0 }, - { "r18", 18, {0, {0}}, 0, 0 }, - { "r19", 19, {0, {0}}, 0, 0 }, - { "r20", 20, {0, {0}}, 0, 0 }, - { "r21", 21, {0, {0}}, 0, 0 }, - { "r22", 22, {0, {0}}, 0, 0 }, - { "r23", 23, {0, {0}}, 0, 0 }, - { "r24", 24, {0, {0}}, 0, 0 }, - { "r25", 25, {0, {0}}, 0, 0 }, - { "r26", 26, {0, {0}}, 0, 0 }, - { "r27", 27, {0, {0}}, 0, 0 }, - { "r28", 28, {0, {0}}, 0, 0 }, - { "r29", 29, {0, {0}}, 0, 0 }, - { "r30", 30, {0, {0}}, 0, 0 }, - { "r31", 31, {0, {0}}, 0, 0 }, - { "r32", 32, {0, {0}}, 0, 0 }, - { "r33", 33, {0, {0}}, 0, 0 }, - { "r34", 34, {0, {0}}, 0, 0 }, - { "r35", 35, {0, {0}}, 0, 0 }, - { "r36", 36, {0, {0}}, 0, 0 }, - { "r37", 37, {0, {0}}, 0, 0 }, - { "r38", 38, {0, {0}}, 0, 0 }, - { "r39", 39, {0, {0}}, 0, 0 }, - { "r40", 40, {0, {0}}, 0, 0 }, - { "r41", 41, {0, {0}}, 0, 0 }, - { "r42", 42, {0, {0}}, 0, 0 }, - { "r43", 43, {0, {0}}, 0, 0 }, - { "r44", 44, {0, {0}}, 0, 0 }, - { "r45", 45, {0, {0}}, 0, 0 }, - { "r46", 46, {0, {0}}, 0, 0 }, - { "r47", 47, {0, {0}}, 0, 0 }, - { "r48", 48, {0, {0}}, 0, 0 }, - { "r49", 49, {0, {0}}, 0, 0 }, - { "r50", 50, {0, {0}}, 0, 0 }, - { "r51", 51, {0, {0}}, 0, 0 }, - { "r52", 52, {0, {0}}, 0, 0 }, - { "r53", 53, {0, {0}}, 0, 0 }, - { "r54", 54, {0, {0}}, 0, 0 }, - { "r55", 55, {0, {0}}, 0, 0 }, - { "r56", 56, {0, {0}}, 0, 0 }, - { "r57", 57, {0, {0}}, 0, 0 }, - { "r58", 58, {0, {0}}, 0, 0 }, - { "r59", 59, {0, {0}}, 0, 0 }, - { "r60", 60, {0, {0}}, 0, 0 }, - { "r61", 61, {0, {0}}, 0, 0 }, - { "r62", 62, {0, {0}}, 0, 0 }, - { "r63", 63, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "r32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "r33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "r34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "r35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "r36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "r37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "r38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "r39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "r40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "r41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "r42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "r43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "r44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "r45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "r46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "r47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "r48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "r49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "r50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "r51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "r52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "r53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "r54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "r55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "r56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "r57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "r58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "r59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "r60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "r61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "r62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "r63", 63, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD sh_cgen_opval_h_gr = { & sh_cgen_opval_h_gr_entries[0], 64, - 0, 0, 0, 0 + 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_grc_entries[] = { - { "r0", 0, {0, {0}}, 0, 0 }, - { "r1", 1, {0, {0}}, 0, 0 }, - { "r2", 2, {0, {0}}, 0, 0 }, - { "r3", 3, {0, {0}}, 0, 0 }, - { "r4", 4, {0, {0}}, 0, 0 }, - { "r5", 5, {0, {0}}, 0, 0 }, - { "r6", 6, {0, {0}}, 0, 0 }, - { "r7", 7, {0, {0}}, 0, 0 }, - { "r8", 8, {0, {0}}, 0, 0 }, - { "r9", 9, {0, {0}}, 0, 0 }, - { "r10", 10, {0, {0}}, 0, 0 }, - { "r11", 11, {0, {0}}, 0, 0 }, - { "r12", 12, {0, {0}}, 0, 0 }, - { "r13", 13, {0, {0}}, 0, 0 }, - { "r14", 14, {0, {0}}, 0, 0 }, - { "r15", 15, {0, {0}}, 0, 0 } + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD sh_cgen_opval_h_grc = { & sh_cgen_opval_h_grc_entries[0], 16, - 0, 0, 0, 0 + 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_cr_entries[] = { - { "cr0", 0, {0, {0}}, 0, 0 }, - { "cr1", 1, {0, {0}}, 0, 0 }, - { "cr2", 2, {0, {0}}, 0, 0 }, - { "cr3", 3, {0, {0}}, 0, 0 }, - { "cr4", 4, {0, {0}}, 0, 0 }, - { "cr5", 5, {0, {0}}, 0, 0 }, - { "cr6", 6, {0, {0}}, 0, 0 }, - { "cr7", 7, {0, {0}}, 0, 0 }, - { "cr8", 8, {0, {0}}, 0, 0 }, - { "cr9", 9, {0, {0}}, 0, 0 }, - { "cr10", 10, {0, {0}}, 0, 0 }, - { "cr11", 11, {0, {0}}, 0, 0 }, - { "cr12", 12, {0, {0}}, 0, 0 }, - { "cr13", 13, {0, {0}}, 0, 0 }, - { "cr14", 14, {0, {0}}, 0, 0 }, - { "cr15", 15, {0, {0}}, 0, 0 }, - { "cr16", 16, {0, {0}}, 0, 0 }, - { "cr17", 17, {0, {0}}, 0, 0 }, - { "cr18", 18, {0, {0}}, 0, 0 }, - { "cr19", 19, {0, {0}}, 0, 0 }, - { "cr20", 20, {0, {0}}, 0, 0 }, - { "cr21", 21, {0, {0}}, 0, 0 }, - { "cr22", 22, {0, {0}}, 0, 0 }, - { "cr23", 23, {0, {0}}, 0, 0 }, - { "cr24", 24, {0, {0}}, 0, 0 }, - { "cr25", 25, {0, {0}}, 0, 0 }, - { "cr26", 26, {0, {0}}, 0, 0 }, - { "cr27", 27, {0, {0}}, 0, 0 }, - { "cr28", 28, {0, {0}}, 0, 0 }, - { "cr29", 29, {0, {0}}, 0, 0 }, - { "cr30", 30, {0, {0}}, 0, 0 }, - { "cr31", 31, {0, {0}}, 0, 0 }, - { "cr32", 32, {0, {0}}, 0, 0 }, - { "cr33", 33, {0, {0}}, 0, 0 }, - { "cr34", 34, {0, {0}}, 0, 0 }, - { "cr35", 35, {0, {0}}, 0, 0 }, - { "cr36", 36, {0, {0}}, 0, 0 }, - { "cr37", 37, {0, {0}}, 0, 0 }, - { "cr38", 38, {0, {0}}, 0, 0 }, - { "cr39", 39, {0, {0}}, 0, 0 }, - { "cr40", 40, {0, {0}}, 0, 0 }, - { "cr41", 41, {0, {0}}, 0, 0 }, - { "cr42", 42, {0, {0}}, 0, 0 }, - { "cr43", 43, {0, {0}}, 0, 0 }, - { "cr44", 44, {0, {0}}, 0, 0 }, - { "cr45", 45, {0, {0}}, 0, 0 }, - { "cr46", 46, {0, {0}}, 0, 0 }, - { "cr47", 47, {0, {0}}, 0, 0 }, - { "cr48", 48, {0, {0}}, 0, 0 }, - { "cr49", 49, {0, {0}}, 0, 0 }, - { "cr50", 50, {0, {0}}, 0, 0 }, - { "cr51", 51, {0, {0}}, 0, 0 }, - { "cr52", 52, {0, {0}}, 0, 0 }, - { "cr53", 53, {0, {0}}, 0, 0 }, - { "cr54", 54, {0, {0}}, 0, 0 }, - { "cr55", 55, {0, {0}}, 0, 0 }, - { "cr56", 56, {0, {0}}, 0, 0 }, - { "cr57", 57, {0, {0}}, 0, 0 }, - { "cr58", 58, {0, {0}}, 0, 0 }, - { "cr59", 59, {0, {0}}, 0, 0 }, - { "cr60", 60, {0, {0}}, 0, 0 }, - { "cr61", 61, {0, {0}}, 0, 0 }, - { "cr62", 62, {0, {0}}, 0, 0 }, - { "cr63", 63, {0, {0}}, 0, 0 } + { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "cr16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "cr17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "cr18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "cr19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "cr20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "cr21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "cr22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "cr23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "cr24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "cr25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "cr26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "cr27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "cr28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "cr29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "cr30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "cr31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "cr32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "cr33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "cr34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "cr35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "cr36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "cr37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "cr38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "cr39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "cr40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "cr41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "cr42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "cr43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "cr44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "cr45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "cr46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "cr47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "cr48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "cr49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "cr50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "cr51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "cr52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "cr53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "cr54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "cr55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "cr56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "cr57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "cr58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "cr59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "cr60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "cr61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "cr62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "cr63", 63, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD sh_cgen_opval_h_cr = { & sh_cgen_opval_h_cr_entries[0], 64, - 0, 0, 0, 0 + 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fr_entries[] = { - { "fr0", 0, {0, {0}}, 0, 0 }, - { "fr1", 1, {0, {0}}, 0, 0 }, - { "fr2", 2, {0, {0}}, 0, 0 }, - { "fr3", 3, {0, {0}}, 0, 0 }, - { "fr4", 4, {0, {0}}, 0, 0 }, - { "fr5", 5, {0, {0}}, 0, 0 }, - { "fr6", 6, {0, {0}}, 0, 0 }, - { "fr7", 7, {0, {0}}, 0, 0 }, - { "fr8", 8, {0, {0}}, 0, 0 }, - { "fr9", 9, {0, {0}}, 0, 0 }, - { "fr10", 10, {0, {0}}, 0, 0 }, - { "fr11", 11, {0, {0}}, 0, 0 }, - { "fr12", 12, {0, {0}}, 0, 0 }, - { "fr13", 13, {0, {0}}, 0, 0 }, - { "fr14", 14, {0, {0}}, 0, 0 }, - { "fr15", 15, {0, {0}}, 0, 0 }, - { "fr16", 16, {0, {0}}, 0, 0 }, - { "fr17", 17, {0, {0}}, 0, 0 }, - { "fr18", 18, {0, {0}}, 0, 0 }, - { "fr19", 19, {0, {0}}, 0, 0 }, - { "fr20", 20, {0, {0}}, 0, 0 }, - { "fr21", 21, {0, {0}}, 0, 0 }, - { "fr22", 22, {0, {0}}, 0, 0 }, - { "fr23", 23, {0, {0}}, 0, 0 }, - { "fr24", 24, {0, {0}}, 0, 0 }, - { "fr25", 25, {0, {0}}, 0, 0 }, - { "fr26", 26, {0, {0}}, 0, 0 }, - { "fr27", 27, {0, {0}}, 0, 0 }, - { "fr28", 28, {0, {0}}, 0, 0 }, - { "fr29", 29, {0, {0}}, 0, 0 }, - { "fr30", 30, {0, {0}}, 0, 0 }, - { "fr31", 31, {0, {0}}, 0, 0 }, - { "fr32", 32, {0, {0}}, 0, 0 }, - { "fr33", 33, {0, {0}}, 0, 0 }, - { "fr34", 34, {0, {0}}, 0, 0 }, - { "fr35", 35, {0, {0}}, 0, 0 }, - { "fr36", 36, {0, {0}}, 0, 0 }, - { "fr37", 37, {0, {0}}, 0, 0 }, - { "fr38", 38, {0, {0}}, 0, 0 }, - { "fr39", 39, {0, {0}}, 0, 0 }, - { "fr40", 40, {0, {0}}, 0, 0 }, - { "fr41", 41, {0, {0}}, 0, 0 }, - { "fr42", 42, {0, {0}}, 0, 0 }, - { "fr43", 43, {0, {0}}, 0, 0 }, - { "fr44", 44, {0, {0}}, 0, 0 }, - { "fr45", 45, {0, {0}}, 0, 0 }, - { "fr46", 46, {0, {0}}, 0, 0 }, - { "fr47", 47, {0, {0}}, 0, 0 }, - { "fr48", 48, {0, {0}}, 0, 0 }, - { "fr49", 49, {0, {0}}, 0, 0 }, - { "fr50", 50, {0, {0}}, 0, 0 }, - { "fr51", 51, {0, {0}}, 0, 0 }, - { "fr52", 52, {0, {0}}, 0, 0 }, - { "fr53", 53, {0, {0}}, 0, 0 }, - { "fr54", 54, {0, {0}}, 0, 0 }, - { "fr55", 55, {0, {0}}, 0, 0 }, - { "fr56", 56, {0, {0}}, 0, 0 }, - { "fr57", 57, {0, {0}}, 0, 0 }, - { "fr58", 58, {0, {0}}, 0, 0 }, - { "fr59", 59, {0, {0}}, 0, 0 }, - { "fr60", 60, {0, {0}}, 0, 0 }, - { "fr61", 61, {0, {0}}, 0, 0 }, - { "fr62", 62, {0, {0}}, 0, 0 }, - { "fr63", 63, {0, {0}}, 0, 0 } + { "fr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "fr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "fr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "fr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "fr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "fr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "fr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "fr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "fr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "fr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "fr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "fr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "fr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "fr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "fr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "fr15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "fr16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "fr17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "fr18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "fr19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "fr20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "fr21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "fr22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "fr23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "fr24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "fr25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "fr26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "fr27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "fr28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "fr29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "fr30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "fr31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "fr32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "fr33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "fr34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "fr35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "fr36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "fr37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "fr38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "fr39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "fr40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "fr41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "fr42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "fr43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "fr44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "fr45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "fr46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "fr47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "fr48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "fr49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "fr50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "fr51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "fr52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "fr53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "fr54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "fr55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "fr56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "fr57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "fr58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "fr59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "fr60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "fr61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "fr62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "fr63", 63, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD sh_cgen_opval_h_fr = { & sh_cgen_opval_h_fr_entries[0], 64, - 0, 0, 0, 0 + 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fp_entries[] = { - { "fp0", 0, {0, {0}}, 0, 0 }, - { "fp1", 1, {0, {0}}, 0, 0 }, - { "fp2", 2, {0, {0}}, 0, 0 }, - { "fp3", 3, {0, {0}}, 0, 0 }, - { "fp4", 4, {0, {0}}, 0, 0 }, - { "fp5", 5, {0, {0}}, 0, 0 }, - { "fp6", 6, {0, {0}}, 0, 0 }, - { "fp7", 7, {0, {0}}, 0, 0 }, - { "fp8", 8, {0, {0}}, 0, 0 }, - { "fp9", 9, {0, {0}}, 0, 0 }, - { "fp10", 10, {0, {0}}, 0, 0 }, - { "fp11", 11, {0, {0}}, 0, 0 }, - { "fp12", 12, {0, {0}}, 0, 0 }, - { "fp13", 13, {0, {0}}, 0, 0 }, - { "fp14", 14, {0, {0}}, 0, 0 }, - { "fp15", 15, {0, {0}}, 0, 0 }, - { "fp16", 16, {0, {0}}, 0, 0 }, - { "fp17", 17, {0, {0}}, 0, 0 }, - { "fp18", 18, {0, {0}}, 0, 0 }, - { "fp19", 19, {0, {0}}, 0, 0 }, - { "fp20", 20, {0, {0}}, 0, 0 }, - { "fp21", 21, {0, {0}}, 0, 0 }, - { "fp22", 22, {0, {0}}, 0, 0 }, - { "fp23", 23, {0, {0}}, 0, 0 }, - { "fp24", 24, {0, {0}}, 0, 0 }, - { "fp25", 25, {0, {0}}, 0, 0 }, - { "fp26", 26, {0, {0}}, 0, 0 }, - { "fp27", 27, {0, {0}}, 0, 0 }, - { "fp28", 28, {0, {0}}, 0, 0 }, - { "fp29", 29, {0, {0}}, 0, 0 }, - { "fp30", 30, {0, {0}}, 0, 0 }, - { "fp31", 31, {0, {0}}, 0, 0 } + { "fp0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "fp2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "fp4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "fp6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "fp8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "fp10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "fp12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "fp14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "fp16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "fp18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "fp20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "fp22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "fp24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "fp26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "fp28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "fp30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "fp32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "fp34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "fp36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "fp38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "fp40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "fp42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "fp44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "fp46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "fp48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "fp50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "fp52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "fp54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "fp56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "fp58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "fp60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "fp62", 62, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD sh_cgen_opval_h_fp = { & sh_cgen_opval_h_fp_entries[0], 32, - 0, 0, 0, 0 + 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fv_entries[] = { - { "fv0", 0, {0, {0}}, 0, 0 }, - { "fv1", 1, {0, {0}}, 0, 0 }, - { "fv2", 2, {0, {0}}, 0, 0 }, - { "fv3", 3, {0, {0}}, 0, 0 }, - { "fv4", 4, {0, {0}}, 0, 0 }, - { "fv5", 5, {0, {0}}, 0, 0 }, - { "fv6", 6, {0, {0}}, 0, 0 }, - { "fv7", 7, {0, {0}}, 0, 0 }, - { "fv8", 8, {0, {0}}, 0, 0 }, - { "fv9", 9, {0, {0}}, 0, 0 }, - { "fv10", 10, {0, {0}}, 0, 0 }, - { "fv11", 11, {0, {0}}, 0, 0 }, - { "fv12", 12, {0, {0}}, 0, 0 }, - { "fv13", 13, {0, {0}}, 0, 0 }, - { "fv14", 14, {0, {0}}, 0, 0 }, - { "fv15", 15, {0, {0}}, 0, 0 } + { "fv0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "fv4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "fv8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "fv12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "fv16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "fv20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "fv24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "fv28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "fv32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "fv36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "fv40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "fv44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "fv48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "fv52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "fv56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "fv60", 60, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD sh_cgen_opval_h_fv = { & sh_cgen_opval_h_fv_entries[0], 16, - 0, 0, 0, 0 + 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fmtx_entries[] = { - { "mtrx0", 0, {0, {0}}, 0, 0 }, - { "mtrx1", 1, {0, {0}}, 0, 0 }, - { "mtrx2", 2, {0, {0}}, 0, 0 }, - { "mtrx3", 3, {0, {0}}, 0, 0 } + { "mtrx0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "mtrx16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "mtrx32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "mtrx48", 48, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD sh_cgen_opval_h_fmtx = { & sh_cgen_opval_h_fmtx_entries[0], 4, - 0, 0, 0, 0 + 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_dr_entries[] = { - { "dr0", 0, {0, {0}}, 0, 0 }, - { "dr1", 1, {0, {0}}, 0, 0 }, - { "dr2", 2, {0, {0}}, 0, 0 }, - { "dr3", 3, {0, {0}}, 0, 0 }, - { "dr4", 4, {0, {0}}, 0, 0 }, - { "dr5", 5, {0, {0}}, 0, 0 }, - { "dr6", 6, {0, {0}}, 0, 0 }, - { "dr7", 7, {0, {0}}, 0, 0 }, - { "dr8", 8, {0, {0}}, 0, 0 }, - { "dr9", 9, {0, {0}}, 0, 0 }, - { "dr10", 10, {0, {0}}, 0, 0 }, - { "dr11", 11, {0, {0}}, 0, 0 }, - { "dr12", 12, {0, {0}}, 0, 0 }, - { "dr13", 13, {0, {0}}, 0, 0 }, - { "dr14", 14, {0, {0}}, 0, 0 }, - { "dr15", 15, {0, {0}}, 0, 0 }, - { "dr16", 16, {0, {0}}, 0, 0 }, - { "dr17", 17, {0, {0}}, 0, 0 }, - { "dr18", 18, {0, {0}}, 0, 0 }, - { "dr19", 19, {0, {0}}, 0, 0 }, - { "dr20", 20, {0, {0}}, 0, 0 }, - { "dr21", 21, {0, {0}}, 0, 0 }, - { "dr22", 22, {0, {0}}, 0, 0 }, - { "dr23", 23, {0, {0}}, 0, 0 }, - { "dr24", 24, {0, {0}}, 0, 0 }, - { "dr25", 25, {0, {0}}, 0, 0 }, - { "dr26", 26, {0, {0}}, 0, 0 }, - { "dr27", 27, {0, {0}}, 0, 0 }, - { "dr28", 28, {0, {0}}, 0, 0 }, - { "dr29", 29, {0, {0}}, 0, 0 }, - { "dr30", 30, {0, {0}}, 0, 0 }, - { "dr31", 31, {0, {0}}, 0, 0 }, - { "dr32", 32, {0, {0}}, 0, 0 }, - { "dr33", 33, {0, {0}}, 0, 0 }, - { "dr34", 34, {0, {0}}, 0, 0 }, - { "dr35", 35, {0, {0}}, 0, 0 }, - { "dr36", 36, {0, {0}}, 0, 0 }, - { "dr37", 37, {0, {0}}, 0, 0 }, - { "dr38", 38, {0, {0}}, 0, 0 }, - { "dr39", 39, {0, {0}}, 0, 0 }, - { "dr40", 40, {0, {0}}, 0, 0 }, - { "dr41", 41, {0, {0}}, 0, 0 }, - { "dr42", 42, {0, {0}}, 0, 0 }, - { "dr43", 43, {0, {0}}, 0, 0 }, - { "dr44", 44, {0, {0}}, 0, 0 }, - { "dr45", 45, {0, {0}}, 0, 0 }, - { "dr46", 46, {0, {0}}, 0, 0 }, - { "dr47", 47, {0, {0}}, 0, 0 }, - { "dr48", 48, {0, {0}}, 0, 0 }, - { "dr49", 49, {0, {0}}, 0, 0 }, - { "dr50", 50, {0, {0}}, 0, 0 }, - { "dr51", 51, {0, {0}}, 0, 0 }, - { "dr52", 52, {0, {0}}, 0, 0 }, - { "dr53", 53, {0, {0}}, 0, 0 }, - { "dr54", 54, {0, {0}}, 0, 0 }, - { "dr55", 55, {0, {0}}, 0, 0 }, - { "dr56", 56, {0, {0}}, 0, 0 }, - { "dr57", 57, {0, {0}}, 0, 0 }, - { "dr58", 58, {0, {0}}, 0, 0 }, - { "dr59", 59, {0, {0}}, 0, 0 }, - { "dr60", 60, {0, {0}}, 0, 0 }, - { "dr61", 61, {0, {0}}, 0, 0 }, - { "dr62", 62, {0, {0}}, 0, 0 }, - { "dr63", 63, {0, {0}}, 0, 0 } + { "dr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "dr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "dr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "dr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "dr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "dr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "dr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "dr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "dr16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "dr18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "dr20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "dr22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "dr24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "dr26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "dr28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "dr30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "dr32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "dr34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "dr36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "dr38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "dr40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "dr42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "dr44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "dr46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "dr48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "dr50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "dr52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "dr54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "dr56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "dr58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "dr60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "dr62", 62, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD sh_cgen_opval_h_dr = { & sh_cgen_opval_h_dr_entries[0], - 64, - 0, 0, 0, 0 + 32, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fsd_entries[] = +{ + { "fr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "fr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "fr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "fr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "fr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "fr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "fr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "fr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "fr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "fr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "fr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "fr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "fr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "fr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "fr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "fr15", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD sh_cgen_opval_h_fsd = +{ + & sh_cgen_opval_h_fsd_entries[0], + 16, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fmov_entries[] = +{ + { "fr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "fr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "fr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "fr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "fr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "fr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "fr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "fr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "fr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "fr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "fr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "fr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "fr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "fr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "fr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "fr15", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD sh_cgen_opval_h_fmov = +{ + & sh_cgen_opval_h_fmov_entries[0], + 16, + 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_tr_entries[] = { - { "tr0", 0, {0, {0}}, 0, 0 }, - { "tr1", 1, {0, {0}}, 0, 0 }, - { "tr2", 2, {0, {0}}, 0, 0 }, - { "tr3", 3, {0, {0}}, 0, 0 }, - { "tr4", 4, {0, {0}}, 0, 0 }, - { "tr5", 5, {0, {0}}, 0, 0 }, - { "tr6", 6, {0, {0}}, 0, 0 }, - { "tr7", 7, {0, {0}}, 0, 0 } + { "tr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "tr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "tr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "tr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "tr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "tr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "tr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "tr7", 7, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD sh_cgen_opval_h_tr = { & sh_cgen_opval_h_tr_entries[0], 8, - 0, 0, 0, 0 + 0, 0, 0, 0, "" }; static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fvc_entries[] = { - { "fv0", 0, {0, {0}}, 0, 0 }, - { "fv4", 4, {0, {0}}, 0, 0 }, - { "fv8", 8, {0, {0}}, 0, 0 }, - { "fv12", 12, {0, {0}}, 0, 0 } + { "fv0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "fv4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "fv8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "fv12", 12, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD sh_cgen_opval_h_fvc = { & sh_cgen_opval_h_fvc_entries[0], 4, - 0, 0, 0, 0 + 0, 0, 0, 0, "" }; @@ -669,43 +735,45 @@ CGEN_KEYWORD sh_cgen_opval_h_fvc = const CGEN_HW_ENTRY sh_cgen_hw_table[] = { - { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE) } } }, - { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_gr, { 0, { (1<<MACH_BASE) } } }, - { "h-grc", HW_H_GRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_grc, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_cr, { 0, { (1<<MACH_BASE) } } }, - { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-fpscr", HW_H_FPSCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-frbit", HW_H_FRBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-szbit", HW_H_SZBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-prbit", HW_H_PRBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-mbit", HW_H_MBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-qbit", HW_H_QBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fr, { 0, { (1<<MACH_BASE) } } }, - { "h-fp", HW_H_FP, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fp, { 0, { (1<<MACH_BASE) } } }, - { "h-fv", HW_H_FV, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fv, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-fmtx", HW_H_FMTX, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fmtx, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_dr, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-tr", HW_H_TR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_tr, { 0, { (1<<MACH_BASE) } } }, - { "h-endian", HW_H_ENDIAN, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-ism", HW_H_ISM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, - { "h-frc", HW_H_FRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_frc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-drc", HW_H_DRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_drc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-xf", HW_H_XF, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_xf_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-xd", HW_H_XD, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_frc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-fvc", HW_H_FVC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fvc, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-fpccr", HW_H_FPCCR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-gbr", HW_H_GBR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-pr", HW_H_PR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-macl", HW_H_MACL, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-mach", HW_H_MACH, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, - { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_gr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-grc", HW_H_GRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_grc, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_cr, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-fpscr", HW_H_FPSCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-frbit", HW_H_FRBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-szbit", HW_H_SZBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-prbit", HW_H_PRBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { "h-mbit", HW_H_MBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { "h-qbit", HW_H_QBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-fp", HW_H_FP, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fp, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-fv", HW_H_FV, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fv, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-fmtx", HW_H_FMTX, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fmtx, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_dr, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-fsd", HW_H_FSD, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fsd, { 0|A(PROFILE), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\xc0" } } } } }, + { "h-fmov", HW_H_FMOV, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fmov, { 0|A(PROFILE), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\xc0" } } } } }, + { "h-tr", HW_H_TR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_tr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { "h-endian", HW_H_ENDIAN, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-ism", HW_H_ISM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, + { "h-frc", HW_H_FRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_frc_names, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { "h-drc", HW_H_DRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_drc_names, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { "h-xf", HW_H_XF, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_xf_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { "h-xd", HW_H_XD, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_frc_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { "h-fvc", HW_H_FVC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fvc, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { "h-gbr", HW_H_GBR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { "h-vbr", HW_H_VBR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { "h-pr", HW_H_PR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { "h-macl", HW_H_MACL, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { "h-mach", HW_H_MACH, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } } }; #undef A @@ -721,60 +789,90 @@ const CGEN_HW_ENTRY sh_cgen_hw_table[] = const CGEN_IFLD sh_cgen_ifld_table[] = { - { SH_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_OP4, "f-op4", 0, 16, 15, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_OP8, "f-op8", 0, 16, 15, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_OP16, "f-op16", 0, 16, 15, 16, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_SUB4, "f-sub4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_SUB8, "f-sub8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_SUB10, "f-sub10", 0, 16, 9, 10, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_RN, "f-rn", 0, 16, 11, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_RM, "f-rm", 0, 16, 7, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_8_1, "f-8-1", 0, 16, 8, 1, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_DISP8, "f-disp8", 0, 16, 7, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_DISP12, "f-disp12", 0, 16, 11, 12, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_IMM8, "f-imm8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_IMM4, "f-imm4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_IMM4X2, "f-imm4x2", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_IMM4X4, "f-imm4x4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_IMM8X2, "f-imm8x2", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_IMM8X4, "f-imm8x4", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_DN, "f-dn", 0, 16, 11, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_DM, "f-dm", 0, 16, 7, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_VN, "f-vn", 0, 16, 11, 2, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_VM, "f-vm", 0, 16, 9, 2, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_XN, "f-xn", 0, 16, 11, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_XM, "f-xm", 0, 16, 7, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, - { SH_F_OP, "f-op", 0, 32, 31, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_EXT, "f-ext", 0, 32, 19, 4, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_RSVD, "f-rsvd", 0, 32, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_LEFT, "f-left", 0, 32, 25, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_RIGHT, "f-right", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_DEST, "f-dest", 0, 32, 9, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_TRA, "f-tra", 0, 32, 6, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_TRB, "f-trb", 0, 32, 22, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_LIKELY, "f-likely", 0, 32, 9, 1, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_25, "f-25", 0, 32, 25, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_IMM6, "f-imm6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_IMM10, "f-imm10", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_IMM16, "f-imm16", 0, 32, 25, 16, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_UIMM6, "f-uimm6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_UIMM16, "f-uimm16", 0, 32, 25, 16, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_DISP6, "f-disp6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_DISP6X32, "f-disp6x32", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_DISP10, "f-disp10", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_DISP10X8, "f-disp10x8", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_DISP10X4, "f-disp10x4", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_DISP10X2, "f-disp10x2", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { SH_F_DISP16, "f-disp16", 0, 32, 25, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { 0, 0, 0, 0, 0, 0, {0, {0}} } + { SH_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_OP4, "f-op4", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_OP8, "f-op8", 0, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_OP16, "f-op16", 0, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_SUB4, "f-sub4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_SUB8, "f-sub8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_SUB10, "f-sub10", 0, 32, 6, 10, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_RN, "f-rn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_RM, "f-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_7_1, "f-7-1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_11_1, "f-11-1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_16_4, "f-16-4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_DISP12, "f-disp12", 0, 32, 4, 12, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_IMM4, "f-imm4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_IMM4X2, "f-imm4x2", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_IMM4X4, "f-imm4x4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_IMM8X2, "f-imm8x2", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_IMM8X4, "f-imm8x4", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_IMM12X4, "f-imm12x4", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_IMM12X8, "f-imm12x8", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_DN, "f-dn", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_DM, "f-dm", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_VN, "f-vn", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_VM, "f-vm", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_XN, "f-xn", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_XM, "f-xm", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_IMM20_HI, "f-imm20-hi", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_IMM20_LO, "f-imm20-lo", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_IMM20, "f-imm20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { SH_F_OP, "f-op", 0, 32, 0, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_EXT, "f-ext", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_RSVD, "f-rsvd", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_LEFT, "f-left", 0, 32, 6, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_RIGHT, "f-right", 0, 32, 16, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_DEST, "f-dest", 0, 32, 22, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_LEFT_RIGHT, "f-left-right", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_TRA, "f-tra", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_TRB, "f-trb", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_LIKELY, "f-likely", 0, 32, 22, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_6_3, "f-6-3", 0, 32, 6, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_23_2, "f-23-2", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_IMM6, "f-imm6", 0, 32, 16, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_IMM10, "f-imm10", 0, 32, 12, 10, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_IMM16, "f-imm16", 0, 32, 6, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_UIMM6, "f-uimm6", 0, 32, 16, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_UIMM16, "f-uimm16", 0, 32, 6, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_DISP6, "f-disp6", 0, 32, 16, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_DISP6X32, "f-disp6x32", 0, 32, 16, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_DISP10, "f-disp10", 0, 32, 12, 10, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_DISP10X8, "f-disp10x8", 0, 32, 12, 10, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_DISP10X4, "f-disp10x4", 0, 32, 12, 10, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_DISP10X2, "f-disp10x2", 0, 32, 12, 10, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { SH_F_DISP16, "f-disp16", 0, 32, 6, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, + { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } } }; #undef A + +/* multi ifield declarations */ + +const CGEN_MAYBE_MULTI_IFLD SH_F_IMM20_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD SH_F_LEFT_RIGHT_MULTI_IFIELD []; + + +/* multi ifield definitions */ + +const CGEN_MAYBE_MULTI_IFLD SH_F_IMM20_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_IMM20_HI] } }, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_IMM20_LO] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD SH_F_LEFT_RIGHT_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_LEFT] } }, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RIGHT] } }, + { 0, { (const PTR) 0 } } +}; + /* The operand table. */ #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) @@ -792,221 +890,324 @@ const CGEN_OPERAND sh_cgen_operand_table[] = { /* pc: program counter */ { "pc", SH_OPERAND_PC, HW_H_PC, 0, 0, - { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_NIL] } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* endian: Endian mode */ { "endian", SH_OPERAND_ENDIAN, HW_H_ENDIAN, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT)|(1<<ISA_MEDIA) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* ism: Instruction set mode */ { "ism", SH_OPERAND_ISM, HW_H_ISM, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT)|(1<<ISA_MEDIA) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } }, /* rm: Left general purpose register */ - { "rm", SH_OPERAND_RM, HW_H_GRC, 7, 4, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "rm", SH_OPERAND_RM, HW_H_GRC, 8, 4, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RM] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rn: Right general purpose register */ - { "rn", SH_OPERAND_RN, HW_H_GRC, 11, 4, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "rn", SH_OPERAND_RN, HW_H_GRC, 4, 4, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* r0: Register 0 */ { "r0", SH_OPERAND_R0, HW_H_GRC, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* frn: Single precision register */ - { "frn", SH_OPERAND_FRN, HW_H_FRC, 11, 4, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "frn", SH_OPERAND_FRN, HW_H_FRC, 4, 4, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* frm: Single precision register */ - { "frm", SH_OPERAND_FRM, HW_H_FRC, 7, 4, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "frm", SH_OPERAND_FRM, HW_H_FRC, 8, 4, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RM] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, +/* fr0: Single precision register 0 */ + { "fr0", SH_OPERAND_FR0, HW_H_FRC, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, +/* fmovn: Register for fmov */ + { "fmovn", SH_OPERAND_FMOVN, HW_H_FMOV, 4, 4, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RN] } }, + { 0, { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } } } } }, +/* fmovm: Register for fmov */ + { "fmovm", SH_OPERAND_FMOVM, HW_H_FMOV, 8, 4, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RM] } }, + { 0, { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } } } } }, /* fvn: Left floating point vector */ - { "fvn", SH_OPERAND_FVN, HW_H_FVC, 11, 2, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "fvn", SH_OPERAND_FVN, HW_H_FVC, 4, 2, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_VN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* fvm: Right floating point vector */ - { "fvm", SH_OPERAND_FVM, HW_H_FVC, 9, 2, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "fvm", SH_OPERAND_FVM, HW_H_FVC, 6, 2, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_VM] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* drn: Left double precision register */ - { "drn", SH_OPERAND_DRN, HW_H_DRC, 11, 3, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "drn", SH_OPERAND_DRN, HW_H_DRC, 4, 3, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* drm: Right double precision register */ - { "drm", SH_OPERAND_DRM, HW_H_DRC, 7, 3, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "drm", SH_OPERAND_DRM, HW_H_DRC, 8, 3, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DM] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* imm4: Immediate value (4 bits) */ - { "imm4", SH_OPERAND_IMM4, HW_H_SINT, 3, 4, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "imm4", SH_OPERAND_IMM4, HW_H_SINT, 12, 4, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_IMM4] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* imm8: Immediate value (8 bits) */ - { "imm8", SH_OPERAND_IMM8, HW_H_SINT, 7, 8, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "imm8", SH_OPERAND_IMM8, HW_H_SINT, 8, 8, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_IMM8] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* uimm8: Immediate value (8 bits unsigned) */ - { "uimm8", SH_OPERAND_UIMM8, HW_H_UINT, 7, 8, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "uimm8", SH_OPERAND_UIMM8, HW_H_UINT, 8, 8, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_IMM8] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, +/* imm20: Immediate value (20 bits) */ + { "imm20", SH_OPERAND_IMM20, HW_H_SINT, 8, 20, + { 2, { (const PTR) &SH_F_IMM20_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* imm4x2: Immediate value (4 bits, 2x scale) */ - { "imm4x2", SH_OPERAND_IMM4X2, HW_H_UINT, 3, 4, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "imm4x2", SH_OPERAND_IMM4X2, HW_H_UINT, 12, 4, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_IMM4X2] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* imm4x4: Immediate value (4 bits, 4x scale) */ - { "imm4x4", SH_OPERAND_IMM4X4, HW_H_UINT, 3, 4, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "imm4x4", SH_OPERAND_IMM4X4, HW_H_UINT, 12, 4, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_IMM4X4] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* imm8x2: Immediate value (8 bits, 2x scale) */ - { "imm8x2", SH_OPERAND_IMM8X2, HW_H_UINT, 7, 8, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "imm8x2", SH_OPERAND_IMM8X2, HW_H_UINT, 8, 8, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_IMM8X2] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* imm8x4: Immediate value (8 bits, 4x scale) */ - { "imm8x4", SH_OPERAND_IMM8X4, HW_H_UINT, 7, 8, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "imm8x4", SH_OPERAND_IMM8X4, HW_H_UINT, 8, 8, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_IMM8X4] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* disp8: Displacement (8 bits) */ - { "disp8", SH_OPERAND_DISP8, HW_H_IADDR, 7, 8, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "disp8", SH_OPERAND_DISP8, HW_H_IADDR, 8, 8, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DISP8] } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* disp12: Displacement (12 bits) */ - { "disp12", SH_OPERAND_DISP12, HW_H_IADDR, 11, 12, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "disp12", SH_OPERAND_DISP12, HW_H_IADDR, 4, 12, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DISP12] } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, +/* imm12x4: Displacement (12 bits) */ + { "imm12x4", SH_OPERAND_IMM12X4, HW_H_SINT, 20, 12, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_IMM12X4] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, +/* imm12x8: Displacement (12 bits) */ + { "imm12x8", SH_OPERAND_IMM12X8, HW_H_SINT, 20, 12, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_IMM12X8] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rm64: Register m (64 bits) */ - { "rm64", SH_OPERAND_RM64, HW_H_GR, 7, 4, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "rm64", SH_OPERAND_RM64, HW_H_GR, 8, 4, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RM] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* rn64: Register n (64 bits) */ - { "rn64", SH_OPERAND_RN64, HW_H_GR, 11, 4, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "rn64", SH_OPERAND_RN64, HW_H_GR, 4, 4, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* gbr: Global base register */ { "gbr", SH_OPERAND_GBR, HW_H_GBR, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, +/* vbr: Vector base register */ + { "vbr", SH_OPERAND_VBR, HW_H_VBR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* pr: Procedure link register */ { "pr", SH_OPERAND_PR, HW_H_PR, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* fpscr: Floating point status/control register */ - { "fpscr", SH_OPERAND_FPSCR, HW_H_FPCCR, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "fpscr", SH_OPERAND_FPSCR, HW_H_FPSCR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* tbit: Condition code flag */ { "tbit", SH_OPERAND_TBIT, HW_H_TBIT, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* sbit: Multiply-accumulate saturation flag */ { "sbit", SH_OPERAND_SBIT, HW_H_SBIT, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mbit: Divide-step M flag */ { "mbit", SH_OPERAND_MBIT, HW_H_MBIT, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* qbit: Divide-step Q flag */ { "qbit", SH_OPERAND_QBIT, HW_H_QBIT, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* fpul: Floating point ??? */ { "fpul", SH_OPERAND_FPUL, HW_H_FR, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* frbit: Floating point register bank bit */ { "frbit", SH_OPERAND_FRBIT, HW_H_FRBIT, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* szbit: Floating point transfer size bit */ { "szbit", SH_OPERAND_SZBIT, HW_H_SZBIT, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* prbit: Floating point precision bit */ { "prbit", SH_OPERAND_PRBIT, HW_H_PRBIT, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* macl: Multiply-accumulate low register */ { "macl", SH_OPERAND_MACL, HW_H_MACL, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* mach: Multiply-accumulate high register */ { "mach", SH_OPERAND_MACH, HW_H_MACH, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, /* fsdm: bar */ - { "fsdm", SH_OPERAND_FSDM, HW_H_FRC, 7, 4, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "fsdm", SH_OPERAND_FSDM, HW_H_FSD, 8, 4, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RM] } }, + { 0, { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } } } } }, /* fsdn: bar */ - { "fsdn", SH_OPERAND_FSDN, HW_H_FRC, 11, 4, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } }, + { "fsdn", SH_OPERAND_FSDN, HW_H_FSD, 4, 4, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RN] } }, + { 0, { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } } } } }, /* rm: Left general purpose reg */ - { "rm", SH_OPERAND_RM, HW_H_GR, 25, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "rm", SH_OPERAND_RM, HW_H_GR, 6, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_LEFT] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rn: Right general purpose reg */ - { "rn", SH_OPERAND_RN, HW_H_GR, 15, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "rn", SH_OPERAND_RN, HW_H_GR, 16, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RIGHT] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* rd: Destination general purpose reg */ - { "rd", SH_OPERAND_RD, HW_H_GR, 9, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "rd", SH_OPERAND_RD, HW_H_GR, 22, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DEST] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* frg: Left single precision register */ - { "frg", SH_OPERAND_FRG, HW_H_FR, 25, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "frg", SH_OPERAND_FRG, HW_H_FR, 6, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_LEFT] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* frh: Right single precision register */ - { "frh", SH_OPERAND_FRH, HW_H_FR, 15, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "frh", SH_OPERAND_FRH, HW_H_FR, 16, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RIGHT] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* frf: Destination single precision reg */ - { "frf", SH_OPERAND_FRF, HW_H_FR, 9, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "frf", SH_OPERAND_FRF, HW_H_FR, 22, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DEST] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* frgh: Single precision register pair */ - { "frgh", SH_OPERAND_FRGH, HW_H_FR, 15, 12, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "frgh", SH_OPERAND_FRGH, HW_H_FR, 6, 12, + { 2, { (const PTR) &SH_F_LEFT_RIGHT_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* fpf: Pair of single precision registers */ - { "fpf", SH_OPERAND_FPF, HW_H_FP, 9, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "fpf", SH_OPERAND_FPF, HW_H_FP, 22, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DEST] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* fvg: Left single precision vector */ - { "fvg", SH_OPERAND_FVG, HW_H_FV, 25, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "fvg", SH_OPERAND_FVG, HW_H_FV, 6, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_LEFT] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* fvh: Right single precision vector */ - { "fvh", SH_OPERAND_FVH, HW_H_FV, 15, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "fvh", SH_OPERAND_FVH, HW_H_FV, 16, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RIGHT] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* fvf: Destination single precision vector */ - { "fvf", SH_OPERAND_FVF, HW_H_FV, 9, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "fvf", SH_OPERAND_FVF, HW_H_FV, 22, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DEST] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* mtrxg: Left single precision matrix */ - { "mtrxg", SH_OPERAND_MTRXG, HW_H_FMTX, 25, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "mtrxg", SH_OPERAND_MTRXG, HW_H_FMTX, 6, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_LEFT] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* drg: Left double precision register */ - { "drg", SH_OPERAND_DRG, HW_H_DR, 25, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "drg", SH_OPERAND_DRG, HW_H_DR, 6, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_LEFT] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* drh: Right double precision register */ - { "drh", SH_OPERAND_DRH, HW_H_DR, 15, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "drh", SH_OPERAND_DRH, HW_H_DR, 16, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_RIGHT] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* drf: Destination double precision reg */ - { "drf", SH_OPERAND_DRF, HW_H_DR, 9, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "drf", SH_OPERAND_DRF, HW_H_DR, 22, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DEST] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* drgh: Double precision register pair */ - { "drgh", SH_OPERAND_DRGH, HW_H_DR, 15, 12, - { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "drgh", SH_OPERAND_DRGH, HW_H_DR, 6, 12, + { 2, { (const PTR) &SH_F_LEFT_RIGHT_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* fpscr: Floating point status register */ { "fpscr", SH_OPERAND_FPSCR, HW_H_FPSCR, 0, 0, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* crj: Control register j */ - { "crj", SH_OPERAND_CRJ, HW_H_CR, 9, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "crj", SH_OPERAND_CRJ, HW_H_CR, 22, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DEST] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* crk: Control register k */ - { "crk", SH_OPERAND_CRK, HW_H_CR, 25, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "crk", SH_OPERAND_CRK, HW_H_CR, 6, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_LEFT] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* tra: Target register a */ - { "tra", SH_OPERAND_TRA, HW_H_TR, 6, 3, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "tra", SH_OPERAND_TRA, HW_H_TR, 25, 3, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_TRA] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* trb: Target register b */ - { "trb", SH_OPERAND_TRB, HW_H_TR, 22, 3, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "trb", SH_OPERAND_TRB, HW_H_TR, 9, 3, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_TRB] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* disp6: Displacement (6 bits) */ - { "disp6", SH_OPERAND_DISP6, HW_H_SINT, 15, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "disp6", SH_OPERAND_DISP6, HW_H_SINT, 16, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DISP6] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* disp6x32: Displacement (6 bits, scale 32) */ - { "disp6x32", SH_OPERAND_DISP6X32, HW_H_SINT, 15, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "disp6x32", SH_OPERAND_DISP6X32, HW_H_SINT, 16, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DISP6X32] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* disp10: Displacement (10 bits) */ - { "disp10", SH_OPERAND_DISP10, HW_H_SINT, 19, 10, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "disp10", SH_OPERAND_DISP10, HW_H_SINT, 12, 10, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DISP10] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* disp10x2: Displacement (10 bits, scale 2) */ - { "disp10x2", SH_OPERAND_DISP10X2, HW_H_SINT, 19, 10, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "disp10x2", SH_OPERAND_DISP10X2, HW_H_SINT, 12, 10, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DISP10X2] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* disp10x4: Displacement (10 bits, scale 4) */ - { "disp10x4", SH_OPERAND_DISP10X4, HW_H_SINT, 19, 10, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "disp10x4", SH_OPERAND_DISP10X4, HW_H_SINT, 12, 10, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DISP10X4] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* disp10x8: Displacement (10 bits, scale 8) */ - { "disp10x8", SH_OPERAND_DISP10X8, HW_H_SINT, 19, 10, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "disp10x8", SH_OPERAND_DISP10X8, HW_H_SINT, 12, 10, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DISP10X8] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* disp16: Displacement (16 bits) */ - { "disp16", SH_OPERAND_DISP16, HW_H_SINT, 25, 16, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "disp16", SH_OPERAND_DISP16, HW_H_SINT, 6, 16, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_DISP16] } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* imm6: Immediate (6 bits) */ - { "imm6", SH_OPERAND_IMM6, HW_H_SINT, 15, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "imm6", SH_OPERAND_IMM6, HW_H_SINT, 16, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_IMM6] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* imm10: Immediate (10 bits) */ - { "imm10", SH_OPERAND_IMM10, HW_H_SINT, 19, 10, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "imm10", SH_OPERAND_IMM10, HW_H_SINT, 12, 10, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_IMM10] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* imm16: Immediate (16 bits) */ - { "imm16", SH_OPERAND_IMM16, HW_H_SINT, 25, 16, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "imm16", SH_OPERAND_IMM16, HW_H_SINT, 6, 16, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_IMM16] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* uimm6: Immediate (6 bits) */ - { "uimm6", SH_OPERAND_UIMM6, HW_H_UINT, 15, 6, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "uimm6", SH_OPERAND_UIMM6, HW_H_UINT, 16, 6, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_UIMM6] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* uimm16: Unsigned immediate (16 bits) */ - { "uimm16", SH_OPERAND_UIMM16, HW_H_UINT, 25, 16, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, + { "uimm16", SH_OPERAND_UIMM16, HW_H_UINT, 6, 16, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_UIMM16] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, /* likely: Likely branch? */ - { "likely", SH_OPERAND_LIKELY, HW_H_UINT, 9, 1, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } }, - { 0, 0, 0, 0, 0, {0, {0}} } + { "likely", SH_OPERAND_LIKELY, HW_H_UINT, 22, 1, + { 0, { (const PTR) &sh_cgen_ifld_table[SH_F_LIKELY] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } } }, +/* sentinel */ + { 0, 0, 0, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } } }; #undef A @@ -1026,1941 +1227,2016 @@ static const CGEN_IBASE sh_cgen_insn_table[MAX_INSNS] = /* Special null first entry. A `num' value of zero is thus invalid. Also, the special `invalid' insn resides here. */ - { 0, 0, 0, 0, {0, {0}} }, + { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* add $rm, $rn */ { SH_INSN_ADD_COMPACT, "add-compact", "add", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* add #$imm8, $rn */ { SH_INSN_ADDI_COMPACT, "addi-compact", "add", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* addc $rm, $rn */ { SH_INSN_ADDC_COMPACT, "addc-compact", "addc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* addv $rm, $rn */ { SH_INSN_ADDV_COMPACT, "addv-compact", "addv", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* and $rm64, $rn64 */ { SH_INSN_AND_COMPACT, "and-compact", "and", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* and #$uimm8, r0 */ { SH_INSN_ANDI_COMPACT, "andi-compact", "and", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* and.b #$imm8, @(r0, gbr) */ { SH_INSN_ANDB_COMPACT, "andb-compact", "and.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_CO, 0 } } } } }, /* bf $disp8 */ { SH_INSN_BF_COMPACT, "bf-compact", "bf", 16, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_BR, 0 } }, { { SH4A_GROUP_BR, 0 } } } } }, /* bf/s $disp8 */ { SH_INSN_BFS_COMPACT, "bfs-compact", "bf/s", 16, - { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_SH2)|(1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH2A_NOFPU)|(1<<MACH_SH3)|(1<<MACH_SH3E)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_BR, 0 } }, { { SH4A_GROUP_BR, 0 } } } } }, /* bra $disp12 */ { SH_INSN_BRA_COMPACT, "bra-compact", "bra", 16, - { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_BR, 0 } }, { { SH4A_GROUP_BR, 0 } } } } }, /* braf $rn */ { SH_INSN_BRAF_COMPACT, "braf-compact", "braf", 16, - { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_SH2)|(1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH2A_NOFPU)|(1<<MACH_SH3)|(1<<MACH_SH3E)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_BR, 0 } } } } }, /* brk */ { SH_INSN_BRK_COMPACT, "brk-compact", "brk", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* bsr $disp12 */ { SH_INSN_BSR_COMPACT, "bsr-compact", "bsr", 16, - { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_BR, 0 } }, { { SH4A_GROUP_BR, 0 } } } } }, /* bsrf $rn */ { SH_INSN_BSRF_COMPACT, "bsrf-compact", "bsrf", 16, - { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_SH2)|(1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH2A_NOFPU)|(1<<MACH_SH3)|(1<<MACH_SH3E)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_BR, 0 } } } } }, /* bt $disp8 */ { SH_INSN_BT_COMPACT, "bt-compact", "bt", 16, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_BR, 0 } }, { { SH4A_GROUP_BR, 0 } } } } }, /* bt/s $disp8 */ { SH_INSN_BTS_COMPACT, "bts-compact", "bt/s", 16, - { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_SH2)|(1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH2A_NOFPU)|(1<<MACH_SH3)|(1<<MACH_SH3E)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_BR, 0 } }, { { SH4A_GROUP_BR, 0 } } } } }, /* clrmac */ { SH_INSN_CLRMAC_COMPACT, "clrmac-compact", "clrmac", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* clrs */ { SH_INSN_CLRS_COMPACT, "clrs-compact", "clrs", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH3)|(1<<MACH_SH3E)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* clrt */ { SH_INSN_CLRT_COMPACT, "clrt-compact", "clrt", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* cmp/eq $rm, $rn */ { SH_INSN_CMPEQ_COMPACT, "cmpeq-compact", "cmp/eq", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* cmp/eq #$imm8, r0 */ { SH_INSN_CMPEQI_COMPACT, "cmpeqi-compact", "cmp/eq", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* cmp/ge $rm, $rn */ { SH_INSN_CMPGE_COMPACT, "cmpge-compact", "cmp/ge", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* cmp/gt $rm, $rn */ { SH_INSN_CMPGT_COMPACT, "cmpgt-compact", "cmp/gt", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* cmp/hi $rm, $rn */ { SH_INSN_CMPHI_COMPACT, "cmphi-compact", "cmp/hi", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* cmp/hs $rm, $rn */ { SH_INSN_CMPHS_COMPACT, "cmphs-compact", "cmp/hs", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* cmp/pl $rn */ { SH_INSN_CMPPL_COMPACT, "cmppl-compact", "cmp/pl", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* cmp/pz $rn */ { SH_INSN_CMPPZ_COMPACT, "cmppz-compact", "cmp/pz", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* cmp/str $rm, $rn */ { SH_INSN_CMPSTR_COMPACT, "cmpstr-compact", "cmp/str", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* div0s $rm, $rn */ { SH_INSN_DIV0S_COMPACT, "div0s-compact", "div0s", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* div0u */ { SH_INSN_DIV0U_COMPACT, "div0u-compact", "div0u", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* div1 $rm, $rn */ { SH_INSN_DIV1_COMPACT, "div1-compact", "div1", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } + }, +/* divu r0, $rn */ + { + SH_INSN_DIVU_COMPACT, "divu-compact", "divu", 16, + { 0, { { { (1<<MACH_SH2A_NOFPU)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH4)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } + }, +/* mulr r0, $rn */ + { + SH_INSN_MULR_COMPACT, "mulr-compact", "mulr", 16, + { 0, { { { (1<<MACH_SH2A_NOFPU)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH4)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* dmuls.l $rm, $rn */ { SH_INSN_DMULSL_COMPACT, "dmulsl-compact", "dmuls.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH2)|(1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH2A_NOFPU)|(1<<MACH_SH3)|(1<<MACH_SH3E)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* dmulu.l $rm, $rn */ { SH_INSN_DMULUL_COMPACT, "dmulul-compact", "dmulu.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH2)|(1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH2A_NOFPU)|(1<<MACH_SH3)|(1<<MACH_SH3E)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* dt $rn */ { SH_INSN_DT_COMPACT, "dt-compact", "dt", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH2)|(1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH2A_NOFPU)|(1<<MACH_SH3)|(1<<MACH_SH3E)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* exts.b $rm, $rn */ { SH_INSN_EXTSB_COMPACT, "extsb-compact", "exts.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* exts.w $rm, $rn */ { SH_INSN_EXTSW_COMPACT, "extsw-compact", "exts.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* extu.b $rm, $rn */ { SH_INSN_EXTUB_COMPACT, "extub-compact", "extu.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* extu.w $rm, $rn */ { SH_INSN_EXTUW_COMPACT, "extuw-compact", "extu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* fabs $fsdn */ { SH_INSN_FABS_COMPACT, "fabs-compact", "fabs", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* fadd $fsdm, $fsdn */ { SH_INSN_FADD_COMPACT, "fadd-compact", "fadd", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, /* fcmp/eq $fsdm, $fsdn */ { SH_INSN_FCMPEQ_COMPACT, "fcmpeq-compact", "fcmp/eq", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, /* fcmp/gt $fsdm, $fsdn */ { SH_INSN_FCMPGT_COMPACT, "fcmpgt-compact", "fcmp/gt", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, /* fcnvds $drn, fpul */ { SH_INSN_FCNVDS_COMPACT, "fcnvds-compact", "fcnvds", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2A_FPU)|(1<<MACH_SH4)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, /* fcnvsd fpul, $drn */ { SH_INSN_FCNVSD_COMPACT, "fcnvsd-compact", "fcnvsd", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2A_FPU)|(1<<MACH_SH4)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, /* fdiv $fsdm, $fsdn */ { SH_INSN_FDIV_COMPACT, "fdiv-compact", "fdiv", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, /* fipr $fvm, $fvn */ { SH_INSN_FIPR_COMPACT, "fipr-compact", "fipr", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, -/* flds $frn */ +/* flds $frn, fpul */ { SH_INSN_FLDS_COMPACT, "flds-compact", "flds", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* fldi0 $frn */ { SH_INSN_FLDI0_COMPACT, "fldi0-compact", "fldi0", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* fldi1 $frn */ { SH_INSN_FLDI1_COMPACT, "fldi1-compact", "fldi1", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* float fpul, $fsdn */ { SH_INSN_FLOAT_COMPACT, "float-compact", "float", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, /* fmac fr0, $frm, $frn */ { SH_INSN_FMAC_COMPACT, "fmac-compact", "fmac", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, -/* fmov $frm, $frn */ +/* fmov $fmovm, $fmovn */ { SH_INSN_FMOV1_COMPACT, "fmov1-compact", "fmov", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, -/* fmov @$rm, $frn */ +/* fmov @$rm, $fmovn */ { SH_INSN_FMOV2_COMPACT, "fmov2-compact", "fmov", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, -/* fmov @${rm}+, frn */ +/* fmov @${rm}+, fmovn */ { SH_INSN_FMOV3_COMPACT, "fmov3-compact", "fmov", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, -/* fmov @(r0, $rm), $frn */ +/* fmov @(r0, $rm), $fmovn */ { SH_INSN_FMOV4_COMPACT, "fmov4-compact", "fmov", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, -/* fmov $frm, @$rn */ +/* fmov $fmovm, @$rn */ { SH_INSN_FMOV5_COMPACT, "fmov5-compact", "fmov", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, -/* fmov $frm, @-$rn */ +/* fmov $fmovm, @-$rn */ { SH_INSN_FMOV6_COMPACT, "fmov6-compact", "fmov", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, -/* fmov $frm, @(r0, $rn) */ +/* fmov $fmovm, @(r0, $rn) */ { SH_INSN_FMOV7_COMPACT, "fmov7-compact", "fmov", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } + }, +/* fmov.d @($imm12x8, $rm), $drn */ + { + SH_INSN_FMOV8_COMPACT, "fmov8-compact", "fmov.d", 32, + { 0|A(32_BIT_INSN), { { { (1<<MACH_SH2A_FPU)|(1<<MACH_SH4)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } + }, +/* mov.l $drm, @($imm12x8, $rn) */ + { + SH_INSN_FMOV9_COMPACT, "fmov9-compact", "mov.l", 32, + { 0|A(32_BIT_INSN), { { { (1<<MACH_SH2A_FPU)|(1<<MACH_SH4)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fmul $fsdm, $fsdn */ { SH_INSN_FMUL_COMPACT, "fmul-compact", "fmul", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, /* fneg $fsdn */ { SH_INSN_FNEG_COMPACT, "fneg-compact", "fneg", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* frchg */ { SH_INSN_FRCHG_COMPACT, "frchg-compact", "frchg", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, /* fschg */ { SH_INSN_FSCHG_COMPACT, "fschg-compact", "fschg", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, /* fsqrt $fsdn */ { SH_INSN_FSQRT_COMPACT, "fsqrt-compact", "fsqrt", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, /* fsts fpul, $frn */ { SH_INSN_FSTS_COMPACT, "fsts-compact", "fsts", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* fsub $fsdm, $fsdn */ { SH_INSN_FSUB_COMPACT, "fsub-compact", "fsub", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, /* ftrc $fsdn, fpul */ { SH_INSN_FTRC_COMPACT, "ftrc-compact", "ftrc", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, /* ftrv xmtrx, $fvn */ { SH_INSN_FTRV_COMPACT, "ftrv-compact", "ftrv", 16, - { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(FP_INSN), { { { (1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_FE, 0 } }, { { SH4A_GROUP_FE, 0 } } } } }, /* jmp @$rn */ { SH_INSN_JMP_COMPACT, "jmp-compact", "jmp", 16, - { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_BR, 0 } } } } }, /* jsr @$rn */ { SH_INSN_JSR_COMPACT, "jsr-compact", "jsr", 16, - { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_BR, 0 } } } } }, /* ldc $rn, gbr */ { - SH_INSN_LDC_COMPACT, "ldc-compact", "ldc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + SH_INSN_LDC_GBR_COMPACT, "ldc-gbr-compact", "ldc", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } + }, +/* ldc $rn, vbr */ + { + SH_INSN_LDC_VBR_COMPACT, "ldc-vbr-compact", "ldc", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } + }, +/* ldc $rn, sr */ + { + SH_INSN_LDC_SR_COMPACT, "ldc-sr-compact", "ldc", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_CO, 0 } } } } }, /* ldc.l @${rn}+, gbr */ { - SH_INSN_LDCL_COMPACT, "ldcl-compact", "ldc.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + SH_INSN_LDCL_GBR_COMPACT, "ldcl-gbr-compact", "ldc.l", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } + }, +/* ldc.l @${rn}+, vbr */ + { + SH_INSN_LDCL_VBR_COMPACT, "ldcl-vbr-compact", "ldc.l", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* lds $rn, fpscr */ { SH_INSN_LDS_FPSCR_COMPACT, "lds-fpscr-compact", "lds", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* lds.l @${rn}+, fpscr */ { SH_INSN_LDSL_FPSCR_COMPACT, "ldsl-fpscr-compact", "lds.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* lds $rn, fpul */ { SH_INSN_LDS_FPUL_COMPACT, "lds-fpul-compact", "lds", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* lds.l @${rn}+, fpul */ { SH_INSN_LDSL_FPUL_COMPACT, "ldsl-fpul-compact", "lds.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* lds $rn, mach */ { SH_INSN_LDS_MACH_COMPACT, "lds-mach-compact", "lds", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* lds.l @${rn}+, mach */ { SH_INSN_LDSL_MACH_COMPACT, "ldsl-mach-compact", "lds.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* lds $rn, macl */ { SH_INSN_LDS_MACL_COMPACT, "lds-macl-compact", "lds", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* lds.l @${rn}+, macl */ { SH_INSN_LDSL_MACL_COMPACT, "ldsl-macl-compact", "lds.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* lds $rn, pr */ { SH_INSN_LDS_PR_COMPACT, "lds-pr-compact", "lds", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* lds.l @${rn}+, pr */ { SH_INSN_LDSL_PR_COMPACT, "ldsl-pr-compact", "lds.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mac.l @${rm}+, @${rn}+ */ { SH_INSN_MACL_COMPACT, "macl-compact", "mac.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH2)|(1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH2A_NOFPU)|(1<<MACH_SH3)|(1<<MACH_SH3E)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_CO, 0 } } } } }, /* mac.w @${rm}+, @${rn}+ */ { SH_INSN_MACW_COMPACT, "macw-compact", "mac.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_CO, 0 } } } } }, /* mov $rm64, $rn64 */ { SH_INSN_MOV_COMPACT, "mov-compact", "mov", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_MT, 0 } } } } }, /* mov #$imm8, $rn */ { SH_INSN_MOVI_COMPACT, "movi-compact", "mov", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_MT, 0 } } } } + }, +/* movi20 #$imm20, $rn */ + { + SH_INSN_MOVI20_COMPACT, "movi20-compact", "movi20", 32, + { 0|A(32_BIT_INSN), { { { (1<<MACH_SH2A_NOFPU)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH4)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mov.b $rm, @$rn */ { SH_INSN_MOVB1_COMPACT, "movb1-compact", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.b $rm, @-$rn */ { SH_INSN_MOVB2_COMPACT, "movb2-compact", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.b $rm, @(r0,$rn) */ { SH_INSN_MOVB3_COMPACT, "movb3-compact", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.b r0, @($imm8, gbr) */ { SH_INSN_MOVB4_COMPACT, "movb4-compact", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.b r0, @($imm4, $rm) */ { SH_INSN_MOVB5_COMPACT, "movb5-compact", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.b @$rm, $rn */ { SH_INSN_MOVB6_COMPACT, "movb6-compact", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.b @${rm}+, $rn */ { SH_INSN_MOVB7_COMPACT, "movb7-compact", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.b @(r0, $rm), $rn */ { SH_INSN_MOVB8_COMPACT, "movb8-compact", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.b @($imm8, gbr), r0 */ { SH_INSN_MOVB9_COMPACT, "movb9-compact", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.b @($imm4, $rm), r0 */ { SH_INSN_MOVB10_COMPACT, "movb10-compact", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.l $rm, @$rn */ { SH_INSN_MOVL1_COMPACT, "movl1-compact", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.l $rm, @-$rn */ { SH_INSN_MOVL2_COMPACT, "movl2-compact", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.l $rm, @(r0, $rn) */ { SH_INSN_MOVL3_COMPACT, "movl3-compact", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.l r0, @($imm8x4, gbr) */ { SH_INSN_MOVL4_COMPACT, "movl4-compact", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.l $rm, @($imm4x4, $rn) */ { SH_INSN_MOVL5_COMPACT, "movl5-compact", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.l @$rm, $rn */ { SH_INSN_MOVL6_COMPACT, "movl6-compact", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.l @${rm}+, $rn */ { SH_INSN_MOVL7_COMPACT, "movl7-compact", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.l @(r0, $rm), $rn */ { SH_INSN_MOVL8_COMPACT, "movl8-compact", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.l @($imm8x4, gbr), r0 */ { SH_INSN_MOVL9_COMPACT, "movl9-compact", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.l @($imm8x4, pc), $rn */ { SH_INSN_MOVL10_COMPACT, "movl10-compact", "mov.l", 16, - { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(ILLSLOT), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.l @($imm4x4, $rm), $rn */ { SH_INSN_MOVL11_COMPACT, "movl11-compact", "mov.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } + }, +/* mov.l @($imm12x4, $rm), $rn */ + { + SH_INSN_MOVL12_COMPACT, "movl12-compact", "mov.l", 32, + { 0|A(32_BIT_INSN), { { { (1<<MACH_SH2A_NOFPU)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH4)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } + }, +/* mov.l $rm, @($imm12x4, $rn) */ + { + SH_INSN_MOVL13_COMPACT, "movl13-compact", "mov.l", 32, + { 0|A(32_BIT_INSN), { { { (1<<MACH_SH2A_NOFPU)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH4)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mov.w $rm, @$rn */ { SH_INSN_MOVW1_COMPACT, "movw1-compact", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.w $rm, @-$rn */ { SH_INSN_MOVW2_COMPACT, "movw2-compact", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.w $rm, @(r0, $rn) */ { SH_INSN_MOVW3_COMPACT, "movw3-compact", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.w r0, @($imm8x2, gbr) */ { SH_INSN_MOVW4_COMPACT, "movw4-compact", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, -/* mov.w r0, @($imm4x2, $rn) */ +/* mov.w r0, @($imm4x2, $rm) */ { SH_INSN_MOVW5_COMPACT, "movw5-compact", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.w @$rm, $rn */ { SH_INSN_MOVW6_COMPACT, "movw6-compact", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.w @${rm}+, $rn */ { SH_INSN_MOVW7_COMPACT, "movw7-compact", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.w @(r0, $rm), $rn */ { SH_INSN_MOVW8_COMPACT, "movw8-compact", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.w @($imm8x2, gbr), r0 */ { SH_INSN_MOVW9_COMPACT, "movw9-compact", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.w @($imm8x2, pc), $rn */ { SH_INSN_MOVW10_COMPACT, "movw10-compact", "mov.w", 16, - { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(ILLSLOT), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mov.w @($imm4x2, $rm), r0 */ { SH_INSN_MOVW11_COMPACT, "movw11-compact", "mov.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mova @($imm8x4, pc), r0 */ { SH_INSN_MOVA_COMPACT, "mova-compact", "mova", 16, - { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(ILLSLOT), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* movca.l r0, @$rn */ { SH_INSN_MOVCAL_COMPACT, "movcal-compact", "movca.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } + }, +/* movco.l r0, @$rn */ + { + SH_INSN_MOVCOL_COMPACT, "movcol-compact", "movco.l", 16, + { 0, { { { (1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_CO, 0 } } } } }, /* movt $rn */ { SH_INSN_MOVT_COMPACT, "movt-compact", "movt", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } + }, +/* movua.l @$rn, r0 */ + { + SH_INSN_MOVUAL_COMPACT, "movual-compact", "movua.l", 16, + { 0, { { { (1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_LS, 0 } } } } + }, +/* movua.l @$rn+, r0 */ + { + SH_INSN_MOVUAL2_COMPACT, "movual2-compact", "movua.l", 16, + { 0, { { { (1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* mul.l $rm, $rn */ { SH_INSN_MULL_COMPACT, "mull-compact", "mul.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH2)|(1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH2A_NOFPU)|(1<<MACH_SH3)|(1<<MACH_SH3E)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* muls.w $rm, $rn */ { SH_INSN_MULSW_COMPACT, "mulsw-compact", "muls.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* mulu.w $rm, $rn */ { SH_INSN_MULUW_COMPACT, "muluw-compact", "mulu.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* neg $rm, $rn */ { SH_INSN_NEG_COMPACT, "neg-compact", "neg", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* negc $rm, $rn */ { SH_INSN_NEGC_COMPACT, "negc-compact", "negc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* nop */ { SH_INSN_NOP_COMPACT, "nop-compact", "nop", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_MT, 0 } } } } }, /* not $rm64, $rn64 */ { SH_INSN_NOT_COMPACT, "not-compact", "not", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* ocbi @$rn */ { SH_INSN_OCBI_COMPACT, "ocbi-compact", "ocbi", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* ocbp @$rn */ { SH_INSN_OCBP_COMPACT, "ocbp-compact", "ocbp", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* ocbwb @$rn */ { SH_INSN_OCBWB_COMPACT, "ocbwb-compact", "ocbwb", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* or $rm64, $rn64 */ { SH_INSN_OR_COMPACT, "or-compact", "or", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* or #$uimm8, r0 */ { SH_INSN_ORI_COMPACT, "ori-compact", "or", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* or.b #$imm8, @(r0, gbr) */ { SH_INSN_ORB_COMPACT, "orb-compact", "or.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_CO, 0 } } } } }, /* pref @$rn */ { SH_INSN_PREF_COMPACT, "pref-compact", "pref", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH3)|(1<<MACH_SH3E)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* rotcl $rn */ { SH_INSN_ROTCL_COMPACT, "rotcl-compact", "rotcl", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* rotcr $rn */ { SH_INSN_ROTCR_COMPACT, "rotcr-compact", "rotcr", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* rotl $rn */ { SH_INSN_ROTL_COMPACT, "rotl-compact", "rotl", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* rotr $rn */ { SH_INSN_ROTR_COMPACT, "rotr-compact", "rotr", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* rts */ { SH_INSN_RTS_COMPACT, "rts-compact", "rts", 16, - { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_BR, 0 } } } } }, /* sets */ { SH_INSN_SETS_COMPACT, "sets-compact", "sets", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH3)|(1<<MACH_SH3E)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* sett */ { SH_INSN_SETT_COMPACT, "sett-compact", "sett", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* shad $rm, $rn */ { SH_INSN_SHAD_COMPACT, "shad-compact", "shad", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH2A_NOFPU)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3)|(1<<MACH_SH3E)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* shal $rn */ { SH_INSN_SHAL_COMPACT, "shal-compact", "shal", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* shar $rn */ { SH_INSN_SHAR_COMPACT, "shar-compact", "shar", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* shld $rm, $rn */ { SH_INSN_SHLD_COMPACT, "shld-compact", "shld", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH3)|(1<<MACH_SH3E)|(1<<MACH_SH4_NOFPU)|(1<<MACH_SH4)|(1<<MACH_SH4A_NOFPU)|(1<<MACH_SH4A)|(1<<MACH_SH4AL)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* shll $rn */ { SH_INSN_SHLL_COMPACT, "shll-compact", "shll", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* shll2 $rn */ { SH_INSN_SHLL2_COMPACT, "shll2-compact", "shll2", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* shll8 $rn */ { SH_INSN_SHLL8_COMPACT, "shll8-compact", "shll8", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* shll16 $rn */ { SH_INSN_SHLL16_COMPACT, "shll16-compact", "shll16", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* shlr $rn */ { SH_INSN_SHLR_COMPACT, "shlr-compact", "shlr", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* shlr2 $rn */ { SH_INSN_SHLR2_COMPACT, "shlr2-compact", "shlr2", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* shlr8 $rn */ { SH_INSN_SHLR8_COMPACT, "shlr8-compact", "shlr8", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* shlr16 $rn */ { SH_INSN_SHLR16_COMPACT, "shlr16-compact", "shlr16", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* stc gbr, $rn */ { SH_INSN_STC_GBR_COMPACT, "stc-gbr-compact", "stc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } + }, +/* stc vbr, $rn */ + { + SH_INSN_STC_VBR_COMPACT, "stc-vbr-compact", "stc", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* stc.l gbr, @-$rn */ { SH_INSN_STCL_GBR_COMPACT, "stcl-gbr-compact", "stc.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } + }, +/* stc.l vbr, @-$rn */ + { + SH_INSN_STCL_VBR_COMPACT, "stcl-vbr-compact", "stc.l", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* sts fpscr, $rn */ { SH_INSN_STS_FPSCR_COMPACT, "sts-fpscr-compact", "sts", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* sts.l fpscr, @-$rn */ { SH_INSN_STSL_FPSCR_COMPACT, "stsl-fpscr-compact", "sts.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* sts fpul, $rn */ { SH_INSN_STS_FPUL_COMPACT, "sts-fpul-compact", "sts", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_LS, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* sts.l fpul, @-$rn */ { SH_INSN_STSL_FPUL_COMPACT, "stsl-fpul-compact", "sts.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_SH2E)|(1<<MACH_SH2A_FPU)|(1<<MACH_SH3E)|(1<<MACH_SH4)|(1<<MACH_SH4A)|(1<<MACH_SH5), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* sts mach, $rn */ { SH_INSN_STS_MACH_COMPACT, "sts-mach-compact", "sts", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* sts.l mach, @-$rn */ { SH_INSN_STSL_MACH_COMPACT, "stsl-mach-compact", "sts.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* sts macl, $rn */ { SH_INSN_STS_MACL_COMPACT, "sts-macl-compact", "sts", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* sts.l macl, @-$rn */ { SH_INSN_STSL_MACL_COMPACT, "stsl-macl-compact", "sts.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* sts pr, $rn */ { SH_INSN_STS_PR_COMPACT, "sts-pr-compact", "sts", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* sts.l pr, @-$rn */ { SH_INSN_STSL_PR_COMPACT, "stsl-pr-compact", "sts.l", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_LS, 0 } } } } }, /* sub $rm, $rn */ { SH_INSN_SUB_COMPACT, "sub-compact", "sub", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* subc $rm, $rn */ { SH_INSN_SUBC_COMPACT, "subc-compact", "subc", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* subv $rm, $rn */ { SH_INSN_SUBV_COMPACT, "subv-compact", "subv", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* swap.b $rm, $rn */ { SH_INSN_SWAPB_COMPACT, "swapb-compact", "swap.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* swap.w $rm, $rn */ { SH_INSN_SWAPW_COMPACT, "swapw-compact", "swap.w", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* tas.b @$rn */ { SH_INSN_TASB_COMPACT, "tasb-compact", "tas.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_CO, 0 } } } } }, /* trapa #$uimm8 */ { SH_INSN_TRAPA_COMPACT, "trapa-compact", "trapa", 16, - { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0|A(ILLSLOT), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_CO, 0 } } } } }, /* tst $rm, $rn */ { SH_INSN_TST_COMPACT, "tst-compact", "tst", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* tst #$uimm8, r0 */ { SH_INSN_TSTI_COMPACT, "tsti-compact", "tst", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_MT, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* tst.b #$imm8, @(r0, gbr) */ { SH_INSN_TSTB_COMPACT, "tstb-compact", "tst.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_CO, 0 } } } } }, /* xor $rm64, $rn64 */ { SH_INSN_XOR_COMPACT, "xor-compact", "xor", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* xor #$uimm8, r0 */ { SH_INSN_XORI_COMPACT, "xori-compact", "xor", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* xor.b #$imm8, @(r0, gbr) */ { SH_INSN_XORB_COMPACT, "xorb-compact", "xor.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_CO, 0 } }, { { SH4A_GROUP_CO, 0 } } } } }, /* xtrct $rm, $rn */ { SH_INSN_XTRCT_COMPACT, "xtrct-compact", "xtrct", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { SH4_GROUP_EX, 0 } }, { { SH4A_GROUP_EX, 0 } } } } }, /* add $rm, $rn, $rd */ { SH_INSN_ADD, "add", "add", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* add.l $rm, $rn, $rd */ { SH_INSN_ADDL, "addl", "add.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* addi $rm, $disp10, $rd */ { SH_INSN_ADDI, "addi", "addi", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* addi.l $rm, $disp10, $rd */ { SH_INSN_ADDIL, "addil", "addi.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* addz.l $rm, $rn, $rd */ { SH_INSN_ADDZL, "addzl", "addz.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* alloco $rm, $disp6x32 */ { SH_INSN_ALLOCO, "alloco", "alloco", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* and $rm, $rn, $rd */ { SH_INSN_AND, "and", "and", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* andc $rm, $rn, $rd */ { SH_INSN_ANDC, "andc", "andc", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* andi $rm, $disp10, $rd */ { SH_INSN_ANDI, "andi", "andi", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* beq$likely $rm, $rn, $tra */ { SH_INSN_BEQ, "beq", "beq", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* beqi$likely $rm, $imm6, $tra */ { SH_INSN_BEQI, "beqi", "beqi", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* bge$likely $rm, $rn, $tra */ { SH_INSN_BGE, "bge", "bge", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* bgeu$likely $rm, $rn, $tra */ { SH_INSN_BGEU, "bgeu", "bgeu", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* bgt$likely $rm, $rn, $tra */ { SH_INSN_BGT, "bgt", "bgt", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* bgtu$likely $rm, $rn, $tra */ { SH_INSN_BGTU, "bgtu", "bgtu", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* blink $trb, $rd */ { SH_INSN_BLINK, "blink", "blink", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* bne$likely $rm, $rn, $tra */ { SH_INSN_BNE, "bne", "bne", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* bnei$likely $rm, $imm6, $tra */ { SH_INSN_BNEI, "bnei", "bnei", 32, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* brk */ { SH_INSN_BRK, "brk", "brk", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* byterev $rm, $rd */ { SH_INSN_BYTEREV, "byterev", "byterev", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* cmpeq $rm, $rn, $rd */ { SH_INSN_CMPEQ, "cmpeq", "cmpeq", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* cmpgt $rm, $rn, $rd */ { SH_INSN_CMPGT, "cmpgt", "cmpgt", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* cmpgtu $rm,$rn, $rd */ { SH_INSN_CMPGTU, "cmpgtu", "cmpgtu", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* cmveq $rm, $rn, $rd */ { SH_INSN_CMVEQ, "cmveq", "cmveq", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* cmvne $rm, $rn, $rd */ { SH_INSN_CMVNE, "cmvne", "cmvne", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fabs.d $drgh, $drf */ { SH_INSN_FABSD, "fabsd", "fabs.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fabs.s $frgh, $frf */ { SH_INSN_FABSS, "fabss", "fabs.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fadd.d $drg, $drh, $drf */ { SH_INSN_FADDD, "faddd", "fadd.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fadd.s $frg, $frh, $frf */ { SH_INSN_FADDS, "fadds", "fadd.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fcmpeq.d $drg, $drh, $rd */ { SH_INSN_FCMPEQD, "fcmpeqd", "fcmpeq.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fcmpeq.s $frg, $frh, $rd */ { SH_INSN_FCMPEQS, "fcmpeqs", "fcmpeq.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fcmpge.d $drg, $drh, $rd */ { SH_INSN_FCMPGED, "fcmpged", "fcmpge.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fcmpge.s $frg, $frh, $rd */ { SH_INSN_FCMPGES, "fcmpges", "fcmpge.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fcmpgt.d $drg, $drh, $rd */ { SH_INSN_FCMPGTD, "fcmpgtd", "fcmpgt.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fcmpgt.s $frg, $frh, $rd */ { SH_INSN_FCMPGTS, "fcmpgts", "fcmpgt.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fcmpun.d $drg, $drh, $rd */ { SH_INSN_FCMPUND, "fcmpund", "fcmpun.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fcmpun.s $frg, $frh, $rd */ { SH_INSN_FCMPUNS, "fcmpuns", "fcmpun.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fcnv.ds $drgh, $frf */ { SH_INSN_FCNVDS, "fcnvds", "fcnv.ds", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fcnv.sd $frgh, $drf */ { SH_INSN_FCNVSD, "fcnvsd", "fcnv.sd", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fdiv.d $drg, $drh, $drf */ { SH_INSN_FDIVD, "fdivd", "fdiv.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fdiv.s $frg, $frh, $frf */ { SH_INSN_FDIVS, "fdivs", "fdiv.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fgetscr $frf */ { SH_INSN_FGETSCR, "fgetscr", "fgetscr", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fipr.s $fvg, $fvh, $frf */ { SH_INSN_FIPRS, "fiprs", "fipr.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fld.d $rm, $disp10x8, $drf */ { SH_INSN_FLDD, "fldd", "fld.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fld.p $rm, $disp10x8, $fpf */ { SH_INSN_FLDP, "fldp", "fld.p", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fld.s $rm, $disp10x4, $frf */ { SH_INSN_FLDS, "flds", "fld.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fldx.d $rm, $rn, $drf */ { SH_INSN_FLDXD, "fldxd", "fldx.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fldx.p $rm, $rn, $fpf */ { SH_INSN_FLDXP, "fldxp", "fldx.p", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fldx.s $rm, $rn, $frf */ { SH_INSN_FLDXS, "fldxs", "fldx.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* float.ld $frgh, $drf */ { SH_INSN_FLOATLD, "floatld", "float.ld", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* float.ls $frgh, $frf */ { SH_INSN_FLOATLS, "floatls", "float.ls", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* float.qd $drgh, $drf */ { SH_INSN_FLOATQD, "floatqd", "float.qd", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* float.qs $drgh, $frf */ { SH_INSN_FLOATQS, "floatqs", "float.qs", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fmac.s $frg, $frh, $frf */ { SH_INSN_FMACS, "fmacs", "fmac.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fmov.d $drgh, $drf */ { SH_INSN_FMOVD, "fmovd", "fmov.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fmov.dq $drgh, $rd */ { SH_INSN_FMOVDQ, "fmovdq", "fmov.dq", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fmov.ls $rm, $frf */ { SH_INSN_FMOVLS, "fmovls", "fmov.ls", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fmov.qd $rm, $drf */ { SH_INSN_FMOVQD, "fmovqd", "fmov.qd", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fmov.s $frgh, $frf */ { SH_INSN_FMOVS, "fmovs", "fmov.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fmov.sl $frgh, $rd */ { SH_INSN_FMOVSL, "fmovsl", "fmov.sl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fmul.d $drg, $drh, $drf */ { SH_INSN_FMULD, "fmuld", "fmul.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fmul.s $frg, $frh, $frf */ { SH_INSN_FMULS, "fmuls", "fmul.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fneg.d $drgh, $drf */ { SH_INSN_FNEGD, "fnegd", "fneg.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fneg.s $frgh, $frf */ { SH_INSN_FNEGS, "fnegs", "fneg.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fputscr $frgh */ { SH_INSN_FPUTSCR, "fputscr", "fputscr", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fsqrt.d $drgh, $drf */ { SH_INSN_FSQRTD, "fsqrtd", "fsqrt.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fsqrt.s $frgh, $frf */ { SH_INSN_FSQRTS, "fsqrts", "fsqrt.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fst.d $rm, $disp10x8, $drf */ { SH_INSN_FSTD, "fstd", "fst.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fst.p $rm, $disp10x8, $fpf */ { SH_INSN_FSTP, "fstp", "fst.p", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fst.s $rm, $disp10x4, $frf */ { SH_INSN_FSTS, "fsts", "fst.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fstx.d $rm, $rn, $drf */ { SH_INSN_FSTXD, "fstxd", "fstx.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fstx.p $rm, $rn, $fpf */ { SH_INSN_FSTXP, "fstxp", "fstx.p", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fstx.s $rm, $rn, $frf */ { SH_INSN_FSTXS, "fstxs", "fstx.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fsub.d $drg, $drh, $drf */ { SH_INSN_FSUBD, "fsubd", "fsub.d", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* fsub.s $frg, $frh, $frf */ { SH_INSN_FSUBS, "fsubs", "fsub.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ftrc.dl $drgh, $frf */ { SH_INSN_FTRCDL, "ftrcdl", "ftrc.dl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ftrc.sl $frgh, $frf */ { SH_INSN_FTRCSL, "ftrcsl", "ftrc.sl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ftrc.dq $drgh, $drf */ { SH_INSN_FTRCDQ, "ftrcdq", "ftrc.dq", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ftrc.sq $frgh, $drf */ { SH_INSN_FTRCSQ, "ftrcsq", "ftrc.sq", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ftrv.s $mtrxg, $fvh, $fvf */ { SH_INSN_FTRVS, "ftrvs", "ftrv.s", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* getcfg $rm, $disp6, $rd */ { SH_INSN_GETCFG, "getcfg", "getcfg", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* getcon $crk, $rd */ { SH_INSN_GETCON, "getcon", "getcon", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* gettr $trb, $rd */ { SH_INSN_GETTR, "gettr", "gettr", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* icbi $rm, $disp6x32 */ { SH_INSN_ICBI, "icbi", "icbi", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ld.b $rm, $disp10, $rd */ { SH_INSN_LDB, "ldb", "ld.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ld.l $rm, $disp10x4, $rd */ { SH_INSN_LDL, "ldl", "ld.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ld.q $rm, $disp10x8, $rd */ { SH_INSN_LDQ, "ldq", "ld.q", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ld.ub $rm, $disp10, $rd */ { SH_INSN_LDUB, "ldub", "ld.ub", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ld.uw $rm, $disp10x2, $rd */ { SH_INSN_LDUW, "lduw", "ld.uw", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ld.w $rm, $disp10x2, $rd */ { SH_INSN_LDW, "ldw", "ld.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ldhi.l $rm, $disp6, $rd */ { SH_INSN_LDHIL, "ldhil", "ldhi.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ldhi.q $rm, $disp6, $rd */ { SH_INSN_LDHIQ, "ldhiq", "ldhi.q", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ldlo.l $rm, $disp6, $rd */ { SH_INSN_LDLOL, "ldlol", "ldlo.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ldlo.q $rm, $disp6, $rd */ { SH_INSN_LDLOQ, "ldloq", "ldlo.q", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ldx.b $rm, $rn, $rd */ { SH_INSN_LDXB, "ldxb", "ldx.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ldx.l $rm, $rn, $rd */ { SH_INSN_LDXL, "ldxl", "ldx.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ldx.q $rm, $rn, $rd */ { SH_INSN_LDXQ, "ldxq", "ldx.q", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ldx.ub $rm, $rn, $rd */ { SH_INSN_LDXUB, "ldxub", "ldx.ub", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ldx.uw $rm, $rn, $rd */ { SH_INSN_LDXUW, "ldxuw", "ldx.uw", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ldx.w $rm, $rn, $rd */ { SH_INSN_LDXW, "ldxw", "ldx.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mabs.l $rm, $rd */ { SH_INSN_MABSL, "mabsl", "mabs.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mabs.w $rm, $rd */ { SH_INSN_MABSW, "mabsw", "mabs.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* madd.l $rm, $rn, $rd */ { SH_INSN_MADDL, "maddl", "madd.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* madd.w $rm, $rn, $rd */ { SH_INSN_MADDW, "maddw", "madd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* madds.l $rm, $rn, $rd */ { SH_INSN_MADDSL, "maddsl", "madds.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* madds.ub $rm, $rn, $rd */ { SH_INSN_MADDSUB, "maddsub", "madds.ub", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* madds.w $rm, $rn, $rd */ { SH_INSN_MADDSW, "maddsw", "madds.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mcmpeq.b $rm, $rn, $rd */ { SH_INSN_MCMPEQB, "mcmpeqb", "mcmpeq.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mcmpeq.l $rm, $rn, $rd */ { SH_INSN_MCMPEQL, "mcmpeql", "mcmpeq.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mcmpeq.w $rm, $rn, $rd */ { SH_INSN_MCMPEQW, "mcmpeqw", "mcmpeq.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mcmpgt.l $rm, $rn, $rd */ { SH_INSN_MCMPGTL, "mcmpgtl", "mcmpgt.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mcmpgt.ub $rm, $rn, $rd */ { SH_INSN_MCMPGTUB, "mcmpgtub", "mcmpgt.ub", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mcmpgt.w $rm, $rn, $rd */ { SH_INSN_MCMPGTW, "mcmpgtw", "mcmpgt.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mcmv $rm, $rn, $rd */ { SH_INSN_MCMV, "mcmv", "mcmv", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mcnvs.lw $rm, $rn, $rd */ { SH_INSN_MCNVSLW, "mcnvslw", "mcnvs.lw", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mcnvs.wb $rm, $rn, $rd */ { SH_INSN_MCNVSWB, "mcnvswb", "mcnvs.wb", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mcnvs.wub $rm, $rn, $rd */ { SH_INSN_MCNVSWUB, "mcnvswub", "mcnvs.wub", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mextr1 $rm, $rn, $rd */ { SH_INSN_MEXTR1, "mextr1", "mextr1", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mextr2 $rm, $rn, $rd */ { SH_INSN_MEXTR2, "mextr2", "mextr2", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mextr3 $rm, $rn, $rd */ { SH_INSN_MEXTR3, "mextr3", "mextr3", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mextr4 $rm, $rn, $rd */ { SH_INSN_MEXTR4, "mextr4", "mextr4", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mextr5 $rm, $rn, $rd */ { SH_INSN_MEXTR5, "mextr5", "mextr5", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mextr6 $rm, $rn, $rd */ { SH_INSN_MEXTR6, "mextr6", "mextr6", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mextr7 $rm, $rn, $rd */ { SH_INSN_MEXTR7, "mextr7", "mextr7", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mmacfx.wl $rm, $rn, $rd */ { SH_INSN_MMACFXWL, "mmacfxwl", "mmacfx.wl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mmacnfx.wl $rm, $rn, $rd */ { SH_INSN_MMACNFX_WL, "mmacnfx.wl", "mmacnfx.wl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mmul.l $rm, $rn, $rd */ { SH_INSN_MMULL, "mmull", "mmul.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mmul.w $rm, $rn, $rd */ { SH_INSN_MMULW, "mmulw", "mmul.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mmulfx.l $rm, $rn, $rd */ { SH_INSN_MMULFXL, "mmulfxl", "mmulfx.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mmulfx.w $rm, $rn, $rd */ { SH_INSN_MMULFXW, "mmulfxw", "mmulfx.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mmulfxrp.w $rm, $rn, $rd */ { SH_INSN_MMULFXRPW, "mmulfxrpw", "mmulfxrp.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mmulhi.wl $rm, $rn, $rd */ { SH_INSN_MMULHIWL, "mmulhiwl", "mmulhi.wl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mmullo.wl $rm, $rn, $rd */ { SH_INSN_MMULLOWL, "mmullowl", "mmullo.wl", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mmulsum.wq $rm, $rn, $rd */ { SH_INSN_MMULSUMWQ, "mmulsumwq", "mmulsum.wq", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* movi $imm16, $rd */ { SH_INSN_MOVI, "movi", "movi", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mperm.w $rm, $rn, $rd */ { SH_INSN_MPERMW, "mpermw", "mperm.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* msad.ubq $rm, $rn, $rd */ { SH_INSN_MSADUBQ, "msadubq", "msad.ubq", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshalds.l $rm, $rn, $rd */ { SH_INSN_MSHALDSL, "mshaldsl", "mshalds.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshalds.w $rm, $rn, $rd */ { SH_INSN_MSHALDSW, "mshaldsw", "mshalds.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshard.l $rm, $rn, $rd */ { SH_INSN_MSHARDL, "mshardl", "mshard.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshard.w $rm, $rn, $rd */ { SH_INSN_MSHARDW, "mshardw", "mshard.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshards.q $rm, $rn, $rd */ { SH_INSN_MSHARDSQ, "mshardsq", "mshards.q", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshfhi.b $rm, $rn, $rd */ { SH_INSN_MSHFHIB, "mshfhib", "mshfhi.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshfhi.l $rm, $rn, $rd */ { SH_INSN_MSHFHIL, "mshfhil", "mshfhi.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshfhi.w $rm, $rn, $rd */ { SH_INSN_MSHFHIW, "mshfhiw", "mshfhi.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshflo.b $rm, $rn, $rd */ { SH_INSN_MSHFLOB, "mshflob", "mshflo.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshflo.l $rm, $rn, $rd */ { SH_INSN_MSHFLOL, "mshflol", "mshflo.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshflo.w $rm, $rn, $rd */ { SH_INSN_MSHFLOW, "mshflow", "mshflo.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshlld.l $rm, $rn, $rd */ { SH_INSN_MSHLLDL, "mshlldl", "mshlld.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshlld.w $rm, $rn, $rd */ { SH_INSN_MSHLLDW, "mshlldw", "mshlld.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshlrd.l $rm, $rn, $rd */ { SH_INSN_MSHLRDL, "mshlrdl", "mshlrd.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mshlrd.w $rm, $rn, $rd */ { SH_INSN_MSHLRDW, "mshlrdw", "mshlrd.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* msub.l $rm, $rn, $rd */ { SH_INSN_MSUBL, "msubl", "msub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* msub.w $rm, $rn, $rd */ { SH_INSN_MSUBW, "msubw", "msub.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* msubs.l $rm, $rn, $rd */ { SH_INSN_MSUBSL, "msubsl", "msubs.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* msubs.ub $rm, $rn, $rd */ { SH_INSN_MSUBSUB, "msubsub", "msubs.ub", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* msubs.w $rm, $rn, $rd */ { SH_INSN_MSUBSW, "msubsw", "msubs.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* muls.l $rm, $rn, $rd */ { SH_INSN_MULSL, "mulsl", "muls.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* mulu.l $rm, $rn, $rd */ { SH_INSN_MULUL, "mulul", "mulu.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* nop */ { SH_INSN_NOP, "nop", "nop", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* nsb $rm, $rd */ { SH_INSN_NSB, "nsb", "nsb", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ocbi $rm, $disp6x32 */ { SH_INSN_OCBI, "ocbi", "ocbi", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ocbp $rm, $disp6x32 */ { SH_INSN_OCBP, "ocbp", "ocbp", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ocbwb $rm, $disp6x32 */ { SH_INSN_OCBWB, "ocbwb", "ocbwb", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* or $rm, $rn, $rd */ { SH_INSN_OR, "or", "or", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ori $rm, $imm10, $rd */ { SH_INSN_ORI, "ori", "ori", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* prefi $rm, $disp6x32 */ { SH_INSN_PREFI, "prefi", "prefi", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* pta$likely $disp16, $tra */ { SH_INSN_PTA, "pta", "pta", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ptabs$likely $rn, $tra */ { SH_INSN_PTABS, "ptabs", "ptabs", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ptb$likely $disp16, $tra */ { SH_INSN_PTB, "ptb", "ptb", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* ptrel$likely $rn, $tra */ { SH_INSN_PTREL, "ptrel", "ptrel", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* putcfg $rm, $disp6, $rd */ { SH_INSN_PUTCFG, "putcfg", "putcfg", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* putcon $rm, $crj */ { SH_INSN_PUTCON, "putcon", "putcon", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* rte */ { SH_INSN_RTE, "rte", "rte", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* shard $rm, $rn, $rd */ { SH_INSN_SHARD, "shard", "shard", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* shard.l $rm, $rn, $rd */ { SH_INSN_SHARDL, "shardl", "shard.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* shari $rm, $uimm6, $rd */ { SH_INSN_SHARI, "shari", "shari", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* shari.l $rm, $uimm6, $rd */ { SH_INSN_SHARIL, "sharil", "shari.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* shlld $rm, $rn, $rd */ { SH_INSN_SHLLD, "shlld", "shlld", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* shlld.l $rm, $rn, $rd */ { SH_INSN_SHLLDL, "shlldl", "shlld.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* shlli $rm, $uimm6, $rd */ { SH_INSN_SHLLI, "shlli", "shlli", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* shlli.l $rm, $uimm6, $rd */ { SH_INSN_SHLLIL, "shllil", "shlli.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* shlrd $rm, $rn, $rd */ { SH_INSN_SHLRD, "shlrd", "shlrd", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* shlrd.l $rm, $rn, $rd */ { SH_INSN_SHLRDL, "shlrdl", "shlrd.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* shlri $rm, $uimm6, $rd */ { SH_INSN_SHLRI, "shlri", "shlri", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* shlri.l $rm, $uimm6, $rd */ { SH_INSN_SHLRIL, "shlril", "shlri.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* shori $uimm16, $rd */ { SH_INSN_SHORI, "shori", "shori", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* sleep */ { SH_INSN_SLEEP, "sleep", "sleep", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* st.b $rm, $disp10, $rd */ { SH_INSN_STB, "stb", "st.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* st.l $rm, $disp10x4, $rd */ { SH_INSN_STL, "stl", "st.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* st.q $rm, $disp10x8, $rd */ { SH_INSN_STQ, "stq", "st.q", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* st.w $rm, $disp10x2, $rd */ { SH_INSN_STW, "stw", "st.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* sthi.l $rm, $disp6, $rd */ { SH_INSN_STHIL, "sthil", "sthi.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* sthi.q $rm, $disp6, $rd */ { SH_INSN_STHIQ, "sthiq", "sthi.q", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* stlo.l $rm, $disp6, $rd */ { SH_INSN_STLOL, "stlol", "stlo.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* stlo.q $rm, $disp6, $rd */ { SH_INSN_STLOQ, "stloq", "stlo.q", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* stx.b $rm, $rn, $rd */ { SH_INSN_STXB, "stxb", "stx.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* stx.l $rm, $rn, $rd */ { SH_INSN_STXL, "stxl", "stx.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* stx.q $rm, $rn, $rd */ { SH_INSN_STXQ, "stxq", "stx.q", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* stx.w $rm, $rn, $rd */ { SH_INSN_STXW, "stxw", "stx.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* sub $rm, $rn, $rd */ { SH_INSN_SUB, "sub", "sub", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* sub.l $rm, $rn, $rd */ { SH_INSN_SUBL, "subl", "sub.l", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* swap.q $rm, $rn, $rd */ { SH_INSN_SWAPQ, "swapq", "swap.q", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* synci */ { SH_INSN_SYNCI, "synci", "synci", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* synco */ { SH_INSN_SYNCO, "synco", "synco", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* trapa $rm */ { SH_INSN_TRAPA, "trapa", "trapa", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* xor $rm, $rn, $rd */ { SH_INSN_XOR, "xor", "xor", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, /* xori $rm, $imm6, $rd */ { SH_INSN_XORI, "xori", "xori", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { SH4_GROUP_NONE, 0 } }, { { SH4A_GROUP_NONE, 0 } } } } }, }; @@ -2970,16 +3246,21 @@ static const CGEN_IBASE sh_cgen_insn_table[MAX_INSNS] = /* Initialize anything needed to be done once, before any cpu_open call. */ static void -init_tables () +init_tables (void) { } +static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); +static void build_hw_table (CGEN_CPU_TABLE *); +static void build_ifield_table (CGEN_CPU_TABLE *); +static void build_operand_table (CGEN_CPU_TABLE *); +static void build_insn_table (CGEN_CPU_TABLE *); +static void sh_cgen_rebuild_tables (CGEN_CPU_TABLE *); + /* Subroutine of sh_cgen_cpu_open to look up a mach via its bfd name. */ static const CGEN_MACH * -lookup_mach_via_bfd_name (table, name) - const CGEN_MACH *table; - const char *name; +lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) { while (table->name) { @@ -2993,8 +3274,7 @@ lookup_mach_via_bfd_name (table, name) /* Subroutine of sh_cgen_cpu_open to build the hardware table. */ static void -build_hw_table (cd) - CGEN_CPU_TABLE *cd; +build_hw_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -3020,8 +3300,7 @@ build_hw_table (cd) /* Subroutine of sh_cgen_cpu_open to build the hardware table. */ static void -build_ifield_table (cd) - CGEN_CPU_TABLE *cd; +build_ifield_table (CGEN_CPU_TABLE *cd) { cd->ifld_table = & sh_cgen_ifld_table[0]; } @@ -3029,8 +3308,7 @@ build_ifield_table (cd) /* Subroutine of sh_cgen_cpu_open to build the hardware table. */ static void -build_operand_table (cd) - CGEN_CPU_TABLE *cd; +build_operand_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -3038,8 +3316,7 @@ build_operand_table (cd) /* MAX_OPERANDS is only an upper bound on the number of selected entries. However each entry is indexed by it's enum so there can be holes in the table. */ - const CGEN_OPERAND **selected = - (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); cd->operand_table.init_entries = init; cd->operand_table.entry_size = sizeof (CGEN_OPERAND); @@ -3062,12 +3339,11 @@ build_operand_table (cd) operand elements to be in the table [which they mightn't be]. */ static void -build_insn_table (cd) - CGEN_CPU_TABLE *cd; +build_insn_table (CGEN_CPU_TABLE *cd) { int i; const CGEN_IBASE *ib = & sh_cgen_insn_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); for (i = 0; i < MAX_INSNS; ++i) @@ -3080,14 +3356,11 @@ build_insn_table (cd) /* Subroutine of sh_cgen_cpu_open to rebuild the tables. */ static void -sh_cgen_rebuild_tables (cd) - CGEN_CPU_TABLE *cd; +sh_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { - int i,n_isas; - unsigned int isas = cd->isas; -#if 0 + int i; + CGEN_BITSET *isas = cd->isas; unsigned int machs = cd->machs; -#endif cd->int_insn_p = CGEN_INT_INSN_P; @@ -3095,28 +3368,28 @@ sh_cgen_rebuild_tables (cd) #define UNSET (CGEN_SIZE_UNKNOWN + 1) cd->default_insn_bitsize = UNSET; cd->base_insn_bitsize = UNSET; - cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) - if (((1 << i) & isas) != 0) + if (cgen_bitset_contains (isas, i)) { const CGEN_ISA *isa = & sh_cgen_isa_table[i]; - /* Default insn sizes of all selected isas must be equal or we set - the result to 0, meaning "unknown". */ + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ if (cd->default_insn_bitsize == UNSET) cd->default_insn_bitsize = isa->default_insn_bitsize; else if (isa->default_insn_bitsize == cd->default_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; - /* Base insn sizes of all selected isas must be equal or we set - the result to 0, meaning "unknown". */ + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ if (cd->base_insn_bitsize == UNSET) cd->base_insn_bitsize = isa->base_insn_bitsize; else if (isa->base_insn_bitsize == cd->base_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -3125,20 +3398,26 @@ sh_cgen_rebuild_tables (cd) cd->min_insn_bitsize = isa->min_insn_bitsize; if (isa->max_insn_bitsize > cd->max_insn_bitsize) cd->max_insn_bitsize = isa->max_insn_bitsize; - - ++n_isas; } -#if 0 /* Does nothing?? */ /* Data derived from the mach spec. */ for (i = 0; i < MAX_MACHS; ++i) if (((1 << i) & machs) != 0) { const CGEN_MACH *mach = & sh_cgen_mach_table[i]; - ++n_machs; + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "sh_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } } -#endif /* Determine which hw elements are used by MACH. */ build_hw_table (cd); @@ -3177,7 +3456,7 @@ sh_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; - unsigned int isas = 0; /* 0 = "unspecified" */ + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ unsigned int machs = 0; /* 0 = "unspecified" */ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; va_list ap; @@ -3196,7 +3475,7 @@ sh_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) switch (arg_type) { case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, unsigned int); + isas = va_arg (ap, CGEN_BITSET *); break; case CGEN_CPU_OPEN_MACHS : machs = va_arg (ap, unsigned int); @@ -3207,7 +3486,7 @@ sh_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) const CGEN_MACH *mach = lookup_mach_via_bfd_name (sh_cgen_mach_table, name); - machs |= mach->num << 1; + machs |= 1 << mach->num; break; } case CGEN_CPU_OPEN_ENDIAN : @@ -3222,14 +3501,11 @@ sh_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) } va_end (ap); - /* mach unspecified means "all" */ + /* Mach unspecified means "all". */ if (machs == 0) machs = (1 << MAX_MACHS) - 1; - /* base mach is always selected */ + /* Base mach is always selected. */ machs |= 1; - /* isa unspecified means "all" */ - if (isas == 0) - isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ @@ -3237,7 +3513,7 @@ sh_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) abort (); } - cd->isas = isas; + cd->isas = cgen_bitset_copy (isas); cd->machs = machs; cd->endian = endian; /* FIXME: for the sparc case we can determine insn-endianness statically. @@ -3260,9 +3536,7 @@ sh_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) MACH_NAME is the bfd name of the mach. */ CGEN_CPU_DESC -sh_cgen_cpu_open_1 (mach_name, endian) - const char *mach_name; - enum cgen_endian endian; +sh_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) { return sh_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, CGEN_CPU_OPEN_ENDIAN, endian, @@ -3275,13 +3549,39 @@ sh_cgen_cpu_open_1 (mach_name, endian) place as some simulator ports use this but they don't use libopcodes. */ void -sh_cgen_cpu_close (cd) - CGEN_CPU_DESC cd; +sh_cgen_cpu_close (CGEN_CPU_DESC cd) { + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + if (cd->insn_table.init_entries) free ((CGEN_INSN *) cd->insn_table.init_entries); + if (cd->hw_table.entries) free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + free (cd); } diff --git a/sim/sh64/sh-desc.h b/sim/sh64/sh-desc.h index 30402cc..2fc0361 100644 --- a/sim/sh64/sh-desc.h +++ b/sim/sh64/sh-desc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -18,13 +18,15 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #ifndef SH_CPU_H #define SH_CPU_H +#include "opcode/cgen-bitset.h" + #define CGEN_ARCH sh /* Given symbol S, return sh_cgen_<S>. */ @@ -38,7 +40,7 @@ with this program; if not, write to the Free Software Foundation, Inc., /* Selected cpu families. */ #define HAVE_CPU_SH64 -#define CGEN_INSN_LSB0_P 1 +#define CGEN_INSN_LSB0_P 0 /* Minimum size of any insn (in bytes). */ #define CGEN_MIN_INSN_SIZE 2 @@ -48,8 +50,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #define CGEN_INT_INSN_P 1 -/* Maximum nymber of syntax bytes in an instruction. */ -#define CGEN_ACTUAL_MAX_SYNTAX_BYTES 22 +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands @@ -87,8 +89,10 @@ typedef enum xf_names { /* Enum declaration for machine type selection. */ typedef enum mach_attr { - MACH_BASE, MACH_SH2, MACH_SH3, MACH_SH3E - , MACH_SH4, MACH_SH5, MACH_MAX + MACH_BASE, MACH_SH2, MACH_SH2E, MACH_SH2A_FPU + , MACH_SH2A_NOFPU, MACH_SH3, MACH_SH3E, MACH_SH4_NOFPU + , MACH_SH4, MACH_SH4A_NOFPU, MACH_SH4A, MACH_SH4AL + , MACH_SH5, MACH_MAX } MACH_ATTR; /* Enum declaration for instruction set selection. */ @@ -96,10 +100,24 @@ typedef enum isa_attr { ISA_COMPACT, ISA_MEDIA, ISA_MAX } ISA_ATTR; +/* Enum declaration for sh4 insn groups. */ +typedef enum sh4_group_attr { + SH4_GROUP_NONE, SH4_GROUP_MT, SH4_GROUP_EX, SH4_GROUP_BR + , SH4_GROUP_LS, SH4_GROUP_FE, SH4_GROUP_CO, SH4_GROUP_MAX +} SH4_GROUP_ATTR; + +/* Enum declaration for sh4a insn groups. */ +typedef enum sh4a_group_attr { + SH4A_GROUP_NONE, SH4A_GROUP_MT, SH4A_GROUP_EX, SH4A_GROUP_BR + , SH4A_GROUP_LS, SH4A_GROUP_FE, SH4A_GROUP_CO, SH4A_GROUP_MAX +} SH4A_GROUP_ATTR; + /* Number of architecture variants. */ #define MAX_ISAS ((int) ISA_MAX) #define MAX_MACHS ((int) MACH_MAX) +/* Ifield support. */ + /* Ifield attribute indices. */ /* Enum declaration for cgen_ifld attrs. */ @@ -112,21 +130,33 @@ typedef enum cgen_ifld_attr { /* Number of non-boolean elements in cgen_ifld_attr. */ #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + /* Enum declaration for sh ifield types. */ typedef enum ifield_type { SH_F_NIL, SH_F_ANYOF, SH_F_OP4, SH_F_OP8 , SH_F_OP16, SH_F_SUB4, SH_F_SUB8, SH_F_SUB10 - , SH_F_RN, SH_F_RM, SH_F_8_1, SH_F_DISP8 - , SH_F_DISP12, SH_F_IMM8, SH_F_IMM4, SH_F_IMM4X2 - , SH_F_IMM4X4, SH_F_IMM8X2, SH_F_IMM8X4, SH_F_DN + , SH_F_RN, SH_F_RM, SH_F_7_1, SH_F_11_1 + , SH_F_16_4, SH_F_DISP8, SH_F_DISP12, SH_F_IMM8 + , SH_F_IMM4, SH_F_IMM4X2, SH_F_IMM4X4, SH_F_IMM8X2 + , SH_F_IMM8X4, SH_F_IMM12X4, SH_F_IMM12X8, SH_F_DN , SH_F_DM, SH_F_VN, SH_F_VM, SH_F_XN - , SH_F_XM, SH_F_OP, SH_F_EXT, SH_F_RSVD - , SH_F_LEFT, SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT - , SH_F_TRA, SH_F_TRB, SH_F_LIKELY, SH_F_25 - , SH_F_8_2, SH_F_IMM6, SH_F_IMM10, SH_F_IMM16 - , SH_F_UIMM6, SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32 - , SH_F_DISP10, SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2 - , SH_F_DISP16, SH_F_MAX + , SH_F_XM, SH_F_IMM20_HI, SH_F_IMM20_LO, SH_F_IMM20 + , SH_F_OP, SH_F_EXT, SH_F_RSVD, SH_F_LEFT + , SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT, SH_F_TRA + , SH_F_TRB, SH_F_LIKELY, SH_F_6_3, SH_F_23_2 + , SH_F_IMM6, SH_F_IMM10, SH_F_IMM16, SH_F_UIMM6 + , SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32, SH_F_DISP10 + , SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2, SH_F_DISP16 + , SH_F_MAX } IFIELD_TYPE; #define MAX_IFLD ((int) SH_F_MAX) @@ -136,12 +166,21 @@ typedef enum ifield_type { /* Enum declaration for cgen_hw attrs. */ typedef enum cgen_hw_attr { CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE - , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA + , CGEN_HW_END_NBOOLS } CGEN_HW_ATTR; /* Number of non-boolean elements in cgen_hw_attr. */ #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + /* Enum declaration for sh hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR @@ -149,11 +188,11 @@ typedef enum cgen_hw_type { , HW_H_CR, HW_H_SR, HW_H_FPSCR, HW_H_FRBIT , HW_H_SZBIT, HW_H_PRBIT, HW_H_SBIT, HW_H_MBIT , HW_H_QBIT, HW_H_FR, HW_H_FP, HW_H_FV - , HW_H_FMTX, HW_H_DR, HW_H_TR, HW_H_ENDIAN - , HW_H_ISM, HW_H_FRC, HW_H_DRC, HW_H_XF - , HW_H_XD, HW_H_FVC, HW_H_FPCCR, HW_H_GBR - , HW_H_PR, HW_H_MACL, HW_H_MACH, HW_H_TBIT - , HW_MAX + , HW_H_FMTX, HW_H_DR, HW_H_FSD, HW_H_FMOV + , HW_H_TR, HW_H_ENDIAN, HW_H_ISM, HW_H_FRC + , HW_H_DRC, HW_H_XF, HW_H_XD, HW_H_FVC + , HW_H_GBR, HW_H_VBR, HW_H_PR, HW_H_MACL + , HW_H_MACH, HW_H_TBIT, HW_MAX } CGEN_HW_TYPE; #define MAX_HW ((int) HW_MAX) @@ -171,30 +210,44 @@ typedef enum cgen_operand_attr { /* Number of non-boolean elements in cgen_operand_attr. */ #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + /* Enum declaration for sh operand types. */ typedef enum cgen_operand_type { SH_OPERAND_PC, SH_OPERAND_ENDIAN, SH_OPERAND_ISM, SH_OPERAND_RM , SH_OPERAND_RN, SH_OPERAND_R0, SH_OPERAND_FRN, SH_OPERAND_FRM - , SH_OPERAND_FVN, SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM - , SH_OPERAND_IMM4, SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM4X2 + , SH_OPERAND_FR0, SH_OPERAND_FMOVN, SH_OPERAND_FMOVM, SH_OPERAND_FVN + , SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM, SH_OPERAND_IMM4 + , SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM20, SH_OPERAND_IMM4X2 , SH_OPERAND_IMM4X4, SH_OPERAND_IMM8X2, SH_OPERAND_IMM8X4, SH_OPERAND_DISP8 - , SH_OPERAND_DISP12, SH_OPERAND_RM64, SH_OPERAND_RN64, SH_OPERAND_GBR - , SH_OPERAND_PR, SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT - , SH_OPERAND_MBIT, SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT - , SH_OPERAND_SZBIT, SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH - , SH_OPERAND_FSDM, SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG - , SH_OPERAND_FRH, SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF - , SH_OPERAND_FVG, SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG - , SH_OPERAND_DRG, SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH - , SH_OPERAND_CRJ, SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB - , SH_OPERAND_DISP6, SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2 - , SH_OPERAND_DISP10X4, SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6 - , SH_OPERAND_IMM10, SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16 - , SH_OPERAND_LIKELY, SH_OPERAND_MAX + , SH_OPERAND_DISP12, SH_OPERAND_IMM12X4, SH_OPERAND_IMM12X8, SH_OPERAND_RM64 + , SH_OPERAND_RN64, SH_OPERAND_GBR, SH_OPERAND_VBR, SH_OPERAND_PR + , SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT, SH_OPERAND_MBIT + , SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT, SH_OPERAND_SZBIT + , SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH, SH_OPERAND_FSDM + , SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG, SH_OPERAND_FRH + , SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF, SH_OPERAND_FVG + , SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG, SH_OPERAND_DRG + , SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH, SH_OPERAND_CRJ + , SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB, SH_OPERAND_DISP6 + , SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2, SH_OPERAND_DISP10X4 + , SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6, SH_OPERAND_IMM10 + , SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16, SH_OPERAND_LIKELY + , SH_OPERAND_MAX } CGEN_OPERAND_TYPE; /* Number of operands types. */ -#define MAX_OPERANDS 72 +#define MAX_OPERANDS 79 /* Maximum number of operands referenced by any insn. */ #define MAX_OPERAND_INSTANCES 8 @@ -204,18 +257,39 @@ typedef enum cgen_operand_type { /* Enum declaration for cgen_insn attrs. */ typedef enum cgen_insn_attr { CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI - , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_ILLSLOT, CGEN_INSN_FP_INSN - , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA - , CGEN_INSN_END_NBOOLS + , CGEN_INSN_32_BIT_INSN, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH + , CGEN_INSN_ISA, CGEN_INSN_SH4_GROUP, CGEN_INSN_SH4A_GROUP, CGEN_INSN_END_NBOOLS } CGEN_INSN_ATTR; /* Number of non-boolean elements in cgen_insn_attr. */ #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_INSN_SH4_GROUP_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SH4_GROUP-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_SH4A_GROUP_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SH4A_GROUP-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_ILLSLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ILLSLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_FP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_FP_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_32_BIT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_32_BIT_INSN)) != 0) + /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" +extern const struct cgen_ifld sh_cgen_ifld_table[]; + /* Attributes. */ extern const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[]; extern const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[]; @@ -232,6 +306,8 @@ extern CGEN_KEYWORD sh_cgen_opval_h_fp; extern CGEN_KEYWORD sh_cgen_opval_h_fv; extern CGEN_KEYWORD sh_cgen_opval_h_fmtx; extern CGEN_KEYWORD sh_cgen_opval_h_dr; +extern CGEN_KEYWORD sh_cgen_opval_h_fsd; +extern CGEN_KEYWORD sh_cgen_opval_h_fmov; extern CGEN_KEYWORD sh_cgen_opval_h_tr; extern CGEN_KEYWORD sh_cgen_opval_frc_names; extern CGEN_KEYWORD sh_cgen_opval_drc_names; @@ -239,10 +315,7 @@ extern CGEN_KEYWORD sh_cgen_opval_xf_names; extern CGEN_KEYWORD sh_cgen_opval_frc_names; extern CGEN_KEYWORD sh_cgen_opval_h_fvc; -/* Ifield support. */ - -extern const struct cgen_ifld sh_cgen_ifld_table[]; - +extern const CGEN_HW_ENTRY sh_cgen_hw_table[]; diff --git a/sim/sh64/sh-opc.h b/sim/sh64/sh-opc.h index 3e0b8e2..915bc44 100644 --- a/sim/sh64/sh-opc.h +++ b/sim/sh64/sh-opc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -18,24 +18,13 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #ifndef SH_OPC_H #define SH_OPC_H -/* -- opc.h */ - -/* Allows reason codes to be output when assembler errors occur. */ -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - -/* Override disassembly hashing - there are variable bits in the top - byte of these instructions. */ -#define CGEN_DIS_HASH_SIZE 8 -#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE) - -/* -- asm.c */ /* Enum declaration for sh instruction types. */ typedef enum cgen_insn_type { SH_INSN_INVALID, SH_INSN_ADD_COMPACT, SH_INSN_ADDI_COMPACT, SH_INSN_ADDC_COMPACT @@ -46,103 +35,106 @@ typedef enum cgen_insn_type { , SH_INSN_CMPEQ_COMPACT, SH_INSN_CMPEQI_COMPACT, SH_INSN_CMPGE_COMPACT, SH_INSN_CMPGT_COMPACT , SH_INSN_CMPHI_COMPACT, SH_INSN_CMPHS_COMPACT, SH_INSN_CMPPL_COMPACT, SH_INSN_CMPPZ_COMPACT , SH_INSN_CMPSTR_COMPACT, SH_INSN_DIV0S_COMPACT, SH_INSN_DIV0U_COMPACT, SH_INSN_DIV1_COMPACT - , SH_INSN_DMULSL_COMPACT, SH_INSN_DMULUL_COMPACT, SH_INSN_DT_COMPACT, SH_INSN_EXTSB_COMPACT - , SH_INSN_EXTSW_COMPACT, SH_INSN_EXTUB_COMPACT, SH_INSN_EXTUW_COMPACT, SH_INSN_FABS_COMPACT - , SH_INSN_FADD_COMPACT, SH_INSN_FCMPEQ_COMPACT, SH_INSN_FCMPGT_COMPACT, SH_INSN_FCNVDS_COMPACT - , SH_INSN_FCNVSD_COMPACT, SH_INSN_FDIV_COMPACT, SH_INSN_FIPR_COMPACT, SH_INSN_FLDS_COMPACT - , SH_INSN_FLDI0_COMPACT, SH_INSN_FLDI1_COMPACT, SH_INSN_FLOAT_COMPACT, SH_INSN_FMAC_COMPACT - , SH_INSN_FMOV1_COMPACT, SH_INSN_FMOV2_COMPACT, SH_INSN_FMOV3_COMPACT, SH_INSN_FMOV4_COMPACT - , SH_INSN_FMOV5_COMPACT, SH_INSN_FMOV6_COMPACT, SH_INSN_FMOV7_COMPACT, SH_INSN_FMUL_COMPACT + , SH_INSN_DIVU_COMPACT, SH_INSN_MULR_COMPACT, SH_INSN_DMULSL_COMPACT, SH_INSN_DMULUL_COMPACT + , SH_INSN_DT_COMPACT, SH_INSN_EXTSB_COMPACT, SH_INSN_EXTSW_COMPACT, SH_INSN_EXTUB_COMPACT + , SH_INSN_EXTUW_COMPACT, SH_INSN_FABS_COMPACT, SH_INSN_FADD_COMPACT, SH_INSN_FCMPEQ_COMPACT + , SH_INSN_FCMPGT_COMPACT, SH_INSN_FCNVDS_COMPACT, SH_INSN_FCNVSD_COMPACT, SH_INSN_FDIV_COMPACT + , SH_INSN_FIPR_COMPACT, SH_INSN_FLDS_COMPACT, SH_INSN_FLDI0_COMPACT, SH_INSN_FLDI1_COMPACT + , SH_INSN_FLOAT_COMPACT, SH_INSN_FMAC_COMPACT, SH_INSN_FMOV1_COMPACT, SH_INSN_FMOV2_COMPACT + , SH_INSN_FMOV3_COMPACT, SH_INSN_FMOV4_COMPACT, SH_INSN_FMOV5_COMPACT, SH_INSN_FMOV6_COMPACT + , SH_INSN_FMOV7_COMPACT, SH_INSN_FMOV8_COMPACT, SH_INSN_FMOV9_COMPACT, SH_INSN_FMUL_COMPACT , SH_INSN_FNEG_COMPACT, SH_INSN_FRCHG_COMPACT, SH_INSN_FSCHG_COMPACT, SH_INSN_FSQRT_COMPACT , SH_INSN_FSTS_COMPACT, SH_INSN_FSUB_COMPACT, SH_INSN_FTRC_COMPACT, SH_INSN_FTRV_COMPACT - , SH_INSN_JMP_COMPACT, SH_INSN_JSR_COMPACT, SH_INSN_LDC_COMPACT, SH_INSN_LDCL_COMPACT - , SH_INSN_LDS_FPSCR_COMPACT, SH_INSN_LDSL_FPSCR_COMPACT, SH_INSN_LDS_FPUL_COMPACT, SH_INSN_LDSL_FPUL_COMPACT - , SH_INSN_LDS_MACH_COMPACT, SH_INSN_LDSL_MACH_COMPACT, SH_INSN_LDS_MACL_COMPACT, SH_INSN_LDSL_MACL_COMPACT - , SH_INSN_LDS_PR_COMPACT, SH_INSN_LDSL_PR_COMPACT, SH_INSN_MACL_COMPACT, SH_INSN_MACW_COMPACT - , SH_INSN_MOV_COMPACT, SH_INSN_MOVI_COMPACT, SH_INSN_MOVB1_COMPACT, SH_INSN_MOVB2_COMPACT + , SH_INSN_JMP_COMPACT, SH_INSN_JSR_COMPACT, SH_INSN_LDC_GBR_COMPACT, SH_INSN_LDC_VBR_COMPACT + , SH_INSN_LDC_SR_COMPACT, SH_INSN_LDCL_GBR_COMPACT, SH_INSN_LDCL_VBR_COMPACT, SH_INSN_LDS_FPSCR_COMPACT + , SH_INSN_LDSL_FPSCR_COMPACT, SH_INSN_LDS_FPUL_COMPACT, SH_INSN_LDSL_FPUL_COMPACT, SH_INSN_LDS_MACH_COMPACT + , SH_INSN_LDSL_MACH_COMPACT, SH_INSN_LDS_MACL_COMPACT, SH_INSN_LDSL_MACL_COMPACT, SH_INSN_LDS_PR_COMPACT + , SH_INSN_LDSL_PR_COMPACT, SH_INSN_MACL_COMPACT, SH_INSN_MACW_COMPACT, SH_INSN_MOV_COMPACT + , SH_INSN_MOVI_COMPACT, SH_INSN_MOVI20_COMPACT, SH_INSN_MOVB1_COMPACT, SH_INSN_MOVB2_COMPACT , SH_INSN_MOVB3_COMPACT, SH_INSN_MOVB4_COMPACT, SH_INSN_MOVB5_COMPACT, SH_INSN_MOVB6_COMPACT , SH_INSN_MOVB7_COMPACT, SH_INSN_MOVB8_COMPACT, SH_INSN_MOVB9_COMPACT, SH_INSN_MOVB10_COMPACT , SH_INSN_MOVL1_COMPACT, SH_INSN_MOVL2_COMPACT, SH_INSN_MOVL3_COMPACT, SH_INSN_MOVL4_COMPACT , SH_INSN_MOVL5_COMPACT, SH_INSN_MOVL6_COMPACT, SH_INSN_MOVL7_COMPACT, SH_INSN_MOVL8_COMPACT - , SH_INSN_MOVL9_COMPACT, SH_INSN_MOVL10_COMPACT, SH_INSN_MOVL11_COMPACT, SH_INSN_MOVW1_COMPACT - , SH_INSN_MOVW2_COMPACT, SH_INSN_MOVW3_COMPACT, SH_INSN_MOVW4_COMPACT, SH_INSN_MOVW5_COMPACT - , SH_INSN_MOVW6_COMPACT, SH_INSN_MOVW7_COMPACT, SH_INSN_MOVW8_COMPACT, SH_INSN_MOVW9_COMPACT - , SH_INSN_MOVW10_COMPACT, SH_INSN_MOVW11_COMPACT, SH_INSN_MOVA_COMPACT, SH_INSN_MOVCAL_COMPACT - , SH_INSN_MOVT_COMPACT, SH_INSN_MULL_COMPACT, SH_INSN_MULSW_COMPACT, SH_INSN_MULUW_COMPACT - , SH_INSN_NEG_COMPACT, SH_INSN_NEGC_COMPACT, SH_INSN_NOP_COMPACT, SH_INSN_NOT_COMPACT - , SH_INSN_OCBI_COMPACT, SH_INSN_OCBP_COMPACT, SH_INSN_OCBWB_COMPACT, SH_INSN_OR_COMPACT - , SH_INSN_ORI_COMPACT, SH_INSN_ORB_COMPACT, SH_INSN_PREF_COMPACT, SH_INSN_ROTCL_COMPACT - , SH_INSN_ROTCR_COMPACT, SH_INSN_ROTL_COMPACT, SH_INSN_ROTR_COMPACT, SH_INSN_RTS_COMPACT - , SH_INSN_SETS_COMPACT, SH_INSN_SETT_COMPACT, SH_INSN_SHAD_COMPACT, SH_INSN_SHAL_COMPACT - , SH_INSN_SHAR_COMPACT, SH_INSN_SHLD_COMPACT, SH_INSN_SHLL_COMPACT, SH_INSN_SHLL2_COMPACT - , SH_INSN_SHLL8_COMPACT, SH_INSN_SHLL16_COMPACT, SH_INSN_SHLR_COMPACT, SH_INSN_SHLR2_COMPACT - , SH_INSN_SHLR8_COMPACT, SH_INSN_SHLR16_COMPACT, SH_INSN_STC_GBR_COMPACT, SH_INSN_STCL_GBR_COMPACT - , SH_INSN_STS_FPSCR_COMPACT, SH_INSN_STSL_FPSCR_COMPACT, SH_INSN_STS_FPUL_COMPACT, SH_INSN_STSL_FPUL_COMPACT - , SH_INSN_STS_MACH_COMPACT, SH_INSN_STSL_MACH_COMPACT, SH_INSN_STS_MACL_COMPACT, SH_INSN_STSL_MACL_COMPACT - , SH_INSN_STS_PR_COMPACT, SH_INSN_STSL_PR_COMPACT, SH_INSN_SUB_COMPACT, SH_INSN_SUBC_COMPACT - , SH_INSN_SUBV_COMPACT, SH_INSN_SWAPB_COMPACT, SH_INSN_SWAPW_COMPACT, SH_INSN_TASB_COMPACT - , SH_INSN_TRAPA_COMPACT, SH_INSN_TST_COMPACT, SH_INSN_TSTI_COMPACT, SH_INSN_TSTB_COMPACT - , SH_INSN_XOR_COMPACT, SH_INSN_XORI_COMPACT, SH_INSN_XORB_COMPACT, SH_INSN_XTRCT_COMPACT - , SH_INSN_ADD, SH_INSN_ADDL, SH_INSN_ADDI, SH_INSN_ADDIL - , SH_INSN_ADDZL, SH_INSN_ALLOCO, SH_INSN_AND, SH_INSN_ANDC - , SH_INSN_ANDI, SH_INSN_BEQ, SH_INSN_BEQI, SH_INSN_BGE - , SH_INSN_BGEU, SH_INSN_BGT, SH_INSN_BGTU, SH_INSN_BLINK - , SH_INSN_BNE, SH_INSN_BNEI, SH_INSN_BRK, SH_INSN_BYTEREV - , SH_INSN_CMPEQ, SH_INSN_CMPGT, SH_INSN_CMPGTU, SH_INSN_CMVEQ - , SH_INSN_CMVNE, SH_INSN_FABSD, SH_INSN_FABSS, SH_INSN_FADDD - , SH_INSN_FADDS, SH_INSN_FCMPEQD, SH_INSN_FCMPEQS, SH_INSN_FCMPGED - , SH_INSN_FCMPGES, SH_INSN_FCMPGTD, SH_INSN_FCMPGTS, SH_INSN_FCMPUND - , SH_INSN_FCMPUNS, SH_INSN_FCNVDS, SH_INSN_FCNVSD, SH_INSN_FDIVD - , SH_INSN_FDIVS, SH_INSN_FGETSCR, SH_INSN_FIPRS, SH_INSN_FLDD - , SH_INSN_FLDP, SH_INSN_FLDS, SH_INSN_FLDXD, SH_INSN_FLDXP - , SH_INSN_FLDXS, SH_INSN_FLOATLD, SH_INSN_FLOATLS, SH_INSN_FLOATQD - , SH_INSN_FLOATQS, SH_INSN_FMACS, SH_INSN_FMOVD, SH_INSN_FMOVDQ - , SH_INSN_FMOVLS, SH_INSN_FMOVQD, SH_INSN_FMOVS, SH_INSN_FMOVSL - , SH_INSN_FMULD, SH_INSN_FMULS, SH_INSN_FNEGD, SH_INSN_FNEGS - , SH_INSN_FPUTSCR, SH_INSN_FSQRTD, SH_INSN_FSQRTS, SH_INSN_FSTD - , SH_INSN_FSTP, SH_INSN_FSTS, SH_INSN_FSTXD, SH_INSN_FSTXP - , SH_INSN_FSTXS, SH_INSN_FSUBD, SH_INSN_FSUBS, SH_INSN_FTRCDL - , SH_INSN_FTRCSL, SH_INSN_FTRCDQ, SH_INSN_FTRCSQ, SH_INSN_FTRVS - , SH_INSN_GETCFG, SH_INSN_GETCON, SH_INSN_GETTR, SH_INSN_ICBI - , SH_INSN_LDB, SH_INSN_LDL, SH_INSN_LDQ, SH_INSN_LDUB - , SH_INSN_LDUW, SH_INSN_LDW, SH_INSN_LDHIL, SH_INSN_LDHIQ - , SH_INSN_LDLOL, SH_INSN_LDLOQ, SH_INSN_LDXB, SH_INSN_LDXL - , SH_INSN_LDXQ, SH_INSN_LDXUB, SH_INSN_LDXUW, SH_INSN_LDXW - , SH_INSN_MABSL, SH_INSN_MABSW, SH_INSN_MADDL, SH_INSN_MADDW - , SH_INSN_MADDSL, SH_INSN_MADDSUB, SH_INSN_MADDSW, SH_INSN_MCMPEQB - , SH_INSN_MCMPEQL, SH_INSN_MCMPEQW, SH_INSN_MCMPGTL, SH_INSN_MCMPGTUB - , SH_INSN_MCMPGTW, SH_INSN_MCMV, SH_INSN_MCNVSLW, SH_INSN_MCNVSWB - , SH_INSN_MCNVSWUB, SH_INSN_MEXTR1, SH_INSN_MEXTR2, SH_INSN_MEXTR3 - , SH_INSN_MEXTR4, SH_INSN_MEXTR5, SH_INSN_MEXTR6, SH_INSN_MEXTR7 - , SH_INSN_MMACFXWL, SH_INSN_MMACNFX_WL, SH_INSN_MMULL, SH_INSN_MMULW - , SH_INSN_MMULFXL, SH_INSN_MMULFXW, SH_INSN_MMULFXRPW, SH_INSN_MMULHIWL - , SH_INSN_MMULLOWL, SH_INSN_MMULSUMWQ, SH_INSN_MOVI, SH_INSN_MPERMW - , SH_INSN_MSADUBQ, SH_INSN_MSHALDSL, SH_INSN_MSHALDSW, SH_INSN_MSHARDL - , SH_INSN_MSHARDW, SH_INSN_MSHARDSQ, SH_INSN_MSHFHIB, SH_INSN_MSHFHIL - , SH_INSN_MSHFHIW, SH_INSN_MSHFLOB, SH_INSN_MSHFLOL, SH_INSN_MSHFLOW - , SH_INSN_MSHLLDL, SH_INSN_MSHLLDW, SH_INSN_MSHLRDL, SH_INSN_MSHLRDW - , SH_INSN_MSUBL, SH_INSN_MSUBW, SH_INSN_MSUBSL, SH_INSN_MSUBSUB - , SH_INSN_MSUBSW, SH_INSN_MULSL, SH_INSN_MULUL, SH_INSN_NOP - , SH_INSN_NSB, SH_INSN_OCBI, SH_INSN_OCBP, SH_INSN_OCBWB - , SH_INSN_OR, SH_INSN_ORI, SH_INSN_PREFI, SH_INSN_PTA - , SH_INSN_PTABS, SH_INSN_PTB, SH_INSN_PTREL, SH_INSN_PUTCFG - , SH_INSN_PUTCON, SH_INSN_RTE, SH_INSN_SHARD, SH_INSN_SHARDL - , SH_INSN_SHARI, SH_INSN_SHARIL, SH_INSN_SHLLD, SH_INSN_SHLLDL - , SH_INSN_SHLLI, SH_INSN_SHLLIL, SH_INSN_SHLRD, SH_INSN_SHLRDL - , SH_INSN_SHLRI, SH_INSN_SHLRIL, SH_INSN_SHORI, SH_INSN_SLEEP - , SH_INSN_STB, SH_INSN_STL, SH_INSN_STQ, SH_INSN_STW - , SH_INSN_STHIL, SH_INSN_STHIQ, SH_INSN_STLOL, SH_INSN_STLOQ - , SH_INSN_STXB, SH_INSN_STXL, SH_INSN_STXQ, SH_INSN_STXW - , SH_INSN_SUB, SH_INSN_SUBL, SH_INSN_SWAPQ, SH_INSN_SYNCI - , SH_INSN_SYNCO, SH_INSN_TRAPA, SH_INSN_XOR, SH_INSN_XORI - , SH_INSN_MAX + , SH_INSN_MOVL9_COMPACT, SH_INSN_MOVL10_COMPACT, SH_INSN_MOVL11_COMPACT, SH_INSN_MOVL12_COMPACT + , SH_INSN_MOVL13_COMPACT, SH_INSN_MOVW1_COMPACT, SH_INSN_MOVW2_COMPACT, SH_INSN_MOVW3_COMPACT + , SH_INSN_MOVW4_COMPACT, SH_INSN_MOVW5_COMPACT, SH_INSN_MOVW6_COMPACT, SH_INSN_MOVW7_COMPACT + , SH_INSN_MOVW8_COMPACT, SH_INSN_MOVW9_COMPACT, SH_INSN_MOVW10_COMPACT, SH_INSN_MOVW11_COMPACT + , SH_INSN_MOVA_COMPACT, SH_INSN_MOVCAL_COMPACT, SH_INSN_MOVCOL_COMPACT, SH_INSN_MOVT_COMPACT + , SH_INSN_MOVUAL_COMPACT, SH_INSN_MOVUAL2_COMPACT, SH_INSN_MULL_COMPACT, SH_INSN_MULSW_COMPACT + , SH_INSN_MULUW_COMPACT, SH_INSN_NEG_COMPACT, SH_INSN_NEGC_COMPACT, SH_INSN_NOP_COMPACT + , SH_INSN_NOT_COMPACT, SH_INSN_OCBI_COMPACT, SH_INSN_OCBP_COMPACT, SH_INSN_OCBWB_COMPACT + , SH_INSN_OR_COMPACT, SH_INSN_ORI_COMPACT, SH_INSN_ORB_COMPACT, SH_INSN_PREF_COMPACT + , SH_INSN_ROTCL_COMPACT, SH_INSN_ROTCR_COMPACT, SH_INSN_ROTL_COMPACT, SH_INSN_ROTR_COMPACT + , SH_INSN_RTS_COMPACT, SH_INSN_SETS_COMPACT, SH_INSN_SETT_COMPACT, SH_INSN_SHAD_COMPACT + , SH_INSN_SHAL_COMPACT, SH_INSN_SHAR_COMPACT, SH_INSN_SHLD_COMPACT, SH_INSN_SHLL_COMPACT + , SH_INSN_SHLL2_COMPACT, SH_INSN_SHLL8_COMPACT, SH_INSN_SHLL16_COMPACT, SH_INSN_SHLR_COMPACT + , SH_INSN_SHLR2_COMPACT, SH_INSN_SHLR8_COMPACT, SH_INSN_SHLR16_COMPACT, SH_INSN_STC_GBR_COMPACT + , SH_INSN_STC_VBR_COMPACT, SH_INSN_STCL_GBR_COMPACT, SH_INSN_STCL_VBR_COMPACT, SH_INSN_STS_FPSCR_COMPACT + , SH_INSN_STSL_FPSCR_COMPACT, SH_INSN_STS_FPUL_COMPACT, SH_INSN_STSL_FPUL_COMPACT, SH_INSN_STS_MACH_COMPACT + , SH_INSN_STSL_MACH_COMPACT, SH_INSN_STS_MACL_COMPACT, SH_INSN_STSL_MACL_COMPACT, SH_INSN_STS_PR_COMPACT + , SH_INSN_STSL_PR_COMPACT, SH_INSN_SUB_COMPACT, SH_INSN_SUBC_COMPACT, SH_INSN_SUBV_COMPACT + , SH_INSN_SWAPB_COMPACT, SH_INSN_SWAPW_COMPACT, SH_INSN_TASB_COMPACT, SH_INSN_TRAPA_COMPACT + , SH_INSN_TST_COMPACT, SH_INSN_TSTI_COMPACT, SH_INSN_TSTB_COMPACT, SH_INSN_XOR_COMPACT + , SH_INSN_XORI_COMPACT, SH_INSN_XORB_COMPACT, SH_INSN_XTRCT_COMPACT, SH_INSN_ADD + , SH_INSN_ADDL, SH_INSN_ADDI, SH_INSN_ADDIL, SH_INSN_ADDZL + , SH_INSN_ALLOCO, SH_INSN_AND, SH_INSN_ANDC, SH_INSN_ANDI + , SH_INSN_BEQ, SH_INSN_BEQI, SH_INSN_BGE, SH_INSN_BGEU + , SH_INSN_BGT, SH_INSN_BGTU, SH_INSN_BLINK, SH_INSN_BNE + , SH_INSN_BNEI, SH_INSN_BRK, SH_INSN_BYTEREV, SH_INSN_CMPEQ + , SH_INSN_CMPGT, SH_INSN_CMPGTU, SH_INSN_CMVEQ, SH_INSN_CMVNE + , SH_INSN_FABSD, SH_INSN_FABSS, SH_INSN_FADDD, SH_INSN_FADDS + , SH_INSN_FCMPEQD, SH_INSN_FCMPEQS, SH_INSN_FCMPGED, SH_INSN_FCMPGES + , SH_INSN_FCMPGTD, SH_INSN_FCMPGTS, SH_INSN_FCMPUND, SH_INSN_FCMPUNS + , SH_INSN_FCNVDS, SH_INSN_FCNVSD, SH_INSN_FDIVD, SH_INSN_FDIVS + , SH_INSN_FGETSCR, SH_INSN_FIPRS, SH_INSN_FLDD, SH_INSN_FLDP + , SH_INSN_FLDS, SH_INSN_FLDXD, SH_INSN_FLDXP, SH_INSN_FLDXS + , SH_INSN_FLOATLD, SH_INSN_FLOATLS, SH_INSN_FLOATQD, SH_INSN_FLOATQS + , SH_INSN_FMACS, SH_INSN_FMOVD, SH_INSN_FMOVDQ, SH_INSN_FMOVLS + , SH_INSN_FMOVQD, SH_INSN_FMOVS, SH_INSN_FMOVSL, SH_INSN_FMULD + , SH_INSN_FMULS, SH_INSN_FNEGD, SH_INSN_FNEGS, SH_INSN_FPUTSCR + , SH_INSN_FSQRTD, SH_INSN_FSQRTS, SH_INSN_FSTD, SH_INSN_FSTP + , SH_INSN_FSTS, SH_INSN_FSTXD, SH_INSN_FSTXP, SH_INSN_FSTXS + , SH_INSN_FSUBD, SH_INSN_FSUBS, SH_INSN_FTRCDL, SH_INSN_FTRCSL + , SH_INSN_FTRCDQ, SH_INSN_FTRCSQ, SH_INSN_FTRVS, SH_INSN_GETCFG + , SH_INSN_GETCON, SH_INSN_GETTR, SH_INSN_ICBI, SH_INSN_LDB + , SH_INSN_LDL, SH_INSN_LDQ, SH_INSN_LDUB, SH_INSN_LDUW + , SH_INSN_LDW, SH_INSN_LDHIL, SH_INSN_LDHIQ, SH_INSN_LDLOL + , SH_INSN_LDLOQ, SH_INSN_LDXB, SH_INSN_LDXL, SH_INSN_LDXQ + , SH_INSN_LDXUB, SH_INSN_LDXUW, SH_INSN_LDXW, SH_INSN_MABSL + , SH_INSN_MABSW, SH_INSN_MADDL, SH_INSN_MADDW, SH_INSN_MADDSL + , SH_INSN_MADDSUB, SH_INSN_MADDSW, SH_INSN_MCMPEQB, SH_INSN_MCMPEQL + , SH_INSN_MCMPEQW, SH_INSN_MCMPGTL, SH_INSN_MCMPGTUB, SH_INSN_MCMPGTW + , SH_INSN_MCMV, SH_INSN_MCNVSLW, SH_INSN_MCNVSWB, SH_INSN_MCNVSWUB + , SH_INSN_MEXTR1, SH_INSN_MEXTR2, SH_INSN_MEXTR3, SH_INSN_MEXTR4 + , SH_INSN_MEXTR5, SH_INSN_MEXTR6, SH_INSN_MEXTR7, SH_INSN_MMACFXWL + , SH_INSN_MMACNFX_WL, SH_INSN_MMULL, SH_INSN_MMULW, SH_INSN_MMULFXL + , SH_INSN_MMULFXW, SH_INSN_MMULFXRPW, SH_INSN_MMULHIWL, SH_INSN_MMULLOWL + , SH_INSN_MMULSUMWQ, SH_INSN_MOVI, SH_INSN_MPERMW, SH_INSN_MSADUBQ + , SH_INSN_MSHALDSL, SH_INSN_MSHALDSW, SH_INSN_MSHARDL, SH_INSN_MSHARDW + , SH_INSN_MSHARDSQ, SH_INSN_MSHFHIB, SH_INSN_MSHFHIL, SH_INSN_MSHFHIW + , SH_INSN_MSHFLOB, SH_INSN_MSHFLOL, SH_INSN_MSHFLOW, SH_INSN_MSHLLDL + , SH_INSN_MSHLLDW, SH_INSN_MSHLRDL, SH_INSN_MSHLRDW, SH_INSN_MSUBL + , SH_INSN_MSUBW, SH_INSN_MSUBSL, SH_INSN_MSUBSUB, SH_INSN_MSUBSW + , SH_INSN_MULSL, SH_INSN_MULUL, SH_INSN_NOP, SH_INSN_NSB + , SH_INSN_OCBI, SH_INSN_OCBP, SH_INSN_OCBWB, SH_INSN_OR + , SH_INSN_ORI, SH_INSN_PREFI, SH_INSN_PTA, SH_INSN_PTABS + , SH_INSN_PTB, SH_INSN_PTREL, SH_INSN_PUTCFG, SH_INSN_PUTCON + , SH_INSN_RTE, SH_INSN_SHARD, SH_INSN_SHARDL, SH_INSN_SHARI + , SH_INSN_SHARIL, SH_INSN_SHLLD, SH_INSN_SHLLDL, SH_INSN_SHLLI + , SH_INSN_SHLLIL, SH_INSN_SHLRD, SH_INSN_SHLRDL, SH_INSN_SHLRI + , SH_INSN_SHLRIL, SH_INSN_SHORI, SH_INSN_SLEEP, SH_INSN_STB + , SH_INSN_STL, SH_INSN_STQ, SH_INSN_STW, SH_INSN_STHIL + , SH_INSN_STHIQ, SH_INSN_STLOL, SH_INSN_STLOQ, SH_INSN_STXB + , SH_INSN_STXL, SH_INSN_STXQ, SH_INSN_STXW, SH_INSN_SUB + , SH_INSN_SUBL, SH_INSN_SWAPQ, SH_INSN_SYNCI, SH_INSN_SYNCO + , SH_INSN_TRAPA, SH_INSN_XOR, SH_INSN_XORI } CGEN_INSN_TYPE; /* Index of `invalid' insn place holder. */ #define CGEN_INSN_INVALID SH_INSN_INVALID /* Total number of insns in table. */ -#define MAX_INSNS ((int) SH_INSN_MAX) +#define MAX_INSNS ((int) SH_INSN_XORI + 1) /* This struct records data prior to insertion or after extraction. */ struct cgen_fields @@ -158,7 +150,9 @@ struct cgen_fields long f_sub10; long f_rn; long f_rm; - long f_8_1; + long f_7_1; + long f_11_1; + long f_16_4; long f_disp8; long f_disp12; long f_imm8; @@ -167,12 +161,17 @@ struct cgen_fields long f_imm4x4; long f_imm8x2; long f_imm8x4; + long f_imm12x4; + long f_imm12x8; long f_dn; long f_dm; long f_vn; long f_vm; long f_xn; long f_xm; + long f_imm20_hi; + long f_imm20_lo; + long f_imm20; long f_op; long f_ext; long f_rsvd; @@ -183,8 +182,8 @@ struct cgen_fields long f_tra; long f_trb; long f_likely; - long f_25; - long f_8_2; + long f_6_3; + long f_23_2; long f_imm6; long f_imm10; long f_imm16; diff --git a/sim/sh64/sh64-sim.h b/sim/sh64/sh64-sim.h index fc3ed7a..2d06188 100644 --- a/sim/sh64/sh64-sim.h +++ b/sim/sh64/sh64-sim.h @@ -1,5 +1,5 @@ /* collection of junk waiting time to sort out - Copyright (C) 2000 Free Software Foundation, Inc. + Copyright (C) 2000, 2006 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of the GNU Simulators. @@ -42,6 +42,7 @@ extern IDESC * sh64_idesc_compact; BI sh64_endian (SIM_CPU *); VOID sh64_break (SIM_CPU *, PCADDR); +SI sh64_movua (SIM_CPU *, PCADDR, SI); VOID sh64_trapa (SIM_CPU *, DI, PCADDR); VOID sh64_compact_trapa (SIM_CPU *, UQI, PCADDR); @@ -74,7 +75,12 @@ DF sh64_ftrcdq (SIM_CPU *, DF); SF sh64_ftrcsl (SIM_CPU *, SF); DF sh64_ftrcsq (SIM_CPU *, SF); VOID sh64_ftrvs (SIM_CPU *, unsigned, unsigned, unsigned); - +VOID sh64_fipr (SIM_CPU *cpu, unsigned m, unsigned n); +SF sh64_fiprs (SIM_CPU *cpu, unsigned g, unsigned h); +VOID sh64_fldp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f); +VOID sh64_fstp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f); +VOID sh64_ftrv (SIM_CPU *cpu, UINT ignored); +VOID sh64_pref (SIM_CPU *cpu, SI addr); BI sh64_fcmpeqs (SIM_CPU *, SF, SF); BI sh64_fcmpeqd (SIM_CPU *, DF, DF); BI sh64_fcmpges (SIM_CPU *, SF, SF); diff --git a/sim/sh64/sh64.c b/sim/sh64/sh64.c index 12ce3f6..51b978a 100644 --- a/sim/sh64/sh64.c +++ b/sim/sh64/sh64.c @@ -1,5 +1,5 @@ /* SH5 simulator support code - Copyright (C) 2000, 2001 Free Software Foundation, Inc. + Copyright (C) 2000, 2001, 2006 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of the GNU simulators. @@ -460,7 +460,7 @@ sh64_ftrcsq(SIM_CPU *current_cpu, SF frgh) return (DF) result; } -void +VOID sh64_ftrvs(SIM_CPU *cpu, unsigned g, unsigned h, unsigned f) { int i, j; @@ -484,6 +484,52 @@ sh64_ftrvs(SIM_CPU *cpu, unsigned g, unsigned h, unsigned f) } } +VOID +sh64_fipr (SIM_CPU *cpu, unsigned m, unsigned n) +{ + SF result = sh64_fmuls (cpu, sh64_h_fvc_get (cpu, m), sh64_h_fvc_get (cpu, n)); + result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 1), sh64_h_frc_get (cpu, n + 1))); + result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 2), sh64_h_frc_get (cpu, n + 2))); + result = sh64_fadds (cpu, result, sh64_fmuls (cpu, sh64_h_frc_get (cpu, m + 3), sh64_h_frc_get (cpu, n + 3))); + sh64_h_frc_set (cpu, n + 3, result); +} + +SF +sh64_fiprs (SIM_CPU *cpu, unsigned g, unsigned h) +{ + SF temp = sh64_fmuls (cpu, sh64_h_fr_get (cpu, g), sh64_h_fr_get (cpu, h)); + temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 1), sh64_h_fr_get (cpu, h + 1))); + temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 2), sh64_h_fr_get (cpu, h + 2))); + temp = sh64_fadds (cpu, temp, sh64_fmuls (cpu, sh64_h_fr_get (cpu, g + 3), sh64_h_fr_get (cpu, h + 3))); + return temp; +} + +VOID +sh64_fldp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f) +{ + sh64_h_fr_set (cpu, f, GETMEMSF (cpu, pc, rm + rn)); + sh64_h_fr_set (cpu, f + 1, GETMEMSF (cpu, pc, rm + rn + 4)); +} + +VOID +sh64_fstp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f) +{ + SETMEMSF (cpu, pc, rm + rn, sh64_h_fr_get (cpu, f)); + SETMEMSF (cpu, pc, rm + rn + 4, sh64_h_fr_get (cpu, f + 1)); +} + +VOID +sh64_ftrv (SIM_CPU *cpu, UINT ignored) +{ + /* TODO: Unimplemented. */ +} + +VOID +sh64_pref (SIM_CPU *cpu, SI addr) +{ + /* TODO: Unimplemented. */ +} + /* Count the number of arguments. */ static int count_argc (cpu) @@ -688,6 +734,22 @@ sh64_break (SIM_CPU *current_cpu, PCADDR pc) sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); } +SI +sh64_movua (SIM_CPU *current_cpu, PCADDR pc, SI rn) +{ + SI v; + int i; + + /* Move the data one byte at a time to avoid alignment problems. + Be aware of endianness. */ + v = 0; + for (i = 0; i < 4; ++i) + v = (v << 8) | (GETMEMQI (current_cpu, pc, rn + i) & 0xff); + + v = T2H_4 (v); + return v; +} + void set_isa (SIM_CPU *current_cpu, int mode) { @@ -971,11 +1033,18 @@ sh64_model_init() static const MODEL sh_models [] = { - { "sh2", & sh2_mach, MODEL_SH5, NULL, sh64_model_init }, - { "sh3", & sh3_mach, MODEL_SH5, NULL, sh64_model_init }, - { "sh3e", & sh3_mach, MODEL_SH5, NULL, sh64_model_init }, - { "sh4", & sh4_mach, MODEL_SH5, NULL, sh64_model_init }, - { "sh5", & sh5_mach, MODEL_SH5, NULL, sh64_model_init }, + { "sh2", & sh2_mach, MODEL_SH5, NULL, sh64_model_init }, + { "sh2e", & sh2e_mach, MODEL_SH5, NULL, sh64_model_init }, + { "sh2a", & sh2a_fpu_mach, MODEL_SH5, NULL, sh64_model_init }, + { "sh2a_nofpu", & sh2a_nofpu_mach, MODEL_SH5, NULL, sh64_model_init }, + { "sh3", & sh3_mach, MODEL_SH5, NULL, sh64_model_init }, + { "sh3e", & sh3_mach, MODEL_SH5, NULL, sh64_model_init }, + { "sh4", & sh4_mach, MODEL_SH5, NULL, sh64_model_init }, + { "sh4_nofpu", & sh4_nofpu_mach, MODEL_SH5, NULL, sh64_model_init }, + { "sh4a", & sh4a_mach, MODEL_SH5, NULL, sh64_model_init }, + { "sh4a_nofpu", & sh4a_nofpu_mach, MODEL_SH5, NULL, sh64_model_init }, + { "sh4al", & sh4al_mach, MODEL_SH5, NULL, sh64_model_init }, + { "sh5", & sh5_mach, MODEL_SH5, NULL, sh64_model_init }, { 0 } }; @@ -997,10 +1066,34 @@ const MACH sh2_mach = sh64_prepare_run }; +const MACH sh2e_mach = +{ + "sh2e", "sh2e", MACH_SH5, + 16, 16, &sh_models[1], &sh5_imp_properties, + shcompact_init_cpu, + sh64_prepare_run +}; + +const MACH sh2a_fpu_mach = +{ + "sh2a", "sh2a", MACH_SH5, + 16, 16, &sh_models[2], &sh5_imp_properties, + shcompact_init_cpu, + sh64_prepare_run +}; + +const MACH sh2a_nofpu_mach = +{ + "sh2a_nofpu", "sh2a_nofpu", MACH_SH5, + 16, 16, &sh_models[3], &sh5_imp_properties, + shcompact_init_cpu, + sh64_prepare_run +}; + const MACH sh3_mach = { "sh3", "sh3", MACH_SH5, - 16, 16, &sh_models[1], &sh5_imp_properties, + 16, 16, &sh_models[4], &sh5_imp_properties, shcompact_init_cpu, sh64_prepare_run }; @@ -1008,7 +1101,7 @@ const MACH sh3_mach = const MACH sh3e_mach = { "sh3e", "sh3e", MACH_SH5, - 16, 16, &sh_models[2], &sh5_imp_properties, + 16, 16, &sh_models[5], &sh5_imp_properties, shcompact_init_cpu, sh64_prepare_run }; @@ -1016,7 +1109,39 @@ const MACH sh3e_mach = const MACH sh4_mach = { "sh4", "sh4", MACH_SH5, - 16, 16, &sh_models[3], &sh5_imp_properties, + 16, 16, &sh_models[6], &sh5_imp_properties, + shcompact_init_cpu, + sh64_prepare_run +}; + +const MACH sh4_nofpu_mach = +{ + "sh4_nofpu", "sh4_nofpu", MACH_SH5, + 16, 16, &sh_models[7], &sh5_imp_properties, + shcompact_init_cpu, + sh64_prepare_run +}; + +const MACH sh4a_mach = +{ + "sh4a", "sh4a", MACH_SH5, + 16, 16, &sh_models[8], &sh5_imp_properties, + shcompact_init_cpu, + sh64_prepare_run +}; + +const MACH sh4a_nofpu_mach = +{ + "sh4a_nofpu", "sh4a_nofpu", MACH_SH5, + 16, 16, &sh_models[9], &sh5_imp_properties, + shcompact_init_cpu, + sh64_prepare_run +}; + +const MACH sh4al_mach = +{ + "sh4al", "sh4al", MACH_SH5, + 16, 16, &sh_models[10], &sh5_imp_properties, shcompact_init_cpu, sh64_prepare_run }; @@ -1024,7 +1149,7 @@ const MACH sh4_mach = const MACH sh5_mach = { "sh5", "sh5", MACH_SH5, - 32, 32, &sh_models[4], &sh5_imp_properties, + 32, 32, &sh_models[11], &sh5_imp_properties, shmedia_init_cpu, sh64_prepare_run }; |