diff options
30 files changed, 303 insertions, 37 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 92aac79..12bef8c 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,10 @@ +2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + + * elf32-arm.c (v8): New array. + (tag_cpu_arch_combine): Add support for ARMv8 attributes. + (elf32_arm_merge_eabi_attributes): Likewise. + (VFP_VERSION_COUNT): New define. + 2012-08-20 Tom Tromey <tromey@redhat.com> * vms-lib.c (_bfd_vms_lib_get_module): Use bfd_zmalloc for diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c index 4f2d00e..a287fbb 100644 --- a/bfd/elf32-arm.c +++ b/bfd/elf32-arm.c @@ -11327,6 +11327,24 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out, T(V7E_M), /* V6S_M. */ T(V7E_M) /* V7E_M. */ }; + const int v8[] = + { + T(V8), /* PRE_V4. */ + T(V8), /* V4. */ + T(V8), /* V4T. */ + T(V8), /* V5T. */ + T(V8), /* V5TE. */ + T(V8), /* V5TEJ. */ + T(V8), /* V6. */ + T(V8), /* V6KZ. */ + T(V8), /* V6T2. */ + T(V8), /* V6K. */ + T(V8), /* V7. */ + T(V8), /* V6_M. */ + T(V8), /* V6S_M. */ + T(V8), /* V7E_M. */ + T(V8) /* V8. */ + }; const int v4t_plus_v6_m[] = { -1, /* PRE_V4. */ @@ -11343,6 +11361,7 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out, T(V6_M), /* V6_M. */ T(V6S_M), /* V6S_M. */ T(V7E_M), /* V7E_M. */ + T(V8), /* V8. */ T(V4T_PLUS_V6_M) /* V4T plus V6_M. */ }; const int *comb[] = @@ -11353,6 +11372,7 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out, v6_m, v6s_m, v7e_m, + v8, /* Pseudo-architecture. */ v4t_plus_v6_m }; @@ -11554,7 +11574,8 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd) "ARM v6K", "ARM v7", "ARM v6-M", - "ARM v6S-M" + "ARM v6S-M", + "ARM v8" }; /* Merge Tag_CPU_arch and Tag_also_compatible_with. */ @@ -11699,11 +11720,12 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd) when it's 0. It might mean absence of FP hardware if Tag_FP_arch is zero, otherwise it is effectively SP + DP. */ +#define VFP_VERSION_COUNT 8 static const struct { int ver; int regs; - } vfp_versions[7] = + } vfp_versions[VFP_VERSION_COUNT] = { {0, 0}, {1, 16}, @@ -11711,7 +11733,8 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd) {3, 32}, {3, 16}, {4, 32}, - {4, 16} + {4, 16}, + {8, 32} }; int ver; int regs; @@ -11751,9 +11774,10 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd) /* Now we can handle Tag_FP_arch. */ - /* Values greater than 6 aren't defined, so just pick the - biggest */ - if (in_attr[i].i > 6 && in_attr[i].i > out_attr[i].i) + /* Values of VFP_VERSION_COUNT or more aren't defined, so just + pick the biggest. */ + if (in_attr[i].i >= VFP_VERSION_COUNT + && in_attr[i].i > out_attr[i].i) { out_attr[i] = in_attr[i]; break; @@ -11768,7 +11792,7 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd) regs = vfp_versions[out_attr[i].i].regs; /* This assumes all possible supersets are also a valid options. */ - for (newval = 6; newval > 0; newval--) + for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--) { if (regs == vfp_versions[newval].regs && ver == vfp_versions[newval].ver) diff --git a/binutils/ChangeLog b/binutils/ChangeLog index 65bb507..922396a 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,9 @@ +2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + + * readelf.c (arm_attr_tag_CPU_arch): Update for ARMv8. + (arm_attr_tag_FP_arch): Likewise. + (arm_attr_tag_Advanced_SIMD_arch): Likewise. + 2012-08-17 Yuri Chornoivan <yurchor@ukr.net> * doc/binutils.texi, * objdump.c, * od-xcoff.c: Typo fixes. diff --git a/binutils/readelf.c b/binutils/readelf.c index 5423c7f..89cff24 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -10868,15 +10868,16 @@ typedef struct static const char * arm_attr_tag_CPU_arch[] = {"Pre-v4", "v4", "v4T", "v5T", "v5TE", "v5TEJ", "v6", "v6KZ", "v6T2", - "v6K", "v7", "v6-M", "v6S-M", "v7E-M"}; + "v6K", "v7", "v6-M", "v6S-M", "v7E-M", "v8"}; static const char * arm_attr_tag_ARM_ISA_use[] = {"No", "Yes"}; static const char * arm_attr_tag_THUMB_ISA_use[] = {"No", "Thumb-1", "Thumb-2"}; static const char * arm_attr_tag_FP_arch[] = - {"No", "VFPv1", "VFPv2", "VFPv3", "VFPv3-D16", "VFPv4", "VFPv4-D16"}; + {"No", "VFPv1", "VFPv2", "VFPv3", "VFPv3-D16", "VFPv4", "VFPv4-D16", + "FP for ARMv8"}; static const char * arm_attr_tag_WMMX_arch[] = {"No", "WMMXv1", "WMMXv2"}; static const char * arm_attr_tag_Advanced_SIMD_arch[] = - {"No", "NEONv1", "NEONv1 with Fused-MAC"}; + {"No", "NEONv1", "NEONv1 with Fused-MAC", "NEON for ARMv8"}; static const char * arm_attr_tag_PCS_config[] = {"None", "Bare platform", "Linux application", "Linux DSO", "PalmOS 2004", "PalmOS (reserved)", "SymbianOS 2004", "SymbianOS (reserved)"}; diff --git a/gas/ChangeLog b/gas/ChangeLog index 53cd98e..0af7f05 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,17 @@ +2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + + * config/tc-arm.h (arm_ext_v8): New variable. + (fpu_vfp_ext_armv8): Likewise. + (fpu_neon_ext_armv8): Likewise. + (fpu_crypto_ext_armv8): Likewise. + (arm_archs): Add armv8-a. + (arm_extensions): Add crypto, fp, and simd. + (arm_fpus): Add fp-armv8, neon-fp-armv8, crypto-neon-fp-armv8. + (cpu_arch_ver): Add support for ARMv8. + (aeabi_set_public_sttributes): Likewise. + * doc/c-arm.texi (ARM Options): Document new architecture and + extension options for ARMv8. + 2012-08-20 H.J. Lu <hongjiu.lu@intel.com> * doc/as.texinfo: Replace --n32 with --x32. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 795a1b5..101f86b 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -195,6 +195,7 @@ static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); +static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0); static const arm_feature_set arm_ext_m = ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0); static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0); @@ -233,6 +234,12 @@ static const arm_feature_set fpu_vfp_v3_or_neon_ext = static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16); static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA); static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA); +static const arm_feature_set fpu_vfp_ext_armv8 = + ARM_FEATURE (0, FPU_VFP_EXT_ARMV8); +static const arm_feature_set fpu_neon_ext_armv8 = + ARM_FEATURE (0, FPU_NEON_EXT_ARMV8); +static const arm_feature_set fpu_crypto_ext_armv8 = + ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8); static int mfloat_abi_opt = -1; /* Record user cpu selection for object attributes. */ @@ -23188,6 +23195,7 @@ static const struct arm_arch_option_table arm_archs[] = ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP), ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP), ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP), + ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP), ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP), ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP), ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP), @@ -23209,6 +23217,10 @@ struct arm_option_extension_value_table #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA } static const struct arm_option_extension_value_table arm_extensions[] = { + ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, + ARM_FEATURE (ARM_EXT_V8, 0)), + ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, + ARM_FEATURE (ARM_EXT_V8, 0)), ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0), ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)), ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY), @@ -23218,6 +23230,8 @@ static const struct arm_option_extension_value_table arm_extensions[] = ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY), ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0), ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)), + ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8, + ARM_FEATURE (ARM_EXT_V8, 0)), ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0), ARM_FEATURE (ARM_EXT_V6M, 0)), ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0), @@ -23275,6 +23289,10 @@ static const struct arm_option_fpu_value_table arm_fpus[] = {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, + {"fp-armv8", FPU_ARCH_VFP_ARMV8}, + {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8}, + {"crypto-neon-fp-armv8", + FPU_ARCH_CRYPTO_NEON_VFP_ARMV8}, {NULL, ARM_ARCH_NONE} }; @@ -23749,9 +23767,10 @@ static const cpu_arch_ver_table cpu_arch_ver[] = {11, ARM_ARCH_V6M}, {12, ARM_ARCH_V6SM}, {8, ARM_ARCH_V6T2}, - {10, ARM_ARCH_V7A}, + {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT}, {10, ARM_ARCH_V7R}, {10, ARM_ARCH_V7M}, + {14, ARM_ARCH_V8A}, {0, ARM_ARCH_NONE} }; @@ -23781,6 +23800,7 @@ aeabi_set_public_attributes (void) int arch; char profile; int virt_sec = 0; + int fp16_optional = 0; arm_feature_set flags; arm_feature_set tmp; const cpu_arch_ver_table *p; @@ -23880,14 +23900,22 @@ aeabi_set_public_attributes (void) ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); /* Tag_VFP_arch. */ - if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) + if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8)) + aeabi_set_attribute_int (Tag_VFP_arch, 7); + else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) aeabi_set_attribute_int (Tag_VFP_arch, ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) ? 5 : 6); else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) - aeabi_set_attribute_int (Tag_VFP_arch, 3); + { + fp16_optional = 1; + aeabi_set_attribute_int (Tag_VFP_arch, 3); + } else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) - aeabi_set_attribute_int (Tag_VFP_arch, 4); + { + aeabi_set_attribute_int (Tag_VFP_arch, 4); + fp16_optional = 1; + } else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) aeabi_set_attribute_int (Tag_VFP_arch, 2); else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) @@ -23906,13 +23934,23 @@ aeabi_set_public_attributes (void) aeabi_set_attribute_int (Tag_WMMX_arch, 1); /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ - if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) - aeabi_set_attribute_int - (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma) - ? 2 : 1)); + if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8)) + aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3); + else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) + { + if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)) + { + aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2); + } + else + { + aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1); + fp16_optional = 1; + } + } /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ - if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16)) + if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional) aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); /* Tag_DIV_use. @@ -23921,12 +23959,17 @@ aeabi_set_public_attributes (void) in ARM state, or when Thumb integer divide instructions have been used, but we have no architecture profile set, nor have we any ARM instructions. + For ARMv8 we set the tag to 0 as integer divide is implied by the base + architecture. + For new architectures we will have to check these tests. */ - gas_assert (arch <= TAG_CPU_ARCH_V7E_M); - if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv) - || (profile == '\0' - && ARM_CPU_HAS_FEATURE (flags, arm_ext_div) - && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))) + gas_assert (arch <= TAG_CPU_ARCH_V8); + if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)) + aeabi_set_attribute_int (Tag_DIV_use, 0); + else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv) + || (profile == '\0' + && ARM_CPU_HAS_FEATURE (flags, arm_ext_div) + && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))) aeabi_set_attribute_int (Tag_DIV_use, 2); /* Tag_MP_extension_use. */ diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi index ae6c488..7d622ef 100644 --- a/gas/doc/c-arm.texi +++ b/gas/doc/c-arm.texi @@ -154,13 +154,16 @@ been added, again in ascending alphabetical order. For example, The following extensions are currently supported: -@code{idiv}, (Integer Divide Extensions for v7-A and v7-R architectures), +@code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}), +@code{fp} (Floating Point Extensions for v8-A architecture), +@code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures), @code{iwmmxt}, @code{iwmmxt2}, @code{maverick}, @code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures), @code{os} (Operating System for v6M architecture), @code{sec} (Security Extensions for v6K and v7-A architectures), +@code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}), @code{virt} (Virtualization Extensions for v7-A architecture, implies @code{idiv}), and @@ -199,6 +202,7 @@ names are recognized: @code{armv7-r}, @code{armv7-m}, @code{armv7e-m}, +@code{armv8-a}, @code{iwmmxt} and @code{xscale}. @@ -241,13 +245,16 @@ The following format options are recognized: @code{vfpv4}, @code{vfpv4-d16}, @code{fpv4-sp-d16}, +@code{fp-armv8}, @code{arm1020t}, @code{arm1020e}, @code{arm1136jf-s}, @code{maverick}, @code{neon}, +@code{neon-vfpv4}, +@code{neon-fp-armv8}, and -@code{neon-vfpv4}. +@code{crypto-neon-fp-armv8}. In addition to determining which instructions are assembled, this option also affects the way in which the @code{.double} assembler directive behaves diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 328cdb0..dd0254d 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,14 @@ +2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + + * gas/arm/attr-march-all.d: Update for change in expected + output. + * gas/arm/attr-mfpu-vfpv4-d16.d: Likewise. + * gas/arm/attr-mfpu-vfpv4.d: Likewise. + * gas/arm/attr-march-armv8-a+crypto.d: New testcase. + * gas/arm/attr-march-armv8-a+fp.d: Likewise. + * gas/arm/attr-march-armv8-a+simd.d: Likewise. + * gas/arm/attr-march-armv8-a.d: Likewise. + 2012-08-21 David S. Miller <davem@davemloft.net> * gas/sparc/crypto.d: Fix opcodes for 4-arg crypto instructions. diff --git a/gas/testsuite/gas/arm/attr-march-all.d b/gas/testsuite/gas/arm/attr-march-all.d index ed4d652..4a80d2f 100644 --- a/gas/testsuite/gas/arm/attr-march-all.d +++ b/gas/testsuite/gas/arm/attr-march-all.d @@ -8,10 +8,9 @@ Attribute Section: aeabi File Attributes Tag_CPU_name: "all" - Tag_CPU_arch: v7 + Tag_CPU_arch: v8 Tag_CPU_arch_profile: Application Tag_ARM_ISA_use: Yes Tag_THUMB_ISA_use: Thumb-2 Tag_MPextension_use: Allowed - Tag_DIV_use: Allowed in v7-A with integer division extension Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/gas/testsuite/gas/arm/attr-march-armv8-a+crypto.d b/gas/testsuite/gas/arm/attr-march-armv8-a+crypto.d new file mode 100644 index 0000000..f1d9cf4 --- /dev/null +++ b/gas/testsuite/gas/arm/attr-march-armv8-a+crypto.d @@ -0,0 +1,18 @@ +# name: attributes for -march=armv8-a+crypto +# source: blank.s +# as: -march=armv8-a+crypto +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8-A" + Tag_CPU_arch: v8 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_FP_arch: FP for ARMv8 + Tag_Advanced_SIMD_arch: NEON for ARMv8 + Tag_MPextension_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/gas/testsuite/gas/arm/attr-march-armv8-a+fp.d b/gas/testsuite/gas/arm/attr-march-armv8-a+fp.d new file mode 100644 index 0000000..54d472f --- /dev/null +++ b/gas/testsuite/gas/arm/attr-march-armv8-a+fp.d @@ -0,0 +1,17 @@ +# name: attributes for -march=armv8-a+fp +# source: blank.s +# as: -march=armv8-a+fp +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8-A" + Tag_CPU_arch: v8 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_FP_arch: FP for ARMv8 + Tag_MPextension_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/gas/testsuite/gas/arm/attr-march-armv8-a+simd.d b/gas/testsuite/gas/arm/attr-march-armv8-a+simd.d new file mode 100644 index 0000000..e8e6af9 --- /dev/null +++ b/gas/testsuite/gas/arm/attr-march-armv8-a+simd.d @@ -0,0 +1,18 @@ +# name: attributes for -march=armv8-a+simd +# source: blank.s +# as: -march=armv8-a+simd +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8-A" + Tag_CPU_arch: v8 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_FP_arch: FP for ARMv8 + Tag_Advanced_SIMD_arch: NEON for ARMv8 + Tag_MPextension_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/gas/testsuite/gas/arm/attr-march-armv8-a.d b/gas/testsuite/gas/arm/attr-march-armv8-a.d new file mode 100644 index 0000000..d02bc651 --- /dev/null +++ b/gas/testsuite/gas/arm/attr-march-armv8-a.d @@ -0,0 +1,16 @@ +# name: attributes for -march=armv8-a +# source: blank.s +# as: -march=armv8-a +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8-A" + Tag_CPU_arch: v8 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_MPextension_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/gas/testsuite/gas/arm/attr-mfpu-vfpv4-d16.d b/gas/testsuite/gas/arm/attr-mfpu-vfpv4-d16.d index 1b0e297..fd71a93 100644 --- a/gas/testsuite/gas/arm/attr-mfpu-vfpv4-d16.d +++ b/gas/testsuite/gas/arm/attr-mfpu-vfpv4-d16.d @@ -10,4 +10,3 @@ File Attributes Tag_ARM_ISA_use: Yes Tag_THUMB_ISA_use: Thumb-1 Tag_FP_arch: VFPv4-D16 - Tag_FP_HP_extension: Allowed diff --git a/gas/testsuite/gas/arm/attr-mfpu-vfpv4.d b/gas/testsuite/gas/arm/attr-mfpu-vfpv4.d index 1be3048..2a3edf7 100644 --- a/gas/testsuite/gas/arm/attr-mfpu-vfpv4.d +++ b/gas/testsuite/gas/arm/attr-mfpu-vfpv4.d @@ -10,4 +10,3 @@ File Attributes Tag_ARM_ISA_use: Yes Tag_THUMB_ISA_use: Thumb-1 Tag_FP_arch: VFPv4 - Tag_FP_HP_extension: Allowed diff --git a/include/ChangeLog b/include/ChangeLog index e8a01af..58ad5ae 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,23 @@ +2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + + * elf/arm.h (TAG_CPU_ARCH_V8): New define. + (MAX_TAG_CPU_ARCH): Update. + * opcode/arm.h (ARM_EXT_V8): New define. + (FPU_VFP_EXT_ARMV8): Likewise. + (FPU_NEON_EXT_ARMV8): Likewise. + (FPU_CRYPTO_EXT_ARMV8): Likewise. + (ARM_AEXT_V8A): Likewise. + (FPU_VFP_ARMV8): Likwise. + (FPU_NEON_ARMV8): Likewise. + (FPU_CRYPTO_ARMV8): Likewise. + (FPU_ARCH_VFP_ARMV8): Likewise. + (FPU_ARCH_NEON_VFP_ARMV8): Likewise. + (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8): Likewise. + (ARM_ARCH_V8A): Likwise. + (ARM_ARCH_V8A_FP): Likewise. + (ARM_ARCH_V8A_SIMD): Likewise. + (ARM_ARCH_V8A_CRYPTO): Likewise. + 2012-08-13 Ian Bolton <ian.bolton@arm.com> Laurent Desnogues <laurent.desnogues@arm.com> Jim MacArthur <jim.macarthur@arm.com> diff --git a/include/elf/arm.h b/include/elf/arm.h index 860fdf7..8ea3fe8 100644 --- a/include/elf/arm.h +++ b/include/elf/arm.h @@ -101,7 +101,8 @@ #define TAG_CPU_ARCH_V6_M 11 #define TAG_CPU_ARCH_V6S_M 12 #define TAG_CPU_ARCH_V7E_M 13 -#define MAX_TAG_CPU_ARCH 13 +#define TAG_CPU_ARCH_V8 14 +#define MAX_TAG_CPU_ARCH 14 /* Pseudo-architecture to allow objects to be compatible with the subset of armv4t and armv6-m. This value should never be stored in object files. */ #define TAG_CPU_ARCH_V4T_PLUS_V6_M (MAX_TAG_CPU_ARCH + 1) diff --git a/include/opcode/arm.h b/include/opcode/arm.h index 86e3d67..1c350c8 100644 --- a/include/opcode/arm.h +++ b/include/opcode/arm.h @@ -34,6 +34,7 @@ #define ARM_EXT_V6 0x00001000 /* ARM V6. */ #define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ /* 0x00004000 Was ARM V6Z. */ +#define ARM_EXT_V8 0x00004000 /* is now ARMv8. */ #define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ #define ARM_EXT_DIV 0x00010000 /* Integer division. */ /* The 'M' in Arm V7M stands for Microcontroller. @@ -77,6 +78,9 @@ #define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */ #define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */ #define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */ +#define FPU_VFP_EXT_ARMV8 0x00020000 /* FP for ARMv8. */ +#define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */ +#define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */ /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, @@ -126,6 +130,9 @@ #define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M) #define ARM_AEXT_V7EM \ (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP) +#define ARM_AEXT_V8A \ + (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \ + | ARM_EXT_VIRT | ARM_EXT_V8) /* Processors with specific extensions in the co-processor space. */ #define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) @@ -143,6 +150,9 @@ #define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) #define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) #define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) +#define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8) +#define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8) +#define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8) #define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \ | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32) @@ -175,6 +185,10 @@ #define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16) #define FPU_ARCH_NEON_VFP_V4 \ ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) +#define FPU_ARCH_VFP_ARMV8 ARM_FEATURE(0, FPU_VFP_ARMV8) +#define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE(0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8) +#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \ + ARM_FEATURE(0, FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE) @@ -211,6 +225,7 @@ #define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0) #define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0) #define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0) +#define ARM_ARCH_V8A ARM_FEATURE (ARM_AEXT_V8A, 0) /* Some useful combinations: */ #define ARM_ARCH_NONE ARM_FEATURE (0, 0) @@ -233,6 +248,14 @@ #define ARM_ARCH_V7R_IDIV ARM_FEATURE (ARM_AEXT_V7R | ARM_EXT_ADIV, 0) /* Features that are present in v6M and v6S-M but not other v6 cores. */ #define ARM_ARCH_V6M_ONLY ARM_FEATURE (ARM_AEXT_V6M_ONLY, 0) +/* v8-a+fp. */ +#define ARM_ARCH_V8A_FP ARM_FEATURE (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8) +/* v8-a+simd (implies fp). */ +#define ARM_ARCH_V8A_SIMD ARM_FEATURE (ARM_AEXT_V8A, \ + FPU_ARCH_NEON_VFP_ARMV8) +/* v8-a+crypto (implies simd+fp). */ +#define ARM_ARCH_V8A_CRYPTOV1 ARM_FEATURE (ARM_AEXT_V8A, \ + FPU_ARCH_CRYPTO_NEON_VFP_ARMV8) /* There are too many feature bits to fit in a single word, so use a structure. For simplicity we put all core features in one word and diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index 28c978c..cb94d3c 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,18 @@ +2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + + * ld-arm/arm-elf.exp: Add new testcases. + * ld-arm/attr-merge-vfp-3.d: Update for change in expected + output. + * ld-arm/attr-merge-vfp-3r.d: Likewise. + * ld-arm/attr-merge-vfp-4.d: Likewise. + * ld-arm/attr-merge-vfp-4r.d: Likewise. + * ld-arm/attr-merge-vfp-5.d: Likewise. + * ld-arm/attr-merge-vfp-5r.d: Likewise. + * ld-arm/attr-merge-vfp-7.d: New testcase. + * ld-arm/attr-merge-vfp-7r.d: Likewise. + * ld-arm/attr-merge-vfp-armv8-hard.s: Likewise. + * ld-arm/attr-merge-vfp-armv8.s: Likewise. + 2012-08-14 Nick Clifton <nickc@redhat.com> PR ld/14265 diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp index 3f2bf92..8e15ffe 100644 --- a/ld/testsuite/ld-arm/arm-elf.exp +++ b/ld/testsuite/ld-arm/arm-elf.exp @@ -767,6 +767,8 @@ run_dump_test "attr-merge-vfp-5" run_dump_test "attr-merge-vfp-5r" run_dump_test "attr-merge-vfp-6" run_dump_test "attr-merge-vfp-6r" +run_dump_test "attr-merge-vfp-7" +run_dump_test "attr-merge-vfp-7r" run_dump_test "attr-merge-incompatible" run_dump_test "unresolved-1" if { ![istarget "arm*-*-nacl*"] } { diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-3.d b/ld/testsuite/ld-arm/attr-merge-vfp-3.d index ee89384..8f9d2e7 100644 --- a/ld/testsuite/ld-arm/attr-merge-vfp-3.d +++ b/ld/testsuite/ld-arm/attr-merge-vfp-3.d @@ -11,4 +11,3 @@ File Attributes Tag_ARM_ISA_use: Yes Tag_THUMB_ISA_use: Thumb-1 Tag_FP_arch: VFPv4-D16 - Tag_FP_HP_extension: Allowed diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-3r.d b/ld/testsuite/ld-arm/attr-merge-vfp-3r.d index d06bd27..ab0ff33 100644 --- a/ld/testsuite/ld-arm/attr-merge-vfp-3r.d +++ b/ld/testsuite/ld-arm/attr-merge-vfp-3r.d @@ -11,4 +11,3 @@ File Attributes Tag_ARM_ISA_use: Yes Tag_THUMB_ISA_use: Thumb-1 Tag_FP_arch: VFPv4-D16 - Tag_FP_HP_extension: Allowed diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-4.d b/ld/testsuite/ld-arm/attr-merge-vfp-4.d index c18d672..e51a41b 100644 --- a/ld/testsuite/ld-arm/attr-merge-vfp-4.d +++ b/ld/testsuite/ld-arm/attr-merge-vfp-4.d @@ -11,4 +11,3 @@ File Attributes Tag_ARM_ISA_use: Yes Tag_THUMB_ISA_use: Thumb-1 Tag_FP_arch: VFPv4 - Tag_FP_HP_extension: Allowed diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-4r.d b/ld/testsuite/ld-arm/attr-merge-vfp-4r.d index 327e0c3..6d19a60 100644 --- a/ld/testsuite/ld-arm/attr-merge-vfp-4r.d +++ b/ld/testsuite/ld-arm/attr-merge-vfp-4r.d @@ -11,4 +11,3 @@ File Attributes Tag_ARM_ISA_use: Yes Tag_THUMB_ISA_use: Thumb-1 Tag_FP_arch: VFPv4 - Tag_FP_HP_extension: Allowed diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-5.d b/ld/testsuite/ld-arm/attr-merge-vfp-5.d index cd55a86..650b264 100644 --- a/ld/testsuite/ld-arm/attr-merge-vfp-5.d +++ b/ld/testsuite/ld-arm/attr-merge-vfp-5.d @@ -11,4 +11,3 @@ File Attributes Tag_ARM_ISA_use: Yes Tag_THUMB_ISA_use: Thumb-1 Tag_FP_arch: VFPv4 - Tag_FP_HP_extension: Allowed diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-5r.d b/ld/testsuite/ld-arm/attr-merge-vfp-5r.d index 505c31b..f5fb7d7 100644 --- a/ld/testsuite/ld-arm/attr-merge-vfp-5r.d +++ b/ld/testsuite/ld-arm/attr-merge-vfp-5r.d @@ -11,4 +11,3 @@ File Attributes Tag_ARM_ISA_use: Yes Tag_THUMB_ISA_use: Thumb-1 Tag_FP_arch: VFPv4 - Tag_FP_HP_extension: Allowed diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-7.d b/ld/testsuite/ld-arm/attr-merge-vfp-7.d new file mode 100644 index 0000000..6b1f9c9 --- /dev/null +++ b/ld/testsuite/ld-arm/attr-merge-vfp-7.d @@ -0,0 +1,14 @@ +#source: attr-merge-vfp-armv8.s +#source: attr-merge-vfp-armv8-hard.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: FP for ARMv8 + Tag_ABI_HardFP_use: SP and DP diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-7r.d b/ld/testsuite/ld-arm/attr-merge-vfp-7r.d new file mode 100644 index 0000000..6b1f9c9 --- /dev/null +++ b/ld/testsuite/ld-arm/attr-merge-vfp-7r.d @@ -0,0 +1,14 @@ +#source: attr-merge-vfp-armv8.s +#source: attr-merge-vfp-armv8-hard.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: FP for ARMv8 + Tag_ABI_HardFP_use: SP and DP diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-armv8-hard.s b/ld/testsuite/ld-arm/attr-merge-vfp-armv8-hard.s new file mode 100644 index 0000000..6457974 --- /dev/null +++ b/ld/testsuite/ld-arm/attr-merge-vfp-armv8-hard.s @@ -0,0 +1,2 @@ +.fpu fp-armv8 +.eabi_attribute Tag_ABI_HardFP_use, 3 diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-armv8.s b/ld/testsuite/ld-arm/attr-merge-vfp-armv8.s new file mode 100644 index 0000000..a7679cd --- /dev/null +++ b/ld/testsuite/ld-arm/attr-merge-vfp-armv8.s @@ -0,0 +1,2 @@ +.fpu fp-armv8 + |