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-rw-r--r--sim/testsuite/sim/bfin/ChangeLog4
-rw-r--r--sim/testsuite/sim/bfin/se_all32bitopcodes.S15
2 files changed, 18 insertions, 1 deletions
diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog
index 11a3072..81cedaf 100644
--- a/sim/testsuite/sim/bfin/ChangeLog
+++ b/sim/testsuite/sim/bfin/ChangeLog
@@ -1,5 +1,9 @@
2013-06-23 Mike Frysinger <vapier@gentoo.org>
+ * se_all32bitopcodes.S (se_all_next_insn): Skip debug insn opcodes.
+
+2013-06-23 Mike Frysinger <vapier@gentoo.org>
+
* se_allopcodes.h (_match): Simplify register test to one less insn.
Omit the SSYNC insn when compiling for the sim.
diff --git a/sim/testsuite/sim/bfin/se_all32bitopcodes.S b/sim/testsuite/sim/bfin/se_all32bitopcodes.S
index f8664e6..6ffe6d1 100644
--- a/sim/testsuite/sim/bfin/se_all32bitopcodes.S
+++ b/sim/testsuite/sim/bfin/se_all32bitopcodes.S
@@ -64,6 +64,19 @@
R0 = R0 + R1;
1:
+.ifndef BFIN_JTAG
+ /* Skip debug insns when running in the sim. */
+ R1.L = 0xff00;
+ R1.H = 0x0000;
+ R2 = R0 & R1;
+ R1.L = 0xf000;
+ CC = R1 == R2;
+ IF !CC jump 1f (bp);
+ R0.L = 0xf100;
+ R0.H = 0x0000;
+1:
+.endif
+
[P5] = R0;
.endm
@@ -34164,7 +34177,7 @@
.dw 0x0000, 0xe5c0, 0xffff, 0xe5ff, 0x21, 0
.dw 0x0000, 0xe6c0, 0xffff, 0xe6ff, 0x21, 0
.dw 0x0000, 0xe740, 0xffff, 0xe7ff, 0x21, 0
- .dw 0x0000, 0xf001, 0xffff, 0xffff, 0x21, 0
+ .dw 0x0000, 0xf001, 0xffff, 0xffff, 0x21, 0
.dw 0x0000, 0x0000, 0x0000, 0x0000, 0x00, 0
.endm