diff options
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/config/tc-i860.c | 8 | ||||
| -rw-r--r-- | gas/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/i860/README.i860 | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/i860/dual02-err.l | 2 |
5 files changed, 22 insertions, 4 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 7bf5fcd..8e1356c 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2003-08-06 Jason Eckhardt <jle@rice.edu> + + * config/tc-i860.c (i860_process_insn): Check that instructions + with their dual-bit set are 8-byte aligned. + 2003-08-06 Nick Clifton <nickc@redhat.com> * po/fr.po: Updated French translation. diff --git a/gas/config/tc-i860.c b/gas/config/tc-i860.c index 37aff49..d170b70 100644 --- a/gas/config/tc-i860.c +++ b/gas/config/tc-i860.c @@ -933,7 +933,13 @@ i860_process_insn (char *str) { if ((opcode & 0xfc000000) == 0x48000000 || opcode == 0xb0000000) { - opcode |= (1 << 9); + /* The instruction is a flop or a fnop, so set its dual bit + (but check that it is 8-byte aligned). */ + if (((frag_now->fr_address + frag_now_fix_octets ()) & 7) == 0) + opcode |= (1 << 9); + else + as_bad (_("'d.%s' must be 8-byte aligned"), insn->name); + if (dual_mode == DUAL_DDOT) dual_mode = DUAL_OFF; else if (dual_mode == DUAL_ONDDOT) diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 3176e6f..30591b7 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2003-08-06 Jason Eckhardt <jle@rice.edu> + + * gas/i860/dual02-err.l: Update expected error message. + * gas/i860/README.i860: Remove dual02-err from known failure list. + 2003-08-05 Jason Eckhardt <jle@rice.edu> * gas/i860/README.i860: Remove dual01 from the known failures. diff --git a/gas/testsuite/gas/i860/README.i860 b/gas/testsuite/gas/i860/README.i860 index e7b0744..ae5c890 100644 --- a/gas/testsuite/gas/i860/README.i860 +++ b/gas/testsuite/gas/i860/README.i860 @@ -25,10 +25,12 @@ TODO: tests of the Intel syntax should be added to prevent bitrot (including relocatable expression syntax, etc). Test file dual03.s uses Intel syntax lightly (i.e., register names without '%' prefix). + - Currently, .align in a .text section fills with 0x00000000. This is + a defect and it needs to fill with nop (0xa0000000). Write a testcase + for it. Contact me (Jason Eckhardt, jle@rice.edu) if you'd like to help. Known testsuite failures: - - dual02-err.s: GAS currently doesn't check that dual mode pairs - are properly aligned. + - none. diff --git a/gas/testsuite/gas/i860/dual02-err.l b/gas/testsuite/gas/i860/dual02-err.l index f8f1a1d..d43d73e 100644 --- a/gas/testsuite/gas/i860/dual02-err.l +++ b/gas/testsuite/gas/i860/dual02-err.l @@ -1,2 +1,2 @@ .*: Assembler messages: -.*:7: Error: FLOP with 'd\.' prefix must be 8-byte aligned +.*:7: Error: 'd\.fadd\.ss' must be 8-byte aligned |