diff options
| -rw-r--r-- | gas/ChangeLog | 71 | ||||
| -rw-r--r-- | gas/config/tc-nios2.c | 1513 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 18 | ||||
| -rw-r--r-- | include/opcode/nios2.h | 79 | ||||
| -rw-r--r-- | include/opcode/nios2r2.h | 1081 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 22 | ||||
| -rw-r--r-- | opcodes/nios2-dis.c | 550 | ||||
| -rw-r--r-- | opcodes/nios2-opc.c | 436 |
8 files changed, 3603 insertions, 167 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 470cd9f..b18637f 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,6 +1,77 @@ 2015-07-01 Sandra Loosemore <sandra@codesourcery.com> Cesar Philippidis <cesar@codesourcery.com> + * config/tc-nios2.c (nios2_min_align): New. + (nop): Replace with.... + (nop_r1, nop_r2, nop_r2_cdx, nop32, nop16): New. + (nios2_align): Handle alignment on 2-byte boundaries when CDX + instructions may be present. + (s_nios2_align): Adjust reference to nop. + (CDXBRANCH, IS_CDXBRANCH): New. + (CDX_UBRANCH_SUBTYPE, CDX_CBRANCH_SUBTYPE): New. + (nios2_relax_subtype_size): Handle 2-byte CDX branches. + (nios2_relax_frag): Likewise. + (md_convert_frag): Handle R2 encodings. + (nios2_check_overflow): Check that low-order bits are zero + before applying rightshift from howto. + (nios2_check_overflow): Correct negative overflow calculation. + (nios2_diagnose_overflow): Handle signed_immed12_overflow. Issue + generic overflow messages for miscellaneous instruction formats. + (md_apply_fix): Recognize new R2 relocations. For pc_relative + relocations, store fixup in *valP. + (nios2_reglist_mask, nios2_reglist_dir): New. + (nios2_parse_reglist): New. + (nios2_parse_base_register): New. + (nios2_assemble_expression): Handle constant expressions designated + by BFD_RELOC_NONE. + (nios2_assemble_reg3): New. + (nios2_assemble_arg_c): Handle R2 instruction formats. + (nios2_assemble_arg_d): Likewise. + (nios2_assemble_arg_s): Likewise. + (nios2_assemble_arg_t): Likewise. + (nios2_assemble_arg_D): New. + (nios2_assemble_arg_S): New. + (nios2_assemble_arg_T): New. + (nios2_assemble_arg_i): Handle R2 instruction formats. + (nios2_assemble_arg_I): New. + (nios2_assemble_arg_u): Handle R2 instruction formats. + (nios2_assemble_arg_U): New. + (nios2_assemble_arg_V): New. + (nios2_assemble_arg_W): New. + (nios2_assemble_arg_X): New. + (nios2_assemble_arg_Y): New. + (nios2_assemble_arg_o): Handle R2 instruction formats. + (nios2_assemble_arg_O): New. + (nios2_assemble_arg_P): New. + (nios2_assemble_arg_j): Handle R2 instruction formats. + (nios2_assemble_arg_k): New. + (nios2_assemble_arg_l): Handle R2 instruction formats. + (nios2_assemble_arg_m): Likewise. + (nios2_assemble_arg_M): New. + (nios2_assemble_arg_N): New. + (nios2_assemble_arg_e): New. + (nios2_assemble_arg_f): New. + (nios2_assemble_arg_g): New. + (nios2_assemble_arg_h): New. + (nios2_assemble_arg_R): New. + (nios2_assemble_arg_B): New. + (nios2_assemble_args): Handle new argument letters. + (nios2_consume_arg): Likewise. + (nios2_translate_pseudo_insn): Avoid dereferencing null pointer + in error message. + (nios2_ps_insn_info_structs): Add nop.n. + (output_ubranch): Handle CDX branches. + (output_cbranch): Likewise. + (output_call): Handle R2 encodings. + (output_movia): Likewise. + (md_begin): Initialize nios2_min_align. + (md_assemble): Align to nios2_min_align. Adjust nios2_min_align + if a 16-bit instruction is seen. + (nios2_cons_align): Use appropriate nop pattern. + +2015-07-01 Sandra Loosemore <sandra@codesourcery.com> + Cesar Philippidis <cesar@codesourcery.com> + * config/tc-nios2.c: Adjust includes. (OPTION_MARCH): Define. (md_longopts): Add -march option. diff --git a/gas/config/tc-nios2.c b/gas/config/tc-nios2.c index 549ca98..4488a47 100644 --- a/gas/config/tc-nios2.c +++ b/gas/config/tc-nios2.c @@ -210,6 +210,11 @@ static int nios2_auto_align_on = 1; labels preceeding instructions. */ static symbolS *nios2_last_label; +/* If we saw a 16-bit CDX instruction, we can align on 2-byte boundaries + instead of 4-bytes. Use this to keep track of the minimum power-of-2 + alignment. */ +static int nios2_min_align = 2; + #ifdef OBJ_ELF /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ symbolS *GOT_symbol; @@ -322,8 +327,12 @@ nios2_special_relocation_p (const char *str) } -/* nop fill pattern for text section. */ -static char const nop[4] = { 0x3a, 0x88, 0x01, 0x00 }; +/* nop fill patterns for text section. */ +static char const nop_r1[4] = { 0x3a, 0x88, 0x01, 0x00 }; +static char const nop_r2[4] = { 0x20, 0x00, 0x00, 0xc4 }; +static char const nop_r2_cdx[2] = { 0x3b, 0x00 }; +static char const *nop32 = nop_r1; +static char const *nop16 = NULL; /* Handles all machine-dependent alignment needs. */ static void @@ -350,16 +359,26 @@ nios2_align (int log_size, const char *pfill, symbolS *label) if (align != 0) { - if (subseg_text_p (now_seg) && align >= 2) + if (subseg_text_p (now_seg) && align >= nios2_min_align) { - /* First, make sure we're on a four-byte boundary, in case + /* First, make sure we're on the minimum boundary, in case someone has been putting .byte values the text section. */ - if (nios2_current_align < 2 || switched_seg_p) - frag_align (2, 0, 0); + if (nios2_current_align < nios2_min_align || switched_seg_p) + frag_align (nios2_min_align, 0, 0); + + /* If we might be on a 2-byte boundary, first align to a + 4-byte boundary using the 2-byte nop as fill. */ + if (nios2_min_align == 1 + && align > nios2_min_align + && pfill == nop32 ) + { + gas_assert (nop16); + frag_align_pattern (2, nop16, 2, 0); + } /* Now fill in the alignment pattern. */ if (pfill != NULL) - frag_align_pattern (align, pfill, sizeof nop, 0); + frag_align_pattern (align, pfill, 4, 0); else frag_align (align, 0, 0); } @@ -470,7 +489,7 @@ s_nios2_align (int ignore ATTRIBUTE_UNUSED) pfill = (const char *) &fill; } else if (subseg_text_p (now_seg)) - pfill = (const char *) &nop; + pfill = (const char *) nop32; else { pfill = NULL; @@ -669,6 +688,11 @@ const pseudo_typeS md_pseudo_table[] = { jmp at skip: respectively. + + 16-bit CDX branch instructions are relaxed first into equivalent + 32-bit branches and then the above transformations are applied + if necessary. + */ /* Arbitrarily limit the number of addis we can insert; we need to be able @@ -685,7 +709,7 @@ const pseudo_typeS md_pseudo_table[] = { /* The fr_subtype field represents the target-specific relocation state. It has type relax_substateT (unsigned int). We use it to track the number of addis necessary, plus a bit to track whether this is a - conditional branch. + conditional branch and a bit for 16-bit CDX instructions. Regardless of the smaller RELAX_MAX_ADDI limit, we reserve 16 bits in the fr_subtype to encode the number of addis so that the whole theoretically-valid range is representable. @@ -693,10 +717,14 @@ const pseudo_typeS md_pseudo_table[] = { represents a branch that needs to be relaxed. */ #define UBRANCH (0 << 16) #define CBRANCH (1 << 16) +#define CDXBRANCH (1 << 17) #define IS_CBRANCH(SUBTYPE) ((SUBTYPE) & CBRANCH) #define IS_UBRANCH(SUBTYPE) (!IS_CBRANCH (SUBTYPE)) +#define IS_CDXBRANCH(SUBTYPE) ((SUBTYPE) & CDXBRANCH) #define UBRANCH_SUBTYPE(N) (UBRANCH | (N)) #define CBRANCH_SUBTYPE(N) (CBRANCH | (N)) +#define CDX_UBRANCH_SUBTYPE(N) (CDXBRANCH | UBRANCH | (N)) +#define CDX_CBRANCH_SUBTYPE(N) (CDXBRANCH | CBRANCH | (N)) #define SUBTYPE_ADDIS(SUBTYPE) ((SUBTYPE) & 0xffff) /* For the -relax-section mode, unconditional branches require 2 extra i @@ -730,7 +758,7 @@ nios2_relax_subtype_size (relax_substateT subtype) int n = SUBTYPE_ADDIS (subtype); if (n == 0) /* Regular conditional/unconditional branch instruction. */ - return 4; + return (IS_CDXBRANCH (subtype) ? 2 : 4); else if (nios2_as_options.relax == relax_all) return (IS_CBRANCH (subtype) ? CBRANCH_JUMP_SIZE : UBRANCH_JUMP_SIZE); else if (IS_CBRANCH (subtype)) @@ -761,6 +789,7 @@ nios2_relax_frag (segT segment, fragS *fragp, long stretch) fragS *sym_frag = symbol_get_frag (symbolp); offsetT offset; int n; + bfd_boolean is_cdx = FALSE; target += S_GET_VALUE (symbolp); @@ -777,7 +806,15 @@ nios2_relax_frag (segT segment, fragS *fragp, long stretch) /* We subtract fr_var (4 for 32-bit insns) because all pc relative branches are from the next instruction. */ offset = target - fragp->fr_address - fragp->fr_fix - fragp->fr_var; - if (offset >= -32768 && offset <= 32764) + if (IS_CDXBRANCH (subtype) && IS_UBRANCH (subtype) + && offset >= -1024 && offset < 1024) + /* PC-relative CDX branch with 11-bit offset. */ + is_cdx = TRUE; + else if (IS_CDXBRANCH (subtype) && IS_CBRANCH (subtype) + && offset >= -128 && offset < 128) + /* PC-relative CDX branch with 8-bit offset. */ + is_cdx = TRUE; + else if (offset >= -32768 && offset < 32768) /* Fits in PC-relative branch. */ n = 0; else if (nios2_as_options.relax == relax_all) @@ -816,7 +853,9 @@ nios2_relax_frag (segT segment, fragS *fragp, long stretch) /* We cannot handle this case, diagnose overflow later. */ return 0; - if (IS_CBRANCH (subtype)) + if (is_cdx) + fragp->fr_subtype = subtype; + else if (IS_CBRANCH (subtype)) fragp->fr_subtype = CBRANCH_SUBTYPE (n); else fragp->fr_subtype = UBRANCH_SUBTYPE (n); @@ -841,16 +880,50 @@ md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED, addressT target = fragp->fr_offset; symbolS *symbolp = fragp->fr_symbol; offsetT offset; - unsigned int addend_mask, addi_mask; + unsigned int addend_mask, addi_mask, op; offsetT addend, remainder; int i; + bfd_boolean is_r2 = (bfd_get_mach (stdoutput) == bfd_mach_nios2r2); + + /* If this is a CDX branch we're not relaxing, just generate the fixup. */ + if (IS_CDXBRANCH (subtype)) + { + gas_assert (is_r2); + fix_new (fragp, fragp->fr_fix, 2, fragp->fr_symbol, + fragp->fr_offset, 1, + (IS_UBRANCH (subtype) + ? BFD_RELOC_NIOS2_R2_I10_1_PCREL + : BFD_RELOC_NIOS2_R2_T1I7_1_PCREL)); + fragp->fr_fix += 2; + return; + } + + /* If this is a CDX branch we are relaxing, turn it into an equivalent + 32-bit branch and then fall through to the normal non-CDX cases. */ + if (fragp->fr_var == 2) + { + unsigned int opcode = md_chars_to_number (buffer, 2); + gas_assert (is_r2); + if (IS_CBRANCH (subtype)) + { + unsigned int reg = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (opcode)]; + if (GET_IW_R2_OP (opcode) == R2_OP_BNEZ_N) + opcode = MATCH_R2_BNE | SET_IW_F2I16_A (reg); + else + opcode = MATCH_R2_BEQ | SET_IW_F2I16_A (reg); + } + else + opcode = MATCH_R2_BR; + md_number_to_chars (buffer, opcode, 4); + fragp->fr_var = 4; + } /* If we didn't or can't relax, this is a regular branch instruction. We just need to generate the fixup for the symbol and offset. */ if (n == 0) { - fix_new (fragp, fragp->fr_fix, 4, fragp->fr_symbol, fragp->fr_offset, 1, - BFD_RELOC_16_PCREL); + fix_new (fragp, fragp->fr_fix, 4, fragp->fr_symbol, + fragp->fr_offset, 1, BFD_RELOC_16_PCREL); fragp->fr_fix += 4; return; } @@ -871,35 +944,66 @@ md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED, nbytes = 12; br_opcode = md_chars_to_number (buffer, 4); - old_op = GET_IW_R1_OP (br_opcode); - switch (old_op) + if (is_r2) { - case R1_OP_BEQ: - new_op = R1_OP_BNE; - break; - case R1_OP_BNE: - new_op = R1_OP_BEQ; - break; - case R1_OP_BGE: - new_op = R1_OP_BLT; - break; - case R1_OP_BGEU: - new_op = R1_OP_BLTU; - break; - case R1_OP_BLT: - new_op = R1_OP_BGE; - break; - case R1_OP_BLTU: - new_op = R1_OP_BGEU; - break; - default: - as_bad_where (fragp->fr_file, fragp->fr_line, - _("expecting conditional branch for relaxation\n")); - abort (); + old_op = GET_IW_R2_OP (br_opcode); + switch (old_op) + { + case R2_OP_BEQ: + new_op = R2_OP_BNE; + break; + case R2_OP_BNE: + new_op = R2_OP_BEQ; + break; + case R2_OP_BGE: + new_op = R2_OP_BLT; + break; + case R2_OP_BGEU: + new_op = R2_OP_BLTU; + break; + case R2_OP_BLT: + new_op = R2_OP_BGE; + break; + case R2_OP_BLTU: + new_op = R2_OP_BGEU; + break; + default: + abort (); + } + br_opcode = ((br_opcode & ~IW_R2_OP_SHIFTED_MASK) + | SET_IW_R2_OP (new_op)); + br_opcode = br_opcode | SET_IW_F2I16_IMM16 (nbytes); + } + else + { + old_op = GET_IW_R1_OP (br_opcode); + switch (old_op) + { + case R1_OP_BEQ: + new_op = R1_OP_BNE; + break; + case R1_OP_BNE: + new_op = R1_OP_BEQ; + break; + case R1_OP_BGE: + new_op = R1_OP_BLT; + break; + case R1_OP_BGEU: + new_op = R1_OP_BLTU; + break; + case R1_OP_BLT: + new_op = R1_OP_BGE; + break; + case R1_OP_BLTU: + new_op = R1_OP_BGEU; + break; + default: + abort (); + } + br_opcode = ((br_opcode & ~IW_R1_OP_SHIFTED_MASK) + | SET_IW_R1_OP (new_op)); + br_opcode = br_opcode | SET_IW_I_IMM16 (nbytes); } - - br_opcode = (br_opcode & ~IW_R1_OP_SHIFTED_MASK) | SET_IW_R1_OP (new_op); - br_opcode = br_opcode | SET_IW_I_IMM16 (nbytes); md_number_to_chars (buffer, br_opcode, 4); fragp->fr_fix += 4; buffer += 4; @@ -909,8 +1013,11 @@ md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED, if (nios2_as_options.relax == relax_section) { /* Insert the nextpc instruction. */ - md_number_to_chars (buffer, - MATCH_R1_NEXTPC | SET_IW_R_C (AT_REGNUM), 4); + if (is_r2) + op = MATCH_R2_NEXTPC | SET_IW_F3X6L5_C (AT_REGNUM); + else + op = MATCH_R1_NEXTPC | SET_IW_R_C (AT_REGNUM); + md_number_to_chars (buffer, op, 4); fragp->fr_fix += 4; buffer += 4; @@ -921,12 +1028,20 @@ md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED, addend = 32767; else addend = -32768; - addend_mask = SET_IW_I_IMM16 ((unsigned int)addend); + if (is_r2) + addend_mask = SET_IW_F2I16_IMM16 ((unsigned int)addend); + else + addend_mask = SET_IW_I_IMM16 ((unsigned int)addend); /* Insert n-1 addi instructions. */ - addi_mask = (MATCH_R1_ADDI - | SET_IW_I_B (AT_REGNUM) - | SET_IW_I_A (AT_REGNUM)); + if (is_r2) + addi_mask = (MATCH_R2_ADDI + | SET_IW_F2I16_B (AT_REGNUM) + | SET_IW_F2I16_A (AT_REGNUM)); + else + addi_mask = (MATCH_R1_ADDI + | SET_IW_I_B (AT_REGNUM) + | SET_IW_I_A (AT_REGNUM)); for (i = 0; i < n - 1; i ++) { md_number_to_chars (buffer, addi_mask | addend_mask, 4); @@ -937,7 +1052,10 @@ md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED, /* Insert the last addi instruction to hold the remainder. */ remainder = offset - addend * (n - 1); gas_assert (remainder >= -32768 && remainder <= 32767); - addend_mask = SET_IW_I_IMM16 ((unsigned int)remainder); + if (is_r2) + addend_mask = SET_IW_F2I16_IMM16 ((unsigned int)remainder); + else + addend_mask = SET_IW_I_IMM16 ((unsigned int)remainder); md_number_to_chars (buffer, addi_mask | addend_mask, 4); fragp->fr_fix += 4; buffer += 4; @@ -946,18 +1064,22 @@ md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED, /* Load at for the absolute case. */ else { - md_number_to_chars (buffer, - (MATCH_R1_ORHI | SET_IW_I_B (AT_REGNUM) - | SET_IW_I_A (0)), - 4); + if (is_r2) + op = MATCH_R2_ORHI | SET_IW_F2I16_B (AT_REGNUM) | SET_IW_F2I16_A (0); + else + op = MATCH_R1_ORHI | SET_IW_I_B (AT_REGNUM) | SET_IW_I_A (0); + md_number_to_chars (buffer, op, 4); fix_new (fragp, fragp->fr_fix, 4, fragp->fr_symbol, fragp->fr_offset, 0, BFD_RELOC_NIOS2_HI16); fragp->fr_fix += 4; buffer += 4; - md_number_to_chars (buffer, - (MATCH_R1_ORI | SET_IW_I_B (AT_REGNUM) - | SET_IW_I_A (AT_REGNUM)), - 4); + if (is_r2) + op = (MATCH_R2_ORI | SET_IW_F2I16_B (AT_REGNUM) + | SET_IW_F2I16_A (AT_REGNUM)); + else + op = (MATCH_R1_ORI | SET_IW_I_B (AT_REGNUM) + | SET_IW_I_A (AT_REGNUM)); + md_number_to_chars (buffer, op, 4); fix_new (fragp, fragp->fr_fix, 4, fragp->fr_symbol, fragp->fr_offset, 0, BFD_RELOC_NIOS2_LO16); fragp->fr_fix += 4; @@ -965,7 +1087,11 @@ md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED, } /* Insert the jmp instruction. */ - md_number_to_chars (buffer, MATCH_R1_JMP | SET_IW_R_A (AT_REGNUM), 4); + if (is_r2) + op = MATCH_R2_JMP | SET_IW_F3X6L5_A (AT_REGNUM); + else + op = MATCH_R1_JMP | SET_IW_R_A (AT_REGNUM); + md_number_to_chars (buffer, op, 4); fragp->fr_fix += 4; buffer += 4; } @@ -977,8 +1103,15 @@ md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED, static bfd_boolean nios2_check_overflow (valueT fixup, reloc_howto_type *howto) { - /* Apply the rightshift before checking for overflow. */ - fixup = ((signed)fixup) >> howto->rightshift; + /* If there is a rightshift, check that the low-order bits are + zero before applying it. */ + if (howto->rightshift) + { + if ((~(~((valueT) 0) << howto->rightshift) & fixup) + && howto->complain_on_overflow != complain_overflow_dont) + return TRUE; + fixup = ((signed)fixup) >> howto->rightshift; + } /* Check for overflow - return TRUE if overflow, FALSE if not. */ switch (howto->complain_on_overflow) @@ -994,7 +1127,7 @@ nios2_check_overflow (valueT fixup, reloc_howto_type *howto) if ((fixup & 0x80000000) > 0) { /* Check for negative overflow. */ - if ((signed) fixup < ((signed) 0x80000000 >> howto->bitsize)) + if ((signed) fixup < ((signed) ~0 << (howto->bitsize-1))) return TRUE; } else @@ -1056,14 +1189,24 @@ nios2_diagnose_overflow (valueT fixup, reloc_howto_type *howto, address, range_min, range_max); break; case branch_target_overflow: - as_bad_where (fixP->fx_file, fixP->fx_line, - _("branch offset %d out of range %d to %d"), - (int)fixup, -32768, 32767); + if (opcode->format == iw_i_type || opcode->format == iw_F2I16_type) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch offset %d out of range %d to %d"), + (int)fixup, -32768, 32767); + else + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch offset %d out of range"), + (int)fixup); break; case address_offset_overflow: - as_bad_where (fixP->fx_file, fixP->fx_line, - _("%s offset %d out of range %d to %d"), - opcode->name, (int)fixup, -32768, 32767); + if (opcode->format == iw_i_type || opcode->format == iw_F2I16_type) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("%s offset %d out of range %d to %d"), + opcode->name, (int)fixup, -32768, 32767); + else + as_bad_where (fixP->fx_file, fixP->fx_line, + _("%s offset %d out of range"), + opcode->name, (int)fixup); break; case signed_immed16_overflow: as_bad_where (fixP->fx_file, fixP->fx_line, @@ -1080,6 +1223,11 @@ nios2_diagnose_overflow (valueT fixup, reloc_howto_type *howto, _("immediate value %u out of range %u to %u"), (unsigned int)fixup, 0, 31); break; + case signed_immed12_overflow: + as_bad_where (fixP->fx_file, fixP->fx_line, + _("immediate value %d out of range %d to %d"), + (int)fixup, -2048, 2047); + break; case custom_opcode_overflow: as_bad_where (fixP->fx_file, fixP->fx_line, _("custom instruction opcode %u out of range %u to %u"), @@ -1137,6 +1285,19 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) || fixP->fx_r_type == BFD_RELOC_NIOS2_GOT_HA || fixP->fx_r_type == BFD_RELOC_NIOS2_CALL_LO || fixP->fx_r_type == BFD_RELOC_NIOS2_CALL_HA + || fixP->fx_r_type == BFD_RELOC_NIOS2_R2_S12 + || fixP->fx_r_type == BFD_RELOC_NIOS2_R2_I10_1_PCREL + || fixP->fx_r_type == BFD_RELOC_NIOS2_R2_T1I7_1_PCREL + || fixP->fx_r_type == BFD_RELOC_NIOS2_R2_T1I7_2 + || fixP->fx_r_type == BFD_RELOC_NIOS2_R2_T2I4 + || fixP->fx_r_type == BFD_RELOC_NIOS2_R2_T2I4_1 + || fixP->fx_r_type == BFD_RELOC_NIOS2_R2_T2I4_2 + || fixP->fx_r_type == BFD_RELOC_NIOS2_R2_X1I7_2 + || fixP->fx_r_type == BFD_RELOC_NIOS2_R2_X2L5 + || fixP->fx_r_type == BFD_RELOC_NIOS2_R2_F1I5_2 + || fixP->fx_r_type == BFD_RELOC_NIOS2_R2_L5I4X1 + || fixP->fx_r_type == BFD_RELOC_NIOS2_R2_T1X1I6 + || fixP->fx_r_type == BFD_RELOC_NIOS2_R2_T1X1I6_2 /* Add other relocs here as we generate them. */ )); @@ -1208,8 +1369,11 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) FIXME : for some reason fixP->fx_pcrel isn't 1 when it should be so I'm using the howto structure instead to determine this. */ if (howto->pc_relative == 1) - fixup = fixup - (fixP->fx_frag->fr_address + fixP->fx_where - + fixP->fx_size); + { + fixup = (fixup - (fixP->fx_frag->fr_address + fixP->fx_where + + fixP->fx_size)); + *valP = fixup; + } /* Get the instruction or data to be fixed up. */ buf = fixP->fx_frag->fr_literal + fixP->fx_where; @@ -1390,6 +1554,198 @@ nios2_parse_reg (const char *token, unsigned long regtype) return reg; } +/* This function parses a reglist for ldwm/stwm and push.n/pop.n + instructions, given as a brace-enclosed register list. The tokenizer + has replaced commas in the token with spaces. + The return value is a bitmask of registers in the set. It also + sets nios2_reglist_mask and nios2_reglist_dir to allow error checking + when parsing the base register. */ + +static unsigned long nios2_reglist_mask; +static int nios2_reglist_dir; + +static unsigned long +nios2_parse_reglist (char *token, const struct nios2_opcode *op) +{ + unsigned long mask = 0; + int dir = 0; + unsigned long regtype = 0; + int last = -1; + const char *regname; + + nios2_reglist_mask = 0; + nios2_reglist_dir = 0; + + if (op->match == MATCH_R2_LDWM || op->match == MATCH_R2_STWM) + { + regtype = REG_LDWM; + dir = 0; + } + else if (op->match == MATCH_R2_PUSH_N) + { + regtype = REG_POP; + dir = -1; + } + else if (op->match == MATCH_R2_POP_N) + { + regtype = REG_POP; + dir = 1; + } + else + bad_opcode (op); + + for (regname = strtok (token, "{ }"); + regname; + regname = strtok (NULL, "{ }")) + { + int regno; + struct nios2_reg *reg = nios2_parse_reg (regname, regtype); + + if (!reg) + break; + regno = reg->index; + + /* Make sure registers are listed in proper sequence. */ + if (last >= 0) + { + if (regno == last) + { + as_bad ("duplicate register %s\n", reg->name); + return 0; + } + else if (dir == 0) + dir = (regno < last ? -1 : 1); + else if ((dir > 0 && regno < last) + || (dir < 0 && regno > last) + || (op->match == MATCH_R2_PUSH_N + && ! ((last == 31 && regno == 28) + || (last == 31 && regno <= 23) + || (last == 28 && regno <= 23) + || (regno < 23 && regno == last - 1))) + || (op->match == MATCH_R2_POP_N + && ! ((regno == 31 && last == 28) + || (regno == 31 && last <= 23) + || (regno == 28 && last <= 23) + || (last < 23 && last == regno - 1)))) + { + as_bad ("invalid register order"); + return 0; + } + } + + mask |= 1 << regno; + last = regno; + } + + /* Check that all ldwm/stwm regs belong to the same set. */ + if ((op->match == MATCH_R2_LDWM || op->match == MATCH_R2_STWM) + && (mask & 0x00003ffc) && (mask & 0x90ffc000)) + { + as_bad ("invalid register set in reglist"); + return 0; + } + + /* Check that push.n/pop.n regs include RA. */ + if ((op->match == MATCH_R2_PUSH_N || op->match == MATCH_R2_POP_N) + && ((mask & 0x80000000) == 0)) + { + as_bad ("reglist must include ra (r31)"); + return 0; + } + + /* Check that there is at least one register in the set. */ + if (!mask) + { + as_bad ("reglist must include at least one register"); + return 0; + } + + /* OK, reglist passed validation. */ + nios2_reglist_mask = mask; + nios2_reglist_dir = dir; + return mask; +} + +/* This function parses the base register and options used by the ldwm/stwm + instructions. Returns the base register and sets the option arguments + accordingly. On failure, returns NULL. */ +static struct nios2_reg * +nios2_parse_base_register (char *str, int *direction, int *writeback, int *ret) +{ + char *regname; + struct nios2_reg *reg; + + *direction = 0; + *writeback = 0; + *ret = 0; + + /* Check for --. */ + if (strncmp (str, "--", 2) == 0) + { + str += 2; + *direction -= 1; + } + + /* Extract the base register. */ + if (*str != '(') + { + as_bad ("expected '(' before base register"); + return NULL; + } + str++; + regname = str; + str = strchr (str, ')'); + if (!str) + { + as_bad ("expected ')' after base register"); + return NULL; + } + *str = '\0'; + str++; + reg = nios2_parse_reg (regname, REG_NORMAL); + if (reg == NULL) + return NULL; + + /* Check for ++. */ + if (strncmp (str, "++", 2) == 0) + { + str += 2; + *direction += 1; + } + + /* Ensure that either -- or ++ is specified, but not both. */ + if (*direction == 0) + { + as_bad ("invalid base register syntax"); + return NULL;; + } + + /* Check for options. The tokenizer has replaced commas with spaces. */ + while (*str) + { + while (*str == ' ') + str++; + if (strncmp (str, "writeback", 9) == 0) + { + *writeback = 1; + str += 9; + } + else if (strncmp (str, "ret", 3) == 0) + { + *ret = 1; + str += 3; + } + else if (*str) + { + as_bad ("invalid option syntax"); + return NULL; + } + } + + return reg; +} + + /* The various nios2_assemble_* functions call this function to generate an expression from a string representing an expression. It then tries to evaluate the expression, and if it can, returns its value. @@ -1398,13 +1754,14 @@ nios2_parse_reg (const char *token, unsigned long regtype) static unsigned long nios2_assemble_expression (const char *exprstr, nios2_insn_infoS *insn, - bfd_reloc_code_real_type reloc_type, + bfd_reloc_code_real_type orig_reloc_type, unsigned int pcrel) { nios2_insn_relocS *reloc; char *saved_line_ptr; - unsigned short value; + unsigned long value = 0; int i; + bfd_reloc_code_real_type reloc_type = orig_reloc_type; gas_assert (exprstr != NULL); gas_assert (insn != NULL); @@ -1431,6 +1788,25 @@ nios2_assemble_expression (const char *exprstr, break; } + /* No relocation allowed; we must have a constant expression. */ + if (orig_reloc_type == BFD_RELOC_NONE) + { + expressionS exp; + + /* Parse the expression string. */ + saved_line_ptr = input_line_pointer; + input_line_pointer = (char *) exprstr; + expression (&exp); + input_line_pointer = saved_line_ptr; + + /* If we don't have a constant, give an error. */ + if (reloc_type != orig_reloc_type || exp.X_op != O_constant) + as_bad (_("expression must be constant")); + else + value = exp.X_add_number; + return (unsigned long) value; + } + /* We potentially have a relocation. */ reloc = nios2_insn_reloc_new (reloc_type, pcrel); reloc->reloc_next = insn->insn_reloc; @@ -1445,7 +1821,6 @@ nios2_assemble_expression (const char *exprstr, /* This is redundant as the fixup will put this into the instruction, but it is included here so that self-test mode (-r) works. */ - value = 0; if (nios2_mode == NIOS2_MODE_TEST && reloc->reloc_expression.X_op == O_constant) value = reloc->reloc_expression.X_add_number; @@ -1453,8 +1828,29 @@ nios2_assemble_expression (const char *exprstr, return (unsigned long) value; } +/* Encode a 3-bit register number, giving an error if this is not possible. */ +static unsigned int +nios2_assemble_reg3 (const char *token) +{ + struct nios2_reg *reg = nios2_parse_reg (token, REG_3BIT); + int j; + + if (reg == NULL) + return 0; + + for (j = 0; j < nios2_num_r2_reg3_mappings; j++) + if (nios2_r2_reg3_mappings[j] == reg->index) + return j; + + /* Should never get here if we passed validation. */ + as_bad (_("invalid register %s"), token); + return 0; +} /* Argument assemble functions. */ + + +/* Control register index. */ static void nios2_assemble_arg_c (const char *token, nios2_insn_infoS *insn) { @@ -1469,11 +1865,15 @@ nios2_assemble_arg_c (const char *token, nios2_insn_infoS *insn) case iw_r_type: insn->insn_code |= SET_IW_R_IMM5 (reg->index); break; + case iw_F3X6L5_type: + insn->insn_code |= SET_IW_F3X6L5_IMM5 (reg->index); + break; default: bad_opcode (op); } } +/* Destination register. */ static void nios2_assemble_arg_d (const char *token, nios2_insn_infoS *insn) { @@ -1481,7 +1881,7 @@ nios2_assemble_arg_d (const char *token, nios2_insn_infoS *insn) unsigned long regtype = REG_NORMAL; struct nios2_reg *reg; - if (op->format == iw_custom_type) + if (op->format == iw_custom_type || op->format == iw_F3X8_type) regtype |= REG_COPROCESSOR; reg = nios2_parse_reg (token, regtype); if (reg == NULL) @@ -1499,11 +1899,26 @@ nios2_assemble_arg_d (const char *token, nios2_insn_infoS *insn) else insn->insn_code |= SET_IW_CUSTOM_READC (1); break; + case iw_F3X6L5_type: + case iw_F3X6_type: + insn->insn_code |= SET_IW_F3X6L5_C (reg->index); + break; + case iw_F3X8_type: + insn->insn_code |= SET_IW_F3X8_C (reg->index); + if (reg->regtype & REG_COPROCESSOR) + insn->insn_code |= SET_IW_F3X8_READC (0); + else + insn->insn_code |= SET_IW_F3X8_READC (1); + break; + case iw_F2_type: + insn->insn_code |= SET_IW_F2_B (reg->index); + break; default: bad_opcode (op); } } +/* Source register 1. */ static void nios2_assemble_arg_s (const char *token, nios2_insn_infoS *insn) { @@ -1511,7 +1926,7 @@ nios2_assemble_arg_s (const char *token, nios2_insn_infoS *insn) unsigned long regtype = REG_NORMAL; struct nios2_reg *reg; - if (op->format == iw_custom_type) + if (op->format == iw_custom_type || op->format == iw_F3X8_type) regtype |= REG_COPROCESSOR; reg = nios2_parse_reg (token, regtype); if (reg == NULL) @@ -1520,6 +1935,8 @@ nios2_assemble_arg_s (const char *token, nios2_insn_infoS *insn) switch (op->format) { case iw_r_type: + if (op->match == MATCH_R1_JMP && reg->index == 31) + as_bad (_("r31 cannot be used with jmp; use ret instead")); insn->insn_code |= SET_IW_R_A (reg->index); break; case iw_i_type: @@ -1532,11 +1949,53 @@ nios2_assemble_arg_s (const char *token, nios2_insn_infoS *insn) else insn->insn_code |= SET_IW_CUSTOM_READA (1); break; + case iw_F2I16_type: + insn->insn_code |= SET_IW_F2I16_A (reg->index); + break; + case iw_F2X4I12_type: + insn->insn_code |= SET_IW_F2X4I12_A (reg->index); + break; + case iw_F1X4I12_type: + insn->insn_code |= SET_IW_F1X4I12_A (reg->index); + break; + case iw_F1X4L17_type: + insn->insn_code |= SET_IW_F1X4L17_A (reg->index); + break; + case iw_F3X6L5_type: + case iw_F3X6_type: + if (op->match == MATCH_R2_JMP && reg->index == 31) + as_bad (_("r31 cannot be used with jmp; use ret instead")); + insn->insn_code |= SET_IW_F3X6L5_A (reg->index); + break; + case iw_F2X6L10_type: + insn->insn_code |= SET_IW_F2X6L10_A (reg->index); + break; + case iw_F3X8_type: + insn->insn_code |= SET_IW_F3X8_A (reg->index); + if (reg->regtype & REG_COPROCESSOR) + insn->insn_code |= SET_IW_F3X8_READA (0); + else + insn->insn_code |= SET_IW_F3X8_READA (1); + break; + case iw_F1X1_type: + if (op->match == MATCH_R2_JMPR_N && reg->index == 31) + as_bad (_("r31 cannot be used with jmpr.n; use ret.n instead")); + insn->insn_code |= SET_IW_F1X1_A (reg->index); + break; + case iw_F1I5_type: + /* Implicit stack pointer reference. */ + if (reg->index != 27) + as_bad (_("invalid register %s"), token); + break; + case iw_F2_type: + insn->insn_code |= SET_IW_F2_A (reg->index); + break; default: bad_opcode (op); } } +/* Source register 2. */ static void nios2_assemble_arg_t (const char *token, nios2_insn_infoS *insn) { @@ -1544,7 +2003,7 @@ nios2_assemble_arg_t (const char *token, nios2_insn_infoS *insn) unsigned long regtype = REG_NORMAL; struct nios2_reg *reg; - if (op->format == iw_custom_type) + if (op->format == iw_custom_type || op->format == iw_F3X8_type) regtype |= REG_COPROCESSOR; reg = nios2_parse_reg (token, regtype); if (reg == NULL) @@ -1565,11 +2024,147 @@ nios2_assemble_arg_t (const char *token, nios2_insn_infoS *insn) else insn->insn_code |= SET_IW_CUSTOM_READB (1); break; + case iw_F2I16_type: + insn->insn_code |= SET_IW_F2I16_B (reg->index); + break; + case iw_F2X4I12_type: + insn->insn_code |= SET_IW_F2X4I12_B (reg->index); + break; + case iw_F3X6L5_type: + case iw_F3X6_type: + insn->insn_code |= SET_IW_F3X6L5_B (reg->index); + break; + case iw_F2X6L10_type: + insn->insn_code |= SET_IW_F2X6L10_B (reg->index); + break; + case iw_F3X8_type: + insn->insn_code |= SET_IW_F3X8_B (reg->index); + if (reg->regtype & REG_COPROCESSOR) + insn->insn_code |= SET_IW_F3X8_READB (0); + else + insn->insn_code |= SET_IW_F3X8_READB (1); + break; + case iw_F1I5_type: + insn->insn_code |= SET_IW_F1I5_B (reg->index); + break; + case iw_F2_type: + insn->insn_code |= SET_IW_F2_B (reg->index); + break; + case iw_T1X1I6_type: + /* Implicit zero register reference. */ + if (reg->index != 0) + as_bad (_("invalid register %s"), token); + break; + + default: + bad_opcode (op); + } +} + +/* Destination register w/3-bit encoding. */ +static void +nios2_assemble_arg_D (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + int reg = nios2_assemble_reg3 (token); + + switch (op->format) + { + case iw_T1I7_type: + insn->insn_code |= SET_IW_T1I7_A3 (reg); + break; + case iw_T2X1L3_type: + insn->insn_code |= SET_IW_T2X1L3_B3 (reg); + break; + case iw_T2X1I3_type: + insn->insn_code |= SET_IW_T2X1I3_B3 (reg); + break; + case iw_T3X1_type: + insn->insn_code |= SET_IW_T3X1_C3 (reg); + break; + case iw_T2X3_type: + /* Some instructions using this encoding take 3 register arguments, + requiring the destination register to be the same as the first + source register. */ + if (op->num_args == 3) + insn->insn_code |= SET_IW_T2X3_A3 (reg); + else + insn->insn_code |= SET_IW_T2X3_B3 (reg); + break; + default: + bad_opcode (op); + } +} + +/* Source register w/3-bit encoding. */ +static void +nios2_assemble_arg_S (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + int reg = nios2_assemble_reg3 (token); + + switch (op->format) + { + case iw_T1I7_type: + insn->insn_code |= SET_IW_T1I7_A3 (reg); + break; + case iw_T2I4_type: + insn->insn_code |= SET_IW_T2I4_A3 (reg); + break; + case iw_T2X1L3_type: + insn->insn_code |= SET_IW_T2X1L3_A3 (reg); + break; + case iw_T2X1I3_type: + insn->insn_code |= SET_IW_T2X1I3_A3 (reg); + break; + case iw_T3X1_type: + insn->insn_code |= SET_IW_T3X1_A3 (reg); + break; + case iw_T2X3_type: + /* Some instructions using this encoding take 3 register arguments, + requiring the destination register to be the same as the first + source register. */ + if (op->num_args == 3) + { + int dreg = GET_IW_T2X3_A3 (insn->insn_code); + if (dreg != reg) + as_bad ("source and destination registers must be the same"); + } + else + insn->insn_code |= SET_IW_T2X3_A3 (reg); + break; + case iw_T1X1I6_type: + insn->insn_code |= SET_IW_T1X1I6_A3 (reg); + break; + default: + bad_opcode (op); + } +} + +/* Source register 2 w/3-bit encoding. */ +static void +nios2_assemble_arg_T (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + int reg = nios2_assemble_reg3 (token); + + switch (op->format) + { + case iw_T2I4_type: + insn->insn_code |= SET_IW_T2I4_B3 (reg); + break; + case iw_T3X1_type: + insn->insn_code |= SET_IW_T3X1_B3 (reg); + break; + case iw_T2X3_type: + insn->insn_code |= SET_IW_T2X3_B3 (reg); + break; default: bad_opcode (op); } } +/* 16-bit signed immediate. */ static void nios2_assemble_arg_i (const char *token, nios2_insn_infoS *insn) { @@ -1583,11 +2178,41 @@ nios2_assemble_arg_i (const char *token, nios2_insn_infoS *insn) BFD_RELOC_NIOS2_S16, 0); insn->constant_bits |= SET_IW_I_IMM16 (val); break; + case iw_F2I16_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_S16, 0); + insn->constant_bits |= SET_IW_F2I16_IMM16 (val); + break; + default: + bad_opcode (op); + } +} + +/* 12-bit signed immediate. */ +static void +nios2_assemble_arg_I (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + + switch (op->format) + { + case iw_F2X4I12_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_R2_S12, 0); + insn->constant_bits |= SET_IW_F2X4I12_IMM12 (val); + break; + case iw_F1X4I12_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_R2_S12, 0); + insn->constant_bits |= SET_IW_F2X4I12_IMM12 (val); + break; default: bad_opcode (op); } } +/* 16-bit unsigned immediate. */ static void nios2_assemble_arg_u (const char *token, nios2_insn_infoS *insn) { @@ -1601,11 +2226,128 @@ nios2_assemble_arg_u (const char *token, nios2_insn_infoS *insn) BFD_RELOC_NIOS2_U16, 0); insn->constant_bits |= SET_IW_I_IMM16 (val); break; + case iw_F2I16_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_U16, 0); + insn->constant_bits |= SET_IW_F2I16_IMM16 (val); + break; + default: + bad_opcode (op); + } +} + +/* 7-bit unsigned immediate with 2-bit shift. */ +static void +nios2_assemble_arg_U (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + + switch (op->format) + { + case iw_T1I7_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_R2_T1I7_2, 0); + insn->constant_bits |= SET_IW_T1I7_IMM7 (val >> 2); + break; + case iw_X1I7_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_R2_X1I7_2, 0); + insn->constant_bits |= SET_IW_X1I7_IMM7 (val >> 2); + break; + default: + bad_opcode (op); + } +} + +/* 5-bit unsigned immediate with 2-bit shift. */ +static void +nios2_assemble_arg_V (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + + switch (op->format) + { + case iw_F1I5_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_R2_F1I5_2, 0); + insn->constant_bits |= SET_IW_F1I5_IMM5 (val >> 2); + break; + default: + bad_opcode (op); + } +} + +/* 4-bit unsigned immediate with 2-bit shift. */ +static void +nios2_assemble_arg_W (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + + switch (op->format) + { + case iw_T2I4_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_R2_T2I4_2, 0); + insn->constant_bits |= SET_IW_T2I4_IMM4 (val >> 2); + break; + case iw_L5I4X1_type: + /* This argument is optional for push.n/pop.n, and defaults to + zero if unspecified. */ + if (token == NULL) + return; + + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_R2_L5I4X1, 0); + insn->constant_bits |= SET_IW_L5I4X1_IMM4 (val >> 2); + break; + default: + bad_opcode (op); + } +} + +/* 4-bit unsigned immediate with 1-bit shift. */ +static void +nios2_assemble_arg_X (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + + switch (op->format) + { + case iw_T2I4_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_R2_T2I4_1, 0); + insn->constant_bits |= SET_IW_T2I4_IMM4 (val >> 1); + break; default: bad_opcode (op); } } +/* 4-bit unsigned immediate without shift. */ +static void +nios2_assemble_arg_Y (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + + switch (op->format) + { + case iw_T2I4_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_R2_T2I4, 0); + insn->constant_bits |= SET_IW_T2I4_IMM4 (val); + break; + default: + bad_opcode (op); + } +} + + +/* 16-bit signed immediate address offset. */ static void nios2_assemble_arg_o (const char *token, nios2_insn_infoS *insn) { @@ -1619,11 +2361,55 @@ nios2_assemble_arg_o (const char *token, nios2_insn_infoS *insn) BFD_RELOC_16_PCREL, 1); insn->constant_bits |= SET_IW_I_IMM16 (val); break; + case iw_F2I16_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_16_PCREL, 1); + insn->constant_bits |= SET_IW_F2I16_IMM16 (val); + break; + default: + bad_opcode (op); + } +} + +/* 10-bit signed address offset with 1-bit shift. */ +static void +nios2_assemble_arg_O (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + + switch (op->format) + { + case iw_I10_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_R2_I10_1_PCREL, 1); + insn->constant_bits |= SET_IW_I10_IMM10 (val >> 1); + break; + default: + bad_opcode (op); + } +} + +/* 7-bit signed address offset with 1-bit shift. */ +static void +nios2_assemble_arg_P (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + + switch (op->format) + { + case iw_T1I7_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_R2_T1I7_1_PCREL, 1); + insn->constant_bits |= SET_IW_T1I7_IMM7 (val >> 1); + break; default: bad_opcode (op); } } +/* 5-bit unsigned immediate. */ static void nios2_assemble_arg_j (const char *token, nios2_insn_infoS *insn) { @@ -1637,11 +2423,66 @@ nios2_assemble_arg_j (const char *token, nios2_insn_infoS *insn) BFD_RELOC_NIOS2_IMM5, 0); insn->constant_bits |= SET_IW_R_IMM5 (val); break; + case iw_F3X6L5_type: + if (op->match == MATCH_R2_ENI) + /* Value must be constant 0 or 1. */ + { + val = nios2_assemble_expression (token, insn, BFD_RELOC_NONE, 0); + if (val != 0 && val != 1) + as_bad ("invalid eni argument %u", val); + insn->insn_code |= SET_IW_F3X6L5_IMM5 (val); + } + else + { + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_IMM5, 0); + insn->constant_bits |= SET_IW_F3X6L5_IMM5 (val); + } + break; + case iw_F2X6L10_type: + /* Only constant expression without relocation permitted for + bit position. */ + val = nios2_assemble_expression (token, insn, BFD_RELOC_NONE, 0); + if (val > 31) + as_bad ("invalid bit position %u", val); + insn->insn_code |= SET_IW_F2X6L10_MSB (val); + break; + case iw_X2L5_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_R2_X2L5, 0); + insn->constant_bits |= SET_IW_X2L5_IMM5 (val); + break; default: bad_opcode (op); } } +/* Second 5-bit unsigned immediate field. */ +static void +nios2_assemble_arg_k (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + + switch (op->format) + { + case iw_F2X6L10_type: + /* Only constant expression without relocation permitted for + bit position. */ + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NONE, 0); + if (val > 31) + as_bad ("invalid bit position %u", val); + else if (GET_IW_F2X6L10_MSB (insn->insn_code) < val) + as_bad ("MSB must be greater than or equal to LSB"); + insn->insn_code |= SET_IW_F2X6L10_LSB (val); + break; + default: + bad_opcode (op); + } +} + +/* 8-bit unsigned immediate. */ static void nios2_assemble_arg_l (const char *token, nios2_insn_infoS *insn) { @@ -1655,11 +2496,17 @@ nios2_assemble_arg_l (const char *token, nios2_insn_infoS *insn) BFD_RELOC_NIOS2_IMM8, 0); insn->constant_bits |= SET_IW_CUSTOM_N (val); break; + case iw_F3X8_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_IMM8, 0); + insn->constant_bits |= SET_IW_F3X8_N (val); + break; default: bad_opcode (op); } } +/* 26-bit unsigned immediate. */ static void nios2_assemble_arg_m (const char *token, nios2_insn_infoS *insn) { @@ -1676,6 +2523,277 @@ nios2_assemble_arg_m (const char *token, nios2_insn_infoS *insn) 0); insn->constant_bits |= SET_IW_J_IMM26 (val); break; + case iw_L26_type: + val = nios2_assemble_expression (token, insn, + (nios2_as_options.noat + ? BFD_RELOC_NIOS2_CALL26_NOAT + : BFD_RELOC_NIOS2_CALL26), + 0); + insn->constant_bits |= SET_IW_L26_IMM26 (val); + break; + default: + bad_opcode (op); + } +} + +/* 6-bit unsigned immediate with no shifting. */ +static void +nios2_assemble_arg_M (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + + switch (op->format) + { + case iw_T1X1I6_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_R2_T1X1I6, 0); + insn->constant_bits |= SET_IW_T1X1I6_IMM6 (val); + break; + default: + bad_opcode (op); + } +} + +/* 6-bit unsigned immediate with 2-bit shift. */ +static void +nios2_assemble_arg_N (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + + switch (op->format) + { + case iw_T1X1I6_type: + val = nios2_assemble_expression (token, insn, + BFD_RELOC_NIOS2_R2_T1X1I6_2, 0); + insn->constant_bits |= SET_IW_T1X1I6_IMM6 (val >> 2); + break; + default: + bad_opcode (op); + } +} + + +/* Encoded enumeration for addi.n/subi.n. */ +static void +nios2_assemble_arg_e (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + int i; + + switch (op->format) + { + case iw_T2X1I3_type: + val = nios2_assemble_expression (token, insn, BFD_RELOC_NONE, 0); + for (i = 0; i < nios2_num_r2_asi_n_mappings; i++) + if (val == nios2_r2_asi_n_mappings[i]) + break; + if (i == nios2_num_r2_asi_n_mappings) + { + as_bad (_("Invalid constant operand %s"), token); + return; + } + insn->insn_code |= SET_IW_T2X1I3_IMM3 ((unsigned)i); + break; + default: + bad_opcode (op); + } +} + +/* Encoded enumeration for slli.n/srli.n. */ +static void +nios2_assemble_arg_f (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + int i; + + switch (op->format) + { + case iw_T2X1L3_type: + val = nios2_assemble_expression (token, insn, BFD_RELOC_NONE, 0); + for (i = 0; i < nios2_num_r2_shi_n_mappings; i++) + if (val == nios2_r2_shi_n_mappings[i]) + break; + if (i == nios2_num_r2_shi_n_mappings) + { + as_bad (_("Invalid constant operand %s"), token); + return; + } + insn->insn_code |= SET_IW_T2X1L3_SHAMT ((unsigned)i); + break; + default: + bad_opcode (op); + } +} + +/* Encoded enumeration for andi.n. */ +static void +nios2_assemble_arg_g (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + int i; + + switch (op->format) + { + case iw_T2I4_type: + val = nios2_assemble_expression (token, insn, BFD_RELOC_NONE, 0); + for (i = 0; i < nios2_num_r2_andi_n_mappings; i++) + if (val == nios2_r2_andi_n_mappings[i]) + break; + if (i == nios2_num_r2_andi_n_mappings) + { + as_bad (_("Invalid constant operand %s"), token); + return; + } + insn->insn_code |= SET_IW_T2I4_IMM4 ((unsigned)i); + break; + default: + bad_opcode (op); + } +} + +/* Encoded enumeration for movi.n. */ +static void +nios2_assemble_arg_h (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned int val; + int i; + + switch (op->format) + { + case iw_T1I7_type: + val = nios2_assemble_expression (token, insn, BFD_RELOC_NONE, 0); + i = (signed) val; + if ((signed) i == -1) + val = 127; + else if (i == -2) + val = 126; + else if (i == 0xff) + val = 125; + else if (i < 0 || i > 125) + { + as_bad (_("Invalid constant operand %s"), token); + return; + } + insn->insn_code |= SET_IW_T1I7_IMM7 (val); + break; + default: + bad_opcode (op); + } +} + +/* Encoded REGMASK for ldwm/stwm or push.n/pop.n. */ +static void +nios2_assemble_arg_R (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + unsigned long mask; + char *buf = strdup (token); + unsigned long reglist = nios2_parse_reglist (buf, op); + free (buf); + + if (reglist == 0) + return; + + switch (op->format) + { + case iw_F1X4L17_type: + /* Encoding for ldwm/stwm. */ + if (reglist & 0x00003ffc) + mask = reglist >> 2; + else + { + insn->insn_code |= SET_IW_F1X4L17_RS (1); + mask = (reglist & 0x00ffc000) >> 14; + if (reglist & (1 << 28)) + mask |= 1 << 10; + if (reglist & (1 << 31)) + mask |= 1 << 11; + } + insn->insn_code |= SET_IW_F1X4L17_REGMASK (mask); + break; + + case iw_L5I4X1_type: + /* Encoding for push.n/pop.n. */ + if (reglist & (1 << 28)) + insn->insn_code |= SET_IW_L5I4X1_FP (1); + mask = reglist & 0x00ff0000; + if (mask) + { + int i; + + for (i = 0; i < nios2_num_r2_reg_range_mappings; i++) + if (nios2_r2_reg_range_mappings[i] == mask) + break; + if (i == nios2_num_r2_reg_range_mappings) + { + as_bad ("invalid reglist"); + return; + } + insn->insn_code |= SET_IW_L5I4X1_REGRANGE (i); + insn->insn_code |= SET_IW_L5I4X1_CS (1); + } + break; + + default: + bad_opcode (op); + } +} + +/* Base register for ldwm/stwm. */ +static void +nios2_assemble_arg_B (const char *token, nios2_insn_infoS *insn) +{ + const struct nios2_opcode *op = insn->insn_nios2_opcode; + int direction, writeback, ret; + char *str = strdup (token); + struct nios2_reg *reg + = nios2_parse_base_register (str, &direction, &writeback, &ret); + + free (str); + if (!reg) + return; + + switch (op->format) + { + case iw_F1X4L17_type: + /* For ldwm, check to see if the base register is already inside the + register list. */ + if (op->match == MATCH_R2_LDWM + && (nios2_reglist_mask & (1 << reg->index))) + { + as_bad ("invalid base register; %s is inside the reglist", reg->name); + return; + } + + /* For stwm, ret option is not allowed. */ + if (op->match == MATCH_R2_STWM && ret) + { + as_bad ("invalid option syntax"); + return; + } + + /* Check that the direction matches the ordering of the reglist. */ + if (nios2_reglist_dir && direction != nios2_reglist_dir) + { + as_bad ("reglist order does not match increment/decrement mode"); + return; + } + + insn->insn_code |= SET_IW_F1X4L17_A (reg->index); + if (direction > 0) + insn->insn_code |= SET_IW_F1X4L17_ID (1); + if (writeback) + insn->insn_code |= SET_IW_F1X4L17_WB (1); + if (ret) + insn->insn_code |= SET_IW_F1X4L17_PC (1); + break; + default: bad_opcode (op); } @@ -1723,22 +2841,70 @@ nios2_assemble_args (nios2_insn_infoS *insn) nios2_assemble_arg_t (insn->insn_tokens[tokidx++], insn); break; + case 'D': + nios2_assemble_arg_D (insn->insn_tokens[tokidx++], insn); + break; + + case 'S': + nios2_assemble_arg_S (insn->insn_tokens[tokidx++], insn); + break; + + case 'T': + nios2_assemble_arg_T (insn->insn_tokens[tokidx++], insn); + break; + case 'i': nios2_assemble_arg_i (insn->insn_tokens[tokidx++], insn); break; + case 'I': + nios2_assemble_arg_I (insn->insn_tokens[tokidx++], insn); + break; + case 'u': nios2_assemble_arg_u (insn->insn_tokens[tokidx++], insn); break; + case 'U': + nios2_assemble_arg_U (insn->insn_tokens[tokidx++], insn); + break; + + case 'V': + nios2_assemble_arg_V (insn->insn_tokens[tokidx++], insn); + break; + + case 'W': + nios2_assemble_arg_W (insn->insn_tokens[tokidx++], insn); + break; + + case 'X': + nios2_assemble_arg_X (insn->insn_tokens[tokidx++], insn); + break; + + case 'Y': + nios2_assemble_arg_Y (insn->insn_tokens[tokidx++], insn); + break; + case 'o': nios2_assemble_arg_o (insn->insn_tokens[tokidx++], insn); break; + case 'O': + nios2_assemble_arg_O (insn->insn_tokens[tokidx++], insn); + break; + + case 'P': + nios2_assemble_arg_P (insn->insn_tokens[tokidx++], insn); + break; + case 'j': nios2_assemble_arg_j (insn->insn_tokens[tokidx++], insn); break; + case 'k': + nios2_assemble_arg_k (insn->insn_tokens[tokidx++], insn); + break; + case 'l': nios2_assemble_arg_l (insn->insn_tokens[tokidx++], insn); break; @@ -1746,7 +2912,39 @@ nios2_assemble_args (nios2_insn_infoS *insn) case 'm': nios2_assemble_arg_m (insn->insn_tokens[tokidx++], insn); break; + + case 'M': + nios2_assemble_arg_M (insn->insn_tokens[tokidx++], insn); + break; + + case 'N': + nios2_assemble_arg_N (insn->insn_tokens[tokidx++], insn); + break; + + case 'e': + nios2_assemble_arg_e (insn->insn_tokens[tokidx++], insn); + break; + + case 'f': + nios2_assemble_arg_f (insn->insn_tokens[tokidx++], insn); + break; + case 'g': + nios2_assemble_arg_g (insn->insn_tokens[tokidx++], insn); + break; + + case 'h': + nios2_assemble_arg_h (insn->insn_tokens[tokidx++], insn); + break; + + case 'R': + nios2_assemble_arg_R (insn->insn_tokens[tokidx++], insn); + break; + + case 'B': + nios2_assemble_arg_B (insn->insn_tokens[tokidx++], insn); + break; + default: bad_opcode (op); break; @@ -1775,6 +2973,9 @@ nios2_consume_arg (char *argstr, const char *parsestr) case 'd': case 's': case 't': + case 'D': + case 'S': + case 'T': break; case 'i': @@ -1798,11 +2999,60 @@ nios2_consume_arg (char *argstr, const char *parsestr) break; case 'm': case 'j': + case 'k': case 'l': + case 'I': + case 'U': + case 'V': + case 'W': + case 'X': + case 'Y': + case 'O': + case 'P': + case 'e': + case 'f': + case 'g': + case 'h': + case 'M': + case 'N': + /* We can't have %hi, %lo or %hiadj here. */ if (*argstr == '%') as_bad (_("badly formed expression near %s"), argstr); break; + + case 'R': + /* Register list for ldwm/stwm or push.n/pop.n. Replace the commas + in the list with spaces so we don't confuse them with separators. */ + if (*argstr != '{') + { + as_bad ("missing '{' in register list"); + break; + } + for (temp = argstr + 1; *temp; temp++) + { + if (*temp == '}') + break; + else if (*temp == ',') + *temp = ' '; + } + if (!*temp) + { + as_bad ("missing '}' in register list"); + break; + } + break; + + case 'B': + /* Base register and options for ldwm/stwm. This is the final argument + and consumes the rest of the argument string; replace commas + with spaces so that the token splitter doesn't think they are + separate arguments. */ + for (temp = argstr; *temp; temp++) + if (*temp == ',') + *temp = ' '; + break; + case 'o': case 'E': break; @@ -1839,7 +3089,6 @@ nios2_consume_separator (char *argstr, const char *separator) return p; } - /* The principal argument parsing function which takes a string argstr representing the instruction arguments for insn, and extracts the argument tokens matching parsestr into parsed_args. */ @@ -2022,7 +3271,7 @@ nios2_translate_pseudo_insn (nios2_insn_infoS *insn) else /* we cannot recover from this. */ as_fatal (_("unrecognized pseudo-instruction %s"), - ps_insn->pseudo_insn); + insn->insn_nios2_opcode->name); return ps_insn; } @@ -2056,7 +3305,8 @@ const nios2_ps_insn_infoS nios2_ps_insn_info_structs[] = { {"cmpgtui", "cmpgeui", nios2_modify_arg, "+1", 0, 3, nios2_free_arg}, {"cmplei", "cmplti", nios2_modify_arg, "+1", 0, 3, nios2_free_arg}, {"cmpleui", "cmpltui", nios2_modify_arg, "+1", 0, 3, nios2_free_arg}, - {"subi", "addi", nios2_negate_arg, "", 0, 3, nios2_free_arg} + {"subi", "addi", nios2_negate_arg, "", 0, 3, nios2_free_arg}, + {"nop.n", "mov.n", nios2_append_arg, "zero", 2, 1, NULL} /* Add further pseudo-ops here. */ }; @@ -2101,6 +3351,7 @@ output_ubranch (nios2_insn_infoS *insn) symbolS *symp = reloc->reloc_expression.X_add_symbol; offsetT offset = reloc->reloc_expression.X_add_number; char *f; + bfd_boolean is_cdx = (insn->insn_nios2_opcode->size == 2); /* Tag dwarf2 debug info to the address at the start of the insn. We must do it before frag_var() below closes off the frag. */ @@ -2111,7 +3362,8 @@ output_ubranch (nios2_insn_infoS *insn) this may generate. */ f = frag_var (rs_machine_dependent, UBRANCH_MAX_SIZE, insn->insn_nios2_opcode->size, - UBRANCH_SUBTYPE (0), symp, offset, NULL); + (is_cdx ? CDX_UBRANCH_SUBTYPE (0) : UBRANCH_SUBTYPE (0)), + symp, offset, NULL); md_number_to_chars (f, insn->insn_code, insn->insn_nios2_opcode->size); @@ -2131,6 +3383,7 @@ output_cbranch (nios2_insn_infoS *insn) symbolS *symp = reloc->reloc_expression.X_add_symbol; offsetT offset = reloc->reloc_expression.X_add_number; char *f; + bfd_boolean is_cdx = (insn->insn_nios2_opcode->size == 2); /* Tag dwarf2 debug info to the address at the start of the insn. We must do it before frag_var() below closes off the frag. */ @@ -2141,7 +3394,8 @@ output_cbranch (nios2_insn_infoS *insn) this may generate. */ f = frag_var (rs_machine_dependent, CBRANCH_MAX_SIZE, insn->insn_nios2_opcode->size, - CBRANCH_SUBTYPE (0), symp, offset, NULL); + (is_cdx ? CDX_CBRANCH_SUBTYPE (0) : CBRANCH_SUBTYPE (0)), + symp, offset, NULL); md_number_to_chars (f, insn->insn_code, insn->insn_nios2_opcode->size); @@ -2162,23 +3416,50 @@ output_call (nios2_insn_infoS *insn) and puts it in the current frag. */ char *f = frag_more (12); nios2_insn_relocS *reloc = insn->insn_reloc; + const struct nios2_opcode *op = insn->insn_nios2_opcode; - md_number_to_chars (f, - (MATCH_R1_ORHI | SET_IW_I_B (AT_REGNUM) - | SET_IW_I_A (0)), - 4); - dwarf2_emit_insn (4); - fix_new_exp (frag_now, f - frag_now->fr_literal, 4, - &reloc->reloc_expression, 0, BFD_RELOC_NIOS2_HI16); - md_number_to_chars (f + 4, - (MATCH_R1_ORI | SET_IW_I_B (AT_REGNUM) - | SET_IW_I_A (AT_REGNUM)), - 4); - dwarf2_emit_insn (4); - fix_new_exp (frag_now, f - frag_now->fr_literal + 4, 4, - &reloc->reloc_expression, 0, BFD_RELOC_NIOS2_LO16); - md_number_to_chars (f + 8, MATCH_R1_CALLR | SET_IW_R_A (AT_REGNUM), 4); - dwarf2_emit_insn (4); + switch (op->format) + { + case iw_j_type: + md_number_to_chars (f, + (MATCH_R1_ORHI | SET_IW_I_B (AT_REGNUM) + | SET_IW_I_A (0)), + 4); + dwarf2_emit_insn (4); + fix_new_exp (frag_now, f - frag_now->fr_literal, 4, + &reloc->reloc_expression, 0, BFD_RELOC_NIOS2_HI16); + md_number_to_chars (f + 4, + (MATCH_R1_ORI | SET_IW_I_B (AT_REGNUM) + | SET_IW_I_A (AT_REGNUM)), + 4); + dwarf2_emit_insn (4); + fix_new_exp (frag_now, f - frag_now->fr_literal + 4, 4, + &reloc->reloc_expression, 0, BFD_RELOC_NIOS2_LO16); + md_number_to_chars (f + 8, MATCH_R1_CALLR | SET_IW_R_A (AT_REGNUM), 4); + dwarf2_emit_insn (4); + break; + case iw_L26_type: + md_number_to_chars (f, + (MATCH_R2_ORHI | SET_IW_F2I16_B (AT_REGNUM) + | SET_IW_F2I16_A (0)), + 4); + dwarf2_emit_insn (4); + fix_new_exp (frag_now, f - frag_now->fr_literal, 4, + &reloc->reloc_expression, 0, BFD_RELOC_NIOS2_HI16); + md_number_to_chars (f + 4, + (MATCH_R2_ORI | SET_IW_F2I16_B (AT_REGNUM) + | SET_IW_F2I16_A (AT_REGNUM)), + 4); + dwarf2_emit_insn (4); + fix_new_exp (frag_now, f - frag_now->fr_literal + 4, 4, + &reloc->reloc_expression, 0, BFD_RELOC_NIOS2_LO16); + md_number_to_chars (f + 8, MATCH_R2_CALLR | SET_IW_F3X6L5_A (AT_REGNUM), + 4); + dwarf2_emit_insn (4); + break; + default: + bad_opcode (op); + } } /* Output a movhi/addi pair for the movia pseudo-op. */ @@ -2189,21 +3470,33 @@ output_movia (nios2_insn_infoS *insn) and puts it in the current frag. */ char *f = frag_more (8); nios2_insn_relocS *reloc = insn->insn_reloc; - unsigned long reg_index = GET_IW_I_B (insn->insn_code); + unsigned long reg, code; + const struct nios2_opcode *op = insn->insn_nios2_opcode; /* If the reloc is NULL, there was an error assembling the movia. */ if (reloc != NULL) { + switch (op->format) + { + case iw_i_type: + reg = GET_IW_I_B (insn->insn_code); + code = MATCH_R1_ADDI | SET_IW_I_A (reg) | SET_IW_I_B (reg); + break; + case iw_F2I16_type: + reg = GET_IW_F2I16_B (insn->insn_code); + code = MATCH_R2_ADDI | SET_IW_F2I16_A (reg) | SET_IW_F2I16_B (reg); + break; + default: + bad_opcode (op); + } + md_number_to_chars (f, insn->insn_code, 4); dwarf2_emit_insn (4); fix_new (frag_now, f - frag_now->fr_literal, 4, reloc->reloc_expression.X_add_symbol, reloc->reloc_expression.X_add_number, 0, BFD_RELOC_NIOS2_HIADJ16); - md_number_to_chars (f + 4, - (MATCH_R1_ADDI | SET_IW_I_A (reg_index) - | SET_IW_I_B (reg_index)), - 4); + md_number_to_chars (f + 4, code, 4); dwarf2_emit_insn (4); fix_new (frag_now, f + 4 - frag_now->fr_literal, 4, reloc->reloc_expression.X_add_symbol, @@ -2387,6 +3680,7 @@ md_begin (void) nios2_current_align_seg = now_seg; nios2_last_label = NULL; nios2_current_align = 0; + nios2_min_align = 2; } @@ -2400,11 +3694,11 @@ md_assemble (char *op_str) nios2_insn_infoS thisinsn; nios2_insn_infoS *insn = &thisinsn; - /* Make sure we are aligned on a 4-byte boundary. */ - if (nios2_current_align < 2) - nios2_align (2, NULL, nios2_last_label); - else if (nios2_current_align > 2) - nios2_current_align = 2; + /* Make sure we are aligned on an appropriate boundary. */ + if (nios2_current_align < nios2_min_align) + nios2_align (nios2_min_align, NULL, nios2_last_label); + else if (nios2_current_align > nios2_min_align) + nios2_current_align = nios2_min_align; nios2_last_label = NULL; /* We don't want to clobber to op_str @@ -2420,6 +3714,11 @@ md_assemble (char *op_str) if (insn->insn_nios2_opcode != NULL) { nios2_ps_insn_infoS *ps_insn = NULL; + + /* Note if we've seen a 16-bit instruction. */ + if (insn->insn_nios2_opcode->size == 2) + nios2_min_align = 1; + /* Set the opcode for the instruction. */ insn->insn_code = insn->insn_nios2_opcode->match; insn->constant_bits = 0; @@ -2667,7 +3966,7 @@ nios2_cons_align (int size) ++log_size; if (subseg_text_p (now_seg)) - pfill = (const char *) &nop; + pfill = (const char *) nop32; else pfill = NULL; diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index f1b3f1f..def2131 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,21 @@ +2015-07-01 Sandra Loosemore <sandra@codesourcery.com> + Cesar Philippidis <cesar@codesourcery.com> + + * nios2.h (enum iw_format_type): Add R2 formats. + (enum overflow_type): Add signed_immed12_overflow and + enumeration_overflow for R2. + (struct nios2_opcode): Document new argument letters for R2. + (REG_3BIT, REG_LDWM, REG_POP): Define. + (includes): Include nios2r2.h. + (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare. + (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare. + (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare. + (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare. + (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare. + (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): + Declare. + * nios2r2.h: New file. + 2015-06-19 Peter Bergner <bergner@vnet.ibm.com> * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New. diff --git a/include/opcode/nios2.h b/include/opcode/nios2.h index cbd2b8c..7dab06f 100644 --- a/include/opcode/nios2.h +++ b/include/opcode/nios2.h @@ -37,11 +37,38 @@ extern "C" { /* Instruction encoding formats. */ enum iw_format_type { - /* R1 formats */ + /* R1 formats. */ iw_i_type, iw_r_type, iw_j_type, - iw_custom_type + iw_custom_type, + + /* 32-bit R2 formats. */ + iw_L26_type, + iw_F2I16_type, + iw_F2X4I12_type, + iw_F1X4I12_type, + iw_F1X4L17_type, + iw_F3X6L5_type, + iw_F2X6L10_type, + iw_F3X6_type, + iw_F3X8_type, + + /* 16-bit R2 formats. */ + iw_I10_type, + iw_T1I7_type, + iw_T2I4_type, + iw_T1X1I6_type, + iw_X1I7_type, + iw_L5I4X1_type, + iw_T2X1L3_type, + iw_T2X1I3_type, + iw_T3X1_type, + iw_T2X3_type, + iw_F1X1_type, + iw_X2L5_type, + iw_F1I5_type, + iw_F2_type }; /* Identify different overflow situations for error messages. */ @@ -53,7 +80,9 @@ enum overflow_type signed_immed16_overflow, unsigned_immed16_overflow, unsigned_immed5_overflow, + signed_immed12_overflow, custom_opcode_overflow, + enumeration_overflow, no_overflow }; @@ -65,12 +94,32 @@ enum overflow_type d - a 5-bit destination register index s - a 5-bit left source register index t - a 5-bit right source register index + D - a 3-bit encoded destination register + S - a 3-bit encoded left source register + T - a 3-bit encoded right source register i - a 16-bit signed immediate - u - a 16-bit unsigned immediate - o - a 16-bit signed program counter relative offset j - a 5-bit unsigned immediate + k - a (second) 5-bit unsigned immediate l - a 8-bit custom instruction constant m - a 26-bit unsigned immediate + o - a 16-bit signed pc-relative offset + u - a 16-bit unsigned immediate + I - a 12-bit signed immediate + M - a 6-bit unsigned immediate + N - a 6-bit unsigned immediate with 2-bit shift + O - a 10-bit signed pc-relative offset with 1-bit shift + P - a 7-bit signed pc-relative offset with 1-bit shift + U - a 7-bit unsigned immediate with 2-bit shift + V - a 5-bit unsigned immediate with 2-bit shift + W - a 4-bit unsigned immediate with 2-bit shift + X - a 4-bit unsigned immediate with 1-bit shift + Y - a 4-bit unsigned immediate + e - an immediate coded as an enumeration for addi.n/subi.n + f - an immediate coded as an enumeration for slli.n/srli.n + g - an immediate coded as an enumeration for andi.n + h - an immediate coded as an enumeration for movi.n + R - a reglist for ldwm/stwm or push.n/pop.n + B - a base register specifier and option list for ldwm/stwm Literal ',', '(', and ')' characters may also appear in the args as delimiters. @@ -130,6 +179,9 @@ struct nios2_opcode #define REG_NORMAL (1<<0) /* Normal registers. */ #define REG_CONTROL (1<<1) /* Control registers. */ #define REG_COPROCESSOR (1<<2) /* For custom instructions. */ +#define REG_3BIT (1<<3) /* For R2 CDX instructions. */ +#define REG_LDWM (1<<4) /* For R2 ldwm/stwm. */ +#define REG_POP (1<<5) /* For R2 pop.n/push.n. */ struct nios2_reg { @@ -140,10 +192,13 @@ struct nios2_reg /* Pull in the instruction field accessors, opcodes, and masks. */ #include "nios2r1.h" +#include "nios2r2.h" /* These are the data structures used to hold the instruction information. */ extern const struct nios2_opcode nios2_r1_opcodes[]; extern const int nios2_num_r1_opcodes; +extern const struct nios2_opcode nios2_r2_opcodes[]; +extern const int nios2_num_r2_opcodes; extern struct nios2_opcode *nios2_opcodes; extern int nios2_num_opcodes; @@ -157,6 +212,22 @@ extern int nios2_num_regs; extern const struct nios2_opcode * nios2_find_opcode_hash (unsigned long, unsigned long); +/* Lookup tables for R2 immediate decodings. */ +extern unsigned int nios2_r2_asi_n_mappings[]; +extern const int nios2_num_r2_asi_n_mappings; +extern unsigned int nios2_r2_shi_n_mappings[]; +extern const int nios2_num_r2_shi_n_mappings; +extern unsigned int nios2_r2_andi_n_mappings[]; +extern const int nios2_num_r2_andi_n_mappings; + +/* Lookup table for 3-bit register decodings. */ +extern int nios2_r2_reg3_mappings[]; +extern const int nios2_num_r2_reg3_mappings; + +/* Lookup table for REG_RANGE value list decodings. */ +extern unsigned long nios2_r2_reg_range_mappings[]; +extern const int nios2_num_r2_reg_range_mappings; + #ifdef __cplusplus } #endif diff --git a/include/opcode/nios2r2.h b/include/opcode/nios2r2.h new file mode 100644 index 0000000..fd50aa0 --- /dev/null +++ b/include/opcode/nios2r2.h @@ -0,0 +1,1081 @@ +/* Nios II R2 opcode list for GAS, the GNU assembler. + Copyright (C) 2013-2015 Free Software Foundation, Inc. + Contributed by Mentor Graphics, Inc. + + This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. + + GAS/GDB is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS/GDB is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS or GDB; see the file COPYING3. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +#ifndef _NIOS2R2_H_ +#define _NIOS2R2_H_ + +/* Fields for 32-bit R2 instructions. */ + +#define IW_R2_OP_LSB 0 +#define IW_R2_OP_SIZE 6 +#define IW_R2_OP_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R2_OP_SIZE)) +#define IW_R2_OP_SHIFTED_MASK (IW_R2_OP_UNSHIFTED_MASK << IW_R2_OP_LSB) +#define GET_IW_R2_OP(W) (((W) >> IW_R2_OP_LSB) & IW_R2_OP_UNSHIFTED_MASK) +#define SET_IW_R2_OP(V) (((V) & IW_R2_OP_UNSHIFTED_MASK) << IW_R2_OP_LSB) + +#define IW_L26_IMM26_LSB 6 +#define IW_L26_IMM26_SIZE 26 +#define IW_L26_IMM26_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L26_IMM26_SIZE)) +#define IW_L26_IMM26_SHIFTED_MASK (IW_L26_IMM26_UNSHIFTED_MASK << IW_L26_IMM26_LSB) +#define GET_IW_L26_IMM26(W) (((W) >> IW_L26_IMM26_LSB) & IW_L26_IMM26_UNSHIFTED_MASK) +#define SET_IW_L26_IMM26(V) (((V) & IW_L26_IMM26_UNSHIFTED_MASK) << IW_L26_IMM26_LSB) + +#define IW_F2I16_A_LSB 6 +#define IW_F2I16_A_SIZE 5 +#define IW_F2I16_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2I16_A_SIZE)) +#define IW_F2I16_A_SHIFTED_MASK (IW_F2I16_A_UNSHIFTED_MASK << IW_F2I16_A_LSB) +#define GET_IW_F2I16_A(W) (((W) >> IW_F2I16_A_LSB) & IW_F2I16_A_UNSHIFTED_MASK) +#define SET_IW_F2I16_A(V) (((V) & IW_F2I16_A_UNSHIFTED_MASK) << IW_F2I16_A_LSB) + +#define IW_F2I16_B_LSB 11 +#define IW_F2I16_B_SIZE 5 +#define IW_F2I16_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2I16_B_SIZE)) +#define IW_F2I16_B_SHIFTED_MASK (IW_F2I16_B_UNSHIFTED_MASK << IW_F2I16_B_LSB) +#define GET_IW_F2I16_B(W) (((W) >> IW_F2I16_B_LSB) & IW_F2I16_B_UNSHIFTED_MASK) +#define SET_IW_F2I16_B(V) (((V) & IW_F2I16_B_UNSHIFTED_MASK) << IW_F2I16_B_LSB) + +#define IW_F2I16_IMM16_LSB 16 +#define IW_F2I16_IMM16_SIZE 16 +#define IW_F2I16_IMM16_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2I16_IMM16_SIZE)) +#define IW_F2I16_IMM16_SHIFTED_MASK (IW_F2I16_IMM16_UNSHIFTED_MASK << IW_F2I16_IMM16_LSB) +#define GET_IW_F2I16_IMM16(W) (((W) >> IW_F2I16_IMM16_LSB) & IW_F2I16_IMM16_UNSHIFTED_MASK) +#define SET_IW_F2I16_IMM16(V) (((V) & IW_F2I16_IMM16_UNSHIFTED_MASK) << IW_F2I16_IMM16_LSB) + +/* Common to all three I12-group formats F2X4I12, F1X4I12, F1X4L17. */ +#define IW_I12_X_LSB 28 +#define IW_I12_X_SIZE 4 +#define IW_I12_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I12_X_SIZE)) +#define IW_I12_X_SHIFTED_MASK (IW_I12_X_UNSHIFTED_MASK << IW_I12_X_LSB) +#define GET_IW_I12_X(W) (((W) >> IW_I12_X_LSB) & IW_I12_X_UNSHIFTED_MASK) +#define SET_IW_I12_X(V) (((V) & IW_I12_X_UNSHIFTED_MASK) << IW_I12_X_LSB) + +#define IW_F2X4I12_A_LSB 6 +#define IW_F2X4I12_A_SIZE 5 +#define IW_F2X4I12_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X4I12_A_SIZE)) +#define IW_F2X4I12_A_SHIFTED_MASK (IW_F2X4I12_A_UNSHIFTED_MASK << IW_F2X4I12_A_LSB) +#define GET_IW_F2X4I12_A(W) (((W) >> IW_F2X4I12_A_LSB) & IW_F2X4I12_A_UNSHIFTED_MASK) +#define SET_IW_F2X4I12_A(V) (((V) & IW_F2X4I12_A_UNSHIFTED_MASK) << IW_F2X4I12_A_LSB) + +#define IW_F2X4I12_B_LSB 11 +#define IW_F2X4I12_B_SIZE 5 +#define IW_F2X4I12_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X4I12_B_SIZE)) +#define IW_F2X4I12_B_SHIFTED_MASK (IW_F2X4I12_B_UNSHIFTED_MASK << IW_F2X4I12_B_LSB) +#define GET_IW_F2X4I12_B(W) (((W) >> IW_F2X4I12_B_LSB) & IW_F2X4I12_B_UNSHIFTED_MASK) +#define SET_IW_F2X4I12_B(V) (((V) & IW_F2X4I12_B_UNSHIFTED_MASK) << IW_F2X4I12_B_LSB) + +#define IW_F2X4I12_IMM12_LSB 16 +#define IW_F2X4I12_IMM12_SIZE 12 +#define IW_F2X4I12_IMM12_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X4I12_IMM12_SIZE)) +#define IW_F2X4I12_IMM12_SHIFTED_MASK (IW_F2X4I12_IMM12_UNSHIFTED_MASK << IW_F2X4I12_IMM12_LSB) +#define GET_IW_F2X4I12_IMM12(W) (((W) >> IW_F2X4I12_IMM12_LSB) & IW_F2X4I12_IMM12_UNSHIFTED_MASK) +#define SET_IW_F2X4I12_IMM12(V) (((V) & IW_F2X4I12_IMM12_UNSHIFTED_MASK) << IW_F2X4I12_IMM12_LSB) + +#define IW_F1X4I12_A_LSB 6 +#define IW_F1X4I12_A_SIZE 5 +#define IW_F1X4I12_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4I12_A_SIZE)) +#define IW_F1X4I12_A_SHIFTED_MASK (IW_F1X4I12_A_UNSHIFTED_MASK << IW_F1X4I12_A_LSB) +#define GET_IW_F1X4I12_A(W) (((W) >> IW_F1X4I12_A_LSB) & IW_F1X4I12_A_UNSHIFTED_MASK) +#define SET_IW_F1X4I12_A(V) (((V) & IW_F1X4I12_A_UNSHIFTED_MASK) << IW_F1X4I12_A_LSB) + +#define IW_F1X4I12_X_LSB 11 +#define IW_F1X4I12_X_SIZE 5 +#define IW_F1X4I12_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4I12_X_SIZE)) +#define IW_F1X4I12_X_SHIFTED_MASK (IW_F1X4I12_X_UNSHIFTED_MASK << IW_F1X4I12_X_LSB) +#define GET_IW_F1X4I12_X(W) (((W) >> IW_F1X4I12_X_LSB) & IW_F1X4I12_X_UNSHIFTED_MASK) +#define SET_IW_F1X4I12_X(V) (((V) & IW_F1X4I12_X_UNSHIFTED_MASK) << IW_F1X4I12_X_LSB) + +#define IW_F1X4I12_IMM12_LSB 16 +#define IW_F1X4I12_IMM12_SIZE 12 +#define IW_F1X4I12_IMM12_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4I12_IMM12_SIZE)) +#define IW_F1X4I12_IMM12_SHIFTED_MASK (IW_F1X4I12_IMM12_UNSHIFTED_MASK << IW_F1X4I12_IMM12_LSB) +#define GET_IW_F1X4I12_IMM12(W) (((W) >> IW_F1X4I12_IMM12_LSB) & IW_F1X4I12_IMM12_UNSHIFTED_MASK) +#define SET_IW_F1X4I12_IMM12(V) (((V) & IW_F1X4I12_IMM12_UNSHIFTED_MASK) << IW_F1X4I12_IMM12_LSB) + +#define IW_F1X4L17_A_LSB 6 +#define IW_F1X4L17_A_SIZE 5 +#define IW_F1X4L17_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_A_SIZE)) +#define IW_F1X4L17_A_SHIFTED_MASK (IW_F1X4L17_A_UNSHIFTED_MASK << IW_F1X4L17_A_LSB) +#define GET_IW_F1X4L17_A(W) (((W) >> IW_F1X4L17_A_LSB) & IW_F1X4L17_A_UNSHIFTED_MASK) +#define SET_IW_F1X4L17_A(V) (((V) & IW_F1X4L17_A_UNSHIFTED_MASK) << IW_F1X4L17_A_LSB) + +#define IW_F1X4L17_ID_LSB 11 +#define IW_F1X4L17_ID_SIZE 1 +#define IW_F1X4L17_ID_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_ID_SIZE)) +#define IW_F1X4L17_ID_SHIFTED_MASK (IW_F1X4L17_ID_UNSHIFTED_MASK << IW_F1X4L17_ID_LSB) +#define GET_IW_F1X4L17_ID(W) (((W) >> IW_F1X4L17_ID_LSB) & IW_F1X4L17_ID_UNSHIFTED_MASK) +#define SET_IW_F1X4L17_ID(V) (((V) & IW_F1X4L17_ID_UNSHIFTED_MASK) << IW_F1X4L17_ID_LSB) + +#define IW_F1X4L17_WB_LSB 12 +#define IW_F1X4L17_WB_SIZE 1 +#define IW_F1X4L17_WB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_WB_SIZE)) +#define IW_F1X4L17_WB_SHIFTED_MASK (IW_F1X4L17_WB_UNSHIFTED_MASK << IW_F1X4L17_WB_LSB) +#define GET_IW_F1X4L17_WB(W) (((W) >> IW_F1X4L17_WB_LSB) & IW_F1X4L17_WB_UNSHIFTED_MASK) +#define SET_IW_F1X4L17_WB(V) (((V) & IW_F1X4L17_WB_UNSHIFTED_MASK) << IW_F1X4L17_WB_LSB) + +#define IW_F1X4L17_RS_LSB 13 +#define IW_F1X4L17_RS_SIZE 1 +#define IW_F1X4L17_RS_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_RS_SIZE)) +#define IW_F1X4L17_RS_SHIFTED_MASK (IW_F1X4L17_RS_UNSHIFTED_MASK << IW_F1X4L17_RS_LSB) +#define GET_IW_F1X4L17_RS(W) (((W) >> IW_F1X4L17_RS_LSB) & IW_F1X4L17_RS_UNSHIFTED_MASK) +#define SET_IW_F1X4L17_RS(V) (((V) & IW_F1X4L17_RS_UNSHIFTED_MASK) << IW_F1X4L17_RS_LSB) + +#define IW_F1X4L17_PC_LSB 14 +#define IW_F1X4L17_PC_SIZE 1 +#define IW_F1X4L17_PC_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_PC_SIZE)) +#define IW_F1X4L17_PC_SHIFTED_MASK (IW_F1X4L17_PC_UNSHIFTED_MASK << IW_F1X4L17_PC_LSB) +#define GET_IW_F1X4L17_PC(W) (((W) >> IW_F1X4L17_PC_LSB) & IW_F1X4L17_PC_UNSHIFTED_MASK) +#define SET_IW_F1X4L17_PC(V) (((V) & IW_F1X4L17_PC_UNSHIFTED_MASK) << IW_F1X4L17_PC_LSB) + +#define IW_F1X4L17_RSV_LSB 15 +#define IW_F1X4L17_RSV_SIZE 1 +#define IW_F1X4L17_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_RSV_SIZE)) +#define IW_F1X4L17_RSV_SHIFTED_MASK (IW_F1X4L17_RSV_UNSHIFTED_MASK << IW_F1X4L17_RSV_LSB) +#define GET_IW_F1X4L17_RSV(W) (((W) >> IW_F1X4L17_RSV_LSB) & IW_F1X4L17_RSV_UNSHIFTED_MASK) +#define SET_IW_F1X4L17_RSV(V) (((V) & IW_F1X4L17_RSV_UNSHIFTED_MASK) << IW_F1X4L17_RSV_LSB) + +#define IW_F1X4L17_REGMASK_LSB 16 +#define IW_F1X4L17_REGMASK_SIZE 12 +#define IW_F1X4L17_REGMASK_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_REGMASK_SIZE)) +#define IW_F1X4L17_REGMASK_SHIFTED_MASK (IW_F1X4L17_REGMASK_UNSHIFTED_MASK << IW_F1X4L17_REGMASK_LSB) +#define GET_IW_F1X4L17_REGMASK(W) (((W) >> IW_F1X4L17_REGMASK_LSB) & IW_F1X4L17_REGMASK_UNSHIFTED_MASK) +#define SET_IW_F1X4L17_REGMASK(V) (((V) & IW_F1X4L17_REGMASK_UNSHIFTED_MASK) << IW_F1X4L17_REGMASK_LSB) + +/* Shared by OPX-group formats F3X6L5, F2X6L10, F3X6. */ +#define IW_OPX_X_LSB 26 +#define IW_OPX_X_SIZE 6 +#define IW_OPX_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_OPX_X_SIZE)) +#define IW_OPX_X_SHIFTED_MASK (IW_OPX_X_UNSHIFTED_MASK << IW_OPX_X_LSB) +#define GET_IW_OPX_X(W) (((W) >> IW_OPX_X_LSB) & IW_OPX_X_UNSHIFTED_MASK) +#define SET_IW_OPX_X(V) (((V) & IW_OPX_X_UNSHIFTED_MASK) << IW_OPX_X_LSB) + +/* F3X6L5 accessors are also used for F3X6 formats. */ +#define IW_F3X6L5_A_LSB 6 +#define IW_F3X6L5_A_SIZE 5 +#define IW_F3X6L5_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_A_SIZE)) +#define IW_F3X6L5_A_SHIFTED_MASK (IW_F3X6L5_A_UNSHIFTED_MASK << IW_F3X6L5_A_LSB) +#define GET_IW_F3X6L5_A(W) (((W) >> IW_F3X6L5_A_LSB) & IW_F3X6L5_A_UNSHIFTED_MASK) +#define SET_IW_F3X6L5_A(V) (((V) & IW_F3X6L5_A_UNSHIFTED_MASK) << IW_F3X6L5_A_LSB) + +#define IW_F3X6L5_B_LSB 11 +#define IW_F3X6L5_B_SIZE 5 +#define IW_F3X6L5_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_B_SIZE)) +#define IW_F3X6L5_B_SHIFTED_MASK (IW_F3X6L5_B_UNSHIFTED_MASK << IW_F3X6L5_B_LSB) +#define GET_IW_F3X6L5_B(W) (((W) >> IW_F3X6L5_B_LSB) & IW_F3X6L5_B_UNSHIFTED_MASK) +#define SET_IW_F3X6L5_B(V) (((V) & IW_F3X6L5_B_UNSHIFTED_MASK) << IW_F3X6L5_B_LSB) + +#define IW_F3X6L5_C_LSB 16 +#define IW_F3X6L5_C_SIZE 5 +#define IW_F3X6L5_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_C_SIZE)) +#define IW_F3X6L5_C_SHIFTED_MASK (IW_F3X6L5_C_UNSHIFTED_MASK << IW_F3X6L5_C_LSB) +#define GET_IW_F3X6L5_C(W) (((W) >> IW_F3X6L5_C_LSB) & IW_F3X6L5_C_UNSHIFTED_MASK) +#define SET_IW_F3X6L5_C(V) (((V) & IW_F3X6L5_C_UNSHIFTED_MASK) << IW_F3X6L5_C_LSB) + +#define IW_F3X6L5_IMM5_LSB 21 +#define IW_F3X6L5_IMM5_SIZE 5 +#define IW_F3X6L5_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_IMM5_SIZE)) +#define IW_F3X6L5_IMM5_SHIFTED_MASK (IW_F3X6L5_IMM5_UNSHIFTED_MASK << IW_F3X6L5_IMM5_LSB) +#define GET_IW_F3X6L5_IMM5(W) (((W) >> IW_F3X6L5_IMM5_LSB) & IW_F3X6L5_IMM5_UNSHIFTED_MASK) +#define SET_IW_F3X6L5_IMM5(V) (((V) & IW_F3X6L5_IMM5_UNSHIFTED_MASK) << IW_F3X6L5_IMM5_LSB) + +#define IW_F2X6L10_A_LSB 6 +#define IW_F2X6L10_A_SIZE 5 +#define IW_F2X6L10_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_A_SIZE)) +#define IW_F2X6L10_A_SHIFTED_MASK (IW_F2X6L10_A_UNSHIFTED_MASK << IW_F2X6L10_A_LSB) +#define GET_IW_F2X6L10_A(W) (((W) >> IW_F2X6L10_A_LSB) & IW_F2X6L10_A_UNSHIFTED_MASK) +#define SET_IW_F2X6L10_A(V) (((V) & IW_F2X6L10_A_UNSHIFTED_MASK) << IW_F2X6L10_A_LSB) + +#define IW_F2X6L10_B_LSB 11 +#define IW_F2X6L10_B_SIZE 5 +#define IW_F2X6L10_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_B_SIZE)) +#define IW_F2X6L10_B_SHIFTED_MASK (IW_F2X6L10_B_UNSHIFTED_MASK << IW_F2X6L10_B_LSB) +#define GET_IW_F2X6L10_B(W) (((W) >> IW_F2X6L10_B_LSB) & IW_F2X6L10_B_UNSHIFTED_MASK) +#define SET_IW_F2X6L10_B(V) (((V) & IW_F2X6L10_B_UNSHIFTED_MASK) << IW_F2X6L10_B_LSB) + +#define IW_F2X6L10_LSB_LSB 16 +#define IW_F2X6L10_LSB_SIZE 5 +#define IW_F2X6L10_LSB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_LSB_SIZE)) +#define IW_F2X6L10_LSB_SHIFTED_MASK (IW_F2X6L10_LSB_UNSHIFTED_MASK << IW_F2X6L10_LSB_LSB) +#define GET_IW_F2X6L10_LSB(W) (((W) >> IW_F2X6L10_LSB_LSB) & IW_F2X6L10_LSB_UNSHIFTED_MASK) +#define SET_IW_F2X6L10_LSB(V) (((V) & IW_F2X6L10_LSB_UNSHIFTED_MASK) << IW_F2X6L10_LSB_LSB) + +#define IW_F2X6L10_MSB_LSB 21 +#define IW_F2X6L10_MSB_SIZE 5 +#define IW_F2X6L10_MSB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_MSB_SIZE)) +#define IW_F2X6L10_MSB_SHIFTED_MASK (IW_F2X6L10_MSB_UNSHIFTED_MASK << IW_F2X6L10_MSB_LSB) +#define GET_IW_F2X6L10_MSB(W) (((W) >> IW_F2X6L10_MSB_LSB) & IW_F2X6L10_MSB_UNSHIFTED_MASK) +#define SET_IW_F2X6L10_MSB(V) (((V) & IW_F2X6L10_MSB_UNSHIFTED_MASK) << IW_F2X6L10_MSB_LSB) + +#define IW_F3X8_A_LSB 6 +#define IW_F3X8_A_SIZE 5 +#define IW_F3X8_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_A_SIZE)) +#define IW_F3X8_A_SHIFTED_MASK (IW_F3X8_A_UNSHIFTED_MASK << IW_F3X8_A_LSB) +#define GET_IW_F3X8_A(W) (((W) >> IW_F3X8_A_LSB) & IW_F3X8_A_UNSHIFTED_MASK) +#define SET_IW_F3X8_A(V) (((V) & IW_F3X8_A_UNSHIFTED_MASK) << IW_F3X8_A_LSB) + +#define IW_F3X8_B_LSB 11 +#define IW_F3X8_B_SIZE 5 +#define IW_F3X8_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_B_SIZE)) +#define IW_F3X8_B_SHIFTED_MASK (IW_F3X8_B_UNSHIFTED_MASK << IW_F3X8_B_LSB) +#define GET_IW_F3X8_B(W) (((W) >> IW_F3X8_B_LSB) & IW_F3X8_B_UNSHIFTED_MASK) +#define SET_IW_F3X8_B(V) (((V) & IW_F3X8_B_UNSHIFTED_MASK) << IW_F3X8_B_LSB) + +#define IW_F3X8_C_LSB 16 +#define IW_F3X8_C_SIZE 5 +#define IW_F3X8_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_C_SIZE)) +#define IW_F3X8_C_SHIFTED_MASK (IW_F3X8_C_UNSHIFTED_MASK << IW_F3X8_C_LSB) +#define GET_IW_F3X8_C(W) (((W) >> IW_F3X8_C_LSB) & IW_F3X8_C_UNSHIFTED_MASK) +#define SET_IW_F3X8_C(V) (((V) & IW_F3X8_C_UNSHIFTED_MASK) << IW_F3X8_C_LSB) + +#define IW_F3X8_READA_LSB 21 +#define IW_F3X8_READA_SIZE 1 +#define IW_F3X8_READA_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_READA_SIZE)) +#define IW_F3X8_READA_SHIFTED_MASK (IW_F3X8_READA_UNSHIFTED_MASK << IW_F3X8_READA_LSB) +#define GET_IW_F3X8_READA(W) (((W) >> IW_F3X8_READA_LSB) & IW_F3X8_READA_UNSHIFTED_MASK) +#define SET_IW_F3X8_READA(V) (((V) & IW_F3X8_READA_UNSHIFTED_MASK) << IW_F3X8_READA_LSB) + +#define IW_F3X8_READB_LSB 22 +#define IW_F3X8_READB_SIZE 1 +#define IW_F3X8_READB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_READB_SIZE)) +#define IW_F3X8_READB_SHIFTED_MASK (IW_F3X8_READB_UNSHIFTED_MASK << IW_F3X8_READB_LSB) +#define GET_IW_F3X8_READB(W) (((W) >> IW_F3X8_READB_LSB) & IW_F3X8_READB_UNSHIFTED_MASK) +#define SET_IW_F3X8_READB(V) (((V) & IW_F3X8_READB_UNSHIFTED_MASK) << IW_F3X8_READB_LSB) + +#define IW_F3X8_READC_LSB 23 +#define IW_F3X8_READC_SIZE 1 +#define IW_F3X8_READC_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_READC_SIZE)) +#define IW_F3X8_READC_SHIFTED_MASK (IW_F3X8_READC_UNSHIFTED_MASK << IW_F3X8_READC_LSB) +#define GET_IW_F3X8_READC(W) (((W) >> IW_F3X8_READC_LSB) & IW_F3X8_READC_UNSHIFTED_MASK) +#define SET_IW_F3X8_READC(V) (((V) & IW_F3X8_READC_UNSHIFTED_MASK) << IW_F3X8_READC_LSB) + +#define IW_F3X8_N_LSB 24 +#define IW_F3X8_N_SIZE 8 +#define IW_F3X8_N_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_N_SIZE)) +#define IW_F3X8_N_SHIFTED_MASK (IW_F3X8_N_UNSHIFTED_MASK << IW_F3X8_N_LSB) +#define GET_IW_F3X8_N(W) (((W) >> IW_F3X8_N_LSB) & IW_F3X8_N_UNSHIFTED_MASK) +#define SET_IW_F3X8_N(V) (((V) & IW_F3X8_N_UNSHIFTED_MASK) << IW_F3X8_N_LSB) + +/* 16-bit R2 fields. */ + +#define IW_I10_IMM10_LSB 6 +#define IW_I10_IMM10_SIZE 10 +#define IW_I10_IMM10_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I10_IMM10_SIZE)) +#define IW_I10_IMM10_SHIFTED_MASK (IW_I10_IMM10_UNSHIFTED_MASK << IW_I10_IMM10_LSB) +#define GET_IW_I10_IMM10(W) (((W) >> IW_I10_IMM10_LSB) & IW_I10_IMM10_UNSHIFTED_MASK) +#define SET_IW_I10_IMM10(V) (((V) & IW_I10_IMM10_UNSHIFTED_MASK) << IW_I10_IMM10_LSB) + +#define IW_T1I7_A3_LSB 6 +#define IW_T1I7_A3_SIZE 3 +#define IW_T1I7_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1I7_A3_SIZE)) +#define IW_T1I7_A3_SHIFTED_MASK (IW_T1I7_A3_UNSHIFTED_MASK << IW_T1I7_A3_LSB) +#define GET_IW_T1I7_A3(W) (((W) >> IW_T1I7_A3_LSB) & IW_T1I7_A3_UNSHIFTED_MASK) +#define SET_IW_T1I7_A3(V) (((V) & IW_T1I7_A3_UNSHIFTED_MASK) << IW_T1I7_A3_LSB) + +#define IW_T1I7_IMM7_LSB 9 +#define IW_T1I7_IMM7_SIZE 7 +#define IW_T1I7_IMM7_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1I7_IMM7_SIZE)) +#define IW_T1I7_IMM7_SHIFTED_MASK (IW_T1I7_IMM7_UNSHIFTED_MASK << IW_T1I7_IMM7_LSB) +#define GET_IW_T1I7_IMM7(W) (((W) >> IW_T1I7_IMM7_LSB) & IW_T1I7_IMM7_UNSHIFTED_MASK) +#define SET_IW_T1I7_IMM7(V) (((V) & IW_T1I7_IMM7_UNSHIFTED_MASK) << IW_T1I7_IMM7_LSB) + +#define IW_T2I4_A3_LSB 6 +#define IW_T2I4_A3_SIZE 3 +#define IW_T2I4_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2I4_A3_SIZE)) +#define IW_T2I4_A3_SHIFTED_MASK (IW_T2I4_A3_UNSHIFTED_MASK << IW_T2I4_A3_LSB) +#define GET_IW_T2I4_A3(W) (((W) >> IW_T2I4_A3_LSB) & IW_T2I4_A3_UNSHIFTED_MASK) +#define SET_IW_T2I4_A3(V) (((V) & IW_T2I4_A3_UNSHIFTED_MASK) << IW_T2I4_A3_LSB) + +#define IW_T2I4_B3_LSB 9 +#define IW_T2I4_B3_SIZE 3 +#define IW_T2I4_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2I4_B3_SIZE)) +#define IW_T2I4_B3_SHIFTED_MASK (IW_T2I4_B3_UNSHIFTED_MASK << IW_T2I4_B3_LSB) +#define GET_IW_T2I4_B3(W) (((W) >> IW_T2I4_B3_LSB) & IW_T2I4_B3_UNSHIFTED_MASK) +#define SET_IW_T2I4_B3(V) (((V) & IW_T2I4_B3_UNSHIFTED_MASK) << IW_T2I4_B3_LSB) + +#define IW_T2I4_IMM4_LSB 12 +#define IW_T2I4_IMM4_SIZE 4 +#define IW_T2I4_IMM4_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2I4_IMM4_SIZE)) +#define IW_T2I4_IMM4_SHIFTED_MASK (IW_T2I4_IMM4_UNSHIFTED_MASK << IW_T2I4_IMM4_LSB) +#define GET_IW_T2I4_IMM4(W) (((W) >> IW_T2I4_IMM4_LSB) & IW_T2I4_IMM4_UNSHIFTED_MASK) +#define SET_IW_T2I4_IMM4(V) (((V) & IW_T2I4_IMM4_UNSHIFTED_MASK) << IW_T2I4_IMM4_LSB) + +#define IW_T1X1I6_A3_LSB 6 +#define IW_T1X1I6_A3_SIZE 3 +#define IW_T1X1I6_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1X1I6_A3_SIZE)) +#define IW_T1X1I6_A3_SHIFTED_MASK (IW_T1X1I6_A3_UNSHIFTED_MASK << IW_T1X1I6_A3_LSB) +#define GET_IW_T1X1I6_A3(W) (((W) >> IW_T1X1I6_A3_LSB) & IW_T1X1I6_A3_UNSHIFTED_MASK) +#define SET_IW_T1X1I6_A3(V) (((V) & IW_T1X1I6_A3_UNSHIFTED_MASK) << IW_T1X1I6_A3_LSB) + +#define IW_T1X1I6_IMM6_LSB 9 +#define IW_T1X1I6_IMM6_SIZE 6 +#define IW_T1X1I6_IMM6_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1X1I6_IMM6_SIZE)) +#define IW_T1X1I6_IMM6_SHIFTED_MASK (IW_T1X1I6_IMM6_UNSHIFTED_MASK << IW_T1X1I6_IMM6_LSB) +#define GET_IW_T1X1I6_IMM6(W) (((W) >> IW_T1X1I6_IMM6_LSB) & IW_T1X1I6_IMM6_UNSHIFTED_MASK) +#define SET_IW_T1X1I6_IMM6(V) (((V) & IW_T1X1I6_IMM6_UNSHIFTED_MASK) << IW_T1X1I6_IMM6_LSB) + +#define IW_T1X1I6_X_LSB 15 +#define IW_T1X1I6_X_SIZE 1 +#define IW_T1X1I6_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1X1I6_X_SIZE)) +#define IW_T1X1I6_X_SHIFTED_MASK (IW_T1X1I6_X_UNSHIFTED_MASK << IW_T1X1I6_X_LSB) +#define GET_IW_T1X1I6_X(W) (((W) >> IW_T1X1I6_X_LSB) & IW_T1X1I6_X_UNSHIFTED_MASK) +#define SET_IW_T1X1I6_X(V) (((V) & IW_T1X1I6_X_UNSHIFTED_MASK) << IW_T1X1I6_X_LSB) + +#define IW_X1I7_IMM7_LSB 6 +#define IW_X1I7_IMM7_SIZE 7 +#define IW_X1I7_IMM7_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X1I7_IMM7_SIZE)) +#define IW_X1I7_IMM7_SHIFTED_MASK (IW_X1I7_IMM7_UNSHIFTED_MASK << IW_X1I7_IMM7_LSB) +#define GET_IW_X1I7_IMM7(W) (((W) >> IW_X1I7_IMM7_LSB) & IW_X1I7_IMM7_UNSHIFTED_MASK) +#define SET_IW_X1I7_IMM7(V) (((V) & IW_X1I7_IMM7_UNSHIFTED_MASK) << IW_X1I7_IMM7_LSB) + +#define IW_X1I7_RSV_LSB 13 +#define IW_X1I7_RSV_SIZE 2 +#define IW_X1I7_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X1I7_RSV_SIZE)) +#define IW_X1I7_RSV_SHIFTED_MASK (IW_X1I7_RSV_UNSHIFTED_MASK << IW_X1I7_RSV_LSB) +#define GET_IW_X1I7_RSV(W) (((W) >> IW_X1I7_RSV_LSB) & IW_X1I7_RSV_UNSHIFTED_MASK) +#define SET_IW_X1I7_RSV(V) (((V) & IW_X1I7_RSV_UNSHIFTED_MASK) << IW_X1I7_RSV_LSB) + +#define IW_X1I7_X_LSB 15 +#define IW_X1I7_X_SIZE 1 +#define IW_X1I7_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X1I7_X_SIZE)) +#define IW_X1I7_X_SHIFTED_MASK (IW_X1I7_X_UNSHIFTED_MASK << IW_X1I7_X_LSB) +#define GET_IW_X1I7_X(W) (((W) >> IW_X1I7_X_LSB) & IW_X1I7_X_UNSHIFTED_MASK) +#define SET_IW_X1I7_X(V) (((V) & IW_X1I7_X_UNSHIFTED_MASK) << IW_X1I7_X_LSB) + +#define IW_L5I4X1_IMM4_LSB 6 +#define IW_L5I4X1_IMM4_SIZE 4 +#define IW_L5I4X1_IMM4_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_IMM4_SIZE)) +#define IW_L5I4X1_IMM4_SHIFTED_MASK (IW_L5I4X1_IMM4_UNSHIFTED_MASK << IW_L5I4X1_IMM4_LSB) +#define GET_IW_L5I4X1_IMM4(W) (((W) >> IW_L5I4X1_IMM4_LSB) & IW_L5I4X1_IMM4_UNSHIFTED_MASK) +#define SET_IW_L5I4X1_IMM4(V) (((V) & IW_L5I4X1_IMM4_UNSHIFTED_MASK) << IW_L5I4X1_IMM4_LSB) + +#define IW_L5I4X1_REGRANGE_LSB 10 +#define IW_L5I4X1_REGRANGE_SIZE 3 +#define IW_L5I4X1_REGRANGE_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_REGRANGE_SIZE)) +#define IW_L5I4X1_REGRANGE_SHIFTED_MASK (IW_L5I4X1_REGRANGE_UNSHIFTED_MASK << IW_L5I4X1_REGRANGE_LSB) +#define GET_IW_L5I4X1_REGRANGE(W) (((W) >> IW_L5I4X1_REGRANGE_LSB) & IW_L5I4X1_REGRANGE_UNSHIFTED_MASK) +#define SET_IW_L5I4X1_REGRANGE(V) (((V) & IW_L5I4X1_REGRANGE_UNSHIFTED_MASK) << IW_L5I4X1_REGRANGE_LSB) + +#define IW_L5I4X1_FP_LSB 13 +#define IW_L5I4X1_FP_SIZE 1 +#define IW_L5I4X1_FP_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_FP_SIZE)) +#define IW_L5I4X1_FP_SHIFTED_MASK (IW_L5I4X1_FP_UNSHIFTED_MASK << IW_L5I4X1_FP_LSB) +#define GET_IW_L5I4X1_FP(W) (((W) >> IW_L5I4X1_FP_LSB) & IW_L5I4X1_FP_UNSHIFTED_MASK) +#define SET_IW_L5I4X1_FP(V) (((V) & IW_L5I4X1_FP_UNSHIFTED_MASK) << IW_L5I4X1_FP_LSB) + +#define IW_L5I4X1_CS_LSB 14 +#define IW_L5I4X1_CS_SIZE 1 +#define IW_L5I4X1_CS_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_CS_SIZE)) +#define IW_L5I4X1_CS_SHIFTED_MASK (IW_L5I4X1_CS_UNSHIFTED_MASK << IW_L5I4X1_CS_LSB) +#define GET_IW_L5I4X1_CS(W) (((W) >> IW_L5I4X1_CS_LSB) & IW_L5I4X1_CS_UNSHIFTED_MASK) +#define SET_IW_L5I4X1_CS(V) (((V) & IW_L5I4X1_CS_UNSHIFTED_MASK) << IW_L5I4X1_CS_LSB) + +#define IW_L5I4X1_X_LSB 15 +#define IW_L5I4X1_X_SIZE 1 +#define IW_L5I4X1_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_X_SIZE)) +#define IW_L5I4X1_X_SHIFTED_MASK (IW_L5I4X1_X_UNSHIFTED_MASK << IW_L5I4X1_X_LSB) +#define GET_IW_L5I4X1_X(W) (((W) >> IW_L5I4X1_X_LSB) & IW_L5I4X1_X_UNSHIFTED_MASK) +#define SET_IW_L5I4X1_X(V) (((V) & IW_L5I4X1_X_UNSHIFTED_MASK) << IW_L5I4X1_X_LSB) + +#define IW_T2X1L3_A3_LSB 6 +#define IW_T2X1L3_A3_SIZE 3 +#define IW_T2X1L3_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_A3_SIZE)) +#define IW_T2X1L3_A3_SHIFTED_MASK (IW_T2X1L3_A3_UNSHIFTED_MASK << IW_T2X1L3_A3_LSB) +#define GET_IW_T2X1L3_A3(W) (((W) >> IW_T2X1L3_A3_LSB) & IW_T2X1L3_A3_UNSHIFTED_MASK) +#define SET_IW_T2X1L3_A3(V) (((V) & IW_T2X1L3_A3_UNSHIFTED_MASK) << IW_T2X1L3_A3_LSB) + +#define IW_T2X1L3_B3_LSB 9 +#define IW_T2X1L3_B3_SIZE 3 +#define IW_T2X1L3_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_B3_SIZE)) +#define IW_T2X1L3_B3_SHIFTED_MASK (IW_T2X1L3_B3_UNSHIFTED_MASK << IW_T2X1L3_B3_LSB) +#define GET_IW_T2X1L3_B3(W) (((W) >> IW_T2X1L3_B3_LSB) & IW_T2X1L3_B3_UNSHIFTED_MASK) +#define SET_IW_T2X1L3_B3(V) (((V) & IW_T2X1L3_B3_UNSHIFTED_MASK) << IW_T2X1L3_B3_LSB) + +#define IW_T2X1L3_SHAMT_LSB 12 +#define IW_T2X1L3_SHAMT_SIZE 3 +#define IW_T2X1L3_SHAMT_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_SHAMT_SIZE)) +#define IW_T2X1L3_SHAMT_SHIFTED_MASK (IW_T2X1L3_SHAMT_UNSHIFTED_MASK << IW_T2X1L3_SHAMT_LSB) +#define GET_IW_T2X1L3_SHAMT(W) (((W) >> IW_T2X1L3_SHAMT_LSB) & IW_T2X1L3_SHAMT_UNSHIFTED_MASK) +#define SET_IW_T2X1L3_SHAMT(V) (((V) & IW_T2X1L3_SHAMT_UNSHIFTED_MASK) << IW_T2X1L3_SHAMT_LSB) + +#define IW_T2X1L3_X_LSB 15 +#define IW_T2X1L3_X_SIZE 1 +#define IW_T2X1L3_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_X_SIZE)) +#define IW_T2X1L3_X_SHIFTED_MASK (IW_T2X1L3_X_UNSHIFTED_MASK << IW_T2X1L3_X_LSB) +#define GET_IW_T2X1L3_X(W) (((W) >> IW_T2X1L3_X_LSB) & IW_T2X1L3_X_UNSHIFTED_MASK) +#define SET_IW_T2X1L3_X(V) (((V) & IW_T2X1L3_X_UNSHIFTED_MASK) << IW_T2X1L3_X_LSB) + +#define IW_T2X1I3_A3_LSB 6 +#define IW_T2X1I3_A3_SIZE 3 +#define IW_T2X1I3_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_A3_SIZE)) +#define IW_T2X1I3_A3_SHIFTED_MASK (IW_T2X1I3_A3_UNSHIFTED_MASK << IW_T2X1I3_A3_LSB) +#define GET_IW_T2X1I3_A3(W) (((W) >> IW_T2X1I3_A3_LSB) & IW_T2X1I3_A3_UNSHIFTED_MASK) +#define SET_IW_T2X1I3_A3(V) (((V) & IW_T2X1I3_A3_UNSHIFTED_MASK) << IW_T2X1I3_A3_LSB) + +#define IW_T2X1I3_B3_LSB 9 +#define IW_T2X1I3_B3_SIZE 3 +#define IW_T2X1I3_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_B3_SIZE)) +#define IW_T2X1I3_B3_SHIFTED_MASK (IW_T2X1I3_B3_UNSHIFTED_MASK << IW_T2X1I3_B3_LSB) +#define GET_IW_T2X1I3_B3(W) (((W) >> IW_T2X1I3_B3_LSB) & IW_T2X1I3_B3_UNSHIFTED_MASK) +#define SET_IW_T2X1I3_B3(V) (((V) & IW_T2X1I3_B3_UNSHIFTED_MASK) << IW_T2X1I3_B3_LSB) + +#define IW_T2X1I3_IMM3_LSB 12 +#define IW_T2X1I3_IMM3_SIZE 3 +#define IW_T2X1I3_IMM3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_IMM3_SIZE)) +#define IW_T2X1I3_IMM3_SHIFTED_MASK (IW_T2X1I3_IMM3_UNSHIFTED_MASK << IW_T2X1I3_IMM3_LSB) +#define GET_IW_T2X1I3_IMM3(W) (((W) >> IW_T2X1I3_IMM3_LSB) & IW_T2X1I3_IMM3_UNSHIFTED_MASK) +#define SET_IW_T2X1I3_IMM3(V) (((V) & IW_T2X1I3_IMM3_UNSHIFTED_MASK) << IW_T2X1I3_IMM3_LSB) + +#define IW_T2X1I3_X_LSB 15 +#define IW_T2X1I3_X_SIZE 1 +#define IW_T2X1I3_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_X_SIZE)) +#define IW_T2X1I3_X_SHIFTED_MASK (IW_T2X1I3_X_UNSHIFTED_MASK << IW_T2X1I3_X_LSB) +#define GET_IW_T2X1I3_X(W) (((W) >> IW_T2X1I3_X_LSB) & IW_T2X1I3_X_UNSHIFTED_MASK) +#define SET_IW_T2X1I3_X(V) (((V) & IW_T2X1I3_X_UNSHIFTED_MASK) << IW_T2X1I3_X_LSB) + +#define IW_T3X1_A3_LSB 6 +#define IW_T3X1_A3_SIZE 3 +#define IW_T3X1_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_A3_SIZE)) +#define IW_T3X1_A3_SHIFTED_MASK (IW_T3X1_A3_UNSHIFTED_MASK << IW_T3X1_A3_LSB) +#define GET_IW_T3X1_A3(W) (((W) >> IW_T3X1_A3_LSB) & IW_T3X1_A3_UNSHIFTED_MASK) +#define SET_IW_T3X1_A3(V) (((V) & IW_T3X1_A3_UNSHIFTED_MASK) << IW_T3X1_A3_LSB) + +#define IW_T3X1_B3_LSB 9 +#define IW_T3X1_B3_SIZE 3 +#define IW_T3X1_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_B3_SIZE)) +#define IW_T3X1_B3_SHIFTED_MASK (IW_T3X1_B3_UNSHIFTED_MASK << IW_T3X1_B3_LSB) +#define GET_IW_T3X1_B3(W) (((W) >> IW_T3X1_B3_LSB) & IW_T3X1_B3_UNSHIFTED_MASK) +#define SET_IW_T3X1_B3(V) (((V) & IW_T3X1_B3_UNSHIFTED_MASK) << IW_T3X1_B3_LSB) + +#define IW_T3X1_C3_LSB 12 +#define IW_T3X1_C3_SIZE 3 +#define IW_T3X1_C3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_C3_SIZE)) +#define IW_T3X1_C3_SHIFTED_MASK (IW_T3X1_C3_UNSHIFTED_MASK << IW_T3X1_C3_LSB) +#define GET_IW_T3X1_C3(W) (((W) >> IW_T3X1_C3_LSB) & IW_T3X1_C3_UNSHIFTED_MASK) +#define SET_IW_T3X1_C3(V) (((V) & IW_T3X1_C3_UNSHIFTED_MASK) << IW_T3X1_C3_LSB) + +#define IW_T3X1_X_LSB 15 +#define IW_T3X1_X_SIZE 1 +#define IW_T3X1_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_X_SIZE)) +#define IW_T3X1_X_SHIFTED_MASK (IW_T3X1_X_UNSHIFTED_MASK << IW_T3X1_X_LSB) +#define GET_IW_T3X1_X(W) (((W) >> IW_T3X1_X_LSB) & IW_T3X1_X_UNSHIFTED_MASK) +#define SET_IW_T3X1_X(V) (((V) & IW_T3X1_X_UNSHIFTED_MASK) << IW_T3X1_X_LSB) + +/* The X field for all three R.N-class instruction formats is represented + here as 4 bits, including the bits defined as constant 0 or 1 that + determine which of the formats T2X3, F1X1, or X2L5 it is. */ +#define IW_R_N_X_LSB 12 +#define IW_R_N_X_SIZE 4 +#define IW_R_N_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_N_X_SIZE)) +#define IW_R_N_X_SHIFTED_MASK (IW_R_N_X_UNSHIFTED_MASK << IW_R_N_X_LSB) +#define GET_IW_R_N_X(W) (((W) >> IW_R_N_X_LSB) & IW_R_N_X_UNSHIFTED_MASK) +#define SET_IW_R_N_X(V) (((V) & IW_R_N_X_UNSHIFTED_MASK) << IW_R_N_X_LSB) + +#define IW_T2X3_A3_LSB 6 +#define IW_T2X3_A3_SIZE 3 +#define IW_T2X3_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X3_A3_SIZE)) +#define IW_T2X3_A3_SHIFTED_MASK (IW_T2X3_A3_UNSHIFTED_MASK << IW_T2X3_A3_LSB) +#define GET_IW_T2X3_A3(W) (((W) >> IW_T2X3_A3_LSB) & IW_T2X3_A3_UNSHIFTED_MASK) +#define SET_IW_T2X3_A3(V) (((V) & IW_T2X3_A3_UNSHIFTED_MASK) << IW_T2X3_A3_LSB) + +#define IW_T2X3_B3_LSB 9 +#define IW_T2X3_B3_SIZE 3 +#define IW_T2X3_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X3_B3_SIZE)) +#define IW_T2X3_B3_SHIFTED_MASK (IW_T2X3_B3_UNSHIFTED_MASK << IW_T2X3_B3_LSB) +#define GET_IW_T2X3_B3(W) (((W) >> IW_T2X3_B3_LSB) & IW_T2X3_B3_UNSHIFTED_MASK) +#define SET_IW_T2X3_B3(V) (((V) & IW_T2X3_B3_UNSHIFTED_MASK) << IW_T2X3_B3_LSB) + +#define IW_F1X1_A_LSB 6 +#define IW_F1X1_A_SIZE 5 +#define IW_F1X1_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X1_A_SIZE)) +#define IW_F1X1_A_SHIFTED_MASK (IW_F1X1_A_UNSHIFTED_MASK << IW_F1X1_A_LSB) +#define GET_IW_F1X1_A(W) (((W) >> IW_F1X1_A_LSB) & IW_F1X1_A_UNSHIFTED_MASK) +#define SET_IW_F1X1_A(V) (((V) & IW_F1X1_A_UNSHIFTED_MASK) << IW_F1X1_A_LSB) + +#define IW_F1X1_RSV_LSB 11 +#define IW_F1X1_RSV_SIZE 1 +#define IW_F1X1_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X1_RSV_SIZE)) +#define IW_F1X1_RSV_SHIFTED_MASK (IW_F1X1_RSV_UNSHIFTED_MASK << IW_F1X1_RSV_LSB) +#define GET_IW_F1X1_RSV(W) (((W) >> IW_F1X1_RSV_LSB) & IW_F1X1_RSV_UNSHIFTED_MASK) +#define SET_IW_F1X1_RSV(V) (((V) & IW_F1X1_RSV_UNSHIFTED_MASK) << IW_F1X1_RSV_LSB) + +#define IW_X2L5_IMM5_LSB 6 +#define IW_X2L5_IMM5_SIZE 5 +#define IW_X2L5_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X2L5_IMM5_SIZE)) +#define IW_X2L5_IMM5_SHIFTED_MASK (IW_X2L5_IMM5_UNSHIFTED_MASK << IW_X2L5_IMM5_LSB) +#define GET_IW_X2L5_IMM5(W) (((W) >> IW_X2L5_IMM5_LSB) & IW_X2L5_IMM5_UNSHIFTED_MASK) +#define SET_IW_X2L5_IMM5(V) (((V) & IW_X2L5_IMM5_UNSHIFTED_MASK) << IW_X2L5_IMM5_LSB) + +#define IW_X2L5_RSV_LSB 11 +#define IW_X2L5_RSV_SIZE 1 +#define IW_X2L5_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X2L5_RSV_SIZE)) +#define IW_X2L5_RSV_SHIFTED_MASK (IW_X2L5_RSV_UNSHIFTED_MASK << IW_X2L5_RSV_LSB) +#define GET_IW_X2L5_RSV(W) (((W) >> IW_X2L5_RSV_LSB) & IW_X2L5_RSV_UNSHIFTED_MASK) +#define SET_IW_X2L5_RSV(V) (((V) & IW_X2L5_RSV_UNSHIFTED_MASK) << IW_X2L5_RSV_LSB) + +#define IW_F1I5_IMM5_LSB 6 +#define IW_F1I5_IMM5_SIZE 5 +#define IW_F1I5_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1I5_IMM5_SIZE)) +#define IW_F1I5_IMM5_SHIFTED_MASK (IW_F1I5_IMM5_UNSHIFTED_MASK << IW_F1I5_IMM5_LSB) +#define GET_IW_F1I5_IMM5(W) (((W) >> IW_F1I5_IMM5_LSB) & IW_F1I5_IMM5_UNSHIFTED_MASK) +#define SET_IW_F1I5_IMM5(V) (((V) & IW_F1I5_IMM5_UNSHIFTED_MASK) << IW_F1I5_IMM5_LSB) + +#define IW_F1I5_B_LSB 11 +#define IW_F1I5_B_SIZE 5 +#define IW_F1I5_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1I5_B_SIZE)) +#define IW_F1I5_B_SHIFTED_MASK (IW_F1I5_B_UNSHIFTED_MASK << IW_F1I5_B_LSB) +#define GET_IW_F1I5_B(W) (((W) >> IW_F1I5_B_LSB) & IW_F1I5_B_UNSHIFTED_MASK) +#define SET_IW_F1I5_B(V) (((V) & IW_F1I5_B_UNSHIFTED_MASK) << IW_F1I5_B_LSB) + +#define IW_F2_A_LSB 6 +#define IW_F2_A_SIZE 5 +#define IW_F2_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2_A_SIZE)) +#define IW_F2_A_SHIFTED_MASK (IW_F2_A_UNSHIFTED_MASK << IW_F2_A_LSB) +#define GET_IW_F2_A(W) (((W) >> IW_F2_A_LSB) & IW_F2_A_UNSHIFTED_MASK) +#define SET_IW_F2_A(V) (((V) & IW_F2_A_UNSHIFTED_MASK) << IW_F2_A_LSB) + +#define IW_F2_B_LSB 11 +#define IW_F2_B_SIZE 5 +#define IW_F2_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2_B_SIZE)) +#define IW_F2_B_SHIFTED_MASK (IW_F2_B_UNSHIFTED_MASK << IW_F2_B_LSB) +#define GET_IW_F2_B(W) (((W) >> IW_F2_B_LSB) & IW_F2_B_UNSHIFTED_MASK) +#define SET_IW_F2_B(V) (((V) & IW_F2_B_UNSHIFTED_MASK) << IW_F2_B_LSB) + +/* R2 opcodes. */ +#define R2_OP_CALL 0 +#define R2_OP_AS_N 1 +#define R2_OP_BR 2 +#define R2_OP_BR_N 3 +#define R2_OP_ADDI 4 +#define R2_OP_LDBU_N 5 +#define R2_OP_LDBU 6 +#define R2_OP_LDB 7 +#define R2_OP_JMPI 8 +#define R2_OP_R_N 9 +#define R2_OP_ANDI_N 11 +#define R2_OP_ANDI 12 +#define R2_OP_LDHU_N 13 +#define R2_OP_LDHU 14 +#define R2_OP_LDH 15 +#define R2_OP_ASI_N 17 +#define R2_OP_BGE 18 +#define R2_OP_LDWSP_N 19 +#define R2_OP_ORI 20 +#define R2_OP_LDW_N 21 +#define R2_OP_CMPGEI 22 +#define R2_OP_LDW 23 +#define R2_OP_SHI_N 25 +#define R2_OP_BLT 26 +#define R2_OP_MOVI_N 27 +#define R2_OP_XORI 28 +#define R2_OP_STZ_N 29 +#define R2_OP_CMPLTI 30 +#define R2_OP_ANDCI 31 +#define R2_OP_OPX 32 +#define R2_OP_PP_N 33 +#define R2_OP_BNE 34 +#define R2_OP_BNEZ_N 35 +#define R2_OP_MULI 36 +#define R2_OP_STB_N 37 +#define R2_OP_CMPNEI 38 +#define R2_OP_STB 39 +#define R2_OP_I12 40 +#define R2_OP_SPI_N 41 +#define R2_OP_BEQ 42 +#define R2_OP_BEQZ_N 43 +#define R2_OP_ANDHI 44 +#define R2_OP_STH_N 45 +#define R2_OP_CMPEQI 46 +#define R2_OP_STH 47 +#define R2_OP_CUSTOM 48 +#define R2_OP_BGEU 50 +#define R2_OP_STWSP_N 51 +#define R2_OP_ORHI 52 +#define R2_OP_STW_N 53 +#define R2_OP_CMPGEUI 54 +#define R2_OP_STW 55 +#define R2_OP_BLTU 58 +#define R2_OP_MOV_N 59 +#define R2_OP_XORHI 60 +#define R2_OP_SPADDI_N 61 +#define R2_OP_CMPLTUI 62 +#define R2_OP_ANDCHI 63 + +#define R2_OPX_WRPIE 0 +#define R2_OPX_ERET 1 +#define R2_OPX_ROLI 2 +#define R2_OPX_ROL 3 +#define R2_OPX_FLUSHP 4 +#define R2_OPX_RET 5 +#define R2_OPX_NOR 6 +#define R2_OPX_MULXUU 7 +#define R2_OPX_ENI 8 +#define R2_OPX_BRET 9 +#define R2_OPX_ROR 11 +#define R2_OPX_FLUSHI 12 +#define R2_OPX_JMP 13 +#define R2_OPX_AND 14 +#define R2_OPX_CMPGE 16 +#define R2_OPX_SLLI 18 +#define R2_OPX_SLL 19 +#define R2_OPX_WRPRS 20 +#define R2_OPX_OR 22 +#define R2_OPX_MULXSU 23 +#define R2_OPX_CMPLT 24 +#define R2_OPX_SRLI 26 +#define R2_OPX_SRL 27 +#define R2_OPX_NEXTPC 28 +#define R2_OPX_CALLR 29 +#define R2_OPX_XOR 30 +#define R2_OPX_MULXSS 31 +#define R2_OPX_CMPNE 32 +#define R2_OPX_INSERT 35 +#define R2_OPX_DIVU 36 +#define R2_OPX_DIV 37 +#define R2_OPX_RDCTL 38 +#define R2_OPX_MUL 39 +#define R2_OPX_CMPEQ 40 +#define R2_OPX_INITI 41 +#define R2_OPX_MERGE 43 +#define R2_OPX_HBREAK 44 +#define R2_OPX_TRAP 45 +#define R2_OPX_WRCTL 46 +#define R2_OPX_CMPGEU 48 +#define R2_OPX_ADD 49 +#define R2_OPX_EXTRACT 51 +#define R2_OPX_BREAK 52 +#define R2_OPX_LDEX 53 +#define R2_OPX_SYNC 54 +#define R2_OPX_LDSEX 55 +#define R2_OPX_CMPLTU 56 +#define R2_OPX_SUB 57 +#define R2_OPX_SRAI 58 +#define R2_OPX_SRA 59 +#define R2_OPX_STEX 61 +#define R2_OPX_STSEX 63 + +#define R2_I12_LDBIO 0 +#define R2_I12_STBIO 1 +#define R2_I12_LDBUIO 2 +#define R2_I12_DCACHE 3 +#define R2_I12_LDHIO 4 +#define R2_I12_STHIO 5 +#define R2_I12_LDHUIO 6 +#define R2_I12_RDPRS 7 +#define R2_I12_LDWIO 8 +#define R2_I12_STWIO 9 +#define R2_I12_LDWM 12 +#define R2_I12_STWM 13 + +#define R2_DCACHE_INITD 0 +#define R2_DCACHE_INITDA 1 +#define R2_DCACHE_FLUSHD 2 +#define R2_DCACHE_FLUSHDA 3 + +#define R2_AS_N_ADD_N 0 +#define R2_AS_N_SUB_N 1 + +#define R2_R_N_AND_N 0 +#define R2_R_N_OR_N 2 +#define R2_R_N_XOR_N 3 +#define R2_R_N_SLL_N 4 +#define R2_R_N_SRL_N 5 +#define R2_R_N_NOT_N 6 +#define R2_R_N_NEG_N 7 +#define R2_R_N_CALLR_N 8 +#define R2_R_N_JMPR_N 10 +#define R2_R_N_BREAK_N 12 +#define R2_R_N_TRAP_N 13 +#define R2_R_N_RET_N 14 + +#define R2_SPI_N_SPINCI_N 0 +#define R2_SPI_N_SPDECI_N 1 + +#define R2_ASI_N_ADDI_N 0 +#define R2_ASI_N_SUBI_N 1 + +#define R2_SHI_N_SLLI_N 0 +#define R2_SHI_N_SRLI_N 1 + +#define R2_PP_N_POP_N 0 +#define R2_PP_N_PUSH_N 1 + +#define R2_STZ_N_STWZ_N 0 +#define R2_STZ_N_STBZ_N 1 + +/* Convenience macros for R2 encodings. */ + +#define MATCH_R2_OP(NAME) \ + (SET_IW_R2_OP (R2_OP_##NAME)) +#define MASK_R2_OP \ + IW_R2_OP_SHIFTED_MASK + +#define MATCH_R2_OPX0(NAME) \ + (SET_IW_R2_OP (R2_OP_OPX) | SET_IW_OPX_X (R2_OPX_##NAME)) +#define MASK_R2_OPX0 \ + (IW_R2_OP_SHIFTED_MASK | IW_OPX_X_SHIFTED_MASK \ + | IW_F3X6L5_IMM5_SHIFTED_MASK) + +#define MATCH_R2_OPX(NAME, A, B, C) \ + (MATCH_R2_OPX0 (NAME) | SET_IW_F3X6L5_A (A) | SET_IW_F3X6L5_B (B) \ + | SET_IW_F3X6L5_C (C)) +#define MASK_R2_OPX(A, B, C, N) \ + (IW_R2_OP_SHIFTED_MASK | IW_OPX_X_SHIFTED_MASK \ + | (A ? IW_F3X6L5_A_SHIFTED_MASK : 0) \ + | (B ? IW_F3X6L5_B_SHIFTED_MASK : 0) \ + | (C ? IW_F3X6L5_C_SHIFTED_MASK : 0) \ + | (N ? IW_F3X6L5_IMM5_SHIFTED_MASK : 0)) + +#define MATCH_R2_I12(NAME) \ + (SET_IW_R2_OP (R2_OP_I12) | SET_IW_I12_X (R2_I12_##NAME)) +#define MASK_R2_I12 \ + (IW_R2_OP_SHIFTED_MASK | IW_I12_X_SHIFTED_MASK ) + +#define MATCH_R2_DCACHE(NAME) \ + (MATCH_R2_I12(DCACHE) | SET_IW_F1X4I12_X (R2_DCACHE_##NAME)) +#define MASK_R2_DCACHE \ + (MASK_R2_I12 | IW_F1X4I12_X_SHIFTED_MASK) + +#define MATCH_R2_R_N(NAME) \ + (SET_IW_R2_OP (R2_OP_R_N) | SET_IW_R_N_X (R2_R_N_##NAME)) +#define MASK_R2_R_N \ + (IW_R2_OP_SHIFTED_MASK | IW_R_N_X_SHIFTED_MASK ) + +/* Match/mask macros for R2 instructions. */ + +#define MATCH_R2_ADD MATCH_R2_OPX0 (ADD) +#define MASK_R2_ADD MASK_R2_OPX0 +#define MATCH_R2_ADDI MATCH_R2_OP (ADDI) +#define MASK_R2_ADDI MASK_R2_OP +#define MATCH_R2_ADD_N (MATCH_R2_OP (AS_N) | SET_IW_T3X1_X (R2_AS_N_ADD_N)) +#define MASK_R2_ADD_N (MASK_R2_OP | IW_T3X1_X_SHIFTED_MASK) +#define MATCH_R2_ADDI_N (MATCH_R2_OP (ASI_N) | SET_IW_T2X1I3_X (R2_ASI_N_ADDI_N)) +#define MASK_R2_ADDI_N (MASK_R2_OP | IW_T2X1I3_X_SHIFTED_MASK) +#define MATCH_R2_AND MATCH_R2_OPX0 (AND) +#define MASK_R2_AND MASK_R2_OPX0 +#define MATCH_R2_ANDCHI MATCH_R2_OP (ANDCHI) +#define MASK_R2_ANDCHI MASK_R2_OP +#define MATCH_R2_ANDCI MATCH_R2_OP (ANDCI) +#define MASK_R2_ANDCI MASK_R2_OP +#define MATCH_R2_ANDHI MATCH_R2_OP (ANDHI) +#define MASK_R2_ANDHI MASK_R2_OP +#define MATCH_R2_ANDI MATCH_R2_OP (ANDI) +#define MASK_R2_ANDI MASK_R2_OP +#define MATCH_R2_ANDI_N MATCH_R2_OP (ANDI_N) +#define MASK_R2_ANDI_N MASK_R2_OP +#define MATCH_R2_AND_N MATCH_R2_R_N (AND_N) +#define MASK_R2_AND_N MASK_R2_R_N +#define MATCH_R2_BEQ MATCH_R2_OP (BEQ) +#define MASK_R2_BEQ MASK_R2_OP +#define MATCH_R2_BEQZ_N MATCH_R2_OP (BEQZ_N) +#define MASK_R2_BEQZ_N MASK_R2_OP +#define MATCH_R2_BGE MATCH_R2_OP (BGE) +#define MASK_R2_BGE MASK_R2_OP +#define MATCH_R2_BGEU MATCH_R2_OP (BGEU) +#define MASK_R2_BGEU MASK_R2_OP +#define MATCH_R2_BGT MATCH_R2_OP (BLT) +#define MASK_R2_BGT MASK_R2_OP +#define MATCH_R2_BGTU MATCH_R2_OP (BLTU) +#define MASK_R2_BGTU MASK_R2_OP +#define MATCH_R2_BLE MATCH_R2_OP (BGE) +#define MASK_R2_BLE MASK_R2_OP +#define MATCH_R2_BLEU MATCH_R2_OP (BGEU) +#define MASK_R2_BLEU MASK_R2_OP +#define MATCH_R2_BLT MATCH_R2_OP (BLT) +#define MASK_R2_BLT MASK_R2_OP +#define MATCH_R2_BLTU MATCH_R2_OP (BLTU) +#define MASK_R2_BLTU MASK_R2_OP +#define MATCH_R2_BNE MATCH_R2_OP (BNE) +#define MASK_R2_BNE MASK_R2_OP +#define MATCH_R2_BNEZ_N MATCH_R2_OP (BNEZ_N) +#define MASK_R2_BNEZ_N MASK_R2_OP +#define MATCH_R2_BR MATCH_R2_OP (BR) +#define MASK_R2_BR MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK | IW_F2I16_B_SHIFTED_MASK +#define MATCH_R2_BREAK MATCH_R2_OPX (BREAK, 0, 0, 0x1e) +#define MASK_R2_BREAK MASK_R2_OPX (1, 1, 1, 0) +#define MATCH_R2_BREAK_N MATCH_R2_R_N (BREAK_N) +#define MASK_R2_BREAK_N MASK_R2_R_N +#define MATCH_R2_BRET MATCH_R2_OPX (BRET, 0x1e, 0, 0) +#define MASK_R2_BRET MASK_R2_OPX (1, 1, 1, 1) +#define MATCH_R2_BR_N MATCH_R2_OP (BR_N) +#define MASK_R2_BR_N MASK_R2_OP +#define MATCH_R2_CALL MATCH_R2_OP (CALL) +#define MASK_R2_CALL MASK_R2_OP +#define MATCH_R2_CALLR MATCH_R2_OPX (CALLR, 0, 0, 0x1f) +#define MASK_R2_CALLR MASK_R2_OPX (0, 1, 1, 1) +#define MATCH_R2_CALLR_N MATCH_R2_R_N (CALLR_N) +#define MASK_R2_CALLR_N MASK_R2_R_N +#define MATCH_R2_CMPEQ MATCH_R2_OPX0 (CMPEQ) +#define MASK_R2_CMPEQ MASK_R2_OPX0 +#define MATCH_R2_CMPEQI MATCH_R2_OP (CMPEQI) +#define MASK_R2_CMPEQI MASK_R2_OP +#define MATCH_R2_CMPGE MATCH_R2_OPX0 (CMPGE) +#define MASK_R2_CMPGE MASK_R2_OPX0 +#define MATCH_R2_CMPGEI MATCH_R2_OP (CMPGEI) +#define MASK_R2_CMPGEI MASK_R2_OP +#define MATCH_R2_CMPGEU MATCH_R2_OPX0 (CMPGEU) +#define MASK_R2_CMPGEU MASK_R2_OPX0 +#define MATCH_R2_CMPGEUI MATCH_R2_OP (CMPGEUI) +#define MASK_R2_CMPGEUI MASK_R2_OP +#define MATCH_R2_CMPGT MATCH_R2_OPX0 (CMPLT) +#define MASK_R2_CMPGT MASK_R2_OPX0 +#define MATCH_R2_CMPGTI MATCH_R2_OP (CMPGEI) +#define MASK_R2_CMPGTI MASK_R2_OP +#define MATCH_R2_CMPGTU MATCH_R2_OPX0 (CMPLTU) +#define MASK_R2_CMPGTU MASK_R2_OPX0 +#define MATCH_R2_CMPGTUI MATCH_R2_OP (CMPGEUI) +#define MASK_R2_CMPGTUI MASK_R2_OP +#define MATCH_R2_CMPLE MATCH_R2_OPX0 (CMPGE) +#define MASK_R2_CMPLE MASK_R2_OPX0 +#define MATCH_R2_CMPLEI MATCH_R2_OP (CMPLTI) +#define MASK_R2_CMPLEI MASK_R2_OP +#define MATCH_R2_CMPLEU MATCH_R2_OPX0 (CMPGEU) +#define MASK_R2_CMPLEU MASK_R2_OPX0 +#define MATCH_R2_CMPLEUI MATCH_R2_OP (CMPLTUI) +#define MASK_R2_CMPLEUI MASK_R2_OP +#define MATCH_R2_CMPLT MATCH_R2_OPX0 (CMPLT) +#define MASK_R2_CMPLT MASK_R2_OPX0 +#define MATCH_R2_CMPLTI MATCH_R2_OP (CMPLTI) +#define MASK_R2_CMPLTI MASK_R2_OP +#define MATCH_R2_CMPLTU MATCH_R2_OPX0 (CMPLTU) +#define MASK_R2_CMPLTU MASK_R2_OPX0 +#define MATCH_R2_CMPLTUI MATCH_R2_OP (CMPLTUI) +#define MASK_R2_CMPLTUI MASK_R2_OP +#define MATCH_R2_CMPNE MATCH_R2_OPX0 (CMPNE) +#define MASK_R2_CMPNE MASK_R2_OPX0 +#define MATCH_R2_CMPNEI MATCH_R2_OP (CMPNEI) +#define MASK_R2_CMPNEI MASK_R2_OP +#define MATCH_R2_CUSTOM MATCH_R2_OP (CUSTOM) +#define MASK_R2_CUSTOM MASK_R2_OP +#define MATCH_R2_DIV MATCH_R2_OPX0 (DIV) +#define MASK_R2_DIV MASK_R2_OPX0 +#define MATCH_R2_DIVU MATCH_R2_OPX0 (DIVU) +#define MASK_R2_DIVU MASK_R2_OPX0 +#define MATCH_R2_ENI MATCH_R2_OPX (ENI, 0, 0, 0) +#define MASK_R2_ENI MASK_R2_OPX (1, 1, 1, 0) +#define MATCH_R2_ERET MATCH_R2_OPX (ERET, 0x1d, 0x1e, 0) +#define MASK_R2_ERET MASK_R2_OPX (1, 1, 1, 1) +#define MATCH_R2_EXTRACT MATCH_R2_OPX (EXTRACT, 0, 0, 0) +#define MASK_R2_EXTRACT MASK_R2_OPX (0, 0, 0, 0) +#define MATCH_R2_FLUSHD MATCH_R2_DCACHE (FLUSHD) +#define MASK_R2_FLUSHD MASK_R2_DCACHE +#define MATCH_R2_FLUSHDA MATCH_R2_DCACHE (FLUSHDA) +#define MASK_R2_FLUSHDA MASK_R2_DCACHE +#define MATCH_R2_FLUSHI MATCH_R2_OPX (FLUSHI, 0, 0, 0) +#define MASK_R2_FLUSHI MASK_R2_OPX (0, 1, 1, 1) +#define MATCH_R2_FLUSHP MATCH_R2_OPX (FLUSHP, 0, 0, 0) +#define MASK_R2_FLUSHP MASK_R2_OPX (1, 1, 1, 1) +#define MATCH_R2_INITD MATCH_R2_DCACHE (INITD) +#define MASK_R2_INITD MASK_R2_DCACHE +#define MATCH_R2_INITDA MATCH_R2_DCACHE (INITDA) +#define MASK_R2_INITDA MASK_R2_DCACHE +#define MATCH_R2_INITI MATCH_R2_OPX (INITI, 0, 0, 0) +#define MASK_R2_INITI MASK_R2_OPX (0, 1, 1, 1) +#define MATCH_R2_INSERT MATCH_R2_OPX (INSERT, 0, 0, 0) +#define MASK_R2_INSERT MASK_R2_OPX (0, 0, 0, 0) +#define MATCH_R2_JMP MATCH_R2_OPX (JMP, 0, 0, 0) +#define MASK_R2_JMP MASK_R2_OPX (0, 1, 1, 1) +#define MATCH_R2_JMPI MATCH_R2_OP (JMPI) +#define MASK_R2_JMPI MASK_R2_OP +#define MATCH_R2_JMPR_N MATCH_R2_R_N (JMPR_N) +#define MASK_R2_JMPR_N MASK_R2_R_N +#define MATCH_R2_LDB MATCH_R2_OP (LDB) +#define MASK_R2_LDB MASK_R2_OP +#define MATCH_R2_LDBIO MATCH_R2_I12 (LDBIO) +#define MASK_R2_LDBIO MASK_R2_I12 +#define MATCH_R2_LDBU MATCH_R2_OP (LDBU) +#define MASK_R2_LDBU MASK_R2_OP +#define MATCH_R2_LDBUIO MATCH_R2_I12 (LDBUIO) +#define MASK_R2_LDBUIO MASK_R2_I12 +#define MATCH_R2_LDBU_N MATCH_R2_OP (LDBU_N) +#define MASK_R2_LDBU_N MASK_R2_OP +#define MATCH_R2_LDEX MATCH_R2_OPX (LDEX, 0, 0, 0) +#define MASK_R2_LDEX MASK_R2_OPX (0, 1, 0, 1) +#define MATCH_R2_LDH MATCH_R2_OP (LDH) +#define MASK_R2_LDH MASK_R2_OP +#define MATCH_R2_LDHIO MATCH_R2_I12 (LDHIO) +#define MASK_R2_LDHIO MASK_R2_I12 +#define MATCH_R2_LDHU MATCH_R2_OP (LDHU) +#define MASK_R2_LDHU MASK_R2_OP +#define MATCH_R2_LDHUIO MATCH_R2_I12 (LDHUIO) +#define MASK_R2_LDHUIO MASK_R2_I12 +#define MATCH_R2_LDHU_N MATCH_R2_OP (LDHU_N) +#define MASK_R2_LDHU_N MASK_R2_OP +#define MATCH_R2_LDSEX MATCH_R2_OPX (LDSEX, 0, 0, 0) +#define MASK_R2_LDSEX MASK_R2_OPX (0, 1, 0, 1) +#define MATCH_R2_LDW MATCH_R2_OP (LDW) +#define MASK_R2_LDW MASK_R2_OP +#define MATCH_R2_LDWIO MATCH_R2_I12 (LDWIO) +#define MASK_R2_LDWIO MASK_R2_I12 +#define MATCH_R2_LDWM MATCH_R2_I12 (LDWM) +#define MASK_R2_LDWM MASK_R2_I12 +#define MATCH_R2_LDWSP_N MATCH_R2_OP (LDWSP_N) +#define MASK_R2_LDWSP_N MASK_R2_OP +#define MATCH_R2_LDW_N MATCH_R2_OP (LDW_N) +#define MASK_R2_LDW_N MASK_R2_OP +#define MATCH_R2_MERGE MATCH_R2_OPX (MERGE, 0, 0, 0) +#define MASK_R2_MERGE MASK_R2_OPX (0, 0, 0, 0) +#define MATCH_R2_MOV MATCH_R2_OPX (ADD, 0, 0, 0) +#define MASK_R2_MOV MASK_R2_OPX (0, 1, 0, 1) +#define MATCH_R2_MOVHI MATCH_R2_OP (ORHI) | SET_IW_F2I16_A (0) +#define MASK_R2_MOVHI MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK +#define MATCH_R2_MOVI MATCH_R2_OP (ADDI) | SET_IW_F2I16_A (0) +#define MASK_R2_MOVI MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK +#define MATCH_R2_MOVUI MATCH_R2_OP (ORI) | SET_IW_F2I16_A (0) +#define MASK_R2_MOVUI MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK +#define MATCH_R2_MOV_N MATCH_R2_OP (MOV_N) +#define MASK_R2_MOV_N MASK_R2_OP +#define MATCH_R2_MOVI_N MATCH_R2_OP (MOVI_N) +#define MASK_R2_MOVI_N MASK_R2_OP +#define MATCH_R2_MUL MATCH_R2_OPX0 (MUL) +#define MASK_R2_MUL MASK_R2_OPX0 +#define MATCH_R2_MULI MATCH_R2_OP (MULI) +#define MASK_R2_MULI MASK_R2_OP +#define MATCH_R2_MULXSS MATCH_R2_OPX0 (MULXSS) +#define MASK_R2_MULXSS MASK_R2_OPX0 +#define MATCH_R2_MULXSU MATCH_R2_OPX0 (MULXSU) +#define MASK_R2_MULXSU MASK_R2_OPX0 +#define MATCH_R2_MULXUU MATCH_R2_OPX0 (MULXUU) +#define MASK_R2_MULXUU MASK_R2_OPX0 +#define MATCH_R2_NEG_N MATCH_R2_R_N (NEG_N) +#define MASK_R2_NEG_N MASK_R2_R_N +#define MATCH_R2_NEXTPC MATCH_R2_OPX (NEXTPC, 0, 0, 0) +#define MASK_R2_NEXTPC MASK_R2_OPX (1, 1, 0, 1) +#define MATCH_R2_NOP MATCH_R2_OPX (ADD, 0, 0, 0) +#define MASK_R2_NOP MASK_R2_OPX (1, 1, 1, 1) +#define MATCH_R2_NOP_N (MATCH_R2_OP (MOV_N) | SET_IW_F2_A (0) | SET_IW_F2_B (0)) +#define MASK_R2_NOP_N (MASK_R2_OP | IW_F2_A_SHIFTED_MASK | IW_F2_B_SHIFTED_MASK) +#define MATCH_R2_NOR MATCH_R2_OPX0 (NOR) +#define MASK_R2_NOR MASK_R2_OPX0 +#define MATCH_R2_NOT_N MATCH_R2_R_N (NOT_N) +#define MASK_R2_NOT_N MASK_R2_R_N +#define MATCH_R2_OR MATCH_R2_OPX0 (OR) +#define MASK_R2_OR MASK_R2_OPX0 +#define MATCH_R2_OR_N MATCH_R2_R_N (OR_N) +#define MASK_R2_OR_N MASK_R2_R_N +#define MATCH_R2_ORHI MATCH_R2_OP (ORHI) +#define MASK_R2_ORHI MASK_R2_OP +#define MATCH_R2_ORI MATCH_R2_OP (ORI) +#define MASK_R2_ORI MASK_R2_OP +#define MATCH_R2_POP_N (MATCH_R2_OP (PP_N) | SET_IW_L5I4X1_X (R2_PP_N_POP_N)) +#define MASK_R2_POP_N (MASK_R2_OP | IW_L5I4X1_X_SHIFTED_MASK) +#define MATCH_R2_PUSH_N (MATCH_R2_OP (PP_N) | SET_IW_L5I4X1_X (R2_PP_N_PUSH_N)) +#define MASK_R2_PUSH_N (MASK_R2_OP | IW_L5I4X1_X_SHIFTED_MASK) +#define MATCH_R2_RDCTL MATCH_R2_OPX (RDCTL, 0, 0, 0) +#define MASK_R2_RDCTL MASK_R2_OPX (1, 1, 0, 0) +#define MATCH_R2_RDPRS MATCH_R2_I12 (RDPRS) +#define MASK_R2_RDPRS MASK_R2_I12 +#define MATCH_R2_RET MATCH_R2_OPX (RET, 0x1f, 0, 0) +#define MASK_R2_RET MASK_R2_OPX (1, 1, 1, 1) +#define MATCH_R2_RET_N (MATCH_R2_R_N (RET_N) | SET_IW_X2L5_IMM5 (0)) +#define MASK_R2_RET_N (MASK_R2_R_N | IW_X2L5_IMM5_SHIFTED_MASK) +#define MATCH_R2_ROL MATCH_R2_OPX0 (ROL) +#define MASK_R2_ROL MASK_R2_OPX0 +#define MATCH_R2_ROLI MATCH_R2_OPX (ROLI, 0, 0, 0) +#define MASK_R2_ROLI MASK_R2_OPX (0, 1, 0, 0) +#define MATCH_R2_ROR MATCH_R2_OPX0 (ROR) +#define MASK_R2_ROR MASK_R2_OPX0 +#define MATCH_R2_SLL MATCH_R2_OPX0 (SLL) +#define MASK_R2_SLL MASK_R2_OPX0 +#define MATCH_R2_SLLI MATCH_R2_OPX (SLLI, 0, 0, 0) +#define MASK_R2_SLLI MASK_R2_OPX (0, 1, 0, 0) +#define MATCH_R2_SLL_N MATCH_R2_R_N (SLL_N) +#define MASK_R2_SLL_N MASK_R2_R_N +#define MATCH_R2_SLLI_N (MATCH_R2_OP (SHI_N) | SET_IW_T2X1L3_X (R2_SHI_N_SLLI_N)) +#define MASK_R2_SLLI_N (MASK_R2_OP | IW_T2X1L3_X_SHIFTED_MASK) +#define MATCH_R2_SPADDI_N MATCH_R2_OP (SPADDI_N) +#define MASK_R2_SPADDI_N MASK_R2_OP +#define MATCH_R2_SPDECI_N (MATCH_R2_OP (SPI_N) | SET_IW_X1I7_X (R2_SPI_N_SPDECI_N)) +#define MASK_R2_SPDECI_N (MASK_R2_OP | IW_X1I7_X_SHIFTED_MASK) +#define MATCH_R2_SPINCI_N (MATCH_R2_OP (SPI_N) | SET_IW_X1I7_X (R2_SPI_N_SPINCI_N)) +#define MASK_R2_SPINCI_N (MASK_R2_OP | IW_X1I7_X_SHIFTED_MASK) +#define MATCH_R2_SRA MATCH_R2_OPX0 (SRA) +#define MASK_R2_SRA MASK_R2_OPX0 +#define MATCH_R2_SRAI MATCH_R2_OPX (SRAI, 0, 0, 0) +#define MASK_R2_SRAI MASK_R2_OPX (0, 1, 0, 0) +#define MATCH_R2_SRL MATCH_R2_OPX0 (SRL) +#define MASK_R2_SRL MASK_R2_OPX0 +#define MATCH_R2_SRLI MATCH_R2_OPX (SRLI, 0, 0, 0) +#define MASK_R2_SRLI MASK_R2_OPX (0, 1, 0, 0) +#define MATCH_R2_SRL_N MATCH_R2_R_N (SRL_N) +#define MASK_R2_SRL_N MASK_R2_R_N +#define MATCH_R2_SRLI_N (MATCH_R2_OP (SHI_N) | SET_IW_T2X1L3_X (R2_SHI_N_SRLI_N)) +#define MASK_R2_SRLI_N (MASK_R2_OP | IW_T2X1L3_X_SHIFTED_MASK) +#define MATCH_R2_STB MATCH_R2_OP (STB) +#define MASK_R2_STB MASK_R2_OP +#define MATCH_R2_STBIO MATCH_R2_I12 (STBIO) +#define MASK_R2_STBIO MASK_R2_I12 +#define MATCH_R2_STB_N MATCH_R2_OP (STB_N) +#define MASK_R2_STB_N MASK_R2_OP +#define MATCH_R2_STBZ_N (MATCH_R2_OP (STZ_N) | SET_IW_T1X1I6_X (R2_STZ_N_STBZ_N)) +#define MASK_R2_STBZ_N (MASK_R2_OP | IW_T1X1I6_X_SHIFTED_MASK) +#define MATCH_R2_STEX MATCH_R2_OPX0 (STEX) +#define MASK_R2_STEX MASK_R2_OPX0 +#define MATCH_R2_STH MATCH_R2_OP (STH) +#define MASK_R2_STH MASK_R2_OP +#define MATCH_R2_STHIO MATCH_R2_I12 (STHIO) +#define MASK_R2_STHIO MASK_R2_I12 +#define MATCH_R2_STH_N MATCH_R2_OP (STH_N) +#define MASK_R2_STH_N MASK_R2_OP +#define MATCH_R2_STSEX MATCH_R2_OPX0 (STSEX) +#define MASK_R2_STSEX MASK_R2_OPX0 +#define MATCH_R2_STW MATCH_R2_OP (STW) +#define MASK_R2_STW MASK_R2_OP +#define MATCH_R2_STWIO MATCH_R2_I12 (STWIO) +#define MASK_R2_STWIO MASK_R2_I12 +#define MATCH_R2_STWM MATCH_R2_I12 (STWM) +#define MASK_R2_STWM MASK_R2_I12 +#define MATCH_R2_STWSP_N MATCH_R2_OP (STWSP_N) +#define MASK_R2_STWSP_N MASK_R2_OP +#define MATCH_R2_STW_N MATCH_R2_OP (STW_N) +#define MASK_R2_STW_N MASK_R2_OP +#define MATCH_R2_STWZ_N MATCH_R2_OP (STZ_N) +#define MASK_R2_STWZ_N MASK_R2_OP +#define MATCH_R2_SUB MATCH_R2_OPX0 (SUB) +#define MASK_R2_SUB MASK_R2_OPX0 +#define MATCH_R2_SUBI MATCH_R2_OP (ADDI) +#define MASK_R2_SUBI MASK_R2_OP +#define MATCH_R2_SUB_N (MATCH_R2_OP (AS_N) | SET_IW_T3X1_X (R2_AS_N_SUB_N)) +#define MASK_R2_SUB_N (MASK_R2_OP | IW_T3X1_X_SHIFTED_MASK) +#define MATCH_R2_SUBI_N (MATCH_R2_OP (ASI_N) | SET_IW_T2X1I3_X (R2_ASI_N_SUBI_N)) +#define MASK_R2_SUBI_N (MASK_R2_OP | IW_T2X1I3_X_SHIFTED_MASK) +#define MATCH_R2_SYNC MATCH_R2_OPX (SYNC, 0, 0, 0) +#define MASK_R2_SYNC MASK_R2_OPX (1, 1, 1, 1) +#define MATCH_R2_TRAP MATCH_R2_OPX (TRAP, 0, 0, 0x1d) +#define MASK_R2_TRAP MASK_R2_OPX (1, 1, 1, 0) +#define MATCH_R2_TRAP_N MATCH_R2_R_N (TRAP_N) +#define MASK_R2_TRAP_N MASK_R2_R_N +#define MATCH_R2_WRCTL MATCH_R2_OPX (WRCTL, 0, 0, 0) +#define MASK_R2_WRCTL MASK_R2_OPX (0, 1, 1, 0) +#define MATCH_R2_WRPIE MATCH_R2_OPX (WRPIE, 0, 0, 0) +#define MASK_R2_WRPIE MASK_R2_OPX (0, 1, 0, 1) +#define MATCH_R2_WRPRS MATCH_R2_OPX (WRPRS, 0, 0, 0) +#define MASK_R2_WRPRS MASK_R2_OPX (0, 1, 0, 1) +#define MATCH_R2_XOR MATCH_R2_OPX0 (XOR) +#define MASK_R2_XOR MASK_R2_OPX0 +#define MATCH_R2_XORHI MATCH_R2_OP (XORHI) +#define MASK_R2_XORHI MASK_R2_OP +#define MATCH_R2_XORI MATCH_R2_OP (XORI) +#define MASK_R2_XORI MASK_R2_OP +#define MATCH_R2_XOR_N MATCH_R2_R_N (XOR_N) +#define MASK_R2_XOR_N MASK_R2_R_N + +#endif /* _NIOS2R2_H */ + + diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 138536a..a3fbc43 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,25 @@ +2015-07-01 Sandra Loosemore <sandra@codesourcery.com> + Cesar Philippidis <cesar@codesourcery.com> + + * nios2-dis.c (nios2_extract_opcode): New. + (nios2_disassembler_state): New. + (nios2_find_opcode_hash): Use mach parameter to select correct + disassembler state. + (nios2_print_insn_arg): Extend to support new R2 argument letters + and formats. + (print_insn_nios2): Check for 16-bit instruction at end of memory. + * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes. + (NIOS2_NUM_OPCODES): Rename to... + (NIOS2_NUM_R1_OPCODES): This. + (nios2_r2_opcodes): New. + (NIOS2_NUM_R2_OPCODES): New. + (nios2_num_r2_opcodes): New. + (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New. + (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New. + (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New. + (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New. + (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New. + 2015-06-30 Amit Pawar <Amit.Pawar@amd.com> * i386-dis.c (OP_Mwaitx): New. diff --git a/opcodes/nios2-dis.c b/opcodes/nios2-dis.c index 80951f1..2735aad 100644 --- a/opcodes/nios2-dis.c +++ b/opcodes/nios2-dis.c @@ -55,7 +55,14 @@ nios2_r1_extract_opcode (unsigned int x) return GET_IW_R1_OP (x); } -/* Pseudo-ops are stored in a different table than regular instructions. */ +static unsigned int +nios2_r2_extract_opcode (unsigned int x) +{ + return GET_IW_R2_OP (x); +} + +/* We maintain separate hash tables for R1 and R2 opcodes, and pseudo-ops + are stored in a different table than regular instructions. */ typedef struct _nios2_disassembler_state { @@ -79,6 +86,17 @@ nios2_r1_disassembler_state = { 0 }; +static nios2_disassembler_state +nios2_r2_disassembler_state = { + nios2_r2_opcodes, + &nios2_num_r2_opcodes, + nios2_r2_extract_opcode, + {}, + {}, + NULL, + 0 +}; + /* Function to initialize the opcode hash table. */ static void nios2_init_opcode_hash (nios2_disassembler_state *state) @@ -155,13 +173,17 @@ nios2_init_opcode_hash (nios2_disassembler_state *state) /* Return a pointer to an nios2_opcode struct for a given instruction word OPCODE for bfd machine MACH, or NULL if there is an error. */ const struct nios2_opcode * -nios2_find_opcode_hash (unsigned long opcode, - unsigned long mach ATTRIBUTE_UNUSED) +nios2_find_opcode_hash (unsigned long opcode, unsigned long mach) { nios2_opcode_hash *entry; nios2_disassembler_state *state; - state = &nios2_r1_disassembler_state; + /* Select the right instruction set, hash tables, and opcode accessor + for the mach variant. */ + if (mach == bfd_mach_nios2r2) + state = &nios2_r2_disassembler_state; + else + state = &nios2_r1_disassembler_state; /* Build a hash table to shorten the search time. */ if (!state->init) @@ -260,19 +282,46 @@ nios2_print_insn_arg (const char *argptr, (*info->fprintf_func) (info->stream, "%c", *argptr); break; + case 'c': + /* Control register index. */ + switch (op->format) + { + case iw_r_type: + i = GET_IW_R_IMM5 (opcode); + break; + case iw_F3X6L5_type: + i = GET_IW_F3X6L5_IMM5 (opcode); + break; + default: + bad_opcode (op); + } + reg_base = nios2_control_regs (); + (*info->fprintf_func) (info->stream, "%s", reg_base[i].name); + break; + case 'd': + reg_base = nios2_regs; switch (op->format) { case iw_r_type: i = GET_IW_R_C (opcode); - reg_base = nios2_regs; break; case iw_custom_type: i = GET_IW_CUSTOM_C (opcode); if (GET_IW_CUSTOM_READC (opcode) == 0) reg_base = nios2_coprocessor_regs (); - else - reg_base = nios2_regs; + break; + case iw_F3X6L5_type: + case iw_F3X6_type: + i = GET_IW_F3X6L5_C (opcode); + break; + case iw_F3X8_type: + i = GET_IW_F3X8_C (opcode); + if (GET_IW_F3X8_READC (opcode) == 0) + reg_base = nios2_coprocessor_regs (); + break; + case iw_F2_type: + i = GET_IW_F2_B (opcode); break; default: bad_opcode (op); @@ -284,22 +333,52 @@ nios2_print_insn_arg (const char *argptr, break; case 's': + reg_base = nios2_regs; switch (op->format) { case iw_r_type: i = GET_IW_R_A (opcode); - reg_base = nios2_regs; break; case iw_i_type: i = GET_IW_I_A (opcode); - reg_base = nios2_regs; break; case iw_custom_type: i = GET_IW_CUSTOM_A (opcode); if (GET_IW_CUSTOM_READA (opcode) == 0) reg_base = nios2_coprocessor_regs (); - else - reg_base = nios2_regs; + break; + case iw_F2I16_type: + i = GET_IW_F2I16_A (opcode); + break; + case iw_F2X4I12_type: + i = GET_IW_F2X4I12_A (opcode); + break; + case iw_F1X4I12_type: + i = GET_IW_F1X4I12_A (opcode); + break; + case iw_F1X4L17_type: + i = GET_IW_F1X4L17_A (opcode); + break; + case iw_F3X6L5_type: + case iw_F3X6_type: + i = GET_IW_F3X6L5_A (opcode); + break; + case iw_F2X6L10_type: + i = GET_IW_F2X6L10_A (opcode); + break; + case iw_F3X8_type: + i = GET_IW_F3X8_A (opcode); + if (GET_IW_F3X8_READA (opcode) == 0) + reg_base = nios2_coprocessor_regs (); + break; + case iw_F1X1_type: + i = GET_IW_F1X1_A (opcode); + break; + case iw_F1I5_type: + i = 27; /* Implicit stack pointer reference. */ + break; + case iw_F2_type: + i = GET_IW_F2_A (opcode); break; default: bad_opcode (op); @@ -311,22 +390,46 @@ nios2_print_insn_arg (const char *argptr, break; case 't': + reg_base = nios2_regs; switch (op->format) { case iw_r_type: i = GET_IW_R_B (opcode); - reg_base = nios2_regs; break; case iw_i_type: i = GET_IW_I_B (opcode); - reg_base = nios2_regs; break; case iw_custom_type: i = GET_IW_CUSTOM_B (opcode); if (GET_IW_CUSTOM_READB (opcode) == 0) reg_base = nios2_coprocessor_regs (); - else - reg_base = nios2_regs; + break; + case iw_F2I16_type: + i = GET_IW_F2I16_B (opcode); + break; + case iw_F2X4I12_type: + i = GET_IW_F2X4I12_B (opcode); + break; + case iw_F3X6L5_type: + case iw_F3X6_type: + i = GET_IW_F3X6L5_B (opcode); + break; + case iw_F2X6L10_type: + i = GET_IW_F2X6L10_B (opcode); + break; + case iw_F3X8_type: + i = GET_IW_F3X8_B (opcode); + if (GET_IW_F3X8_READB (opcode) == 0) + reg_base = nios2_coprocessor_regs (); + break; + case iw_F1I5_type: + i = GET_IW_F1I5_B (opcode); + break; + case iw_F2_type: + i = GET_IW_F2_B (opcode); + break; + case iw_T1X1I6_type: + i = 0; break; default: bad_opcode (op); @@ -337,6 +440,110 @@ nios2_print_insn_arg (const char *argptr, (*info->fprintf_func) (info->stream, "unknown"); break; + case 'D': + switch (op->format) + { + case iw_T1I7_type: + i = GET_IW_T1I7_A3 (opcode); + break; + case iw_T2X1L3_type: + i = GET_IW_T2X1L3_B3 (opcode); + break; + case iw_T2X1I3_type: + i = GET_IW_T2X1I3_B3 (opcode); + break; + case iw_T3X1_type: + i = GET_IW_T3X1_C3 (opcode); + break; + case iw_T2X3_type: + if (op->num_args == 3) + i = GET_IW_T2X3_A3 (opcode); + else + i = GET_IW_T2X3_B3 (opcode); + break; + default: + bad_opcode (op); + } + i = nios2_r2_reg3_mappings[i]; + (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name); + break; + + case 'M': + /* 6-bit unsigned immediate with no shift. */ + switch (op->format) + { + case iw_T1X1I6_type: + i = GET_IW_T1X1I6_IMM6 (opcode); + break; + default: + bad_opcode (op); + } + (*info->fprintf_func) (info->stream, "%ld", i); + break; + + case 'N': + /* 6-bit unsigned immediate with 2-bit shift. */ + switch (op->format) + { + case iw_T1X1I6_type: + i = GET_IW_T1X1I6_IMM6 (opcode) << 2; + break; + default: + bad_opcode (op); + } + (*info->fprintf_func) (info->stream, "%ld", i); + break; + + case 'S': + switch (op->format) + { + case iw_T1I7_type: + i = GET_IW_T1I7_A3 (opcode); + break; + case iw_T2I4_type: + i = GET_IW_T2I4_A3 (opcode); + break; + case iw_T2X1L3_type: + i = GET_IW_T2X1L3_A3 (opcode); + break; + case iw_T2X1I3_type: + i = GET_IW_T2X1I3_A3 (opcode); + break; + case iw_T3X1_type: + i = GET_IW_T3X1_A3 (opcode); + break; + case iw_T2X3_type: + i = GET_IW_T2X3_A3 (opcode); + break; + case iw_T1X1I6_type: + i = GET_IW_T1X1I6_A3 (opcode); + break; + default: + bad_opcode (op); + } + i = nios2_r2_reg3_mappings[i]; + (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name); + break; + + case 'T': + switch (op->format) + { + case iw_T2I4_type: + i = GET_IW_T2I4_B3 (opcode); + break; + case iw_T3X1_type: + i = GET_IW_T3X1_B3 (opcode); + break; + case iw_T2X3_type: + i = GET_IW_T2X3_B3 (opcode); + break; + default: + bad_opcode (op); + } + i = nios2_r2_reg3_mappings[i]; + (*info->fprintf_func) (info->stream, "%s", nios2_regs[i].name); + break; + case 'i': /* 16-bit signed immediate. */ switch (op->format) @@ -344,6 +551,25 @@ nios2_print_insn_arg (const char *argptr, case iw_i_type: i = (signed) (GET_IW_I_IMM16 (opcode) << 16) >> 16; break; + case iw_F2I16_type: + i = (signed) (GET_IW_F2I16_IMM16 (opcode) << 16) >> 16; + break; + default: + bad_opcode (op); + } + (*info->fprintf_func) (info->stream, "%ld", i); + break; + + case 'I': + /* 12-bit signed immediate. */ + switch (op->format) + { + case iw_F2X4I12_type: + i = (signed) (GET_IW_F2X4I12_IMM12 (opcode) << 20) >> 20; + break; + case iw_F1X4I12_type: + i = (signed) (GET_IW_F1X4I12_IMM12 (opcode) << 20) >> 20; + break; default: bad_opcode (op); } @@ -357,6 +583,80 @@ nios2_print_insn_arg (const char *argptr, case iw_i_type: i = GET_IW_I_IMM16 (opcode); break; + case iw_F2I16_type: + i = GET_IW_F2I16_IMM16 (opcode); + break; + default: + bad_opcode (op); + } + (*info->fprintf_func) (info->stream, "%ld", i); + break; + + case 'U': + /* 7-bit unsigned immediate with 2-bit shift. */ + switch (op->format) + { + case iw_T1I7_type: + i = GET_IW_T1I7_IMM7 (opcode) << 2; + break; + case iw_X1I7_type: + i = GET_IW_X1I7_IMM7 (opcode) << 2; + break; + default: + bad_opcode (op); + } + (*info->fprintf_func) (info->stream, "%ld", i); + break; + + case 'V': + /* 5-bit unsigned immediate with 2-bit shift. */ + switch (op->format) + { + case iw_F1I5_type: + i = GET_IW_F1I5_IMM5 (opcode) << 2; + break; + default: + bad_opcode (op); + } + (*info->fprintf_func) (info->stream, "%ld", i); + break; + + case 'W': + /* 4-bit unsigned immediate with 2-bit shift. */ + switch (op->format) + { + case iw_T2I4_type: + i = GET_IW_T2I4_IMM4 (opcode) << 2; + break; + case iw_L5I4X1_type: + i = GET_IW_L5I4X1_IMM4 (opcode) << 2; + break; + default: + bad_opcode (op); + } + (*info->fprintf_func) (info->stream, "%ld", i); + break; + + case 'X': + /* 4-bit unsigned immediate with 1-bit shift. */ + switch (op->format) + { + case iw_T2I4_type: + i = GET_IW_T2I4_IMM4 (opcode) << 1; + break; + default: + bad_opcode (op); + } + (*info->fprintf_func) (info->stream, "%ld", i); + break; + + case 'Y': + /* 4-bit unsigned immediate without shift. */ + switch (op->format) + { + case iw_T2I4_type: + i = GET_IW_T2I4_IMM4 (opcode); + break; default: bad_opcode (op); } @@ -370,6 +670,9 @@ nios2_print_insn_arg (const char *argptr, case iw_i_type: i = (signed) (GET_IW_I_IMM16 (opcode) << 16) >> 16; break; + case iw_F2I16_type: + i = (signed) (GET_IW_F2I16_IMM16 (opcode) << 16) >> 16; + break; default: bad_opcode (op); } @@ -377,6 +680,34 @@ nios2_print_insn_arg (const char *argptr, (*info->print_address_func) (address, info); break; + case 'O': + /* 10-bit signed address offset with 1-bit shift. */ + switch (op->format) + { + case iw_I10_type: + i = (signed) (GET_IW_I10_IMM10 (opcode) << 22) >> 21; + break; + default: + bad_opcode (op); + } + address = address + 2 + i; + (*info->print_address_func) (address, info); + break; + + case 'P': + /* 7-bit signed address offset with 1-bit shift. */ + switch (op->format) + { + case iw_T1I7_type: + i = (signed) (GET_IW_T1I7_IMM7 (opcode) << 25) >> 24; + break; + default: + bad_opcode (op); + } + address = address + 2 + i; + (*info->print_address_func) (address, info); + break; + case 'j': /* 5-bit unsigned immediate. */ switch (op->format) @@ -384,6 +715,28 @@ nios2_print_insn_arg (const char *argptr, case iw_r_type: i = GET_IW_R_IMM5 (opcode); break; + case iw_F3X6L5_type: + i = GET_IW_F3X6L5_IMM5 (opcode); + break; + case iw_F2X6L10_type: + i = GET_IW_F2X6L10_MSB (opcode); + break; + case iw_X2L5_type: + i = GET_IW_X2L5_IMM5 (opcode); + break; + default: + bad_opcode (op); + } + (*info->fprintf_func) (info->stream, "%ld", i); + break; + + case 'k': + /* Second 5-bit unsigned immediate field. */ + switch (op->format) + { + case iw_F2X6L10_type: + i = GET_IW_F2X6L10_LSB (opcode); + break; default: bad_opcode (op); } @@ -397,6 +750,9 @@ nios2_print_insn_arg (const char *argptr, case iw_custom_type: i = GET_IW_CUSTOM_N (opcode); break; + case iw_F3X8_type: + i = GET_IW_F3X8_N (opcode); + break; default: bad_opcode (op); } @@ -410,6 +766,9 @@ nios2_print_insn_arg (const char *argptr, case iw_j_type: i = GET_IW_J_IMM26 (opcode); break; + case iw_L26_type: + i = GET_IW_L26_IMM26 (opcode); + break; default: bad_opcode (op); } @@ -419,18 +778,144 @@ nios2_print_insn_arg (const char *argptr, (*info->print_address_func) (address, info); break; - case 'c': - /* Control register index. */ + case 'e': + /* Encoded enumeration for addi.n/subi.n. */ switch (op->format) { - case iw_r_type: - i = GET_IW_R_IMM5 (opcode); + case iw_T2X1I3_type: + i = nios2_r2_asi_n_mappings[GET_IW_T2X1I3_IMM3 (opcode)]; + break; + default: + bad_opcode (op); + } + (*info->fprintf_func) (info->stream, "%lu", i); + break; + + case 'f': + /* Encoded enumeration for slli.n/srli.n. */ + switch (op->format) + { + case iw_T2X1L3_type: + i = nios2_r2_shi_n_mappings[GET_IW_T2X1I3_IMM3 (opcode)]; + break; + default: + bad_opcode (op); + } + (*info->fprintf_func) (info->stream, "%lu", i); + break; + + case 'g': + /* Encoded enumeration for andi.n. */ + switch (op->format) + { + case iw_T2I4_type: + i = nios2_r2_andi_n_mappings[GET_IW_T2I4_IMM4 (opcode)]; + break; + default: + bad_opcode (op); + } + (*info->fprintf_func) (info->stream, "%lu", i); + break; + + case 'h': + /* Encoded enumeration for movi.n. */ + switch (op->format) + { + case iw_T1I7_type: + i = GET_IW_T1I7_IMM7 (opcode); + if (i == 125) + i = 0xff; + else if (i == 126) + i = -2; + else if (i == 127) + i = -1; + break; + default: + bad_opcode (op); + } + (*info->fprintf_func) (info->stream, "%ld", i); + break; + + case 'R': + { + unsigned long reglist = 0; + int dir = 1; + int k, t; + + switch (op->format) + { + case iw_F1X4L17_type: + /* Encoding for ldwm/stwm. */ + i = GET_IW_F1X4L17_REGMASK (opcode); + if (GET_IW_F1X4L17_RS (opcode)) + { + reglist = ((i << 14) & 0x00ffc000); + if (i & (1 << 10)) + reglist |= (1 << 28); + if (i & (1 << 11)) + reglist |= (1 << 31); + } + else + reglist = i << 2; + dir = GET_IW_F1X4L17_REGMASK (opcode) ? 1 : -1; + break; + + case iw_L5I4X1_type: + /* Encoding for push.n/pop.n. */ + reglist |= (1 << 31); + if (GET_IW_L5I4X1_FP (opcode)) + reglist |= (1 << 28); + if (GET_IW_L5I4X1_CS (opcode)) + { + int val = GET_IW_L5I4X1_REGRANGE (opcode); + reglist |= nios2_r2_reg_range_mappings[val]; + } + dir = (op->match == MATCH_R2_POP_N ? 1 : -1); + break; + + default: + bad_opcode (op); + } + + t = 0; + (*info->fprintf_func) (info->stream, "{"); + for (k = (dir == 1 ? 0 : 31); + (dir == 1 && k < 32) || (dir == -1 && k >= 0); + k += dir) + if (reglist & (1 << k)) + { + if (t) + (*info->fprintf_func) (info->stream, ","); + else + t++; + (*info->fprintf_func) (info->stream, "%s", nios2_regs[k].name); + } + (*info->fprintf_func) (info->stream, "}"); + break; + } + + case 'B': + /* Base register and options for ldwm/stwm. */ + switch (op->format) + { + case iw_F1X4L17_type: + if (GET_IW_F1X4L17_ID (opcode) == 0) + (*info->fprintf_func) (info->stream, "--"); + + i = GET_IW_F1X4I12_A (opcode); + (*info->fprintf_func) (info->stream, "(%s)", + nios2_builtin_regs[i].name); + + if (GET_IW_F1X4L17_ID (opcode)) + (*info->fprintf_func) (info->stream, "++"); + if (GET_IW_F1X4L17_WB (opcode)) + (*info->fprintf_func) (info->stream, ",writeback"); + if (GET_IW_F1X4L17_PC (opcode)) + (*info->fprintf_func) (info->stream, ",ret"); break; default: bad_opcode (op); } - reg_base = nios2_control_regs (); - (*info->fprintf_func) (info->stream, "%s", reg_base[i].name); break; default: @@ -512,14 +997,27 @@ print_insn_nios2 (bfd_vma address, disassemble_info *info, insn = (unsigned long) bfd_getb32 (buffer); else insn = (unsigned long) bfd_getl32 (buffer); - status = nios2_disassemble (address, insn, info); + return nios2_disassemble (address, insn, info); } - else + + /* We might have a 16-bit R2 instruction at the end of memory. Try that. */ + if (info->mach == bfd_mach_nios2r2) { - (*info->memory_error_func) (status, address, info); - status = -1; + status = (*info->read_memory_func) (address, buffer, 2, info); + if (status == 0) + { + unsigned long insn; + if (endianness == BFD_ENDIAN_BIG) + insn = (unsigned long) bfd_getb16 (buffer); + else + insn = (unsigned long) bfd_getl16 (buffer); + return nios2_disassemble (address, insn, info); + } } - return status; + + /* If we got here, we couldn't read anything. */ + (*info->memory_error_func) (status, address, info); + return -1; } /* These two functions are the main entry points, accessed from diff --git a/opcodes/nios2-opc.c b/opcodes/nios2-opc.c index d5ec06f..d119f9a 100644 --- a/opcodes/nios2-opc.c +++ b/opcodes/nios2-opc.c @@ -30,36 +30,36 @@ const struct nios2_reg nios2_builtin_regs[] = { /* Standard register names. */ {"zero", 0, REG_NORMAL}, {"at", 1, REG_NORMAL}, /* assembler temporary */ - {"r2", 2, REG_NORMAL}, - {"r3", 3, REG_NORMAL}, - {"r4", 4, REG_NORMAL}, - {"r5", 5, REG_NORMAL}, - {"r6", 6, REG_NORMAL}, - {"r7", 7, REG_NORMAL}, - {"r8", 8, REG_NORMAL}, - {"r9", 9, REG_NORMAL}, - {"r10", 10, REG_NORMAL}, - {"r11", 11, REG_NORMAL}, - {"r12", 12, REG_NORMAL}, - {"r13", 13, REG_NORMAL}, - {"r14", 14, REG_NORMAL}, - {"r15", 15, REG_NORMAL}, - {"r16", 16, REG_NORMAL}, - {"r17", 17, REG_NORMAL}, - {"r18", 18, REG_NORMAL}, - {"r19", 19, REG_NORMAL}, - {"r20", 20, REG_NORMAL}, - {"r21", 21, REG_NORMAL}, - {"r22", 22, REG_NORMAL}, - {"r23", 23, REG_NORMAL}, + {"r2", 2, REG_NORMAL | REG_3BIT | REG_LDWM}, + {"r3", 3, REG_NORMAL | REG_3BIT | REG_LDWM}, + {"r4", 4, REG_NORMAL | REG_3BIT | REG_LDWM}, + {"r5", 5, REG_NORMAL | REG_3BIT | REG_LDWM}, + {"r6", 6, REG_NORMAL | REG_3BIT | REG_LDWM}, + {"r7", 7, REG_NORMAL | REG_3BIT | REG_LDWM}, + {"r8", 8, REG_NORMAL | REG_LDWM}, + {"r9", 9, REG_NORMAL | REG_LDWM}, + {"r10", 10, REG_NORMAL | REG_LDWM}, + {"r11", 11, REG_NORMAL | REG_LDWM}, + {"r12", 12, REG_NORMAL | REG_LDWM}, + {"r13", 13, REG_NORMAL | REG_LDWM}, + {"r14", 14, REG_NORMAL | REG_LDWM}, + {"r15", 15, REG_NORMAL | REG_LDWM}, + {"r16", 16, REG_NORMAL | REG_3BIT | REG_LDWM | REG_POP}, + {"r17", 17, REG_NORMAL | REG_3BIT | REG_LDWM | REG_POP}, + {"r18", 18, REG_NORMAL | REG_LDWM | REG_POP}, + {"r19", 19, REG_NORMAL | REG_LDWM | REG_POP}, + {"r20", 20, REG_NORMAL | REG_LDWM | REG_POP}, + {"r21", 21, REG_NORMAL | REG_LDWM | REG_POP}, + {"r22", 22, REG_NORMAL | REG_LDWM | REG_POP}, + {"r23", 23, REG_NORMAL | REG_LDWM | REG_POP}, {"et", 24, REG_NORMAL}, {"bt", 25, REG_NORMAL}, {"gp", 26, REG_NORMAL}, /* global pointer */ {"sp", 27, REG_NORMAL}, /* stack pointer */ - {"fp", 28, REG_NORMAL}, /* frame pointer */ + {"fp", 28, REG_NORMAL | REG_LDWM | REG_POP}, /* frame pointer */ {"ea", 29, REG_NORMAL}, /* exception return address */ {"sstatus", 30, REG_NORMAL}, /* saved processor status */ - {"ra", 31, REG_NORMAL}, /* return address */ + {"ra", 31, REG_NORMAL | REG_LDWM | REG_POP}, /* return address */ /* Alternative names for special registers. */ {"r0", 0, REG_NORMAL}, @@ -68,11 +68,11 @@ const struct nios2_reg nios2_builtin_regs[] = { {"r25", 25, REG_NORMAL}, {"r26", 26, REG_NORMAL}, {"r27", 27, REG_NORMAL}, - {"r28", 28, REG_NORMAL}, + {"r28", 28, REG_NORMAL | REG_LDWM | REG_POP}, {"r29", 29, REG_NORMAL}, {"r30", 30, REG_NORMAL}, {"ba", 30, REG_NORMAL}, /* breakpoint return address */ - {"r31", 31, REG_NORMAL}, + {"r31", 31, REG_NORMAL | REG_LDWM | REG_POP}, /* Control register names. */ {"status", 0, REG_CONTROL}, @@ -398,10 +398,386 @@ const struct nios2_opcode nios2_r1_opcodes[] = MATCH_R1_XORI, MASK_R1_XORI, 0, unsigned_immed16_overflow} }; -#define NIOS2_NUM_OPCODES \ +#define NIOS2_NUM_R1_OPCODES \ ((sizeof nios2_r1_opcodes) / (sizeof (nios2_r1_opcodes[0]))) -const int nios2_num_r1_opcodes = NIOS2_NUM_OPCODES; +const int nios2_num_r1_opcodes = NIOS2_NUM_R1_OPCODES; + +const struct nios2_opcode nios2_r2_opcodes[] = +{ + /* { name, args, args_test, num_args, size, format, + match, mask, pinfo, overflow } */ + {"add", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_ADD, MASK_R2_ADD, 0, no_overflow}, + {"addi", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, + MATCH_R2_ADDI, MASK_R2_ADDI, 0, signed_immed16_overflow}, + {"add.n", "D,S,T", "D,S,T,E", 3, 2, iw_T3X1_type, + MATCH_R2_ADD_N, MASK_R2_ADD_N, 0, no_overflow}, + {"addi.n", "D,S,e", "D,S,e,E", 3, 2, iw_T2X1I3_type, + MATCH_R2_ADDI_N, MASK_R2_ADDI_N, 0, enumeration_overflow}, + {"and", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_AND, MASK_R2_AND, 0, no_overflow}, + {"andchi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, + MATCH_R2_ANDCHI, MASK_R2_ANDCHI, 0, unsigned_immed16_overflow}, + {"andci", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, + MATCH_R2_ANDCI, MASK_R2_ANDCI, 0, unsigned_immed16_overflow}, + {"andhi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, + MATCH_R2_ANDHI, MASK_R2_ANDHI, 0, unsigned_immed16_overflow}, + {"andi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, + MATCH_R2_ANDI, MASK_R2_ANDI, 0, unsigned_immed16_overflow}, + {"andi.n", "T,S,g", "T,S,g,E", 3, 2, iw_T2I4_type, + MATCH_R2_ANDI_N, MASK_R2_ANDI_N, 0, enumeration_overflow}, + {"and.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type, + MATCH_R2_AND_N, MASK_R2_AND_N, 0, no_overflow}, + {"beq", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, + MATCH_R2_BEQ, MASK_R2_BEQ, NIOS2_INSN_CBRANCH, branch_target_overflow}, + {"beqz.n", "S,P", "S,P,E", 2, 2, iw_T1I7_type, + MATCH_R2_BEQZ_N, MASK_R2_BEQZ_N, NIOS2_INSN_CBRANCH, branch_target_overflow}, + {"bge", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, + MATCH_R2_BGE, MASK_R2_BGE, NIOS2_INSN_CBRANCH, branch_target_overflow}, + {"bgeu", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, + MATCH_R2_BGEU, MASK_R2_BGEU, NIOS2_INSN_CBRANCH, branch_target_overflow}, + {"bgt", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, + MATCH_R2_BGT, MASK_R2_BGT, + NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, + {"bgtu", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, + MATCH_R2_BGTU, MASK_R2_BGTU, + NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, + {"ble", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, + MATCH_R2_BLE, MASK_R2_BLE, + NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, + {"bleu", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, + MATCH_R2_BLEU, MASK_R2_BLEU, + NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow}, + {"blt", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, + MATCH_R2_BLT, MASK_R2_BLT, NIOS2_INSN_CBRANCH, branch_target_overflow}, + {"bltu", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, + MATCH_R2_BLTU, MASK_R2_BLTU, NIOS2_INSN_CBRANCH, branch_target_overflow}, + {"bne", "s,t,o", "s,t,o,E", 3, 4, iw_F2I16_type, + MATCH_R2_BNE, MASK_R2_BNE, NIOS2_INSN_CBRANCH, branch_target_overflow}, + {"bnez.n", "S,P", "S,P,E", 2, 2, iw_T1I7_type, + MATCH_R2_BNEZ_N, MASK_R2_BNEZ_N, NIOS2_INSN_CBRANCH, branch_target_overflow}, + {"br", "o", "o,E", 1, 4, iw_F2I16_type, + MATCH_R2_BR, MASK_R2_BR, NIOS2_INSN_UBRANCH, branch_target_overflow}, + {"break", "j", "j,E", 1, 4, iw_F3X6L5_type, + MATCH_R2_BREAK, MASK_R2_BREAK, NIOS2_INSN_OPTARG, no_overflow}, + {"break.n", "j", "j,E", 1, 2, iw_X2L5_type, + MATCH_R2_BREAK_N, MASK_R2_BREAK_N, NIOS2_INSN_OPTARG, no_overflow}, + {"bret", "", "E", 0, 4, iw_F3X6_type, + MATCH_R2_BRET, MASK_R2_BRET, 0, no_overflow}, + {"br.n", "O", "O,E", 1, 2, iw_I10_type, + MATCH_R2_BR_N, MASK_R2_BR_N, NIOS2_INSN_UBRANCH, branch_target_overflow}, + {"call", "m", "m,E", 1, 4, iw_L26_type, + MATCH_R2_CALL, MASK_R2_CALL, NIOS2_INSN_CALL, call_target_overflow}, + {"callr", "s", "s,E", 1, 4, iw_F3X6_type, + MATCH_R2_CALLR, MASK_R2_CALLR, 0, no_overflow}, + {"callr.n", "s", "s,E", 1, 2, iw_F1X1_type, + MATCH_R2_CALLR_N, MASK_R2_CALLR_N, 0, no_overflow}, + {"cmpeq", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_CMPEQ, MASK_R2_CMPEQ, 0, no_overflow}, + {"cmpeqi", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, + MATCH_R2_CMPEQI, MASK_R2_CMPEQI, 0, signed_immed16_overflow}, + {"cmpge", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_CMPGE, MASK_R2_CMPGE, 0, no_overflow}, + {"cmpgei", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, + MATCH_R2_CMPGEI, MASK_R2_CMPGEI, 0, signed_immed16_overflow}, + {"cmpgeu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_CMPGEU, MASK_R2_CMPGEU, 0, no_overflow}, + {"cmpgeui", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, + MATCH_R2_CMPGEUI, MASK_R2_CMPGEUI, 0, unsigned_immed16_overflow}, + {"cmpgt", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_CMPGT, MASK_R2_CMPGT, NIOS2_INSN_MACRO, no_overflow}, + {"cmpgti", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, + MATCH_R2_CMPGTI, MASK_R2_CMPGTI, NIOS2_INSN_MACRO, signed_immed16_overflow}, + {"cmpgtu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_CMPGTU, MASK_R2_CMPGTU, NIOS2_INSN_MACRO, no_overflow}, + {"cmpgtui", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, + MATCH_R2_CMPGTUI, MASK_R2_CMPGTUI, + NIOS2_INSN_MACRO, unsigned_immed16_overflow}, + {"cmple", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_CMPLE, MASK_R2_CMPLE, NIOS2_INSN_MACRO, no_overflow}, + {"cmplei", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, + MATCH_R2_CMPLEI, MASK_R2_CMPLEI, NIOS2_INSN_MACRO, signed_immed16_overflow}, + {"cmpleu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_CMPLEU, MASK_R2_CMPLEU, NIOS2_INSN_MACRO, no_overflow}, + {"cmpleui", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, + MATCH_R2_CMPLEUI, MASK_R2_CMPLEUI, + NIOS2_INSN_MACRO, unsigned_immed16_overflow}, + {"cmplt", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_CMPLT, MASK_R2_CMPLT, 0, no_overflow}, + {"cmplti", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, + MATCH_R2_CMPLTI, MASK_R2_CMPLTI, 0, signed_immed16_overflow}, + {"cmpltu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_CMPLTU, MASK_R2_CMPLTU, 0, no_overflow}, + {"cmpltui", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, + MATCH_R2_CMPLTUI, MASK_R2_CMPLTUI, 0, unsigned_immed16_overflow}, + {"cmpne", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_CMPNE, MASK_R2_CMPNE, 0, no_overflow}, + {"cmpnei", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, + MATCH_R2_CMPNEI, MASK_R2_CMPNEI, 0, signed_immed16_overflow}, + {"custom", "l,d,s,t", "l,d,s,t,E", 4, 4, iw_F3X8_type, + MATCH_R2_CUSTOM, MASK_R2_CUSTOM, 0, custom_opcode_overflow}, + {"div", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_DIV, MASK_R2_DIV, 0, no_overflow}, + {"divu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_DIVU, MASK_R2_DIVU, 0, no_overflow}, + {"eni", "j", "j,E", 1, 4, iw_F3X6L5_type, + MATCH_R2_ENI, MASK_R2_ENI, NIOS2_INSN_OPTARG, no_overflow}, + {"eret", "", "E", 0, 4, iw_F3X6_type, + MATCH_R2_ERET, MASK_R2_ERET, 0, no_overflow}, + {"extract", "t,s,j,k", "t,s,j,k,E", 4, 4, iw_F2X6L10_type, + MATCH_R2_EXTRACT, MASK_R2_EXTRACT, 0, no_overflow}, + {"flushd", "I(s)", "I(s),E", 2, 4, iw_F1X4I12_type, + MATCH_R2_FLUSHD, MASK_R2_FLUSHD, 0, address_offset_overflow}, + {"flushda", "I(s)", "I(s),E", 2, 4, iw_F1X4I12_type, + MATCH_R2_FLUSHDA, MASK_R2_FLUSHDA, 0, address_offset_overflow}, + {"flushi", "s", "s,E", 1, 4, iw_F3X6_type, + MATCH_R2_FLUSHI, MASK_R2_FLUSHI, 0, no_overflow}, + {"flushp", "", "E", 0, 4, iw_F3X6_type, + MATCH_R2_FLUSHP, MASK_R2_FLUSHP, 0, no_overflow}, + {"initd", "I(s)", "I(s),E", 2, 4, iw_F1X4I12_type, + MATCH_R2_INITD, MASK_R2_INITD, 0, address_offset_overflow}, + {"initda", "I(s)", "I(s),E", 2, 4, iw_F1X4I12_type, + MATCH_R2_INITDA, MASK_R2_INITDA, 0, address_offset_overflow}, + {"initi", "s", "s,E", 1, 4, iw_F3X6_type, + MATCH_R2_INITI, MASK_R2_INITI, 0, no_overflow}, + {"insert", "t,s,j,k", "t,s,j,k,E", 4, 4, iw_F2X6L10_type, + MATCH_R2_INSERT, MASK_R2_INSERT, 0, no_overflow}, + {"jmp", "s", "s,E", 1, 4, iw_F3X6_type, + MATCH_R2_JMP, MASK_R2_JMP, 0, no_overflow}, + {"jmpi", "m", "m,E", 1, 4, iw_L26_type, + MATCH_R2_JMPI, MASK_R2_JMPI, 0, call_target_overflow}, + {"jmpr.n", "s", "s,E", 1, 2, iw_F1X1_type, + MATCH_R2_JMPR_N, MASK_R2_JMPR_N, 0, no_overflow}, + {"ldb", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, + MATCH_R2_LDB, MASK_R2_LDB, 0, address_offset_overflow}, + {"ldbio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, + MATCH_R2_LDBIO, MASK_R2_LDBIO, 0, signed_immed12_overflow}, + {"ldbu", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, + MATCH_R2_LDBU, MASK_R2_LDBU, 0, address_offset_overflow}, + {"ldbuio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, + MATCH_R2_LDBUIO, MASK_R2_LDBUIO, 0, signed_immed12_overflow}, + {"ldbu.n", "T,Y(S)", "T,Y(S),E", 3, 2, iw_T2I4_type, + MATCH_R2_LDBU_N, MASK_R2_LDBU_N, 0, address_offset_overflow}, + {"ldex", "d,(s)", "d,(s),E", 2, 4, iw_F3X6_type, + MATCH_R2_LDEX, MASK_R2_LDEX, 0, no_overflow}, + {"ldh", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, + MATCH_R2_LDH, MASK_R2_LDH, 0, address_offset_overflow}, + {"ldhio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, + MATCH_R2_LDHIO, MASK_R2_LDHIO, 0, signed_immed12_overflow}, + {"ldhu", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, + MATCH_R2_LDHU, MASK_R2_LDHU, 0, address_offset_overflow}, + {"ldhuio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, + MATCH_R2_LDHUIO, MASK_R2_LDHUIO, 0, signed_immed12_overflow}, + {"ldhu.n", "T,X(S)", "T,X(S),E", 3, 2, iw_T2I4_type, + MATCH_R2_LDHU_N, MASK_R2_LDHU_N, 0, address_offset_overflow}, + {"ldsex", "d,(s)", "d,(s),E", 2, 4, iw_F3X6_type, + MATCH_R2_LDSEX, MASK_R2_LDSEX, 0, no_overflow}, + {"ldw", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, + MATCH_R2_LDW, MASK_R2_LDW, 0, address_offset_overflow}, + {"ldwio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, + MATCH_R2_LDWIO, MASK_R2_LDWIO, 0, signed_immed12_overflow}, + {"ldwm", "R,B", "R,B,E", 2, 4, iw_F1X4L17_type, + MATCH_R2_LDWM, MASK_R2_LDWM, 0, no_overflow}, + {"ldw.n", "T,W(S)", "T,W(S),E", 3, 2, iw_T2I4_type, + MATCH_R2_LDW_N, MASK_R2_LDW_N, 0, address_offset_overflow}, + {"ldwsp.n", "t,V(s)", "t,V(s),E", 3, 2, iw_F1I5_type, + MATCH_R2_LDWSP_N, MASK_R2_LDWSP_N, 0, address_offset_overflow}, + {"merge", "t,s,j,k", "t,s,j,k,E", 4, 4, iw_F2X6L10_type, + MATCH_R2_MERGE, MASK_R2_MERGE, 0, no_overflow}, + {"mov", "d,s", "d,s,E", 2, 4, iw_F3X6_type, + MATCH_R2_MOV, MASK_R2_MOV, NIOS2_INSN_MACRO_MOV, no_overflow}, + {"mov.n", "d,s", "d,s,E", 2, 2, iw_F2_type, + MATCH_R2_MOV_N, MASK_R2_MOV_N, 0, no_overflow}, + {"movi.n", "D,h", "D,h,E", 2, 2, iw_T1I7_type, + MATCH_R2_MOVI_N, MASK_R2_MOVI_N, 0, enumeration_overflow}, + {"movhi", "t,u", "t,u,E", 2, 4, iw_F2I16_type, + MATCH_R2_MOVHI, MASK_R2_MOVHI, + NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow}, + {"movi", "t,i", "t,i,E", 2, 4, iw_F2I16_type, + MATCH_R2_MOVI, MASK_R2_MOVI, NIOS2_INSN_MACRO_MOVI, signed_immed16_overflow}, + {"movia", "t,o", "t,o,E", 2, 4, iw_F2I16_type, + MATCH_R2_ORHI, MASK_R2_ORHI, NIOS2_INSN_MACRO_MOVIA, no_overflow}, + {"movui", "t,u", "t,u,E", 2, 4, iw_F2I16_type, + MATCH_R2_MOVUI, MASK_R2_MOVUI, + NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow}, + {"mul", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_MUL, MASK_R2_MUL, 0, no_overflow}, + {"muli", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, + MATCH_R2_MULI, MASK_R2_MULI, 0, signed_immed16_overflow}, + {"mulxss", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_MULXSS, MASK_R2_MULXSS, 0, no_overflow}, + {"mulxsu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_MULXSU, MASK_R2_MULXSU, 0, no_overflow}, + {"mulxuu", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_MULXUU, MASK_R2_MULXUU, 0, no_overflow}, + /* The encoding of the neg.n operands is backwards, not + the interpretation -- the first operand is still the + destination and the second the source. */ + {"neg.n", "S,D", "S,D,E", 2, 2, iw_T2X3_type, + MATCH_R2_NEG_N, MASK_R2_NEG_N, 0, no_overflow}, + {"nextpc", "d", "d,E", 1, 4, iw_F3X6_type, + MATCH_R2_NEXTPC, MASK_R2_NEXTPC, 0, no_overflow}, + {"nop", "", "E", 0, 4, iw_F3X6_type, + MATCH_R2_NOP, MASK_R2_NOP, NIOS2_INSN_MACRO_MOV, no_overflow}, + {"nop.n", "", "E", 0, 2, iw_F2_type, + MATCH_R2_NOP_N, MASK_R2_NOP_N, NIOS2_INSN_MACRO_MOV, no_overflow}, + {"nor", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_NOR, MASK_R2_NOR, 0, no_overflow}, + {"not.n", "D,S", "D,S,E", 2, 2, iw_T2X3_type, + MATCH_R2_NOT_N, MASK_R2_NOT_N, 0, no_overflow}, + {"or", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_OR, MASK_R2_OR, 0, no_overflow}, + {"orhi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, + MATCH_R2_ORHI, MASK_R2_ORHI, 0, unsigned_immed16_overflow}, + {"ori", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, + MATCH_R2_ORI, MASK_R2_ORI, 0, unsigned_immed16_overflow}, + {"or.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type, + MATCH_R2_OR_N, MASK_R2_OR_N, 0, no_overflow}, + {"pop.n", "R,W", "R,W,E", 2, 2, iw_L5I4X1_type, + MATCH_R2_POP_N, MASK_R2_POP_N, NIOS2_INSN_OPTARG, no_overflow}, + {"push.n", "R,W", "R,W,E", 2, 2, iw_L5I4X1_type, + MATCH_R2_PUSH_N, MASK_R2_PUSH_N, NIOS2_INSN_OPTARG, no_overflow}, + {"rdctl", "d,c", "d,c,E", 2, 4, iw_F3X6L5_type, + MATCH_R2_RDCTL, MASK_R2_RDCTL, 0, no_overflow}, + {"rdprs", "t,s,I", "t,s,I,E", 3, 4, iw_F2X4I12_type, + MATCH_R2_RDPRS, MASK_R2_RDPRS, 0, signed_immed12_overflow}, + {"ret", "", "E", 0, 4, iw_F3X6_type, + MATCH_R2_RET, MASK_R2_RET, 0, no_overflow}, + {"ret.n", "", "E", 0, 2, iw_X2L5_type, + MATCH_R2_RET_N, MASK_R2_RET_N, 0, no_overflow}, + {"rol", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_ROL, MASK_R2_ROL, 0, no_overflow}, + {"roli", "d,s,j", "d,s,j,E", 3, 4, iw_F3X6L5_type, + MATCH_R2_ROLI, MASK_R2_ROLI, 0, unsigned_immed5_overflow}, + {"ror", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_ROR, MASK_R2_ROR, 0, no_overflow}, + {"sll", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_SLL, MASK_R2_SLL, 0, no_overflow}, + {"slli", "d,s,j", "d,s,j,E", 3, 4, iw_F3X6L5_type, + MATCH_R2_SLLI, MASK_R2_SLLI, 0, unsigned_immed5_overflow}, + {"sll.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type, + MATCH_R2_SLL_N, MASK_R2_SLL_N, 0, no_overflow}, + {"slli.n", "D,S,f", "D,S,f,E", 3, 2, iw_T2X1L3_type, + MATCH_R2_SLLI_N, MASK_R2_SLLI_N, 0, enumeration_overflow}, + {"spaddi.n", "D,U", "D,U,E", 2, 2, iw_T1I7_type, + MATCH_R2_SPADDI_N, MASK_R2_SPADDI_N, 0, address_offset_overflow}, + {"spdeci.n", "U", "U,E", 1, 2, iw_X1I7_type, + MATCH_R2_SPDECI_N, MASK_R2_SPDECI_N, 0, address_offset_overflow}, + {"spinci.n", "U", "U,E", 1, 2, iw_X1I7_type, + MATCH_R2_SPINCI_N, MASK_R2_SPINCI_N, 0, address_offset_overflow}, + {"sra", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_SRA, MASK_R2_SRA, 0, no_overflow}, + {"srai", "d,s,j", "d,s,j,E", 3, 4, iw_F3X6L5_type, + MATCH_R2_SRAI, MASK_R2_SRAI, 0, unsigned_immed5_overflow}, + {"srl", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_SRL, MASK_R2_SRL, 0, no_overflow}, + {"srli", "d,s,j", "d,s,j,E", 3, 4, iw_F3X6L5_type, + MATCH_R2_SRLI, MASK_R2_SRLI, 0, unsigned_immed5_overflow}, + {"srl.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type, + MATCH_R2_SRL_N, MASK_R2_SRL_N, 0, no_overflow}, + {"srli.n", "D,S,f", "D,S,f,E", 3, 2, iw_T2X1L3_type, + MATCH_R2_SRLI_N, MASK_R2_SRLI_N, 0, enumeration_overflow}, + {"stb", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, + MATCH_R2_STB, MASK_R2_STB, 0, address_offset_overflow}, + {"stbio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, + MATCH_R2_STBIO, MASK_R2_STBIO, 0, signed_immed12_overflow}, + {"stb.n", "T,Y(S)", "T,Y(S),E", 3, 2, iw_T2I4_type, + MATCH_R2_STB_N, MASK_R2_STB_N, 0, address_offset_overflow}, + {"stbz.n", "t,M(S)", "t,M(S),E", 3, 2, iw_T1X1I6_type, + MATCH_R2_STBZ_N, MASK_R2_STBZ_N, 0, address_offset_overflow}, + {"stex", "d,t,(s)", "d,t,(s),E", 3, 4, iw_F3X6_type, + MATCH_R2_STEX, MASK_R2_STEX, 0, no_overflow}, + {"sth", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, + MATCH_R2_STH, MASK_R2_STH, 0, address_offset_overflow}, + {"sthio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, + MATCH_R2_STHIO, MASK_R2_STHIO, 0, signed_immed12_overflow}, + {"sth.n", "T,X(S)", "T,X(S),E", 3, 2, iw_T2I4_type, + MATCH_R2_STH_N, MASK_R2_STH_N, 0, address_offset_overflow}, + {"stsex", "d,t,(s)", "d,t,(s),E", 3, 4, iw_F3X6_type, + MATCH_R2_STSEX, MASK_R2_STSEX, 0, no_overflow}, + {"stw", "t,i(s)", "t,i(s),E", 3, 4, iw_F2I16_type, + MATCH_R2_STW, MASK_R2_STW, 0, address_offset_overflow}, + {"stwio", "t,I(s)", "t,I(s),E", 3, 4, iw_F2X4I12_type, + MATCH_R2_STWIO, MASK_R2_STWIO, 0, signed_immed12_overflow}, + {"stwm", "R,B", "R,B,E", 2, 4, iw_F1X4L17_type, + MATCH_R2_STWM, MASK_R2_STWM, 0, no_overflow}, + {"stwsp.n", "t,V(s)", "t,V(s),E", 3, 2, iw_F1I5_type, + MATCH_R2_STWSP_N, MASK_R2_STWSP_N, 0, address_offset_overflow}, + {"stw.n", "T,W(S)", "T,W(S),E", 3, 2, iw_T2I4_type, + MATCH_R2_STW_N, MASK_R2_STW_N, 0, address_offset_overflow}, + {"stwz.n", "t,N(S)", "t,N(S),E", 3, 2, iw_T1X1I6_type, + MATCH_R2_STWZ_N, MASK_R2_STWZ_N, 0, address_offset_overflow}, + {"sub", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_SUB, MASK_R2_SUB, 0, no_overflow}, + {"subi", "t,s,i", "t,s,i,E", 3, 4, iw_F2I16_type, + MATCH_R2_SUBI, MASK_R2_SUBI, NIOS2_INSN_MACRO, signed_immed16_overflow}, + {"sub.n", "D,S,T", "D,S,T,E", 3, 2, iw_T3X1_type, + MATCH_R2_SUB_N, MASK_R2_SUB_N, 0, no_overflow}, + {"subi.n", "D,S,e", "D,S,e,E", 3, 2, iw_T2X1I3_type, + MATCH_R2_SUBI_N, MASK_R2_SUBI_N, 0, enumeration_overflow}, + {"sync", "", "E", 0, 4, iw_F3X6_type, + MATCH_R2_SYNC, MASK_R2_SYNC, 0, no_overflow}, + {"trap", "j", "j,E", 1, 4, iw_F3X6L5_type, + MATCH_R2_TRAP, MASK_R2_TRAP, NIOS2_INSN_OPTARG, no_overflow}, + {"trap.n", "j", "j,E", 1, 2, iw_X2L5_type, + MATCH_R2_TRAP_N, MASK_R2_TRAP_N, NIOS2_INSN_OPTARG, no_overflow}, + {"wrctl", "c,s", "c,s,E", 2, 4, iw_F3X6L5_type, + MATCH_R2_WRCTL, MASK_R2_WRCTL, 0, no_overflow}, + {"wrpie", "d,s", "d,s,E", 2, 4, iw_F3X6L5_type, + MATCH_R2_WRPIE, MASK_R2_WRPIE, 0, no_overflow}, + {"wrprs", "d,s", "d,s,E", 2, 4, iw_F3X6_type, + MATCH_R2_WRPRS, MASK_R2_WRPRS, 0, no_overflow}, + {"xor", "d,s,t", "d,s,t,E", 3, 4, iw_F3X6_type, + MATCH_R2_XOR, MASK_R2_XOR, 0, no_overflow}, + {"xorhi", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, + MATCH_R2_XORHI, MASK_R2_XORHI, 0, unsigned_immed16_overflow}, + {"xori", "t,s,u", "t,s,u,E", 3, 4, iw_F2I16_type, + MATCH_R2_XORI, MASK_R2_XORI, 0, unsigned_immed16_overflow}, + {"xor.n", "D,S,T", "D,S,T,E", 3, 2, iw_T2X3_type, + MATCH_R2_XOR_N, MASK_R2_XOR_N, 0, no_overflow}, +}; + +#define NIOS2_NUM_R2_OPCODES \ + ((sizeof nios2_r2_opcodes) / (sizeof (nios2_r2_opcodes[0]))) +const int nios2_num_r2_opcodes = NIOS2_NUM_R2_OPCODES; + +/* Default to using the R1 instruction tables. */ struct nios2_opcode *nios2_opcodes = (struct nios2_opcode *) nios2_r1_opcodes; -int nios2_num_opcodes = NIOS2_NUM_OPCODES; -#undef NIOS2_NUM_OPCODES +int nios2_num_opcodes = NIOS2_NUM_R1_OPCODES; +#undef NIOS2_NUM_R1_OPCODES +#undef NIOS2_NUM_R2_OPCODES + +/* Decodings for R2 asi.n (addi.n/subi.n) immediate values. */ +unsigned int nios2_r2_asi_n_mappings[] = + {1, 2, 4, 8, 16, 32, 64, 128}; +const int nios2_num_r2_asi_n_mappings = 8; + +/* Decodings for R2 shi.n (slli.n/srli.n) immediate values. */ +unsigned int nios2_r2_shi_n_mappings[] = + {1, 2, 3, 8, 12, 16, 24, 31}; +const int nios2_num_r2_shi_n_mappings = 8; + +/* Decodings for R2 andi.n immediate values. */ +unsigned int nios2_r2_andi_n_mappings[] = + {1, 2, 3, 4, 8, 0xf, 0x10, 0x1f, + 0x20, 0x3f, 0x7f, 0x80, 0xff, 0x7ff, 0xff00, 0xffff}; +const int nios2_num_r2_andi_n_mappings = 16; + +/* Decodings for R2 3-bit register fields. */ +int nios2_r2_reg3_mappings[] = + {16, 17, 2, 3, 4, 5, 6, 7}; +const int nios2_num_r2_reg3_mappings = 8; + +/* Decodings for R2 push.n/pop.n REG_RANGE value list. */ +unsigned long nios2_r2_reg_range_mappings[] = { + 0x00010000, + 0x00030000, + 0x00070000, + 0x000f0000, + 0x001f0000, + 0x003f0000, + 0x007f0000, + 0x00ff0000 +}; +const int nios2_num_r2_reg_range_mappings = 8; |