diff options
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/config/tc-mips.c | 14 | ||||
| -rw-r--r-- | gas/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/lb.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/sb.d | 2 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/mips.h | 9 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 8 | ||||
| -rw-r--r-- | opcodes/micromips-opc.c | 8 | ||||
| -rw-r--r-- | opcodes/mips-dis.c | 163 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 10 |
11 files changed, 87 insertions, 143 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 333eb03..0ab8ff0 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + + * config/tc-mips.c (validate_mips_insn, validate_micromips_insn) + (mips_ip): Remove "+D" and "+T" handling. + 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * config/tc-s390.c (md_gather_operands, md_apply_fix): Support new diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index d2b1f63..395230d 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -10889,8 +10889,6 @@ validate_mips_insn (const struct mips_opcode *opc) case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; - case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); - USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; @@ -10898,8 +10896,6 @@ validate_mips_insn (const struct mips_opcode *opc) case 'I': break; case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break; case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; - case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); - USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; @@ -11069,7 +11065,6 @@ validate_micromips_insn (const struct mips_opcode *opc) case 'A': USE_BITS (EXTLSB); break; case 'B': USE_BITS (INSMSB); break; case 'C': USE_BITS (EXTMSBD); break; - case 'D': USE_BITS (RS); USE_BITS (SEL); break; case 'E': USE_BITS (EXTLSB); break; case 'F': USE_BITS (INSMSB); break; case 'G': USE_BITS (EXTMSBD); break; @@ -11938,10 +11933,6 @@ mips_ip (char *str, struct mips_cl_insn *ip) s = expr_end; continue; - case 'D': - /* +D is for disassembly only; never match. */ - break; - case 'I': /* "+I" is like "I", except that imm2_expr is used. */ my_getExpression (&imm2_expr, s); @@ -11953,11 +11944,6 @@ mips_ip (char *str, struct mips_cl_insn *ip) s = expr_end; continue; - case 'T': /* Coprocessor register. */ - gas_assert (!mips_opts.micromips); - /* +T is for disassembly only; never match. */ - break; - case 't': /* Coprocessor register number. */ gas_assert (!mips_opts.micromips); if (s[0] == '$' && ISDIGIT (s[1])) diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 82b437c..bf440eb 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + + * gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names + for LWC0 and SWC0. + 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/zarch-zEC12.s: Change bprp second operand and add diff --git a/gas/testsuite/gas/mips/lb.d b/gas/testsuite/gas/mips/lb.d index 4a43c7f..918b842 100644 --- a/gas/testsuite/gas/mips/lb.d +++ b/gas/testsuite/gas/mips/lb.d @@ -388,7 +388,7 @@ Disassembly of section .text: 0+0378 <[^>]*> lw a0,0\(zero\) 0+037c <[^>]*> lwl a0,0\(zero\) 0+0380 <[^>]*> lwr a0,0\(zero\) -0+0384 <[^>]*> lwc0 \$4,0\(zero\) +0+0384 <[^>]*> lwc0 (c0_context|\$4),0\(zero\) 0+0388 <[^>]*> lwc1 \$f4,0\(zero\) 0+038c <[^>]*> lwc2 \$4,0\(zero\) 0+0390 <[^>]*> lwc3 \$4,0\(zero\) diff --git a/gas/testsuite/gas/mips/sb.d b/gas/testsuite/gas/mips/sb.d index 627c658..d25c43e 100644 --- a/gas/testsuite/gas/mips/sb.d +++ b/gas/testsuite/gas/mips/sb.d @@ -386,7 +386,7 @@ Disassembly of section .text: 0+0370 <[^>]*> sw a1,4\(zero\) 0+0374 <[^>]*> sh a0,0\(zero\) 0+0378 <[^>]*> sw a0,0\(zero\) -0+037c <[^>]*> swc0 \$4,0\(zero\) +0+037c <[^>]*> swc0 c0_context,0\(zero\) 0+0380 <[^>]*> swc1 \$f4,0\(zero\) 0+0384 <[^>]*> swc2 \$4,0\(zero\) 0+0388 <[^>]*> swc3 \$4,0\(zero\) diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index b927a2c..c3d05fa 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Remove documentation of "+D" and "+T". + 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com> * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 68cd9b6..7ad60cb 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -448,8 +448,6 @@ struct mips_opcode "e" 5 bit vector register byte specifier (OP_*_VECBYTE) "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) see also "k" above - "+D" Combined destination register ("G") and sel ("H") for CP0 ops, - for pretty-printing in disassembly only. Macro instructions: "A" General 32 bit expression @@ -489,7 +487,6 @@ struct mips_opcode "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) "+t" 5 bit coprocessor 0 destination register (OP_*_RT) - "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only MCU ASE usage: "~" 12 bit offset (OP_*_OFFSET12) @@ -543,7 +540,7 @@ struct mips_opcode Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: "1234" - "ABCDEFGHIJPQSTXZ" + "ABCEFGHIJPQSXZ" "abcjpstxz" */ @@ -1816,8 +1813,6 @@ extern const int bfd_mips16_num_opcodes; "E" 5-bit target register (MICROMIPSOP_*_RT) "G" 5-bit source register (MICROMIPSOP_*_RS) "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) - "+D" combined source register ("G") and sel ("H") for CP0 ops, - for pretty-printing in disassembly only Macro instructions: "A" general 32 bit expression @@ -1859,7 +1854,7 @@ extern const int bfd_mips16_num_opcodes; following), for quick reference when adding more: "j" "" - "ABCDEFGHI" + "ABCEFGHI" "" Extension character sequences used so far ("m" followed by the diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 17c69d4..0e3ee0f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + + * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries. + * micromips-opc.c (micromips_opcodes): Likewise. + * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D" + and "+T" handling. Check for a "0" suffix when deciding whether to + use coprocessor 0 names. In that case, also check for ",H" selectors. + 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.c (J12_12, J24_24): New macros. diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index c583d7a..64caf8a 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -463,16 +463,12 @@ const struct mips_opcode micromips_opcodes[] = {"dli", "t,i", 0x50000000, 0xfc1f0000, WR_t, 0, I3 }, /* ori */ {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 }, {"dmfc0", "t,G", 0x580000fc, 0xfc00ffff, WR_t|RD_C0, 0, I3 }, -{"dmfc0", "t,+D", 0x580000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I3 }, {"dmfc0", "t,G,H", 0x580000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I3 }, {"dmfgc0", "t,G", 0x580000e7, 0xfc00ffff, WR_t|RD_C0, 0, 0, IVIRT64 }, -{"dmfgc0", "t,+D", 0x580000e7, 0xfc00c7ff, WR_t|RD_C0, 0, 0, IVIRT64 }, {"dmfgc0", "t,G,H", 0x580000e7, 0xfc00c7ff, WR_t|RD_C0, 0, 0, IVIRT64 }, {"dmtc0", "t,G", 0x580002fc, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, I3 }, -{"dmtc0", "t,+D", 0x580002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I3 }, {"dmtc0", "t,G,H", 0x580002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I3 }, {"dmtgc0", "t,G", 0x580002e7, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, 0, IVIRT64 }, -{"dmtgc0", "t,+D", 0x580002e7, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, 0, IVIRT64 }, {"dmtgc0", "t,G,H", 0x580002e7, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, 0, IVIRT64 }, {"dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I3 }, {"dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I3 }, @@ -689,13 +685,11 @@ const struct mips_opcode micromips_opcodes[] = {"maddu", "s,t", 0x0000db3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 }, {"maddu", "7,s,t", 0x00001abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 }, {"mfc0", "t,G", 0x000000fc, 0xfc00ffff, WR_t|RD_C0, 0, I1 }, -{"mfc0", "t,+D", 0x000000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I1 }, {"mfc0", "t,G,H", 0x000000fc, 0xfc00c7ff, WR_t|RD_C0, 0, I1 }, {"mfc1", "t,S", 0x5400203b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I1 }, {"mfc1", "t,G", 0x5400203b, 0xfc00ffff, WR_t|RD_S|FP_S, 0, I1 }, {"mfc2", "t,G", 0x00004d3c, 0xfc00ffff, WR_t|RD_C2, 0, I1 }, {"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_t|RD_C0, 0, 0, IVIRT }, -{"mfgc0", "t,+D", 0x000004fc, 0xfc00c7ff, WR_t|RD_C0, 0, 0, IVIRT }, {"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_t|RD_C0, 0, 0, IVIRT }, {"mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_t|RD_S|FP_D, 0, I1 }, {"mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_t|RD_S|FP_D, 0, I1 }, @@ -737,13 +731,11 @@ const struct mips_opcode micromips_opcodes[] = {"msubu", "s,t", 0x0000fb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 }, {"msubu", "7,s,t", 0x00003abc, 0xfc003fff, MOD_a|RD_s|RD_t, 0, 0, D32 }, {"mtc0", "t,G", 0x000002fc, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, I1 }, -{"mtc0", "t,+D", 0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I1 }, {"mtc0", "t,G,H", 0x000002fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, I1 }, {"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_t|WR_S|FP_S, 0, I1 }, {"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_t|WR_S|FP_S, 0, I1 }, {"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_t|WR_C2|WR_CC, 0, I1 }, {"mtgc0", "t,G", 0x000006fc, 0xfc00ffff, RD_t|WR_C0|WR_CC, 0, 0, IVIRT }, -{"mtgc0", "t,+D", 0x000006fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, 0, IVIRT }, {"mtgc0", "t,G,H", 0x000006fc, 0xfc00c7ff, RD_t|WR_C0|WR_CC, 0, 0, IVIRT }, {"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_t|WR_S|FP_D, 0, I1 }, {"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_t|WR_S|FP_D, 0, I1 }, diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index ee5827c..333d4fe 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -977,9 +977,8 @@ print_insn_args (const char *d, const struct mips_opcode *opp) { const fprintf_ftype infprintf = info->fprintf_func; - unsigned int lsb, msb, msbd; + unsigned int lsb, msb, msbd, cpreg; void *is = info->stream; - int op; lsb = 0; @@ -1044,28 +1043,6 @@ print_insn_args (const char *d, infprintf (is, "0x%x", msbd + 1); break; - case 'D': - { - const struct mips_cp0sel_name *n; - unsigned int cp0reg, sel; - - cp0reg = GET_OP (l, RD); - sel = GET_OP (l, SEL); - - /* CP0 register including 'sel' code for mtcN (et al.), to be - printed textually if known. If not known, print both - CP0 register name and sel numerically since CP0 register - with sel 0 may have a name unrelated to register being - printed. */ - n = lookup_mips_cp0sel_name(mips_cp0sel_names, - mips_cp0sel_names_len, cp0reg, sel); - if (n != NULL) - infprintf (is, "%s", n->name); - else - infprintf (is, "$%d,%d", cp0reg, sel); - break; - } - case 'E': lsb = GET_OP (l, SHAMT) + 32; infprintf (is, "0x%x", lsb); @@ -1089,28 +1066,6 @@ print_insn_args (const char *d, infprintf (is, "%s", mips_cp0_names[GET_OP (l, RT)]); break; - case 'T': /* Coprocessor 0 reg name */ - { - const struct mips_cp0sel_name *n; - unsigned int cp0reg, sel; - - cp0reg = GET_OP (l, RT); - sel = GET_OP (l, SEL); - - /* CP0 register including 'sel' code for mftc0, to be - printed textually if known. If not known, print both - CP0 register name and sel numerically since CP0 register - with sel 0 may have a name unrelated to register being - printed. */ - n = lookup_mips_cp0sel_name(mips_cp0sel_names, - mips_cp0sel_names_len, cp0reg, sel); - if (n != NULL) - infprintf (is, "%s", n->name); - else - infprintf (is, "$%d,%d", cp0reg, sel); - break; - } - case 'x': /* bbit bit index */ infprintf (is, "0x%x", GET_OP (l, BBITIND)); break; @@ -1364,26 +1319,44 @@ print_insn_args (const char *d, break; case 'E': - /* Coprocessor register for lwcN instructions, et al. - - Note that there is no load/store cp0 instructions, and - that FPU (cp1) instructions disassemble this field using - 'T' format. Therefore, until we gain understanding of - cp2 register names, we can simply print the register - numbers. */ - infprintf (is, "$%d", GET_OP (l, RT)); - break; + cpreg = GET_OP (l, RT); + goto copro; case 'G': + cpreg = GET_OP (l, RD); + copro: /* Coprocessor register for mtcN instructions, et al. Note that FPU (cp1) instructions disassemble this field using 'S' format. Therefore, we only need to worry about cp0, cp2, and cp3. */ - op = GET_OP (l, OP); - if (op == OP_OP_COP0) - infprintf (is, "%s", mips_cp0_names[GET_OP (l, RD)]); + if (opp->name[strlen (opp->name) - 1] == '0') + { + if (d[1] == ',' && d[2] == 'H') + { + const struct mips_cp0sel_name *n; + unsigned int sel; + + sel = GET_OP (l, SEL); + + /* CP0 register including 'sel' code for mtcN (et al.), to be + printed textually if known. If not known, print both + CP0 register name and sel numerically since CP0 register + with sel 0 may have a name unrelated to register being + printed. */ + n = lookup_mips_cp0sel_name (mips_cp0sel_names, + mips_cp0sel_names_len, + cpreg, sel); + if (n != NULL) + infprintf (is, "%s", n->name); + else + infprintf (is, "$%d,%d", cpreg, sel); + d += 2; + } + else + infprintf (is, "%s", mips_cp0_names[cpreg]); + } else - infprintf (is, "$%d", GET_OP (l, RD)); + infprintf (is, "$%d", cpreg); break; case 'K': @@ -2586,28 +2559,37 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) /* Coprocessor register for mtcN instructions, et al. Note that FPU (cp1) instructions disassemble this field using 'S' format. Therefore, we only need to worry about cp0, - cp2, and cp3. - The microMIPS encoding does not have a coprocessor - identifier field as such, so we must work out the - coprocessor number by looking at the opcode. */ - switch (insn - & ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) - | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS))) + cp2, and cp3. */ + if (op->name[strlen (op->name) - 1] == '0') { - case 0x000000fc: /* mfc0 */ - case 0x000002fc: /* mtc0 */ - case 0x000004fc: /* mfgc0 */ - case 0x000006fc: /* mtgc0 */ - case 0x580000fc: /* dmfc0 */ - case 0x580002fc: /* dmtc0 */ - case 0x580000e7: /* dmfgc0 */ - case 0x580002e7: /* dmtgc0 */ - infprintf (is, "%s", mips_cp0_names[GET_OP (insn, RS)]); - break; - default: - infprintf (is, "$%d", GET_OP (insn, RS)); - break; + if (s[1] == ',' && s[2] == 'H') + { + const struct mips_cp0sel_name *n; + unsigned int cp0reg, sel; + + cp0reg = GET_OP (insn, RS); + sel = GET_OP (insn, SEL); + + /* CP0 register including 'sel' code for mtcN + (et al.), to be printed textually if known. + If not known, print both CP0 register name and + sel numerically since CP0 register with sel 0 may + have a name unrelated to register being + printed. */ + n = lookup_mips_cp0sel_name (mips_cp0sel_names, + mips_cp0sel_names_len, + cp0reg, sel); + if (n != NULL) + infprintf (is, "%s", n->name); + else + infprintf (is, "$%d,%d", cp0reg, sel); + s += 2; + } + else + infprintf (is, "%s", mips_cp0_names[GET_OP (insn, RS)]); } + else + infprintf (is, "$%d", GET_OP (insn, RS)); break; case 'H': @@ -2663,29 +2645,6 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) infprintf (is, "0x%x", msbd + 1); break; - case 'D': - { - const struct mips_cp0sel_name *n; - unsigned int cp0reg, sel; - - cp0reg = GET_OP (insn, RS); - sel = GET_OP (insn, SEL); - - /* CP0 register including 'sel' code for mtcN - (et al.), to be printed textually if known. - If not known, print both CP0 register name and - sel numerically since CP0 register with sel 0 may - have a name unrelated to register being printed. */ - n = lookup_mips_cp0sel_name (mips_cp0sel_names, - mips_cp0sel_names_len, - cp0reg, sel); - if (n != NULL) - infprintf (is, "%s", n->name); - else - infprintf (is, "$%d,%d", cp0reg, sel); - break; - } - case 'E': lsb = GET_OP (insn, EXTLSB) + 32; infprintf (is, "0x%x", lsb); diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index d12701b..72f5842 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -724,18 +724,14 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 }, {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3, 0, EE }, -{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, LCD|WR_t|RD_C0, 0, 0, IVIRT64 }, -{"dmfgc0", "t,+D", 0x40600100, 0xffe007f8, LCD|WR_t|RD_C0, 0, 0, IVIRT64 }, {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, LCD|WR_t|RD_C0, 0, 0, IVIRT64 }, {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32 }, {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, 0, MT32 }, {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3, 0, EE }, -{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, {"dmtgc0", "t,G", 0x40600300, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT64 }, -{"dmtgc0", "t,+D", 0x40600300, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT64 }, {"dmtgc0", "t,G,H", 0x40600300, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT64 }, {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3, 0, SF }, {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3, 0, SF }, @@ -1010,7 +1006,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, 0, MT32 }, {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, 0, MT32 }, {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, 0, MT32 }, -{"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, 0, MT32 }, {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, 0, MT32 }, {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, 0, MT32 }, {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, 0, MT32 }, @@ -1026,10 +1021,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, 0, MT32 }, {"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, 0, MT32 }, {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, -{"mfc0", "t,+D",0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, {"mfgc0", "t,G", 0x40600000, 0xffe007ff, LCD|WR_t|RD_C0, 0, 0, IVIRT }, -{"mfgc0", "t,+D", 0x40600000, 0xffe007f8, LCD|WR_t|RD_C0, 0, 0, IVIRT }, {"mfgc0", "t,G,H", 0x40600000, 0xffe007f8, LCD|WR_t|RD_C0, 0, 0, IVIRT }, {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, @@ -1123,10 +1116,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5|EE }, {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5|EE }, {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 }, -{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, {"mtgc0", "t,G", 0x40600200, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT }, -{"mtgc0", "t,+D", 0x40600200, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT }, {"mtgc0", "t,G,H", 0x40600200, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, 0, IVIRT }, {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, @@ -1154,7 +1145,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_s, 0, EE }, {"mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_s, 0, EE }, {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, 0, MT32 }, -{"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, 0, MT32 }, {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, 0, MT32 }, {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, 0, MT32 }, {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, 0, MT32 }, |