diff options
| -rw-r--r-- | sim/arm/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/arm/armemu.c | 75 |
2 files changed, 47 insertions, 34 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog index 6dc8bd5..2f1d531 100644 --- a/sim/arm/ChangeLog +++ b/sim/arm/ChangeLog @@ -1,3 +1,9 @@ +2000-08-14 Nick Clifton <nickc@redhat.com> + + * armemu.c (LHPOSTDOWN): Compute write back value before + performing load in case the offset register is overwritten. + (LHPOSTUP): Ditto. + 2000-07-14 Fernando Nasser <fnasser@cygnus.com> * wrapper.c (sim_create_inferior): Fix typo in the previous patch. diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c index 7152023..9d3dcba 100644 --- a/sim/arm/armemu.c +++ b/sim/arm/armemu.c @@ -106,60 +106,67 @@ extern int stop_simulator; if (StoreHalfWord(state, instr, temp)) \ LSBase = temp ; -/* load post decrement writeback */ +/* Load post decrement writeback. */ #define LHPOSTDOWN() \ { \ - int done = 1 ; \ - lhs = LHS ; \ - switch (BITS(5,6)) { \ + int done = 1; \ + lhs = LHS; \ + temp = lhs - GetLS7RHS (state, instr); \ + \ + switch (BITS (5, 6)) \ + { \ case 1: /* H */ \ - if (LoadHalfWord(state,instr,lhs,LUNSIGNED)) \ - LSBase = lhs - GetLS7RHS(state,instr) ; \ - break ; \ + if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \ + LSBase = temp; \ + break; \ case 2: /* SB */ \ - if (LoadByte(state,instr,lhs,LSIGNED)) \ - LSBase = lhs - GetLS7RHS(state,instr) ; \ - break ; \ + if (LoadByte (state, instr, lhs, LSIGNED)) \ + LSBase = temp; \ + break; \ case 3: /* SH */ \ - if (LoadHalfWord(state,instr,lhs,LSIGNED)) \ - LSBase = lhs - GetLS7RHS(state,instr) ; \ - break ; \ - case 0: /* SWP handled elsewhere */ \ + if (LoadHalfWord (state, instr, lhs, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 0: /* SWP handled elsewhere. */ \ default: \ - done = 0 ; \ - break ; \ + done = 0; \ + break; \ } \ if (done) \ - break ; \ + break; \ } -/* load post increment writeback */ +/* Load post increment writeback. */ #define LHPOSTUP() \ { \ - int done = 1 ; \ - lhs = LHS ; \ - switch (BITS(5,6)) { \ + int done = 1; \ + lhs = LHS; \ + temp = lhs + GetLS7RHS (state, instr); \ + \ + switch (BITS (5, 6)) \ + { \ case 1: /* H */ \ - if (LoadHalfWord(state,instr,lhs,LUNSIGNED)) \ - LSBase = lhs + GetLS7RHS(state,instr) ; \ - break ; \ + if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \ + LSBase = temp; \ + break; \ case 2: /* SB */ \ - if (LoadByte(state,instr,lhs,LSIGNED)) \ - LSBase = lhs + GetLS7RHS(state,instr) ; \ - break ; \ + if (LoadByte (state, instr, lhs, LSIGNED)) \ + LSBase = temp; \ + break; \ case 3: /* SH */ \ - if (LoadHalfWord(state,instr,lhs,LSIGNED)) \ - LSBase = lhs + GetLS7RHS(state,instr) ; \ - break ; \ - case 0: /* SWP handled elsewhere */ \ + if (LoadHalfWord (state, instr, lhs, LSIGNED)) \ + LSBase = temp; \ + break; \ + case 0: /* SWP handled elsewhere. */ \ default: \ - done = 0 ; \ - break ; \ + done = 0; \ + break; \ } \ if (done) \ - break ; \ + break; \ } + /* load pre decrement */ #define LHPREDOWN() \ { \ |