diff options
| -rw-r--r-- | gas/testsuite/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86-64-inval.l | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86-64-inval.s | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86_64.s | 2 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/i386-dis.c | 6 |
6 files changed, 21 insertions, 4 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index cfd50e7..42ee1ca 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2006-12-15 H.J. Lu <hongjiu.lu@intel.com> + + * gas/i386/x86-64-inval.s: cmpxchg16b needs oword ptr, instead + of xmmword ptr. + * gas/i386/x86_64.s: Likewise. + * gas/i386/x86-64-inval.l: Updated. + 2006-12-14 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-inval.s: Add cmpxchg16b. diff --git a/gas/testsuite/gas/i386/x86-64-inval.l b/gas/testsuite/gas/i386/x86-64-inval.l index 2cbb867..87503e5 100644 --- a/gas/testsuite/gas/i386/x86-64-inval.l +++ b/gas/testsuite/gas/i386/x86-64-inval.l @@ -106,4 +106,4 @@ GAS LISTING .* 51 [ ]*retl # can't have 32-bit stack operands 52 [ ]*insertq \$4,\$2,%xmm2,%ebx # The last operand must be XMM register. 53 [ ]*.intel_syntax noprefix - 54 [ ]*cmpxchg16b dword ptr \[rax\] # Must be xmmword + 54 [ ]*cmpxchg16b dword ptr \[rax\] # Must be oword diff --git a/gas/testsuite/gas/i386/x86-64-inval.s b/gas/testsuite/gas/i386/x86-64-inval.s index 7178ede..f7a4379 100644 --- a/gas/testsuite/gas/i386/x86-64-inval.s +++ b/gas/testsuite/gas/i386/x86-64-inval.s @@ -51,4 +51,4 @@ foo: jcxz foo # No prefix exists to select CX as a counter retl # can't have 32-bit stack operands insertq $4,$2,%xmm2,%ebx # The last operand must be XMM register. .intel_syntax noprefix - cmpxchg16b dword ptr [rax] # Must be xmmword + cmpxchg16b dword ptr [rax] # Must be oword diff --git a/gas/testsuite/gas/i386/x86_64.s b/gas/testsuite/gas/i386/x86_64.s index c89d393..aad9b27 100644 --- a/gas/testsuite/gas/i386/x86_64.s +++ b/gas/testsuite/gas/i386/x86_64.s @@ -191,7 +191,7 @@ movq %rax,0xffffffffff332211 cmpxchg16b (%rax) .intel_syntax noprefix -cmpxchg16b xmmword ptr [rax] +cmpxchg16b oword ptr [rax] # Get a good alignment. .p2align 4,0 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 9bebc48..ee62f00 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2006-12-15 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (o_mode): New for 16-byte operand. + (intel_operand_size): Generate "OWORD PTR " for o_mode. + (CMPXCHG8B_Fixup): Set bytemode to o_mode instead of x_mode. + 2006-12-14 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (CMPXCHG8B_Fixup): New. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 009d0f6..eb751bc 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -356,6 +356,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define const_1_mode 14 #define stack_v_mode 15 /* v_mode for stack-related opcodes. */ #define z_mode 16 /* non-quad operand size depends on prefixes */ +#define o_mode 17 /* 16-byte operand */ #define es_reg 100 #define cs_reg 101 @@ -4183,6 +4184,9 @@ intel_operand_size (int bytemode, int sizeflag) case x_mode: oappend ("XMMWORD PTR "); break; + case o_mode: + oappend ("OWORD PTR "); + break; default: break; } @@ -5778,7 +5782,7 @@ CMPXCHG8B_Fixup (int bytemode, int sizeflag) /* Change cmpxchg8b to cmpxchg16b. */ char *p = obuf + strlen (obuf) - 2; strcpy (p, "16b"); - bytemode = x_mode; + bytemode = o_mode; } OP_M (bytemode, sizeflag); } |