aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--opcodes/ChangeLog12
-rw-r--r--opcodes/fr30-asm.c118
-rw-r--r--opcodes/fr30-dis.c125
-rw-r--r--opcodes/fr30-opc.c1588
-rw-r--r--opcodes/fr30-opc.h86
5 files changed, 1891 insertions, 38 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a489ac2..0bbb9a2 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,9 +1,17 @@
+start-sanitize-fr30
+Thu Nov 12 19:24:18 1998 Dave Brolley <brolley@cygnus.com>
+
+ * po/opcodes.pot: Regenerated.
+ * fr30-opc.c: Regenerated.
+ * fr30-opc.h: Regenerated.
+ * fr30-dis.c: Regenerated.
+ * fr30-asm.c: Regenerated.
+
Tue Nov 10 15:26:27 1998 Nick Clifton <nickc@cygnus.com>
-start-sanitize-fr30
* disassemble.c (disassembler): Add support for FR30 target.
+
end-sanitize-fr30
-
Tue Nov 10 11:00:04 1998 Doug Evans <devans@canuck.cygnus.com>
start-sanitize-cygnus
diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c
index 461536b..22f452c 100644
--- a/opcodes/fr30-asm.c
+++ b/opcodes/fr30-asm.c
@@ -85,6 +85,51 @@ fr30_cgen_parse_operand (od, opindex, strp, fields)
case FR30_OPERAND_RJ :
errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_gr, & fields->f_Rj);
break;
+ case FR30_OPERAND_RS1 :
+ errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_dr, & fields->f_Rs1);
+ break;
+ case FR30_OPERAND_RS2 :
+ errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_dr, & fields->f_Rs2);
+ break;
+ case FR30_OPERAND_U4 :
+ errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_U4, &fields->f_u4);
+ break;
+ case FR30_OPERAND_M4 :
+ errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_M4, &fields->f_m4);
+ break;
+ case FR30_OPERAND_I8 :
+ errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_I8, &fields->f_i8);
+ break;
+ case FR30_OPERAND_U8 :
+ errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_U8, &fields->f_u8);
+ break;
+ case FR30_OPERAND_O8 :
+ errmsg = cgen_parse_signed_integer (od, strp, FR30_OPERAND_O8, &fields->f_o8);
+ break;
+ case FR30_OPERAND_S10 :
+ errmsg = cgen_parse_signed_integer (od, strp, FR30_OPERAND_S10, &fields->f_s10);
+ break;
+ case FR30_OPERAND_U10 :
+ errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_U10, &fields->f_u10);
+ break;
+ case FR30_OPERAND_DIR8 :
+ errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_DIR8, &fields->f_dir8);
+ break;
+ case FR30_OPERAND_DIR9 :
+ errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_DIR9, &fields->f_dir9);
+ break;
+ case FR30_OPERAND_DIR10 :
+ errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_DIR10, &fields->f_dir10);
+ break;
+ case FR30_OPERAND_LABEL9 :
+ errmsg = cgen_parse_signed_integer (od, strp, FR30_OPERAND_LABEL9, &fields->f_rel8);
+ break;
+ case FR30_OPERAND_LABEL12 :
+ errmsg = cgen_parse_signed_integer (od, strp, FR30_OPERAND_LABEL12, &fields->f_rel11);
+ break;
+ case FR30_OPERAND_CC :
+ errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_CC, &fields->f_cc);
+ break;
default :
/* xgettext:c-format */
@@ -128,6 +173,79 @@ fr30_cgen_insert_operand (od, opindex, fields, buffer, pc)
case FR30_OPERAND_RJ :
errmsg = insert_normal (od, fields->f_Rj, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
+ case FR30_OPERAND_RS1 :
+ errmsg = insert_normal (od, fields->f_Rs1, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case FR30_OPERAND_RS2 :
+ errmsg = insert_normal (od, fields->f_Rs2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case FR30_OPERAND_U4 :
+ errmsg = insert_normal (od, fields->f_u4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case FR30_OPERAND_M4 :
+ {
+ long value = fields->f_m4;
+ value = ((value) & (15));
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
+ }
+ break;
+ case FR30_OPERAND_I8 :
+ errmsg = insert_normal (od, fields->f_i8, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 4, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case FR30_OPERAND_U8 :
+ errmsg = insert_normal (od, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case FR30_OPERAND_O8 :
+ errmsg = insert_normal (od, fields->f_o8, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 4, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case FR30_OPERAND_S10 :
+ {
+ long value = fields->f_s10;
+ value = ((((unsigned int) (value) >> (2))) & (255));
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
+ }
+ break;
+ case FR30_OPERAND_U10 :
+ {
+ long value = fields->f_u10;
+ value = ((((unsigned int) (value) >> (2))) & (255));
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
+ }
+ break;
+ case FR30_OPERAND_DIR8 :
+ errmsg = insert_normal (od, fields->f_dir8, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
+ case FR30_OPERAND_DIR9 :
+ {
+ long value = fields->f_dir9;
+ value = ((((unsigned int) (value) >> (1))) & (255));
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
+ }
+ break;
+ case FR30_OPERAND_DIR10 :
+ {
+ long value = fields->f_dir10;
+ value = ((((unsigned int) (value) >> (2))) & (255));
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
+ }
+ break;
+ case FR30_OPERAND_LABEL9 :
+ {
+ long value = fields->f_rel8;
+ value = ((((unsigned int) (value) >> (1))) & (255));
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_SIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
+ }
+ break;
+ case FR30_OPERAND_LABEL12 :
+ {
+ long value = fields->f_rel11;
+ value = ((((unsigned int) (value) >> (1))) & (2047));
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_SIGNED), 5, 11, CGEN_FIELDS_BITSIZE (fields), buffer);
+ }
+ break;
+ case FR30_OPERAND_CC :
+ errmsg = insert_normal (od, fields->f_cc, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
default :
/* xgettext:c-format */
diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c
index d2cbab3..3e17061 100644
--- a/opcodes/fr30-dis.c
+++ b/opcodes/fr30-dis.c
@@ -95,6 +95,86 @@ fr30_cgen_extract_operand (od, opindex, ex_info, insn_value, fields, pc)
case FR30_OPERAND_RJ :
length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_Rj);
break;
+ case FR30_OPERAND_RS1 :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_Rs1);
+ break;
+ case FR30_OPERAND_RS2 :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_Rs2);
+ break;
+ case FR30_OPERAND_U4 :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_u4);
+ break;
+ case FR30_OPERAND_M4 :
+ {
+ long value;
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), & value);
+ value = ((value) | ((! (15))));
+ fields->f_m4 = value;
+ }
+ break;
+ case FR30_OPERAND_I8 :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 4, 8, CGEN_FIELDS_BITSIZE (fields), & fields->f_i8);
+ break;
+ case FR30_OPERAND_U8 :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), & fields->f_u8);
+ break;
+ case FR30_OPERAND_O8 :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 4, 8, CGEN_FIELDS_BITSIZE (fields), & fields->f_o8);
+ break;
+ case FR30_OPERAND_S10 :
+ {
+ long value;
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), & value);
+ value = ((value) << (2));
+ fields->f_s10 = value;
+ }
+ break;
+ case FR30_OPERAND_U10 :
+ {
+ long value;
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), & value);
+ value = ((value) << (2));
+ fields->f_u10 = value;
+ }
+ break;
+ case FR30_OPERAND_DIR8 :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), & fields->f_dir8);
+ break;
+ case FR30_OPERAND_DIR9 :
+ {
+ long value;
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), & value);
+ value = ((value) << (1));
+ fields->f_dir9 = value;
+ }
+ break;
+ case FR30_OPERAND_DIR10 :
+ {
+ long value;
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), & value);
+ value = ((value) << (2));
+ fields->f_dir10 = value;
+ }
+ break;
+ case FR30_OPERAND_LABEL9 :
+ {
+ long value;
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_SIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), & value);
+ value = ((value) << (1));
+ fields->f_rel8 = value;
+ }
+ break;
+ case FR30_OPERAND_LABEL12 :
+ {
+ long value;
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_SIGNED), 5, 11, CGEN_FIELDS_BITSIZE (fields), & value);
+ value = ((value) << (1));
+ fields->f_rel11 = value;
+ }
+ break;
+ case FR30_OPERAND_CC :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_cc);
+ break;
default :
/* xgettext:c-format */
@@ -138,6 +218,51 @@ fr30_cgen_print_operand (od, opindex, info, fields, attrs, pc, length)
case FR30_OPERAND_RJ :
print_keyword (od, info, & fr30_cgen_opval_h_gr, fields->f_Rj, 0|(1<<CGEN_OPERAND_UNSIGNED));
break;
+ case FR30_OPERAND_RS1 :
+ print_keyword (od, info, & fr30_cgen_opval_h_dr, fields->f_Rs1, 0|(1<<CGEN_OPERAND_UNSIGNED));
+ break;
+ case FR30_OPERAND_RS2 :
+ print_keyword (od, info, & fr30_cgen_opval_h_dr, fields->f_Rs2, 0|(1<<CGEN_OPERAND_UNSIGNED));
+ break;
+ case FR30_OPERAND_U4 :
+ print_normal (od, info, fields->f_u4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case FR30_OPERAND_M4 :
+ print_normal (od, info, fields->f_m4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case FR30_OPERAND_I8 :
+ print_normal (od, info, fields->f_i8, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case FR30_OPERAND_U8 :
+ print_normal (od, info, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case FR30_OPERAND_O8 :
+ print_normal (od, info, fields->f_o8, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case FR30_OPERAND_S10 :
+ print_normal (od, info, fields->f_s10, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case FR30_OPERAND_U10 :
+ print_normal (od, info, fields->f_u10, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case FR30_OPERAND_DIR8 :
+ print_normal (od, info, fields->f_dir8, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case FR30_OPERAND_DIR9 :
+ print_normal (od, info, fields->f_dir9, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case FR30_OPERAND_DIR10 :
+ print_normal (od, info, fields->f_dir10, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case FR30_OPERAND_LABEL9 :
+ print_normal (od, info, fields->f_rel8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case FR30_OPERAND_LABEL12 :
+ print_normal (od, info, fields->f_rel11, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case FR30_OPERAND_CC :
+ print_normal (od, info, fields->f_cc, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
default :
/* xgettext:c-format */
diff --git a/opcodes/fr30-opc.c b/opcodes/fr30-opc.c
index 04d8df9..2dfb082 100644
--- a/opcodes/fr30-opc.c
+++ b/opcodes/fr30-opc.c
@@ -277,7 +277,6 @@ static const CGEN_ATTR_ENTRY MACH_attr[] =
const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
{
{ "CACHE-ADDR", NULL },
- { "FUN-ACCESS", NULL },
{ "PC", NULL },
{ "PROFILE", NULL },
{ 0, 0 }
@@ -286,11 +285,13 @@ const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
{
{ "ABS-ADDR", NULL },
+ { "HASH-PREFIX", NULL },
{ "NEGATIVE", NULL },
{ "PCREL-ADDR", NULL },
{ "RELAX", NULL },
{ "SEM-ONLY", NULL },
{ "SIGN-OPT", NULL },
+ { "SIGNED", NULL },
{ "UNSIGNED", NULL },
{ 0, 0 }
};
@@ -342,25 +343,15 @@ CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
{ "tbr", 0 },
{ "rp", 1 },
{ "ssp", 2 },
- { "usp", 3 }
-};
-
-CGEN_KEYWORD fr30_cgen_opval_h_dr =
-{
- & fr30_cgen_opval_h_dr_entries[0],
- 4
-};
-
-CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_mdr_entries[] =
-{
+ { "usp", 3 },
{ "mdh", 4 },
{ "mdl", 5 }
};
-CGEN_KEYWORD fr30_cgen_opval_h_mdr =
+CGEN_KEYWORD fr30_cgen_opval_h_dr =
{
- & fr30_cgen_opval_h_mdr_entries[0],
- 2
+ & fr30_cgen_opval_h_dr_entries[0],
+ 6
};
CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
@@ -389,12 +380,11 @@ static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
{ HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
{ HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
{ HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0, { 0 } } },
- { HW_H_MDR, & HW_ENT (HW_H_MDR + 1), "h-mdr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_mdr, { 0, 0, { 0 } } },
{ HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0, { 0 } } },
- { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
- { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
- { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
- { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
+ { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
+ { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
+ { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
+ { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
{ 0 }
};
@@ -414,6 +404,54 @@ const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
/* Rj: source register */
{ "Rj", & HW_ENT (HW_H_GR), 8, 4,
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* Rs1: dedicated register */
+ { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* Rs2: dedicated register */
+ { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* ps: Program Status register */
+ { "ps", & HW_ENT (HW_H_CR), 0, 0,
+ { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+/* u4: 4 bit unsigned immediate */
+ { "u4", & HW_ENT (HW_H_UINT), 8, 4,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* m4: 4 bit negative immediate */
+ { "m4", & HW_ENT (HW_H_UINT), 8, 4,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* i8: 8 bit unsigned immediate */
+ { "i8", & HW_ENT (HW_H_UINT), 4, 8,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* u8: 8 bit unsigned immediate */
+ { "u8", & HW_ENT (HW_H_UINT), 8, 8,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* o8: 8 bit signed immediate */
+ { "o8", & HW_ENT (HW_H_SINT), 4, 8,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* s10: 10 bit signed immediate */
+ { "s10", & HW_ENT (HW_H_SINT), 8, 8,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
+/* u10: 10 bit unsigned immediate */
+ { "u10", & HW_ENT (HW_H_UINT), 8, 8,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* dir8: 8 bit direct address */
+ { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* dir9: 9 bit direct address */
+ { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* dir10: 10 bit direct address */
+ { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* label9: 9 bit pc relative address */
+ { "label9", & HW_ENT (HW_H_SINT), 8, 8,
+ { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
+/* label12: 12 bit pc relative address */
+ { "label12", & HW_ENT (HW_H_SINT), 5, 11,
+ { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
+/* cc: condition codes */
+ { "cc", & HW_ENT (HW_H_UINT), 4, 4,
+ { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* nbit: negative bit */
{ "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
{ 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
@@ -434,13 +472,137 @@ const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
{ INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
+ { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
{ INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0 },
+ { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
{ OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0 },
{ OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
{ OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
+ { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
+ { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0 },
+ { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0 },
+ { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0 },
+ { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
{ OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
{ OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0 },
+ { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0 },
+ { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
{ 0 }
};
@@ -470,6 +632,1212 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
(PTR) & fmt_add_ops[0],
{ 0, 0, { 0 } }
},
+/* add $u4,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ADDI, "addi", "add",
+ { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xa400,
+ (PTR) & fmt_addi_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* add2 $m4,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ADD2, "add2", "add2",
+ { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xa500,
+ (PTR) & fmt_add2_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* addc $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ADDC, "addc", "addc",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xa700,
+ (PTR) & fmt_addc_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* addn $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ADDN, "addn", "addn",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xa200,
+ (PTR) & fmt_addn_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* addn $u4,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ADDNI, "addni", "addn",
+ { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xa000,
+ (PTR) & fmt_addni_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* addn2 $m4,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ADDN2, "addn2", "addn2",
+ { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xa100,
+ (PTR) & fmt_addn2_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* sub $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_SUB, "sub", "sub",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xac00,
+ (PTR) & fmt_add_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* subc $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_SUBC, "subc", "subc",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xad00,
+ (PTR) & fmt_addc_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* subn $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_SUBN, "subn", "subn",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xae00,
+ (PTR) & fmt_addn_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* cmp $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_CMP, "cmp", "cmp",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xaa00,
+ (PTR) & fmt_cmp_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* cmp $u4,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_CMPI, "cmpi", "cmp",
+ { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xa800,
+ (PTR) & fmt_cmpi_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* cmp2 $m4,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_CMP2, "cmp2", "cmp2",
+ { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xa900,
+ (PTR) & fmt_cmp2_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* and $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_AND, "and", "and",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x8200,
+ (PTR) & fmt_and_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* or $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_OR, "or", "or",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x9200,
+ (PTR) & fmt_and_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* eor $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_EOR, "eor", "eor",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x9a00,
+ (PTR) & fmt_and_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* and $Rj,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ANDM, "andm", "and",
+ { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x8400,
+ (PTR) & fmt_andm_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* andh $Rj,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ANDH, "andh", "andh",
+ { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x8500,
+ (PTR) & fmt_andh_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* andb $Rj,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ANDB, "andb", "andb",
+ { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x8600,
+ (PTR) & fmt_andb_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* or $Rj,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ORM, "orm", "or",
+ { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x9400,
+ (PTR) & fmt_andm_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* orh $Rj,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ORH, "orh", "orh",
+ { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x9500,
+ (PTR) & fmt_andh_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* orb $Rj,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ORB, "orb", "orb",
+ { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x9600,
+ (PTR) & fmt_andb_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* eor $Rj,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_EORM, "eorm", "eor",
+ { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x9c00,
+ (PTR) & fmt_andm_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* eorh $Rj,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_EORH, "eorh", "eorh",
+ { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x9d00,
+ (PTR) & fmt_andh_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* eorb $Rj,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_EORB, "eorb", "eorb",
+ { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x9e00,
+ (PTR) & fmt_andb_ops[0],
+ { 0, 0, { 0 } }
+ },
+/* bandl $u4,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BANDL, "bandl", "bandl",
+ { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x8000,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* borl $u4,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BORL, "borl", "borl",
+ { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x9000,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* beorl $u4,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BEORL, "beorl", "beorl",
+ { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x9800,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* bandh $u4,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BANDH, "bandh", "bandh",
+ { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x8100,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* borh $u4,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BORH, "borh", "borh",
+ { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x9100,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* beorh $u4,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BEORH, "beorh", "beorh",
+ { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x9900,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* btstl $u4,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BTSTL, "btstl", "btstl",
+ { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x8800,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* btsth $u4,@$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BTSTH, "btsth", "btsth",
+ { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x8900,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* mul $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_MUL, "mul", "mul",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xaf00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* mulu $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_MULU, "mulu", "mulu",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xab00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* mulh $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_MULH, "mulh", "mulh",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xbf00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* muluh $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_MULUH, "muluh", "muluh",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xbb00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* div0s $Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DIV0S, "div0s", "div0s",
+ { { MNEM, ' ', OP (RI), 0 } },
+ { 16, 16, 0xfff0 }, 0x9740,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* div0u $Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DIV0U, "div0u", "div0u",
+ { { MNEM, ' ', OP (RI), 0 } },
+ { 16, 16, 0xfff0 }, 0x9750,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* div1 $Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DIV1, "div1", "div1",
+ { { MNEM, ' ', OP (RI), 0 } },
+ { 16, 16, 0xfff0 }, 0x9760,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* div2 $Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DIV2, "div2", "div2",
+ { { MNEM, ' ', OP (RI), 0 } },
+ { 16, 16, 0xfff0 }, 0x9770,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* div3 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DIV3, "div3", "div3",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x9f60,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* div4s */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DIV4S, "div4s", "div4s",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x9f70,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* lsl $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LSL, "lsl", "lsl",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xb600,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* lsl $u4,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LSLI, "lsli", "lsl",
+ { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xb400,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* lsl2 $u4,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LSL2, "lsl2", "lsl2",
+ { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xb500,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* lsr $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LSR, "lsr", "lsr",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xb200,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* lsr $u4,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LSRI, "lsri", "lsr",
+ { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xb000,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* lsr2 $u4,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LSR2, "lsr2", "lsr2",
+ { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xb100,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* asr $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ASR, "asr", "asr",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xba00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* asr $u4,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ASRI, "asri", "asr",
+ { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xb800,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* asr2 $u4,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ASR2, "asr2", "asr2",
+ { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xb900,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ldi:8 $i8,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDI_8, "ldi:8", "ldi:8",
+ { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
+ { 16, 16, 0xf000 }, 0xc000,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ld @$Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LD, "ld", "ld",
+ { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x400,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* lduh @$Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDUH, "lduh", "lduh",
+ { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x500,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ldub @$Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDUB, "ldub", "ldub",
+ { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x600,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ld @(R13,$Rj),$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDR13, "ldr13", "ld",
+ { { MNEM, ' ', '@', '(', 'R', '1', '3', ',', OP (RJ), ')', ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x0,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* lduh @(R13,$Rj),$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDR13UH, "ldr13uh", "lduh",
+ { { MNEM, ' ', '@', '(', 'R', '1', '3', ',', OP (RJ), ')', ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x100,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ldub @(R13,$Rj),$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDR13UB, "ldr13ub", "ldub",
+ { { MNEM, ' ', '@', '(', 'R', '1', '3', ',', OP (RJ), ')', ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x200,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ld @(R14,$o8),$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDR14, "ldr14", "ld",
+ { { MNEM, ' ', '@', '(', 'R', '1', '4', ',', OP (O8), ')', ',', OP (RI), 0 } },
+ { 16, 16, 0xf000 }, 0x2000,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* lduh @(R14,$o8),$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDR14UH, "ldr14uh", "lduh",
+ { { MNEM, ' ', '@', '(', 'R', '1', '4', ',', OP (O8), ')', ',', OP (RI), 0 } },
+ { 16, 16, 0xf000 }, 0x4000,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ldub @(R14,$o8),$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDR14UB, "ldr14ub", "ldub",
+ { { MNEM, ' ', '@', '(', 'R', '1', '4', ',', OP (O8), ')', ',', OP (RI), 0 } },
+ { 16, 16, 0xf000 }, 0x6000,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ld @(R15,$u4),$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDR15, "ldr15", "ld",
+ { { MNEM, ' ', '@', '(', 'R', '1', '5', ',', OP (U4), ')', ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x300,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ld @R15+,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDR15GR, "ldr15gr", "ld",
+ { { MNEM, ' ', '@', 'R', '1', '5', '+', ',', OP (RI), 0 } },
+ { 16, 16, 0xfff0 }, 0x700,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ld @R15+,$Rs2 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDR15DR, "ldr15dr", "ld",
+ { { MNEM, ' ', '@', 'R', '1', '5', '+', ',', OP (RS2), 0 } },
+ { 16, 16, 0xfff0 }, 0x780,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ld @R15+,ps */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDR15PS, "ldr15ps", "ld",
+ { { MNEM, ' ', '@', 'R', '1', '5', '+', ',', 'p', 's', 0 } },
+ { 16, 16, 0xffff }, 0x790,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* st $Ri,@Rj */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ST, "st", "st",
+ { { MNEM, ' ', OP (RI), ',', '@', 'R', 'j', 0 } },
+ { 16, 16, 0xff00 }, 0x1400,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* sth $Ri,@Rj */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STH, "sth", "sth",
+ { { MNEM, ' ', OP (RI), ',', '@', 'R', 'j', 0 } },
+ { 16, 16, 0xff00 }, 0x1500,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* stb $Ri,@Rj */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STB, "stb", "stb",
+ { { MNEM, ' ', OP (RI), ',', '@', 'R', 'j', 0 } },
+ { 16, 16, 0xff00 }, 0x1600,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* st $Ri,@(R13,$Rj) */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STR13, "str13", "st",
+ { { MNEM, ' ', OP (RI), ',', '@', '(', 'R', '1', '3', ',', OP (RJ), ')', 0 } },
+ { 16, 16, 0xff00 }, 0x1000,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* sth $Ri,@(R13,$Rj) */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STR13H, "str13h", "sth",
+ { { MNEM, ' ', OP (RI), ',', '@', '(', 'R', '1', '3', ',', OP (RJ), ')', 0 } },
+ { 16, 16, 0xff00 }, 0x1100,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* stb $Ri,@(R13,$Rj) */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STR13B, "str13b", "stb",
+ { { MNEM, ' ', OP (RI), ',', '@', '(', 'R', '1', '3', ',', OP (RJ), ')', 0 } },
+ { 16, 16, 0xff00 }, 0x1200,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* st $Ri,@(R14,$o8) */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STR14, "str14", "st",
+ { { MNEM, ' ', OP (RI), ',', '@', '(', 'R', '1', '4', ',', OP (O8), ')', 0 } },
+ { 16, 16, 0xf000 }, 0x3000,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* sth $Ri,@(R14,$o8) */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STR14H, "str14h", "sth",
+ { { MNEM, ' ', OP (RI), ',', '@', '(', 'R', '1', '4', ',', OP (O8), ')', 0 } },
+ { 16, 16, 0xf000 }, 0x5000,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* stb $Ri,@(R14,$o8) */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STR14B, "str14b", "stb",
+ { { MNEM, ' ', OP (RI), ',', '@', '(', 'R', '1', '4', ',', OP (O8), ')', 0 } },
+ { 16, 16, 0xf000 }, 0x7000,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* st $Ri,@(R15,$u4) */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STR15, "str15", "st",
+ { { MNEM, ' ', OP (RI), ',', '@', '(', 'R', '1', '5', ',', OP (U4), ')', 0 } },
+ { 16, 16, 0xff00 }, 0x1300,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* st $Ri,@-R15 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STR15GR, "str15gr", "st",
+ { { MNEM, ' ', OP (RI), ',', '@', '-', 'R', '1', '5', 0 } },
+ { 16, 16, 0xfff0 }, 0x1700,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* st $Rs2,@-R15 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STR15DR, "str15dr", "st",
+ { { MNEM, ' ', OP (RS2), ',', '@', '-', 'R', '1', '5', 0 } },
+ { 16, 16, 0xfff0 }, 0x1780,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* st ps,@-R15 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STR15PS, "str15ps", "st",
+ { { MNEM, ' ', 'p', 's', ',', '@', '-', 'R', '1', '5', 0 } },
+ { 16, 16, 0xffff }, 0x1790,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* mov $Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_MOV, "mov", "mov",
+ { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x8b00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* mov $Rs1,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_MOVDR, "movdr", "mov",
+ { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0xb700,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* mov ps,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_MOVPS, "movps", "mov",
+ { { MNEM, ' ', 'p', 's', ',', OP (RI), 0 } },
+ { 16, 16, 0xfff0 }, 0x1710,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* mov $Ri,$Rs1 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_MOV2DR, "mov2dr", "mov",
+ { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
+ { 16, 16, 0xff00 }, 0xb300,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* mov $Ri,ps */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_MOV2PS, "mov2ps", "mov",
+ { { MNEM, ' ', OP (RI), ',', 'p', 's', 0 } },
+ { 16, 16, 0xfff0 }, 0x710,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* jmp @$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_JMP, "jmp", "jmp",
+ { { MNEM, ' ', '@', OP (RI), 0 } },
+ { 16, 16, 0xfff0 }, 0x9700,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* call $label12 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_CALL, "call", "call",
+ { { MNEM, ' ', OP (LABEL12), 0 } },
+ { 16, 16, 0xf400 }, 0xd000,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* call @$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_CALLR, "callr", "call",
+ { { MNEM, ' ', '@', OP (RI), 0 } },
+ { 16, 16, 0xfff0 }, 0x9710,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ret */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_RET, "ret", "ret",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x9720,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* int $u8 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_INT, "int", "int",
+ { { MNEM, ' ', OP (U8), 0 } },
+ { 16, 16, 0xff00 }, 0x1f00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* int3 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_INTE, "inte", "int3",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x9f30,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* reti */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_RETI, "reti", "reti",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x9730,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* bra:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BRA, "bra", "bra:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xe000,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* bno:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BNO, "bno", "bno:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xe100,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* beq:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BEQ, "beq", "beq:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xe200,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* bne:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BNE, "bne", "bne:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xe300,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* bc:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BC, "bc", "bc:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xe400,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* bnc:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BNC, "bnc", "bnc:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xe500,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* bn:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BN, "bn", "bn:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xe600,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* bp:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BP, "bp", "bp:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xe700,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* bv:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BV, "bv", "bv:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xe800,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* bnv:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BNV, "bnv", "bnv:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xe900,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* blt:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BLT, "blt", "blt:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xea00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* bge:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BGE, "bge", "bge:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xeb00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ble:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BLE, "ble", "ble:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xec00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* bgt:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BGT, "bgt", "bgt:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xed00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* bls:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BLS, "bls", "bls:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xee00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* bhi:D $label9 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_BHI, "bhi", "bhi:D",
+ { { MNEM, ' ', OP (LABEL9), 0 } },
+ { 16, 16, 0xff00 }, 0xef00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmov @$dir10,R13 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
+ { { MNEM, ' ', '@', OP (DIR10), ',', 'R', '1', '3', 0 } },
+ { 16, 16, 0xff00 }, 0x800,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmovh @$dir10,R13 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
+ { { MNEM, ' ', '@', OP (DIR10), ',', 'R', '1', '3', 0 } },
+ { 16, 16, 0xff00 }, 0x900,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmovb @$dir10,R13 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
+ { { MNEM, ' ', '@', OP (DIR10), ',', 'R', '1', '3', 0 } },
+ { 16, 16, 0xff00 }, 0xa00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmov R13,@$dir10 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOVR13, "dmovr13", "dmov",
+ { { MNEM, ' ', 'R', '1', '3', ',', '@', OP (DIR10), 0 } },
+ { 16, 16, 0xff00 }, 0x1800,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmovh R13,@$dir10 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
+ { { MNEM, ' ', 'R', '1', '3', ',', '@', OP (DIR10), 0 } },
+ { 16, 16, 0xff00 }, 0x1900,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmovb R13,@$dir10 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
+ { { MNEM, ' ', 'R', '1', '3', ',', '@', OP (DIR10), 0 } },
+ { 16, 16, 0xff00 }, 0x1a00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmov @$dir10,R13+ */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
+ { { MNEM, ' ', '@', OP (DIR10), ',', 'R', '1', '3', '+', 0 } },
+ { 16, 16, 0xff00 }, 0xc00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmovh @$dir10,R13+ */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
+ { { MNEM, ' ', '@', OP (DIR10), ',', 'R', '1', '3', '+', 0 } },
+ { 16, 16, 0xff00 }, 0xd00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmovb @$dir10,R13+ */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
+ { { MNEM, ' ', '@', OP (DIR10), ',', 'R', '1', '3', '+', 0 } },
+ { 16, 16, 0xff00 }, 0xe00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmov R13+,@$dir10 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOV13PI, "dmov13pi", "dmov",
+ { { MNEM, ' ', 'R', '1', '3', '+', ',', '@', OP (DIR10), 0 } },
+ { 16, 16, 0xff00 }, 0x1c00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmovh R13+,@$dir10 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOV13PIH, "dmov13pih", "dmovh",
+ { { MNEM, ' ', 'R', '1', '3', '+', ',', '@', OP (DIR10), 0 } },
+ { 16, 16, 0xff00 }, 0x1d00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmovb R13+,@$dir10 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOV13PIB, "dmov13pib", "dmovb",
+ { { MNEM, ' ', 'R', '1', '3', '+', ',', '@', OP (DIR10), 0 } },
+ { 16, 16, 0xff00 }, 0x1e00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmov @$dir10,-R15 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
+ { { MNEM, ' ', '@', OP (DIR10), ',', '-', 'R', '1', '5', 0 } },
+ { 16, 16, 0xff00 }, 0xb00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* dmov R15+,@$dir10 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_DMOV15PI, "dmov15pi", "dmov",
+ { { MNEM, ' ', 'R', '1', '5', '+', ',', '@', OP (DIR10), 0 } },
+ { 16, 16, 0xff00 }, 0x1b00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ldres @$Ri+,$u4 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDRES, "ldres", "ldres",
+ { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
+ { 16, 16, 0xff00 }, 0xbc00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* ldres $u4,@$Ri+ */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STRES, "stres", "ldres",
+ { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
+ { 16, 16, 0xff00 }, 0xbd00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* nop */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_NOP, "nop", "nop",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x9fa0,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* andccr $u8 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ANDCCR, "andccr", "andccr",
+ { { MNEM, ' ', OP (U8), 0 } },
+ { 16, 16, 0xff00 }, 0x8300,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* orccr $u8 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ORCCR, "orccr", "orccr",
+ { { MNEM, ' ', OP (U8), 0 } },
+ { 16, 16, 0xff00 }, 0x9300,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* stilm $u8 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_STILM, "stilm", "stilm",
+ { { MNEM, ' ', OP (U8), 0 } },
+ { 16, 16, 0xff00 }, 0x8700,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* addsp $s10 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ADDSP, "addsp", "addsp",
+ { { MNEM, ' ', OP (S10), 0 } },
+ { 16, 16, 0xff00 }, 0xa300,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* extsb $Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_EXTSB, "extsb", "extsb",
+ { { MNEM, ' ', OP (RI), 0 } },
+ { 16, 16, 0xfff0 }, 0x9780,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* extub $Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_EXTUB, "extub", "extub",
+ { { MNEM, ' ', OP (RI), 0 } },
+ { 16, 16, 0xfff0 }, 0x9790,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* extsh $Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_EXTSH, "extsh", "extsh",
+ { { MNEM, ' ', OP (RI), 0 } },
+ { 16, 16, 0xfff0 }, 0x97a0,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* extuh $Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_EXTUH, "extuh", "extuh",
+ { { MNEM, ' ', OP (RI), 0 } },
+ { 16, 16, 0xfff0 }, 0x97b0,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* enter $u10 */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_ENTER, "enter", "enter",
+ { { MNEM, ' ', OP (U10), 0 } },
+ { 16, 16, 0xff00 }, 0xf00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* leave */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LEAVE, "leave", "leave",
+ { { MNEM, 0 } },
+ { 16, 16, 0xffff }, 0x9f90,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
+/* xchb @$Rj,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_XCHB, "xchb", "xchb",
+ { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
+ { 16, 16, 0xff00 }, 0x8a00,
+ (PTR) 0,
+ { 0, 0, { 0 } }
+ },
};
#undef A
@@ -632,6 +2000,51 @@ fr30_cgen_get_int_operand (opindex, fields)
case FR30_OPERAND_RJ :
value = fields->f_Rj;
break;
+ case FR30_OPERAND_RS1 :
+ value = fields->f_Rs1;
+ break;
+ case FR30_OPERAND_RS2 :
+ value = fields->f_Rs2;
+ break;
+ case FR30_OPERAND_U4 :
+ value = fields->f_u4;
+ break;
+ case FR30_OPERAND_M4 :
+ value = fields->f_m4;
+ break;
+ case FR30_OPERAND_I8 :
+ value = fields->f_i8;
+ break;
+ case FR30_OPERAND_U8 :
+ value = fields->f_u8;
+ break;
+ case FR30_OPERAND_O8 :
+ value = fields->f_o8;
+ break;
+ case FR30_OPERAND_S10 :
+ value = fields->f_s10;
+ break;
+ case FR30_OPERAND_U10 :
+ value = fields->f_u10;
+ break;
+ case FR30_OPERAND_DIR8 :
+ value = fields->f_dir8;
+ break;
+ case FR30_OPERAND_DIR9 :
+ value = fields->f_dir9;
+ break;
+ case FR30_OPERAND_DIR10 :
+ value = fields->f_dir10;
+ break;
+ case FR30_OPERAND_LABEL9 :
+ value = fields->f_rel8;
+ break;
+ case FR30_OPERAND_LABEL12 :
+ value = fields->f_rel11;
+ break;
+ case FR30_OPERAND_CC :
+ value = fields->f_cc;
+ break;
default :
/* xgettext:c-format */
@@ -658,6 +2071,51 @@ fr30_cgen_get_vma_operand (opindex, fields)
case FR30_OPERAND_RJ :
value = fields->f_Rj;
break;
+ case FR30_OPERAND_RS1 :
+ value = fields->f_Rs1;
+ break;
+ case FR30_OPERAND_RS2 :
+ value = fields->f_Rs2;
+ break;
+ case FR30_OPERAND_U4 :
+ value = fields->f_u4;
+ break;
+ case FR30_OPERAND_M4 :
+ value = fields->f_m4;
+ break;
+ case FR30_OPERAND_I8 :
+ value = fields->f_i8;
+ break;
+ case FR30_OPERAND_U8 :
+ value = fields->f_u8;
+ break;
+ case FR30_OPERAND_O8 :
+ value = fields->f_o8;
+ break;
+ case FR30_OPERAND_S10 :
+ value = fields->f_s10;
+ break;
+ case FR30_OPERAND_U10 :
+ value = fields->f_u10;
+ break;
+ case FR30_OPERAND_DIR8 :
+ value = fields->f_dir8;
+ break;
+ case FR30_OPERAND_DIR9 :
+ value = fields->f_dir9;
+ break;
+ case FR30_OPERAND_DIR10 :
+ value = fields->f_dir10;
+ break;
+ case FR30_OPERAND_LABEL9 :
+ value = fields->f_rel8;
+ break;
+ case FR30_OPERAND_LABEL12 :
+ value = fields->f_rel11;
+ break;
+ case FR30_OPERAND_CC :
+ value = fields->f_cc;
+ break;
default :
/* xgettext:c-format */
@@ -688,6 +2146,51 @@ fr30_cgen_set_int_operand (opindex, fields, value)
case FR30_OPERAND_RJ :
fields->f_Rj = value;
break;
+ case FR30_OPERAND_RS1 :
+ fields->f_Rs1 = value;
+ break;
+ case FR30_OPERAND_RS2 :
+ fields->f_Rs2 = value;
+ break;
+ case FR30_OPERAND_U4 :
+ fields->f_u4 = value;
+ break;
+ case FR30_OPERAND_M4 :
+ fields->f_m4 = value;
+ break;
+ case FR30_OPERAND_I8 :
+ fields->f_i8 = value;
+ break;
+ case FR30_OPERAND_U8 :
+ fields->f_u8 = value;
+ break;
+ case FR30_OPERAND_O8 :
+ fields->f_o8 = value;
+ break;
+ case FR30_OPERAND_S10 :
+ fields->f_s10 = value;
+ break;
+ case FR30_OPERAND_U10 :
+ fields->f_u10 = value;
+ break;
+ case FR30_OPERAND_DIR8 :
+ fields->f_dir8 = value;
+ break;
+ case FR30_OPERAND_DIR9 :
+ fields->f_dir9 = value;
+ break;
+ case FR30_OPERAND_DIR10 :
+ fields->f_dir10 = value;
+ break;
+ case FR30_OPERAND_LABEL9 :
+ fields->f_rel8 = value;
+ break;
+ case FR30_OPERAND_LABEL12 :
+ fields->f_rel11 = value;
+ break;
+ case FR30_OPERAND_CC :
+ fields->f_cc = value;
+ break;
default :
/* xgettext:c-format */
@@ -711,6 +2214,51 @@ fr30_cgen_set_vma_operand (opindex, fields, value)
case FR30_OPERAND_RJ :
fields->f_Rj = value;
break;
+ case FR30_OPERAND_RS1 :
+ fields->f_Rs1 = value;
+ break;
+ case FR30_OPERAND_RS2 :
+ fields->f_Rs2 = value;
+ break;
+ case FR30_OPERAND_U4 :
+ fields->f_u4 = value;
+ break;
+ case FR30_OPERAND_M4 :
+ fields->f_m4 = value;
+ break;
+ case FR30_OPERAND_I8 :
+ fields->f_i8 = value;
+ break;
+ case FR30_OPERAND_U8 :
+ fields->f_u8 = value;
+ break;
+ case FR30_OPERAND_O8 :
+ fields->f_o8 = value;
+ break;
+ case FR30_OPERAND_S10 :
+ fields->f_s10 = value;
+ break;
+ case FR30_OPERAND_U10 :
+ fields->f_u10 = value;
+ break;
+ case FR30_OPERAND_DIR8 :
+ fields->f_dir8 = value;
+ break;
+ case FR30_OPERAND_DIR9 :
+ fields->f_dir9 = value;
+ break;
+ case FR30_OPERAND_DIR10 :
+ fields->f_dir10 = value;
+ break;
+ case FR30_OPERAND_LABEL9 :
+ fields->f_rel8 = value;
+ break;
+ case FR30_OPERAND_LABEL12 :
+ fields->f_rel11 = value;
+ break;
+ case FR30_OPERAND_CC :
+ fields->f_cc = value;
+ break;
default :
/* xgettext:c-format */
diff --git a/opcodes/fr30-opc.h b/opcodes/fr30-opc.h
index eb2dac9..2a8259a 100644
--- a/opcodes/fr30-opc.h
+++ b/opcodes/fr30-opc.h
@@ -80,11 +80,24 @@ typedef enum insn_op3 {
, OP3_C, OP3_D, OP3_E, OP3_F
} INSN_OP3;
+/* Enum declaration for insn op4 enums. */
+typedef enum insn_op4 {
+ OP4_0
+} INSN_OP4;
+
/* Enum declaration for insn op5 enums. */
typedef enum insn_op5 {
OP5_0, OP5_1
} INSN_OP5;
+/* Enum declaration for insn cc enums. */
+typedef enum insn_cc {
+ CC_RA, CC_NO, CC_EQ, CC_NE
+ , CC_C, CC_NC, CC_N, CC_P
+ , CC_V, CC_NV, CC_LT, CC_GE
+ , CC_LE, CC_GT, CC_LS, CC_HI
+} INSN_CC;
+
/* Enum declaration for general registers. */
typedef enum h_gr {
H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15, H_GR_R0 = 0
@@ -97,13 +110,9 @@ typedef enum h_gr {
/* Enum declaration for dedicated registers. */
typedef enum h_dr {
H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
+ , H_DR_MDH, H_DR_MDL
} H_DR;
-/* Enum declaration for multiplication and division registers. */
-typedef enum h_mdr {
- H_MDR_MDH = 4, H_MDR_MDL = 5
-} H_MDR;
-
/* Enum declaration for control registers. */
typedef enum h_cr {
H_CR_PC, H_CR_PS
@@ -111,7 +120,11 @@ typedef enum h_cr {
/* Enum declaration for fr30 operand types. */
typedef enum cgen_operand_type {
- FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_NBIT
+ FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RS1
+ , FR30_OPERAND_RS2, FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_M4
+ , FR30_OPERAND_I8, FR30_OPERAND_U8, FR30_OPERAND_O8, FR30_OPERAND_S10
+ , FR30_OPERAND_U10, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9, FR30_OPERAND_DIR10
+ , FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_CC, FR30_OPERAND_NBIT
, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_MAX
} CGEN_OPERAND_TYPE;
@@ -129,13 +142,13 @@ typedef enum mach_attr {
#define MAX_OPERANDS ((int) FR30_OPERAND_MAX)
/* Maximum number of operands referenced by any insn. */
-#define MAX_OPERAND_INSTANCES 7
+#define MAX_OPERAND_INSTANCES 8
/* Hardware, operand and instruction attribute indices. */
/* Enum declaration for cgen_hw attrs. */
typedef enum cgen_hw_attr {
- CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS, CGEN_HW_PC, CGEN_HW_PROFILE
+ CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
} CGEN_HW_ATTR;
/* Number of non-boolean elements in cgen_hw. */
@@ -143,8 +156,9 @@ typedef enum cgen_hw_attr {
/* Enum declaration for cgen_operand attrs. */
typedef enum cgen_operand_attr {
- CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX
- , CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_UNSIGNED
+ CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PCREL_ADDR
+ , CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED
+ , CGEN_OPERAND_UNSIGNED
} CGEN_OPERAND_ATTR;
/* Number of non-boolean elements in cgen_operand. */
@@ -161,7 +175,41 @@ typedef enum cgen_insn_attr {
/* Enum declaration for fr30 instruction types. */
typedef enum cgen_insn_type {
- FR30_INSN_INVALID, FR30_INSN_ADD, FR30_INSN_MAX
+ FR30_INSN_INVALID, FR30_INSN_ADD, FR30_INSN_ADDI, FR30_INSN_ADD2
+ , FR30_INSN_ADDC, FR30_INSN_ADDN, FR30_INSN_ADDNI, FR30_INSN_ADDN2
+ , FR30_INSN_SUB, FR30_INSN_SUBC, FR30_INSN_SUBN, FR30_INSN_CMP
+ , FR30_INSN_CMPI, FR30_INSN_CMP2, FR30_INSN_AND, FR30_INSN_OR
+ , FR30_INSN_EOR, FR30_INSN_ANDM, FR30_INSN_ANDH, FR30_INSN_ANDB
+ , FR30_INSN_ORM, FR30_INSN_ORH, FR30_INSN_ORB, FR30_INSN_EORM
+ , FR30_INSN_EORH, FR30_INSN_EORB, FR30_INSN_BANDL, FR30_INSN_BORL
+ , FR30_INSN_BEORL, FR30_INSN_BANDH, FR30_INSN_BORH, FR30_INSN_BEORH
+ , FR30_INSN_BTSTL, FR30_INSN_BTSTH, FR30_INSN_MUL, FR30_INSN_MULU
+ , FR30_INSN_MULH, FR30_INSN_MULUH, FR30_INSN_DIV0S, FR30_INSN_DIV0U
+ , FR30_INSN_DIV1, FR30_INSN_DIV2, FR30_INSN_DIV3, FR30_INSN_DIV4S
+ , FR30_INSN_LSL, FR30_INSN_LSLI, FR30_INSN_LSL2, FR30_INSN_LSR
+ , FR30_INSN_LSRI, FR30_INSN_LSR2, FR30_INSN_ASR, FR30_INSN_ASRI
+ , FR30_INSN_ASR2, FR30_INSN_LDI_8, FR30_INSN_LD, FR30_INSN_LDUH
+ , FR30_INSN_LDUB, FR30_INSN_LDR13, FR30_INSN_LDR13UH, FR30_INSN_LDR13UB
+ , FR30_INSN_LDR14, FR30_INSN_LDR14UH, FR30_INSN_LDR14UB, FR30_INSN_LDR15
+ , FR30_INSN_LDR15GR, FR30_INSN_LDR15DR, FR30_INSN_LDR15PS, FR30_INSN_ST
+ , FR30_INSN_STH, FR30_INSN_STB, FR30_INSN_STR13, FR30_INSN_STR13H
+ , FR30_INSN_STR13B, FR30_INSN_STR14, FR30_INSN_STR14H, FR30_INSN_STR14B
+ , FR30_INSN_STR15, FR30_INSN_STR15GR, FR30_INSN_STR15DR, FR30_INSN_STR15PS
+ , FR30_INSN_MOV, FR30_INSN_MOVDR, FR30_INSN_MOVPS, FR30_INSN_MOV2DR
+ , FR30_INSN_MOV2PS, FR30_INSN_JMP, FR30_INSN_CALL, FR30_INSN_CALLR
+ , FR30_INSN_RET, FR30_INSN_INT, FR30_INSN_INTE, FR30_INSN_RETI
+ , FR30_INSN_BRA, FR30_INSN_BNO, FR30_INSN_BEQ, FR30_INSN_BNE
+ , FR30_INSN_BC, FR30_INSN_BNC, FR30_INSN_BN, FR30_INSN_BP
+ , FR30_INSN_BV, FR30_INSN_BNV, FR30_INSN_BLT, FR30_INSN_BGE
+ , FR30_INSN_BLE, FR30_INSN_BGT, FR30_INSN_BLS, FR30_INSN_BHI
+ , FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B, FR30_INSN_DMOVR13
+ , FR30_INSN_DMOVR13H, FR30_INSN_DMOVR13B, FR30_INSN_DMOV2R13PI, FR30_INSN_DMOV2R13PIH
+ , FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOV13PI, FR30_INSN_DMOV13PIH, FR30_INSN_DMOV13PIB
+ , FR30_INSN_DMOV2R15PD, FR30_INSN_DMOV15PI, FR30_INSN_LDRES, FR30_INSN_STRES
+ , FR30_INSN_NOP, FR30_INSN_ANDCCR, FR30_INSN_ORCCR, FR30_INSN_STILM
+ , FR30_INSN_ADDSP, FR30_INSN_EXTSB, FR30_INSN_EXTUB, FR30_INSN_EXTSH
+ , FR30_INSN_EXTUH, FR30_INSN_ENTER, FR30_INSN_LEAVE, FR30_INSN_XCHB
+ , FR30_INSN_MAX
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
@@ -179,18 +227,25 @@ struct cgen_fields
long f_op1;
long f_op2;
long f_op3;
+ long f_op4;
long f_op5;
+ long f_cc;
long f_Rj;
long f_Ri;
- long f_Rs;
+ long f_Rs1;
+ long f_Rs2;
long f_u4;
long f_i4;
long f_m4;
long f_u8;
long f_i8;
long f_o8;
+ long f_s10;
+ long f_u10;
long f_rel8;
- long f_dir;
+ long f_dir8;
+ long f_dir9;
+ long f_dir10;
long f_rlist;
long f_rel11;
int length;
@@ -205,8 +260,8 @@ extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
typedef enum hw_type {
HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
, HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_DR
- , HW_H_MDR, HW_H_CR, HW_H_NBIT, HW_H_ZBIT
- , HW_H_VBIT, HW_H_CBIT, HW_MAX
+ , HW_H_CR, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
+ , HW_H_CBIT, HW_MAX
} HW_TYPE;
#define MAX_HW ((int) HW_MAX)
@@ -215,7 +270,6 @@ typedef enum hw_type {
extern CGEN_KEYWORD fr30_cgen_opval_h_gr;
extern CGEN_KEYWORD fr30_cgen_opval_h_dr;
-extern CGEN_KEYWORD fr30_cgen_opval_h_mdr;
extern CGEN_KEYWORD fr30_cgen_opval_h_cr;
#define CGEN_INIT_PARSE(od) \
generated by cgit v1.1 at 2024-12-20 05:06:24 +0000