diff options
| -rw-r--r-- | sim/testsuite/sim/sh/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/testsuite/sim/sh/allinsn.exp | 3 | ||||
| -rw-r--r-- | sim/testsuite/sim/sh/and.s | 89 | ||||
| -rw-r--r-- | sim/testsuite/sim/sh/movi.s | 35 | ||||
| -rw-r--r-- | sim/testsuite/sim/sh/sett.s | 65 | ||||
| -rw-r--r-- | sim/testsuite/sim/sh/testutils.inc | 6 |
6 files changed, 201 insertions, 3 deletions
diff --git a/sim/testsuite/sim/sh/ChangeLog b/sim/testsuite/sim/sh/ChangeLog index ed3f5ba..e3fecbd 100644 --- a/sim/testsuite/sim/sh/ChangeLog +++ b/sim/testsuite/sim/sh/ChangeLog @@ -1,3 +1,9 @@ +2004-02-12 Michael Snyder <msnyder@redhat.com> + + * and.s, movi.s, sett.s: New files. + * allinsn.exp: Add new tests. + * testutils.inc (set_sr_bit): Fix macro labels. + 2004-01-07 Michael Snyder <msnyder@redhat.com> * dmxy.s, fipr.s, fpchg.s, ldrc.s, loop.s, movli.s, movua.s, diff --git a/sim/testsuite/sim/sh/allinsn.exp b/sim/testsuite/sim/sh/allinsn.exp index 23a53db..0ec39f5 100644 --- a/sim/testsuite/sim/sh/allinsn.exp +++ b/sim/testsuite/sim/sh/allinsn.exp @@ -4,6 +4,7 @@ set all "sh shdsp" if [istarget sh-*elf] { run_sim_test add.s $all + run_sim_test and.s $all run_sim_test dmxy.s shdsp run_sim_test fabs.s sh run_sim_test fadd.s sh @@ -31,6 +32,7 @@ if [istarget sh-*elf] { run_sim_test loop.s shdsp run_sim_test macl.s sh run_sim_test macw.s sh + run_sim_test movi.s $all run_sim_test movli.s $all run_sim_test movua.s $all run_sim_test movxy.s shdsp @@ -50,6 +52,7 @@ if [istarget sh-*elf] { run_sim_test pshlr.s shdsp run_sim_test psub.s shdsp run_sim_test pswap.s shdsp + run_sim_test sett.s $all run_sim_test shll.s $all run_sim_test shll2.s $all run_sim_test shll8.s $all diff --git a/sim/testsuite/sim/sh/and.s b/sim/testsuite/sim/sh/and.s new file mode 100644 index 0000000..0093447 --- /dev/null +++ b/sim/testsuite/sim/sh/and.s @@ -0,0 +1,89 @@ +# sh testcase for and +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 +_y: .long 0x55555555 + + start + +and_reg_reg_direct: + set_grs_a5a5 + mov.l i, r1 + mov.l j, r2 + and r1, r2 + test_gr0_a5a5 + assertreg 0xa5a5a5a5 r1 + assertreg 0xa0a0a0a0 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + bra and_imm_reg + nop + + .align 2 +i: .long 0xa5a5a5a5 +j: .long 0xaaaaaaaa + +and_imm_reg: + set_grs_a5a5 + and #0xff, r0 + assertreg 0xa5, r0 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +and_b_imm_ind: + set_grs_a5a5 + mov.l x, r0 + and.b #0x55, @(r0, GBR) + mov.l @r0, r0 + + assertreg 0xa5a5a505, r0 + test_gr_a5a5 r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + .align 2 +x: .long _x +y: .long _y + diff --git a/sim/testsuite/sim/sh/movi.s b/sim/testsuite/sim/sh/movi.s new file mode 100644 index 0000000..b79f8d2 --- /dev/null +++ b/sim/testsuite/sim/sh/movi.s @@ -0,0 +1,35 @@ +# sh testcase for mov <#imm> +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +mov_i_reg: # Test <imm8> + set_grs_a5a5 + mov #-0x55, r1 + + assertreg 0xffffffab, r1 + + test_gr_a5a5 r0 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 + + diff --git a/sim/testsuite/sim/sh/sett.s b/sim/testsuite/sim/sh/sett.s new file mode 100644 index 0000000..fff2d2d --- /dev/null +++ b/sim/testsuite/sim/sh/sett.s @@ -0,0 +1,65 @@ +# sh testcase for sett, clrt, movt +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start +sett_1: set_grs_a5a5 + sett + bt .Lsett + nop + fail +.Lsett: + test_grs_a5a5 + +clrt_1: set_grs_a5a5 + clrt + bf .Lclrt + nop + fail +.Lclrt: + test_grs_a5a5 + +movt_1: set_grs_a5a5 + sett + movt r1 + test_gr_a5a5 r0 + assertreg 1, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + +movt_2: set_grs_a5a5 + clrt + movt r1 + test_gr_a5a5 r0 + assertreg 0, r1 + test_gr_a5a5 r2 + test_gr_a5a5 r3 + test_gr_a5a5 r4 + test_gr_a5a5 r5 + test_gr_a5a5 r6 + test_gr_a5a5 r7 + test_gr_a5a5 r8 + test_gr_a5a5 r9 + test_gr_a5a5 r10 + test_gr_a5a5 r11 + test_gr_a5a5 r12 + test_gr_a5a5 r13 + test_gr_a5a5 r14 + + pass + + exit 0 diff --git a/sim/testsuite/sim/sh/testutils.inc b/sim/testsuite/sim/sh/testutils.inc index 736934c..8d3895e 100644 --- a/sim/testsuite/sim/sh/testutils.inc +++ b/sim/testsuite/sim/sh/testutils.inc @@ -485,9 +485,9 @@ set_greg\@: bra .Lsrbit\@ nop .align 2 -.Lsrbitval: +.Lsrbitval\@: .long \val -.Lsrbit: +.Lsrbit\@: .endm .macro test_sr_bit_set val @@ -559,7 +559,7 @@ set_greg\@: .macro set_creg val reg - # + # [gbr, vbr, ssr, spc, sgr, dbr... ] push r0 mov.l .Lscrval\@, r0 ldc r0, \reg |