diff options
| -rw-r--r-- | cpu/ChangeLog | 4 | ||||
| -rw-r--r-- | cpu/frv.cpu | 17 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/frv-desc.c | 45 | ||||
| -rw-r--r-- | opcodes/frv-desc.h | 13 |
5 files changed, 68 insertions, 16 deletions
diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 3da548a..1fa7b9b 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,7 @@ +2007-04-30 Mark Salter <msalter@sadr.localdomain> + + * frv.cpu (spr-names): Support new coprocessor SPR registers. + 2007-04-20 Nick Clifton <nickc@redhat.com> * xc16x.cpu: Restore after accidentally overwriting this file with diff --git a/cpu/frv.cpu b/cpu/frv.cpu index 03f22a5..bae036d 100644 --- a/cpu/frv.cpu +++ b/cpu/frv.cpu @@ -2808,12 +2808,21 @@ (dbmr20 2084) (dbmr21 2085) (dbmr22 2086) (dbmr23 2087) (dbmr30 2088) (dbmr31 2089) (dbmr32 2090) (dbmr33 2091) - (cpcfr 2092) (cpcr 2093) (cpsr 2094) + (cpcfr 2304) (cpcr 2305) (cpsr 2306) (cptr 2307) + (cphsr0 2308) (cphsr1 2309) (cpesr0 2320) (cpesr1 2321) + (cpemr0 2322) (cpemr1 2323) - (cpesr0 2096) (cpesr1 2097) - (cpemr0 2098) (cpemr1 2099) + (iperr0 2324) (iperr1 2325) (ipjsr 2326) (ipjrr 2327) + (ipcsr0 2336) (ipcsr1 2337) (ipcwer0 2338) (ipcwer1 2339) + (ipcwr 2340) - (ihsr8 3848) + (mbhsr 2352) (mbssr 2353) (mbrsr 2354) (mbsdr 2355) + (mbrdr 2356) (mbsmr 2357) (mbstr0 2359) (mbstr1 2360) + + (slpr 2368) (sldr 2369) (slhsr 2370) (sltr 2371) + (slwr 2372) + + (ihsr8 3848) (ihsr9 3849) (ihsr10 3850) ) ) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0fa39c1..e751f9f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2007-04-30 Mark Salter <msalter@redhat.com> + + * frv-desc.c: Regenerate. + * frv-desc.h: Regenerate. + 2007-04-30 Alan Modra <amodra@bigpond.net.au> PR 4436 diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c index 39235a6..394b0cc 100644 --- a/opcodes/frv-desc.c +++ b/opcodes/frv-desc.c @@ -1537,20 +1537,47 @@ static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] = { "dbmr31", 2089, {0, {{{0, 0}}}}, 0, 0 }, { "dbmr32", 2090, {0, {{{0, 0}}}}, 0, 0 }, { "dbmr33", 2091, {0, {{{0, 0}}}}, 0, 0 }, - { "cpcfr", 2092, {0, {{{0, 0}}}}, 0, 0 }, - { "cpcr", 2093, {0, {{{0, 0}}}}, 0, 0 }, - { "cpsr", 2094, {0, {{{0, 0}}}}, 0, 0 }, - { "cpesr0", 2096, {0, {{{0, 0}}}}, 0, 0 }, - { "cpesr1", 2097, {0, {{{0, 0}}}}, 0, 0 }, - { "cpemr0", 2098, {0, {{{0, 0}}}}, 0, 0 }, - { "cpemr1", 2099, {0, {{{0, 0}}}}, 0, 0 }, - { "ihsr8", 3848, {0, {{{0, 0}}}}, 0, 0 } + { "cpcfr", 2304, {0, {{{0, 0}}}}, 0, 0 }, + { "cpcr", 2305, {0, {{{0, 0}}}}, 0, 0 }, + { "cpsr", 2306, {0, {{{0, 0}}}}, 0, 0 }, + { "cptr", 2307, {0, {{{0, 0}}}}, 0, 0 }, + { "cphsr0", 2308, {0, {{{0, 0}}}}, 0, 0 }, + { "cphsr1", 2309, {0, {{{0, 0}}}}, 0, 0 }, + { "cpesr0", 2320, {0, {{{0, 0}}}}, 0, 0 }, + { "cpesr1", 2321, {0, {{{0, 0}}}}, 0, 0 }, + { "cpemr0", 2322, {0, {{{0, 0}}}}, 0, 0 }, + { "cpemr1", 2323, {0, {{{0, 0}}}}, 0, 0 }, + { "iperr0", 2324, {0, {{{0, 0}}}}, 0, 0 }, + { "iperr1", 2325, {0, {{{0, 0}}}}, 0, 0 }, + { "ipjsr", 2326, {0, {{{0, 0}}}}, 0, 0 }, + { "ipjrr", 2327, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcsr0", 2336, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcsr1", 2337, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcwer0", 2338, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcwer1", 2339, {0, {{{0, 0}}}}, 0, 0 }, + { "ipcwr", 2340, {0, {{{0, 0}}}}, 0, 0 }, + { "mbhsr", 2352, {0, {{{0, 0}}}}, 0, 0 }, + { "mbssr", 2353, {0, {{{0, 0}}}}, 0, 0 }, + { "mbrsr", 2354, {0, {{{0, 0}}}}, 0, 0 }, + { "mbsdr", 2355, {0, {{{0, 0}}}}, 0, 0 }, + { "mbrdr", 2356, {0, {{{0, 0}}}}, 0, 0 }, + { "mbsmr", 2357, {0, {{{0, 0}}}}, 0, 0 }, + { "mbstr0", 2359, {0, {{{0, 0}}}}, 0, 0 }, + { "mbstr1", 2360, {0, {{{0, 0}}}}, 0, 0 }, + { "slpr", 2368, {0, {{{0, 0}}}}, 0, 0 }, + { "sldr", 2369, {0, {{{0, 0}}}}, 0, 0 }, + { "slhsr", 2370, {0, {{{0, 0}}}}, 0, 0 }, + { "sltr", 2371, {0, {{{0, 0}}}}, 0, 0 }, + { "slwr", 2372, {0, {{{0, 0}}}}, 0, 0 }, + { "ihsr8", 3848, {0, {{{0, 0}}}}, 0, 0 }, + { "ihsr9", 3849, {0, {{{0, 0}}}}, 0, 0 }, + { "ihsr10", 3850, {0, {{{0, 0}}}}, 0, 0 } }; CGEN_KEYWORD frv_cgen_opval_spr_names = { & frv_cgen_opval_spr_names_entries[0], - 1022, + 1049, 0, 0, 0, 0, "" }; diff --git a/opcodes/frv-desc.h b/opcodes/frv-desc.h index d94447f..96a3d99 100644 --- a/opcodes/frv-desc.h +++ b/opcodes/frv-desc.h @@ -470,9 +470,16 @@ typedef enum spr_names { , H_SPR_DBMR02 = 2078, H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080, H_SPR_DBMR11 = 2081 , H_SPR_DBMR12 = 2082, H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084, H_SPR_DBMR21 = 2085 , H_SPR_DBMR22 = 2086, H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088, H_SPR_DBMR31 = 2089 - , H_SPR_DBMR32 = 2090, H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2092, H_SPR_CPCR = 2093 - , H_SPR_CPSR = 2094, H_SPR_CPESR0 = 2096, H_SPR_CPESR1 = 2097, H_SPR_CPEMR0 = 2098 - , H_SPR_CPEMR1 = 2099, H_SPR_IHSR8 = 3848 + , H_SPR_DBMR32 = 2090, H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2304, H_SPR_CPCR = 2305 + , H_SPR_CPSR = 2306, H_SPR_CPTR = 2307, H_SPR_CPHSR0 = 2308, H_SPR_CPHSR1 = 2309 + , H_SPR_CPESR0 = 2320, H_SPR_CPESR1 = 2321, H_SPR_CPEMR0 = 2322, H_SPR_CPEMR1 = 2323 + , H_SPR_IPERR0 = 2324, H_SPR_IPERR1 = 2325, H_SPR_IPJSR = 2326, H_SPR_IPJRR = 2327 + , H_SPR_IPCSR0 = 2336, H_SPR_IPCSR1 = 2337, H_SPR_IPCWER0 = 2338, H_SPR_IPCWER1 = 2339 + , H_SPR_IPCWR = 2340, H_SPR_MBHSR = 2352, H_SPR_MBSSR = 2353, H_SPR_MBRSR = 2354 + , H_SPR_MBSDR = 2355, H_SPR_MBRDR = 2356, H_SPR_MBSMR = 2357, H_SPR_MBSTR0 = 2359 + , H_SPR_MBSTR1 = 2360, H_SPR_SLPR = 2368, H_SPR_SLDR = 2369, H_SPR_SLHSR = 2370 + , H_SPR_SLTR = 2371, H_SPR_SLWR = 2372, H_SPR_IHSR8 = 3848, H_SPR_IHSR9 = 3849 + , H_SPR_IHSR10 = 3850 } SPR_NAMES; /* Enum declaration for . */ |