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-rw-r--r--opcodes/ChangeLog18
-rw-r--r--opcodes/tic80-dis.c8
-rw-r--r--opcodes/tic80-opc.c83
3 files changed, 108 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0203c27..fb553c4 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,21 @@
+start-sanitize-tic80
+Mon Jan 13 15:58:56 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-dis.c (print_insn_tic80): Print floating point operands
+ as floats.
+ * tic80-opc.c (SPFI): Add single precision floating point
+ immediate operand type.
+ (ROTATE): Add rotate operand type for shifts.
+ (ENDMASK): Add for shifts.
+ (n): Macro for the 'n' bit.
+ (i): Macro for the 'i' bit.
+ (PD): Macro for the 'PD' field.
+ (P2): Macro for the 'P2' field.
+ (P1): Macro for the 'P1' field.
+ (tic80_operands): Add entries for "exts", "extu", "fadd",
+ "fcmp", and "fdiv".
+
+end-sanitize-tic80
Mon Jan 6 15:06:55 1997 Jeffrey A Law (law@cygnus.com)
* mn10200-dis.c (disassemble): Mask off unwanted bits after
diff --git a/opcodes/tic80-dis.c b/opcodes/tic80-dis.c
index fed68ae..02a4110 100644
--- a/opcodes/tic80-dis.c
+++ b/opcodes/tic80-dis.c
@@ -280,6 +280,14 @@ print_insn_tic80 (memaddr, info)
(*info -> fprintf_func) (info -> stream, "%#lx", value);
}
}
+ else if ((operand -> flags & TIC80_OPERAND_FLOAT) != 0)
+ {
+ /* FIXME: depends upon sizeof (long) == sizeof (float) */
+ union { float f; long l; } fval;
+
+ fval.l = value;
+ (*info -> fprintf_func) (info -> stream, "%g", fval.f);
+ }
else
{
if ((value > 999 || value < -999)
diff --git a/opcodes/tic80-opc.c b/opcodes/tic80-opc.c
index 54ae51d..8a0d082 100644
--- a/opcodes/tic80-opc.c
+++ b/opcodes/tic80-opc.c
@@ -77,9 +77,15 @@ const struct tic80_operand tic80_operands[] =
#define LUBF (LUI + 1)
{ 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
+ /* Single precision floating point immediate in following 32 bit
+ word. */
+
+#define SPFI (LUBF + 1)
+ { 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT },
+
/* Register in bits 4-0 */
-#define REG_0 (LUBF + 1)
+#define REG_0 (SPFI + 1)
{ 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
/* Register in bits 26-22 */
@@ -144,6 +150,16 @@ const struct tic80_operand tic80_operands[] =
#define LSI_SCALED (REG_SCALED + 1)
{ 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
+
+ /* Unsigned immediate in bits 4-0, used only for shift instructions */
+
+#define ROTATE (LSI_SCALED + 1)
+ { 5, 0, NULL, NULL, 0 },
+
+ /* Unsigned immediate in bits 9-5, used only for shift instructions */
+#define ENDMASK (ROTATE + 1)
+ { 5, 5, NULL, NULL, 0 },
+
};
const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
@@ -165,6 +181,12 @@ const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
#define OP_REG(x) OP_LI(x) /* For readability */
#define MASK_REG MASK_LI /* For readability */
+/* The 'n' bit at bit 10 */
+#define n(x) ((x) << 10)
+
+/* The 'i' bit at bit 11 */
+#define i(x) ((x) << 11)
+
/* The 'F' bit at bit 27 */
#define F(x) ((x) << 27)
@@ -193,6 +215,15 @@ const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
and register opcodes. */
#define S(x) ((x) << 11)
+/* The 'PD' field at bits 10-9 in floating point instructions */
+#define PD(x) ((x) << 9)
+
+/* The 'P2' field at bits 8-7 in floating point instructions */
+#define P2(x) ((x) << 7)
+
+/* The 'P1' field at bits 6-5 in floating point instructions */
+#define P1(x) ((x) << 5)
+
const struct tic80_opcode tic80_opcodes[] = {
@@ -377,6 +408,56 @@ const struct tic80_opcode tic80_opcodes[] = {
{"etrap", OP_LI(0x303) | E(1), MASK_LI | E(1), FMT_LI, {LUI} },
{"etrap", OP_REG(0x302) | E(1), MASK_REG | E(1), FMT_REG, {REG_0} },
+ /* Extract signed field (actually an sr.ds instruction) */
+
+ {"exts", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+ {"exts", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
+
+ /* Extract unsigned field (actually an sr.dz instruction */
+
+ {"extu", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+ {"extu", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
+
+ /* Floating-point addition */
+
+ {"fadd.sss", OP_LI(0x3E1) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
+ {"fadd.ssd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
+ {"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
+ {"fadd.dsd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
+ {"fadd.ddd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
+
+ {"fadd.sss", OP_REG(0x3E0) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
+ {"fadd.ssd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
+ {"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
+ {"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
+ {"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
+
+ /* Floating point compare */
+
+ {"fcmp.ss", OP_LI(0x3EB) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
+ {"fcmp.sd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
+ {"fcmp.ds", OP_LI(0x3EB) | PD(0) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
+ {"fcmp.dd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_REG, {SPFI, REG_22, REG_DEST} },
+
+ {"fcmp.ss", OP_REG(0x3EA) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
+ {"fcmp.sd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
+ {"fcmp.ds", OP_REG(0x3EA) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
+ {"fcmp.dd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
+
+ /* Floating point divide */
+
+ {"fdiv.sss", OP_LI(0x3E7) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
+ {"fdiv.ssd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
+ {"fdiv.sdd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
+ {"fdiv.dsd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
+ {"fdiv.ddd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(1), MASK_LI | PD(3) | P2(3) | P1(3), FMT_LI, {SPFI, REG_22, REG_DEST} },
+
+ {"fdiv.sss", OP_REG(0x3E6) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
+ {"fdiv.ssd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
+ {"fdiv.sdd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
+ {"fdiv.dsd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
+ {"fdiv.ddd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), FMT_REG, {REG_0, REG_22, REG_DEST} },
+
/* WORK IN PROGRESS BELOW THIS POINT */
{"illop0", OP_SI(0), MASK_SI, FMT_SI, FIXME},
generated by cgit v1.1 at 2024-12-15 17:16:01 +0000